A silicon-based millimeter wave high-energy-efficiency digitized transmitter chip and a control method thereof

Abstract

The application discloses a silicon-based millimeter wave high-energy-efficiency digital transmitter chip and a control method thereof, and the chip comprises a quadrature digital modulation module, a hybrid Doherty power amplification module, a self-shielding passive network module and an adaptive linear optimization control module; the quadrature digital modulation module is used for receiving a carrier signal and a baseband signal, and generating a high-order modulation signal according to the carrier signal and the baseband signal; the hybrid Doherty power amplification module is used for receiving the high-order modulation signal, and performing power amplification and synthesis output on the high-order modulation signal; the self-shielding passive network module is used for providing a low-loss signal transmission and power synthesis path for the transmitter chip; and the adaptive linear optimization control module is used for detecting an output signal of the transmitter chip, and adaptively optimizing working parameters of the hybrid Doherty power amplification module according to the output signal.

Description

Technical Field

[0001] This invention belongs to the field of millimeter-wave integrated circuits and wireless communication technology, and particularly relates to a silicon-based millimeter-wave high-efficiency digital transmitter chip and its control method. Background Technology

[0002] With the development of 5G+ / 6G communication, high-speed video transmission, and the Industrial Internet of Things, communication frequency bands are gradually expanding into the millimeter-wave band. Millimeter-wave transmitter chips need to simultaneously meet the requirements of high data rate, high output power, high energy efficiency, and high linearity.

[0003] Traditional millimeter-wave transmitter architectures (such as the classic Doherty power amplifier) ​​experience a sharp decline in system efficiency during deep power back-off. Furthermore, existing technologies suffer from high losses (substrate losses, radiation losses) in on-chip passive circuitry, and the linearity of the power amplifier is susceptible to process variations and operating temperature changes, lacking efficient and rapid adaptive linearization methods. Therefore, there is an urgent need for a millimeter-wave transmitter solution that can maintain high efficiency and high linearity under wide bandwidth and high power back-off conditions. Summary of the Invention

[0004] The present invention aims to provide a silicon-based millimeter-wave high-efficiency digital transmitter chip and its control method to solve the technical problems of low efficiency, large on-chip passive loss and slow linearity adaptive compensation speed of existing millimeter-wave transmitters during deep power back-off.

[0005] To achieve the above objectives, the present invention provides a silicon-based millimeter-wave high-efficiency digital transmitter chip, comprising: an orthogonal digital modulation module, a hybrid Doherty power amplifier module, a self-shielded passive network module, and an adaptive linear optimization control module; The orthogonal digital modulation module is used to receive carrier signals and baseband signals, and generate high-order modulation signals based on the carrier signals and baseband signals; The hybrid Doherty power amplifier module is used to receive the high-order modulation signal and amplify and synthesize the high-order modulation signal for output. The self-shielded passive network module is used to provide a low-loss signal transmission and power combining path for the transmitter chip; The adaptive linear optimization control module is used to detect the output signal of the transmitter chip and adaptively optimize the operating parameters of the hybrid Doherty power amplifier module based on the output signal.

[0006] Optionally, the quadrature digital modulation module includes: an orthogonal allocation network and two RFDAC micro-modulation units; The orthogonal allocation network is used to allocate the input carrier signal into I-channel carrier signals and Q-channel carrier signals, and output them to the two RFDAC micro-modulation units respectively. Each of the RFDAC micro-modulation units is configured to receive a corresponding I-channel or Q-channel carrier signal and a baseband signal, and to digitally mix the I-channel or Q-channel carrier signal with the baseband signal to synthesize a high-order QAM modulated signal.

[0007] Optionally, the RFDAC micro-modulation unit includes a logic AND gate, a signal buffer, and a differential amplifier cascaded in sequence; The logical AND gate is used to perform a logical AND operation between the corresponding I-channel or Q-channel carrier signal and the baseband signal to obtain the mixing signal; The signal buffer is used to buffer and drive the mixing signal to obtain a buffered signal; The differential amplifier is used to differentially amplify the buffered signal and output the high-order QAM modulated signal.

[0008] Optionally, the hybrid Doherty power amplifier module includes a coupler, a main power amplifier, two auxiliary power amplifiers, and a broadband low-loss passive combining network. The coupler is used to receive the high-order modulation signal and to orthogonally distribute the high-order modulation signal into three signals of equal amplitude, which are then output to the main power amplifier and the two auxiliary power amplifiers respectively. The main power amplifier and the two auxiliary power amplifiers are configured to amplify their respective received signals to generate three amplified signals. The broadband low-loss passive synthesis network is used to receive the three amplified signals and output them after power superposition of the three amplified signals.

[0009] Optionally, the self-shielded passive network module includes: a three-dimensional self-shielded passive structure on the sheet, the three-dimensional self-shielded passive structure on the sheet includes: a via penetrating the metal layers from M1 to M8, a full-coverage metal plate of the top layer M8, and a spacer metal layer disposed below the passive circuit. The vias, full-coverage metal plates, and spacer metal layers are configured to form shielding interfaces in three directions of the on-chip passive structure to confine the electromagnetic field within the on-chip passive structure.

[0010] Optionally, the method for detecting the output signal of the transmitter chip and adaptively optimizing the operating parameters of the hybrid Doherty power amplifier module based on the output signal includes: Identify the orthogonal components of the transmitter chip's output signal, and determine the degree of nonlinearity of the hybrid Doherty power amplifier module based on the orthogonal components; Based on the degree of nonlinearity, efficiency points that satisfy the error vector magnitude threshold are selected by traversing the preset bias and matching parameter space, and the amplifier bias voltage and adjustable matching network state corresponding to each efficiency point are recorded. Using the recorded efficiency point as the initial solution, optimization is performed based on the bias control algorithm and the matching network tuning algorithm to obtain the optimized combination of bias and matching parameters; The linearity index calculated based on theory is used to determine whether the combination of bias and matching parameters meets the decision criteria, and if the decision criteria are met, the combination of bias and matching parameters is configured to the hybrid Doherty power amplifier module.

[0011] Optionally, the adaptive linear optimization control module includes an adaptive control circuit structure; The adaptive control circuit structure is used to generate a control signal based on the quadrature components of the output signal and feed the control signal back to the hybrid Doherty power amplifier module to adjust the bias and matching parameters of the hybrid Doherty power amplifier module.

[0012] Optionally, a capacitor-resistor type low-pass filter network is embedded in the key signal path of the adaptive control circuit structure; The capacitor-resistor type low-pass filter network is used to receive the control signal and filter out the high-order harmonic components in the control signal.

[0013] This invention also discloses a control method for a silicon-based millimeter-wave high-efficiency digital transmitter chip, comprising: S1. The input carrier signal is generated into I / Q signals through an orthogonal distribution network and fed to the corresponding RFDAC micro-modulation unit respectively. The signals are digitally mixed with the baseband signal to synthesize a modulation signal. S2. The synthesized modulation signal is orthogonally distributed to the main power amplifier and two auxiliary power amplifiers of the hybrid Doherty power amplifier module through a 0° / 90° coupler. After power amplification, the power of each channel is superimposed and output through a broadband low-loss passive synthesis network. S3. Identify the quadrature components of the output signal to determine the degree of nonlinearity of the power amplifier; S4. In the preset bias and matching parameter space, traverse and select each efficiency point that satisfies the error vector amplitude threshold, and record the corresponding amplifier bias voltage and adjustable matching network state. S5. Based on the bias control algorithm and the matching network tuning algorithm, the selected efficiency point is used as the initial solution to find the optimization combination of bias and matching parameters. S6. Using the linearity index obtained from theoretical calculations as the basis for judgment, evaluate whether the parameter combination is suitable for the current target; S7. If the decision criteria are met, the final configuration parameters will be set in the power amplifier.

[0014] Compared with the prior art, the present invention has the following advantages and technical effects: 1. Significantly improved deep back-off efficiency: By using a hybrid third-order Doherty architecture, combined with parallel and series impedance transformation networks, the deep back-off efficiency of the transmitter when transmitting peak-to-average power ratio (PAPR) signals (such as modulated signals) is significantly improved, breaking through the bottleneck of efficiency degradation in the back-off region of traditional architectures.

[0015] 2. Significantly reduced passive losses: The adoption of a three-dimensional self-shielded passive structure on the chip effectively reduces substrate loss and radiation loss in the millimeter-wave band, improves the quality factor of the passive circuit, and thus improves the overall energy efficiency of the transmitter.

[0016] 3. Adaptive linearity optimization and fast response: Combining orthogonal component detection and low-delay control circuits, it achieves fast adaptive linear compensation for process angle and temperature changes, with fast response time, and can support high-quality transmission of high data rate and high-order modulation signals in the millimeter wave band.

[0017] 4. High overall energy efficiency: The adoption of a digital modulation unit avoids the high power consumption problem of high-speed DAC circuits, and combined with a high-efficiency analog power amplifier, it achieves high system-level energy efficiency. Attached Figure Description

[0018] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a diagram of the hybrid third-order digital Doherty transmitter architecture according to an embodiment of the present invention; Figure 2 This is a schematic diagram of a wideband, low-loss, self-shielded passive circuit according to an embodiment of the present invention. Figure 3 This is a schematic diagram of a high-response-speed adaptive linear optimization control strategy according to an embodiment of the present invention. Detailed Implementation

[0019] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0020] It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.

[0021] This embodiment proposes a silicon-based millimeter-wave high-efficiency digital transmitter chip, which specifically includes: an orthogonal digital modulation module, a hybrid Doherty power amplifier module, a self-shielded passive network module, and an adaptive linear optimization control module; The orthogonal digital modulation module is used to receive carrier signals and baseband signals, and generate high-order modulation signals based on the carrier signals and baseband signals; The hybrid Doherty power amplifier module is used to receive the high-order modulation signal and amplify and synthesize the high-order modulation signal for output. The self-shielded passive network module is used to provide a low-loss signal transmission and power combining path for the transmitter chip; The adaptive linear optimization control module is used to detect the output signal of the transmitter chip and adaptively optimize the operating parameters of the hybrid Doherty power amplifier module based on the output signal.

[0022] Furthermore, the orthogonal digital modulation module includes: an orthogonal allocation network and two RFDAC micro-modulation units; The orthogonal allocation network is used to allocate the input carrier signal into I-channel carrier signals and Q-channel carrier signals, and output them to the two RFDAC micro-modulation units respectively. Each of the RFDAC micro-modulation units is configured to receive a corresponding I-channel or Q-channel carrier signal and a baseband signal, and to digitally mix the I-channel or Q-channel carrier signal with the baseband signal to synthesize a high-order quadrature amplitude modulation (QAM) signal.

[0023] Furthermore, the RFDAC micro-modulation unit includes a logic AND gate, a signal buffer, and a differential amplifier cascaded in sequence; The logical AND gate is used to perform a logical AND operation between the corresponding I-channel or Q-channel carrier signal and the baseband signal to obtain the mixing signal; The signal buffer is used to buffer and drive the mixing signal to obtain a buffered signal; The differential amplifier is used to differentially amplify the buffered signal and output the high-order QAM modulated signal.

[0024] Furthermore, the hybrid Doherty power amplifier module includes a coupler, a main power amplifier, two auxiliary power amplifiers, and a broadband low-loss passive combining network; The coupler is used to receive the high-order modulation signal and to orthogonally distribute the high-order modulation signal into three signals of equal amplitude, which are then output to the main power amplifier and the two auxiliary power amplifiers respectively. The main power amplifier and the two auxiliary power amplifiers are configured to amplify their respective received signals to generate three amplified signals. The broadband low-loss passive synthesis network is used to receive the three amplified signals and output them after power superposition of the three amplified signals.

[0025] Specifically, a hybrid third-order digital transmitter architecture, such as Figure 1 As shown: To address the issues of complex architecture, limited efficiency improvement in deep back-off, and low system energy efficiency in existing millimeter-wave transmitters, a high-efficiency digital transmitter architecture will be adopted, combined with a hybrid third-order Doherty impedance enhancement technology, to improve the energy efficiency of the transmitter system under deep back-off. The proposed transmitter architecture consists of two stages: the first stage is a millimeter-wave high-speed quadrature digital modulator, and the second stage is a hybrid Doherty power amplifier.

[0026] The first stage employs an orthogonal digital modulation structure, consisting of two identical RFDAC micro-modulation units. The input carrier signal, after passing through an orthogonal distribution network, generates I / Q signals, which are then fed to the corresponding RFDAC micro-modulation units. Each RFDAC unit comprises cascaded AND gates, signal buffers, and differential amplifiers, digitally mixing the I / Q signals with the baseband signal to synthesize a high-order QAM modulated signal. This structure offers advantages such as low power consumption and low heat generation, effectively preventing degradation of the transmitter system efficiency.

[0027] The second stage employs a series-parallel Doherty impedance transformation network, consisting of one main power amplifier and two auxiliary power amplifiers. The input signal is orthogonally distributed to each amplifier via 0° / 90° couplers. This structure significantly improves efficiency in the power back-off region while maintaining signal linearity. At the output, a broadband, low-loss passive synthesizer network is used to superimpose the power from each amplifier, combined with adaptive linear optimization control to achieve synergistic optimization of system efficiency and linearity.

[0028] Furthermore, the self-shielded passive network module includes: a three-dimensional self-shielded passive structure on the sheet, the three-dimensional self-shielded passive structure on the sheet includes: a via penetrating the metal layers from M1 to M8, a full-coverage metal plate of the top layer M8, and a spacer metal layer disposed below the passive circuit. The vias, full-coverage metal plates, and spacer metal layers are configured to form shielding interfaces in three directions of the on-chip passive structure to confine the electromagnetic field within the on-chip passive structure.

[0029] Specifically, wideband, low-loss, self-shielded passive circuits, such as Figure 2 As shown: As the operating frequency of wireless transmission chips expands to the millimeter-wave band, the increased passive loss due to the aggravated skin effect of metals and the increased parasitic effects of transistors are challenges in millimeter-wave chip design. This project will study a novel on-chip low-loss passive circuit structure. Through three-dimensional self-shielding technology, it effectively reduces the substrate loss and radiation loss of the passive structure, overcoming the technical bottlenecks of high loss and low passive efficiency in millimeter-wave passive circuits. Traditional on-chip passive circuit structures mostly adopt microwave structures such as striplines or coplanar waveguides. Most of the electromagnetic field passes through the lossy substrate, resulting in significant substrate loss; a large portion of the electromagnetic field is also radiated through space, resulting in significant radiation loss. To further improve the efficiency of passive circuits and reduce losses, a three-dimensional self-shielded on-chip passive structure is proposed. This structure includes vias penetrating M1–M8, a fully covered metal plate on the top M8, and a spacer metal layer beneath the passive circuit. By utilizing the shielding interfaces in three directions between the aforementioned metal layers (top layer – passive circuit, via – passive circuit, via – spacer metal), the electromagnetic field is effectively confined within the on-chip passive structure, thereby effectively reducing silicon substrate loss and radiation loss, reducing passive circuit loss, and improving the efficiency of the transmission system.

[0030] Furthermore, the method for detecting the output signal of the transmitter chip and adaptively optimizing the operating parameters of the hybrid Doherty power amplifier module based on the output signal includes: Identify the quadrature components of the transmitter chip's output signal, and determine the degree of nonlinearity of the hybrid Doherty power amplifier module based on the quadrature components; Based on the degree of nonlinearity, efficiency points that satisfy the error vector magnitude threshold are selected by traversing the preset bias and matching parameter space, and the amplifier bias voltage and adjustable matching network state corresponding to each efficiency point are recorded. Using the recorded efficiency point as the initial solution, optimization is performed based on the bias control algorithm and the matching network tuning algorithm to obtain the optimized combination of bias and matching parameters; The linearity index calculated based on theory is used to determine whether the combination of bias and matching parameters meets the decision criteria, and if the decision criteria are met, the combination of bias and matching parameters is configured to the hybrid Doherty power amplifier module.

[0031] Furthermore, the adaptive linear optimization control module includes an adaptive control circuit structure; The adaptive control circuit structure is used to generate a control signal based on the quadrature components of the output signal and feed the control signal back to the hybrid Doherty power amplifier module to adjust the bias and matching parameters of the hybrid Doherty power amplifier module.

[0032] Furthermore, a capacitor-resistor type low-pass filter network is embedded in the key signal path of the adaptive control circuit structure; The capacitor-resistor type low-pass filter network is used to receive the control signal and filter out the high-order harmonic components in the control signal.

[0033] Specifically, Figure 3 A block diagram of a high-response-speed adaptive linear optimization control strategy is presented. The nonlinearity of the power amplifier is determined by identifying the quadrature components of the output signal, and then optimization is performed accordingly.

[0034] The specific process is as follows: First, the system iterates through the preset bias and matching parameter space, selecting each efficiency point where the error vector magnitude (EVM) is less than a preset threshold, and records the amplifier bias voltage and adjustable matching network state corresponding to these points. Then, based on the bias control algorithm and matching network tuning algorithm, using the selected efficiency points as initial solutions, local or global optimization is performed to obtain the optimized bias and matching parameter combination. Next, the system uses the theoretically calculated linearity index as the criterion to automatically evaluate whether the set of parameters is suitable for the current target. If the criterion is met, the final configuration parameters are set in the power amplifier, thereby achieving a synergistic effect of gain adjustment and linearity optimization. The overall control logic is as follows: Figure 3 As shown.

[0035] This adaptive optimization control logic can dynamically adjust the linearity of the power amplifier in real time, compensating for deviations caused by process variations and temperature, ensuring stable linearity and efficiency throughout the system's lifespan. At the circuit implementation level, the control loop employs a low-parasitic, low-delay adaptive control circuit structure to minimize feedback response time. Simultaneously, a capacitor-resistor type low-pass filter network is embedded in the critical signal path to effectively filter out interference introduced by higher harmonic components, further improving the convergence stability and control accuracy of the optimization algorithm.

[0036] This invention also discloses a control method for a silicon-based millimeter-wave high-efficiency digital transmitter chip, comprising: S1. The input carrier signal is generated into I / Q signals through an orthogonal distribution network and fed to the corresponding RFDAC micro-modulation unit respectively. The signals are digitally mixed with the baseband signal to synthesize a modulation signal. S2. The synthesized modulation signal is orthogonally distributed to the main power amplifier and two auxiliary power amplifiers of the hybrid Doherty power amplifier module through a 0° / 90° coupler. After power amplification, the power of each channel is superimposed and output through a broadband low-loss passive synthesis network. S3. Identify the quadrature components of the output signal to determine the degree of nonlinearity of the power amplifier; S4. In the preset bias and matching parameter space, traverse and select each efficiency point that satisfies the error vector amplitude threshold, and record the corresponding amplifier bias voltage and adjustable matching network state. S5. Based on the bias control algorithm and the matching network tuning algorithm, the selected efficiency point is used as the initial solution to find the optimization combination of bias and matching parameters. S6. Using the linearity index obtained from theoretical calculations as the basis for judgment, evaluate whether the parameter combination is suitable for the current target; S7. If the decision criteria are met, the final configuration parameters will be set in the power amplifier.

[0037] The above are merely preferred embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A silicon-based millimeter-wave high-efficiency digital transmitter chip, characterized in that, include: Orthogonal digital modulation module, hybrid Doherty power amplifier module, self-shielded passive network module, and adaptive linear optimization control module; The orthogonal digital modulation module is used to receive carrier signals and baseband signals, and generate high-order modulation signals based on the carrier signals and baseband signals; The hybrid Doherty power amplifier module is used to receive the high-order modulation signal and amplify and synthesize the high-order modulation signal for output. The self-shielded passive network module is used to provide a low-loss signal transmission and power combining path for the transmitter chip; The adaptive linear optimization control module is used to detect the output signal of the transmitter chip and adaptively optimize the operating parameters of the hybrid Doherty power amplifier module based on the output signal.

2. The silicon-based millimeter-wave high-efficiency digital transmitter chip according to claim 1, characterized in that, The orthogonal digital modulation module includes: an orthogonal allocation network and two RFDAC micro-modulation units; The orthogonal allocation network is used to allocate the input carrier signal into I-channel carrier signals and Q-channel carrier signals, and output them to the two RFDAC micro-modulation units respectively. Each of the RFDAC micro-modulation units is configured to receive a corresponding I-channel or Q-channel carrier signal and a baseband signal, and to digitally mix the I-channel or Q-channel carrier signal with the baseband signal to synthesize a high-order QAM modulated signal.

3. A silicon-based millimeter-wave high-efficiency digital transmitter chip according to claim 2, characterized in that, The RFDAC micro-modulation unit includes a logic AND gate, a signal buffer, and a differential amplifier cascaded in sequence. The logical AND gate is used to perform a logical AND operation between the corresponding I-channel or Q-channel carrier signal and the baseband signal to obtain the mixing signal; The signal buffer is used to buffer and drive the mixing signal to obtain a buffered signal; The differential amplifier is used to differentially amplify the buffered signal and output the high-order QAM modulated signal.

4. A silicon-based millimeter-wave high-efficiency digital transmitter chip according to claim 1, characterized in that, The hybrid Doherty power amplifier module includes a coupler, a main power amplifier, two auxiliary power amplifiers, and a broadband low-loss passive combining network. The coupler is used to receive the high-order modulation signal and to orthogonally distribute the high-order modulation signal into three signals of equal amplitude, which are then output to the main power amplifier and the two auxiliary power amplifiers respectively. The main power amplifier and the two auxiliary power amplifiers are configured to amplify their respective received signals to generate three amplified signals. The broadband low-loss passive synthesis network is used to receive the three amplified signals and output them after power superposition of the three amplified signals.

5. A silicon-based millimeter-wave high-efficiency digital transmitter chip according to claim 1, characterized in that, The self-shielded passive network module includes: a three-dimensional self-shielded passive structure on a sheet, which includes: a via penetrating metal layers M1 to M8, a full-coverage metal plate of the top layer M8, and a spacer metal layer disposed below the passive circuit. The vias, full-coverage metal plates, and spacer metal layers are configured to form shielding interfaces in three directions of the on-chip passive structure to confine the electromagnetic field within the on-chip passive structure.

6. A silicon-based millimeter-wave high-efficiency digital transmitter chip according to claim 1, characterized in that, The method for detecting the output signal of the transmitter chip and adaptively optimizing the operating parameters of the hybrid Doherty power amplifier module based on the output signal includes: Identify the orthogonal components of the transmitter chip's output signal, and determine the degree of nonlinearity of the hybrid Doherty power amplifier module based on the orthogonal components; Based on the degree of nonlinearity, efficiency points that satisfy the error vector magnitude threshold are selected by traversing the preset bias and matching parameter space, and the amplifier bias voltage and adjustable matching network state corresponding to each efficiency point are recorded. Using the recorded efficiency point as the initial solution, optimization is performed based on the bias control algorithm and the matching network tuning algorithm to obtain the optimized combination of bias and matching parameters; The linearity index calculated based on theory is used to determine whether the combination of bias and matching parameters meets the decision criteria, and if the decision criteria are met, the combination of bias and matching parameters is configured to the hybrid Doherty power amplifier module.

7. A silicon-based millimeter-wave high-efficiency digital transmitter chip according to claim 6, characterized in that, The adaptive linear optimization control module includes an adaptive control circuit structure; The adaptive control circuit structure is used to generate a control signal based on the quadrature components of the output signal and feed the control signal back to the hybrid Doherty power amplifier module to adjust the bias and matching parameters of the hybrid Doherty power amplifier module.

8. A silicon-based millimeter-wave high-efficiency digital transmitter chip according to claim 7, characterized in that, The adaptive control circuit structure incorporates a capacitor-resistor type low-pass filter network in its key signal path. The capacitor-resistor type low-pass filter network is used to receive the control signal and filter out the high-order harmonic components in the control signal.

9. A control method based on the silicon-based millimeter-wave high-efficiency digital transmitter chip according to any one of claims 1-8, characterized in that, include: S1. The input carrier signal is generated into I / Q signals through an orthogonal distribution network and fed to the corresponding RFDAC micro-modulation unit respectively. The signals are digitally mixed with the baseband signal to synthesize a modulation signal. S2. The synthesized modulation signal is orthogonally distributed to the main power amplifier and two auxiliary power amplifiers of the hybrid Doherty power amplifier module through a 0° / 90° coupler. After power amplification, the power of each channel is superimposed and output through a broadband low-loss passive synthesis network. S3. Identify the quadrature components of the output signal to determine the degree of nonlinearity of the power amplifier; S4. In the preset bias and matching parameter space, traverse and select each efficiency point that satisfies the error vector amplitude threshold, and record the corresponding amplifier bias voltage and adjustable matching network state. S5. Based on the bias control algorithm and the matching network tuning algorithm, the selected efficiency point is used as the initial solution to find the optimization combination of bias and matching parameters. S6. Use the linearity index obtained from theoretical calculations as the basis for judgment to evaluate whether the parameter combination is suitable for the current target. S7. If the decision criteria are met, the final configuration parameters will be set in the power amplifier.

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