Receiver and electronic device

Abstract

The application provides a receiver and an electronic device, and belongs to the technical field of radio frequency. The receiver comprises a first signal receiving circuit, a first frequency divider, a first oscillator, a second oscillator, a first switch and a second switch. The first signal receiving circuit is coupled with the first frequency divider, the first switch is coupled with the first frequency divider and the first oscillator respectively, and the second switch is coupled with the first frequency divider and the second oscillator respectively. The first oscillator outputs a first oscillation signal to the first frequency divider, the second oscillator outputs a second oscillation signal to the first frequency divider, and the first frequency divider divides the first oscillation signal or the second oscillation signal. When the first frequency divider receives a first radio frequency signal, a second radio frequency signal occupies the first frequency divider, and at this time, the first radio frequency signal has not been received completely. After the first frequency divider receives the second radio frequency signal, the first frequency divider continues to receive the first radio frequency signal, and it is not necessary to retransmit the first radio frequency signal, so that the efficiency of receiving the first radio frequency signal is improved.

Description

Technical Field

[0001] This application relates to the field of radio frequency technology, and more particularly to a receiver and electronic device. Background Technology

[0002] With the development of wireless communication technology, user devices transmit information to each other wirelessly. Common wireless communication technologies include Wireless Fidelity (Wi-Fi) and Bluetooth (BT). Both Wi-Fi and BT signals require transceivers to receive or send information, so Wi-Fi and BT need to occupy the transceiver according to a preset priority.

[0003] The Aggregate Medium Access Control (MAC) Protocol Data Unit (A-MPDU) is an ultra-long data unit for Wi-Fi signals, designed to improve transmission efficiency. The time required to receive an A-MPDU may exceed the time required to receive a single BT signal. If the BT signal occupies the transceiver during A-MPDU transmission, the overall transmission efficiency of the A-MPDU will be reduced. Summary of the Invention

[0004] This application provides a receiver and electronic device, which aims to solve the technical problem in the prior art where the BT signal occupies the transceiver during the A-MPDU reception process, resulting in low A-MPDU reception efficiency.

[0005] In a first aspect, embodiments of this application provide a receiver, which includes a first signal receiving circuit, a first frequency divider, a first oscillator, a second oscillator, a first switch, and a second switch. The first signal receiving circuit is coupled to the first frequency divider, the first switch is coupled to both the first frequency divider and the first oscillator, and the second switch is coupled to the node between the first frequency divider and the first switch, as well as to the second oscillator. The first switch and the second switch are not simultaneously turned on. The first oscillator outputs a first oscillation signal to the first frequency divider via the first switch, and the second oscillator outputs a second oscillation signal to the first frequency divider via the second switch. The first frequency divider divides either the first oscillation signal or the second oscillation signal, and outputs the divided signal to the first signal receiving circuit.

[0006] Understandably, when the first signal receiving circuit receives the first radio frequency signal corresponding to the Wi-Fi signal, the first frequency divider divides the first oscillation signal. When the first signal receiving circuit receives the second radio frequency signal corresponding to the BT signal, the first frequency divider divides the second oscillation signal. The first frequency divider is selectively coupled to the first oscillator or the second oscillator, allowing it to switch back and forth between dividing the first and second oscillation signals. When the first frequency divider receives the first radio frequency signal, the second radio frequency signal preempts it, meaning the first radio frequency signal has not yet been fully received. After the first frequency divider finishes receiving the second radio frequency signal, it resumes receiving the first radio frequency signal. This eliminates the need to retransmit the first radio frequency signal, improving the efficiency of receiving the first radio frequency signal. Furthermore, in this application, a single first signal receiving circuit only needs one first frequency divider, which can switch between dividing the first and second oscillation signals, reducing product cost, footprint, and power consumption.

[0007] In an exemplary embodiment, the receiver further includes a first controller coupled to the first frequency divider. The first controller is configured to output a first control signal to the first frequency divider, and the first frequency divider, in response to the first control signal at a first potential, divides the first oscillation signal or the second oscillation signal.

[0008] Understandably, by outputting a first control signal of the first potential to the first frequency divider through the first controller, the first frequency divider performs frequency division, which can better control when the first frequency divider performs frequency division.

[0009] In an exemplary embodiment, the first frequency divider is reset in response to the first control signal at the second potential. The reset of the first frequency divider is between the first frequency divider dividing the second oscillation signal and the first frequency divider dividing the first oscillation signal. The first potential is greater than or less than the second potential.

[0010] Understandably, the first frequency divider is reset in response to the first control signal at the second potential. This reset occurs between the first frequency divider's division of the second oscillation signal and its division of the first oscillation signal. The mixing of the first radio frequency signal and the first divided signal must be performed strictly according to the timing sequence; otherwise, the first analog baseband signal with the correct frequency cannot be obtained after mixing. Therefore, the timing of the first divided signal must be strictly guaranteed. Between switching from dividing the second oscillation signal to dividing the first oscillation signal, the first frequency divider needs to be reset, and then the first frequency divider must be controlled to divide the first oscillation signal according to the correct timing sequence.

[0011] In one possible implementation, the first control signal includes a first frequency division stage, a second frequency division stage, a third frequency division stage, and a reset stage, wherein the first frequency division stage, the second frequency division stage, the reset stage, and the third frequency division stage are arranged sequentially in time. In the first frequency division stage, the first frequency divider divides the first oscillation signal in response to the first control signal at a first potential. In the second frequency division stage, the first frequency divider divides the second oscillation signal in response to the first control signal at a first potential. In the reset stage, the first frequency divider resets in response to the first control signal at a second potential; and in the third frequency division stage, the first frequency divider divides the first oscillation signal in response to the first control signal at a first potential.

[0012] Understandably, during the reset phase between the second and third frequency division stages, the first controller outputs a first control signal at a second potential to the first frequency divider, and the first frequency divider resets in response to the first control signal at the second potential. Reset can be understood as the first frequency divider becoming inactive, effectively shutting down the first frequency divider.

[0013] In another possible implementation, the first control signal further includes a reset phase, which occurs between the first frequency division phase and the second frequency division phase. During the reset phase, the first frequency divider resets in response to the first control signal at a second potential.

[0014] Understandably, without a reset phase, the first frequency divider directly switches from dividing the first oscillation signal to dividing the second oscillation signal. In this case, the first oscillation signal becomes an interference signal, and at the start of the second frequency division phase, the second frequency-divided signal will have noise. Therefore, to eliminate the influence of the first oscillation signal, a reset phase is set after the first frequency division phase ends to shut down the first frequency divider before starting the second frequency division phase. Whether or not there is a reset phase, i.e., whether or not the first frequency divider is shut down from the first to the second frequency division phase, does not affect the first frequency divider's division of the second oscillation signal, nor does it affect the first signal receiving circuit's mixing of the second RF signal with the second frequency-divided signal.

[0015] In one embodiment, the receiver further includes a second signal receiving circuit and a second frequency divider. The second signal receiving circuit is coupled to the second frequency divider, which is also coupled to a node between the first oscillator and the first switch. The first controller is also coupled to the node between the second signal receiving circuit and the second frequency divider. The first frequency divider is used to divide the first oscillation signal and output the divided signal to the first signal receiving circuit. The second frequency divider is used to output the divided signal of the first oscillation signal as a first trigger signal to the first controller. During the first frequency division stage and the third frequency division stage, the first controller responds to the first trigger signal by outputting a first control signal at a first potential to the first frequency divider.

[0016] Understandably, the first electromagnetic wave signal is received simultaneously by two antennas, namely a first antenna and a second antenna. The first oscillation signal is then divided into frequencies simultaneously by two frequency dividers, namely a first frequency divider and a second frequency divider. This increases the receiver's reception rate of the first electromagnetic wave signal and saves time. Furthermore, during the first and third frequency division stages, the first antenna and the second antenna simultaneously receive the first electromagnetic wave signal, requiring both the first and second frequency dividers to divide the first oscillation signal into frequencies concurrently. At the beginning of either the first or third frequency division stage, the second frequency divider divides the first oscillation signal, and transmits the divided first oscillation signal as the first trigger signal to the first controller. The first controller responds to the first trigger signal by outputting a first control signal at a first potential. The first frequency divider, in response to the first control signal at the first potential, divides the first oscillation signal, ensuring that in both the first and third frequency division stages, the first and second frequency dividers simultaneously divide the first oscillation signal. Consequently, the first frequency-divided signal (derived from the first frequency divider's division of the first oscillation signal) and the third frequency-divided signal (derived from the second frequency divider's division of the first oscillation signal) are synchronized. The third frequency-divided signal must be synchronized with the first frequency-divided signal; otherwise, the first radio frequency signal mixed with the first frequency-divided signal will not produce a first analog baseband signal with the correct frequency.

[0017] In an exemplary embodiment, the first controller includes a first multiplexer, a second multiplexer, and a first flip-flop. The first multiplexer includes a first input terminal, a second input terminal, a first selection input terminal, and a first output terminal. The second multiplexer includes a third input terminal, a fourth input terminal, a second selection input terminal, and a second output terminal. The first flip-flop includes a first clock input terminal, a first data input terminal, and a first data output terminal. The first input terminal receives a multiple-transmit multiple-receive signal, the second input terminal receives a first enable signal, the first selection input terminal receives a first selection signal, the first output terminal is coupled to the first data input terminal, the first clock input terminal is coupled to the node between the second frequency divider and the second signal receiving circuit, the first data output terminal is coupled to the third input terminal, the fourth input terminal receives a second enable signal, the second selection input terminal receives a second selection signal, and the second output terminal is coupled to the first frequency divider. The first multiplexer selectively turns on the first input terminal and the first output terminal or the second input terminal and the first output terminal in response to the first selection signal. The second multiplexer selectively turns on the third input terminal and the second output terminal or the fourth input terminal and the second output terminal in response to the second selection signal. The first trigger transmits the potential of the first data input terminal to the first data output terminal in response to the change edge of the potential of the first clock input terminal.

[0018] In an exemplary embodiment, the first frequency division stage includes a synchronization stage and a handover preparation stage, wherein the handover preparation stage follows the synchronization stage, and the reset stage follows the handover preparation stage.

[0019] During the synchronization phase, the multiple-receive-multiple-transmit signal is a first potential, the first enable signal is a first potential, the first selection signal is a second potential, and the second selection signal is a second potential. The first multiplexer connects the first input terminal and the first output terminal, the first trigger responds to the edge of the change in the potential of the first clock input terminal and transmits the potential of the first data input terminal to the first data output terminal, the second multiplexer connects the third input terminal and the second output terminal, and the first controller outputs the first control signal at the first potential to the first frequency divider.

[0020] Understandably, during the synchronization phase, while the second frequency divider divides the first oscillation signal, the potential of the first multi-transmit and multi-receive signal is transmitted to the first frequency divider. The first frequency divider then divides the first oscillation signal, so that the first frequency divider divides the first oscillation signal and the second frequency divider divide the first oscillation signal synchronously. This helps to ensure that the third frequency divider signal needs to be synchronized with the first frequency divider signal.

[0021] In an exemplary embodiment, during the switching preparation phase, the first enable signal is a first potential, the first selection signal is a first potential, and the second selection signal is a second potential. The first multiplexer connects the second input terminal to the first output terminal, the first trigger transmits the potential of the first data input terminal to the first data output terminal in response to the edge of the change in the potential of the first clock input terminal, the second multiplexer connects the third input terminal to the second output terminal, and the first controller outputs the first control signal at the first potential to the first frequency divider.

[0022] Understandably, during the switching preparation phase, the first enable signal of the first potential is transmitted to the first frequency divider, causing the first frequency divider to divide the first oscillation signal. In subsequent phases, the second frequency divider will continue to perform frequency division, while the first frequency divider needs to be turned off. Therefore, switching the first control signal of the first potential from being provided by a multi-transmit / multi-receive signal to being provided by the first enable signal facilitates a more convenient shutdown of the first frequency divider in subsequent phases.

[0023] In an exemplary embodiment, during the reset phase, the second enable signal is a second potential, the second selection signal is a first potential, the second multiplexer connects the fourth input terminal to the second output terminal, and the first controller outputs the first control signal at the second potential to the first frequency divider.

[0024] In an exemplary embodiment, during the second frequency division stage, the second enable signal is at a first potential, the second selection signal is at a first potential, the second multiplexer connects the fourth input terminal to the second output terminal, and the first controller outputs the first control signal at the first potential to the first frequency divider.

[0025] In an exemplary embodiment, during the reset phase, the first enable signal is a second potential, the first selection signal is a first potential, the second selection signal is a second potential, the first multiplexer connects the second input terminal to the first output terminal, the first trigger transmits the potential of the first data input terminal to the first data output terminal in response to the change edge of the potential of the first clock input terminal, the second multiplexer connects the third input terminal to the second output terminal, and the first controller outputs the first control signal at the second potential to the first frequency divider.

[0026] In an exemplary embodiment, during the third frequency division stage, the first enable signal is a first potential, the first selection signal is a first potential, the second selection signal is a second potential, the first multiplexer connects the second input terminal to the first output terminal, the first trigger transmits the potential of the first data input terminal to the first data output terminal in response to the change edge of the potential of the first clock input terminal, the second multiplexer connects the third input terminal to the second output terminal, and the first controller outputs the first control signal at the first potential to the first frequency divider.

[0027] In an exemplary embodiment, the receiver further includes a third signal receiving circuit, a third frequency divider, a third switch, a fourth switch, and a second controller. The third frequency divider is coupled to the second controller and the third switch, respectively. The third switch is also coupled to the node between the first oscillator and the first switch. The fourth switch is coupled to the node between the third frequency divider and the third switch, and the node between the second switch and the second oscillator, respectively. The second controller is also coupled to the node between the first frequency divider and the first signal receiving circuit.

[0028] The first frequency divider divides the first oscillation signal and outputs the divided signal as a second trigger signal to the second controller. During the first and third frequency division phases, the second controller, in response to the second trigger signal, outputs a third control signal at a first potential to the third frequency divider. The third frequency divider, in response to the third control signal at the first potential, divides the first oscillation signal. During the second frequency division phase, the second controller outputs the third control signal at the first potential to the third frequency divider. The third frequency divider, in response to the third control signal at the first potential, divides the second oscillation signal.

[0029] Understandably, the first electromagnetic wave signal is received simultaneously by two antennas, namely the first antenna and the third antenna. The first oscillation signal is then divided into frequencies simultaneously by two frequency dividers, namely the first frequency divider and the third frequency divider. This increases the receiver's reception rate of the first electromagnetic wave signal and saves time. Furthermore, during the first and third frequency division stages, since both the first and third antennas receive the first electromagnetic wave signal simultaneously, the first and third frequency dividers must simultaneously divide the first oscillation signal into frequencies. At the beginning of either the first or third frequency division stage, the first frequency divider divides the first oscillation signal, and transmits the divided first oscillation signal as a second trigger signal to the second controller. The second controller, in response to the second trigger signal, outputs a third control signal at a first potential. The second frequency divider, in response to the third control signal at the first potential, divides the first oscillation signal, ensuring that both the first and third frequency dividers divide the first oscillation signal simultaneously during both stages. Consequently, the fourth frequency-divided signal (derived from the third frequency divider's division of the first oscillation signal) is synchronized with the first frequency-divided signal (derived from the first frequency divider's division of the first oscillation signal). The fourth frequency-divided signal must be synchronized with the first frequency-divided signal; otherwise, the fourth RF signal will mix with the fourth frequency-divided signal, resulting in an incorrect fourth analog baseband signal.

[0030] In an exemplary embodiment, the third frequency divider is reset in response to the third control signal at the second potential, and the reset of the third frequency divider is between the frequency division of the second oscillation signal by the third frequency divider and the frequency division of the first oscillation signal by the third frequency divider.

[0031] Understandably, the third frequency divider is reset in response to the third control signal at the second potential. This reset occurs between the third frequency divider's division of the second oscillation signal and its division of the first oscillation signal. The mixing of the fourth RF signal and the fourth divided signal must be performed strictly according to the timing sequence; otherwise, the resulting fourth analog baseband signal will not have the correct frequency. Therefore, the timing of the fourth divided signal must be strictly guaranteed. Between switching from dividing the second oscillation signal to dividing the first oscillation signal, the third frequency divider needs to be reset, and then the third frequency divider must be controlled according to the correct timing sequence to divide the first oscillation signal.

[0032] Secondly, embodiments of this application also provide an electronic device, the electronic device including a processor and the receiver described above, wherein the data processor is coupled to the receiver. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this application or the background art, the accompanying drawings used in the embodiments of this application or the background art will be described below.

[0034] Figure 1 This is a functional architecture diagram of the electronic device disclosed in the embodiments of this application;

[0035] Figure 2 This is a schematic diagram of the first functional structure of the receiver disclosed in the embodiments of this application;

[0036] Figure 3 for Figure 2 The diagram shows a first specific circuit structure of the receiver.

[0037] Figure 4 for Figure 2 The diagram shows a second specific circuit structure of the receiver.

[0038] Figure 5 for Figure 2 The diagram shows a third specific circuit structure of the receiver.

[0039] Figure 6 for Figure 2 The diagram shows the fourth specific circuit structure of the receiver.

[0040] Figure 7 for Figure 2 The diagram shows the fifth specific circuit structure of the receiver.

[0041] Figure 8 This is a schematic diagram of a second functional structure of the receiver disclosed in an embodiment of this application;

[0042] Figure 9 This is a first timing diagram of the first control signal output by the first controller disclosed in an embodiment of this application;

[0043] Figure 10 This is a second timing diagram of the first control signal output by the first controller disclosed in the embodiments of this application;

[0044] Figure 11 This is a schematic diagram of the third functional structure of the receiver disclosed in the embodiments of this application;

[0045] Figure 12 This is a timing diagram of the first oscillation signal and the third frequency division signal;

[0046] Figure 13 for Figure 11 The diagram shows a first specific circuit structure of the receiver.

[0047] Figure 14 for Figure 13 The diagram shows the timing sequence of the signals received and output by the first controller.

[0048] Figure 15 for Figure 13 The diagram shows the signal flow of the first controller during the synchronization phase.

[0049] Figure 16 for Figure 13 The diagram shows the signal flow of the first controller during the switching preparation phase, reset phase, and third frequency division phase.

[0050] Figure 17 for Figure 13 The diagram shows the signal flow of the first controller during the reset phase and the second frequency division phase.

[0051] Figure 18 for Figure 11 The diagram shows a second specific circuit structure of the receiver.

[0052] Figure 19 This is a schematic diagram of the third functional structure of the receiver disclosed in the embodiments of this application;

[0053] Figure 20 for Figure 19 The diagram shows the specific circuit structure of the receiver.

[0054] Figure 21 This is a schematic diagram of the fourth functional structure of the receiver disclosed in the embodiments of this application;

[0055] Figure 22 This is a timing diagram of the second control signal output by the first controller disclosed in an embodiment of this application;

[0056] Figure 23 for Figure 21 The diagram shows the specific circuit structure of the receiver.

[0057] Figure 24 for Figure 23 The diagram shows the timing sequence of the signals received and output by the first controller.

[0058] Figure 25 This is a schematic diagram of the fifth functional structure of the receiver disclosed in the embodiments of this application;

[0059] Figure 26 This is a timing diagram of the third control signal output by the second controller disclosed in an embodiment of this application;

[0060] Figure 27 for Figure 25 The diagram shows the specific circuit structure of the receiver.

[0061] Figure 28 for Figure 25 The diagram shows the timing sequence of the signals received and output by the second controller. Detailed Implementation

[0062] In the description of the embodiments of this application, it should be noted that, unless otherwise explicitly specified and limited, the term "coupling" refers to electrical connection. Electrical connection includes direct electrical connection and indirect electrical connection. Direct electrical connection means that when two components are in contact or connected by a wire, electrical signals can be transmitted between the two components. For example, A and B are directly electrically connected, either in contact or connected by a wire, allowing electrical signals from A to be transmitted to B, and vice versa. Indirect electrical connection means that two components are electrically connected through other components, allowing electrical signals to be transmitted between the two components. For example, A and B are indirectly electrically connected through C, where changes in the current or voltage of A can affect changes in the current or voltage of C, and changes in the current or voltage of C can affect changes in the current or voltage of B. This situation is called an indirect electrical connection between A and B.

[0063] In the embodiments of this application, the terms "first," "second," "third," and "fourth" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first," "second," "third," and "fourth" may explicitly or implicitly include one or more of that feature.

[0064] Unless otherwise specified, the terms "connection" and "linkage" used in this application include both direct and indirect connections. Directional terms used in this application, such as "up," "down," "front," "back," "left," "right," "inner," and "outer," are merely for reference to the accompanying drawings. Therefore, the use of directional terms is for better and clearer explanation and understanding of this application, and does not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0065] In the embodiments of this application, "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0066] References or phrases such as "some embodiments" described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, phrases such as "in some embodiments," "in other embodiments," "in still others," "in other still others," etc., appearing in different parts of this specification do not necessarily refer to the same embodiments, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized. The term "a plurality of" means at least two.

[0067] It is understood that the specific embodiments described herein are merely illustrative of related embodiments and not intended to limit the scope of the embodiments. Furthermore, it should be noted that, for ease of description, the accompanying drawings only show the parts relevant to the embodiments. It should be understood that, unless otherwise specified, the embodiments and features described in this application can be combined with each other.

[0068] The embodiments of this application are described below with reference to the accompanying drawings.

[0069] This application provides a receiver and an electronic device.

[0070] The receiver provided in this application is used in electronic devices. Indicatively, the electronic devices in this application embodiment can be mobile phones, laptops, tablets, smart TVs, augmented reality (AR) devices, virtual reality (VR) devices, artificial intelligence (AI) devices, smart wearable devices (e.g., smartwatches, smart bracelets, smart glasses), in-vehicle devices, smart home devices, smart city devices, terminal devices, and other electronic products. The electronic devices can also be handheld devices with wireless communication capabilities, computing devices or other processing devices connected to a wireless modem, in-vehicle devices (e.g., vehicle radar), electronic devices in 5G networks, or electronic devices in future evolved Public Land Mobile Networks (PLMNs), etc. This application embodiment does not impose any special limitations on the specific type of electronic device.

[0071] Please see Figure 1 , Figure 1This is a functional architecture diagram of an electronic device disclosed in an embodiment of this application, using a mobile phone as an example. Electronic device 1 may include a processor, an external memory interface, internal memory, a Universal Serial Bus (USB) interface, a charging management module, a power management module, a battery, a receiver, a transmitter, an audio module, a sensor module, buttons, a motor, an indicator, a camera, a display screen, and a Subscriber Identification Module (SIM) card interface, etc. The audio module may include a speaker, a receiver, a microphone, and a headphone jack.

[0072] It is understood that the functional architecture illustrated in the embodiments of this application does not constitute a specific limitation on the electronic device 1. In other embodiments of this application, the electronic device 1 may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. For example, the electronic device 1 may not include a USB interface, but may include a Lightning interface, and the illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0073] A processor may include one or more processing units, such as an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural network processing unit (NPU). These different processing units may be independent devices or integrated into one or more processors.

[0074] Wireless communication functionality in electronic devices can be achieved through a receiver and a transmitter. The receiver and transmitter can be integrated into one or more devices, collectively known as a transceiver. The receiver receives electromagnetic wave signals and performs filtering, amplification, and demodulation on the received waves. A processor is coupled to both the receiver and the transmitter, processing the signal output from the receiver to demodulate the desired data. The transmitter modulates the low-frequency baseband signal to be transmitted into a mid-to-high frequency signal and then converts the mid-to-high frequency signal into the corresponding electromagnetic wave signal for transmission.

[0075] In an exemplary embodiment, the receiver disclosed in this application is an orthogonal receiver.

[0076] The receiver and transmitter can provide wireless communication solutions for electronic devices 1, including Wireless Local Area Networks (WLAN), Wireless Fidelity (Wi-Fi), Bluetooth (BT), Ultra Wide Band (UWB), Global Navigation Satellite System (GNSS), Near Field Communication (NFC), and Infrared (IR) technologies.

[0077] In some embodiments, electronic device 1 is coupled to a receiver and to a transmitter, enabling electronic device 1 to communicate with a network and other electronic devices via wireless communication technology. This wireless communication technology may include Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Wideband Code Division Multiple Access (WCDMA), Time-Division Code Division Multiple Access (TDSCDMA), Long Term Evolution (LTE), BT, GNSS, WLAN, NFC, FM, IR, etc. The GNSS may include Global Positioning System (GPS), Global Navigation Satellite System (GLONASS), BeiDou Navigation Satellite System (BDS), Quasi-Zenith Satellite System (QZSS), and / or Satellite Based Augmentation Systems (SBAS).

[0078] Please see Figure 2 , Figure 2This is a schematic diagram of the first functional structure of the receiver disclosed in this application. The receiver 10 includes a first antenna 11, a first signal receiving circuit 12, a first analog-to-digital converter 13, a baseband unit 14, a first frequency divider 15, a first oscillator 16, a second oscillator 17, a first switch 21, and a second switch 22. The first signal receiving circuit 12 is coupled to the first antenna 11, the first analog-to-digital converter 13, and the first frequency divider 15, respectively. The first analog-to-digital converter 13 is also coupled to the baseband unit 14. The first switch 21 is coupled between the first oscillator 16 and the first frequency divider 15, and a first node N1 is formed between the first switch 21 and the first frequency divider 15. The second switch 22 is coupled between the first node N1 between the first switch 21 and the first frequency divider 15 and the second oscillator 17.

[0079] The first antenna 11 is used to receive a first electromagnetic wave signal, convert the first electromagnetic wave signal into a first radio frequency (RF) signal, and transmit the first RF signal to the first signal receiving circuit 12. The first antenna 11 is also used to receive a second electromagnetic wave signal, convert the second electromagnetic wave signal into a second RF signal, and transmit the second RF signal to the first signal receiving circuit 12. The first electromagnetic wave signal is a Wi-Fi signal, the second electromagnetic wave signal is a BitTorrent (BT) signal, and both the first and second RF signals are analog electrical signals. The Wi-Fi signal includes an Aggregated Media Access Control Protocol Data Unit (A-MPDU).

[0080] When the first switch 21 is on, the first oscillator 16 is coupled to the first frequency divider 15. When the first switch 21 is off, the first oscillator 16 is not coupled to the first frequency divider 15. When the second switch 22 is on, the second oscillator 17 is coupled to the first frequency divider 15. When the second switch 22 is off, the second oscillator 17 is not coupled to the first frequency divider 15. Specifically, the first switch 21 and the second switch 22 are not on simultaneously; that is, the first frequency divider 15 selectively couples with either the first oscillator 16 or the second oscillator 17.

[0081] The first oscillator 16 generates a first oscillation signal and transmits it to the first frequency divider 15 via the first switch 21. The first frequency divider 15 divides the first oscillation signal to form a first frequency-divided signal and transmits the first frequency-divided signal to the first signal receiving circuit 12. The second oscillator 17 generates a second oscillation signal and transmits it to the first frequency divider 15 via the second switch 22. The first frequency divider 15 divides the second oscillation signal to form a second frequency-divided signal and transmits the second frequency-divided signal to the first signal receiving circuit 12.

[0082] Specifically, when the first antenna 11 receives the first electromagnetic wave signal, the first frequency divider 15 outputs the first frequency-divided signal (after dividing the first oscillation signal) to the first signal receiving circuit 12. When the first antenna 11 receives the second electromagnetic wave signal, the first frequency divider 15 outputs the second frequency-divided signal (after dividing the second oscillation signal) to the first signal receiving circuit 12.

[0083] It should be noted that in this application, the first frequency divider 15 divides the first oscillation signal to form two first frequency-divided signals. The two first frequency-divided signals have the same frequency but are 90 degrees out of phase, and both frequencies are half the frequency of the first oscillation signal. Both first frequency-divided signals are output to the first signal receiving circuit 12. Similarly, the first frequency divider 15 divides the second oscillation signal to form two second frequency-divided signals. The two second frequency-divided signals have the same frequency but are 90 degrees out of phase, and both frequencies are half the frequency of the second oscillation signal. Both second frequency-divided signals are output to the first signal receiving circuit 12.

[0084] The first signal receiving circuit 12 mixes the first radio frequency signal with the first frequency divider signal to form a first analog baseband signal, and transmits the first analog baseband signal to the first analog-to-digital converter 13. The first analog-to-digital converter 13 receives the first analog baseband signal, converts the first analog baseband signal into a corresponding first digital baseband signal, and transmits the first digital baseband signal to the baseband unit 14. The baseband unit 14 is responsible for the modulation, demodulation, encoding, and decoding of the digital baseband signal.

[0085] The first signal receiving circuit 12 is further configured to mix the second radio frequency signal with the second frequency division signal to form a second analog baseband signal, and the first signal receiving circuit 12 transmits the second analog baseband signal to the first analog-to-digital converter 13. The first analog-to-digital converter 13 is configured to receive the second analog baseband signal, convert the second analog baseband signal into a corresponding second digital baseband signal, and transmit the second digital baseband signal to the baseband unit 14.

[0086] It should be noted that the first radio frequency signal has a relatively high frequency, making it difficult for the first signal receiving circuit 12 to filter it. Therefore, the first radio frequency signal needs to be mixed with a first frequency divider signal to form a lower-frequency first analog baseband signal. The first signal receiving circuit 12 also performs filtering on the first analog baseband signal. Similarly, the second radio frequency signal has a relatively high frequency, making it difficult for the first signal receiving circuit 12 to filter it. Therefore, the second radio frequency signal needs to be mixed with a second frequency divider signal to form a lower-frequency second analog baseband signal. The first signal receiving circuit 12 also performs filtering on the second analog baseband signal. This process of reducing the frequency of the radio frequency signals by the first signal receiving circuit 12 is also known as down-conversion.

[0087] In an exemplary embodiment, the first electromagnetic wave signal includes an Aggregated Media Intervention Control Protocol Data Unit (A-MPDU), and the second electromagnetic wave signal is a BitTorrent (BT) signal. The time required to receive the A-MPDU exceeds the time required for the BT to receive one piece of information. During the A-MPDU reception process, the BT occupies the receiver 10, and the A-MPDU reception is not yet complete. After the receiver 10 finishes receiving the BT signal, it continues to receive the remaining A-MPDU. Therefore, there is no need to retransmit the A-MPDU, thereby improving the efficiency of A-MPDU reception.

[0088] It should be noted that during the A-MPDU reception process, the BT occupies the receiver 10, and then the receiver 10 continues to receive A-MPDUs, which may result in the loss of some A-MPDUs. After the receiver 10 finishes receiving A-MPDUs, it re-receives the lost A-MPDUs. Compared to re-receiving the complete A-MPDU, receiving only the lost A-MPDUs saves a lot of time, thereby improving the efficiency of A-MPDU reception.

[0089] Understandably, if a first signal receiving circuit 12 requires two frequency dividers—one to divide the first oscillation signal and the other to divide the second oscillation signal—it would occupy more area. Furthermore, while dividing the second oscillation signal, the division of the first oscillation signal must continue, increasing power consumption. For example, for a 2G receiver, an additional frequency divider would increase power consumption by 10mA, and for a 5G receiver, by 20mA. In this application, a first signal receiving circuit 12 only needs one first frequency divider 15, which can switch between dividing the first and second oscillation signals, reducing overall cost, area occupied, and power consumption.

[0090] Please see Figure 3 , Figure 3 for Figure 2The diagram shows a first specific circuit structure of the receiver, where LNA is an abbreviation for Low Noise Amplifier, ADC is an abbreviation for Analog to Digital Converter, and 1 / 2 is a frequency divider. The first signal receiving circuit 12 includes a first low-noise amplifier 121, a first mixer 122, and a first filter 123. The first low-noise amplifier 121 is coupled between the first antenna 11 and the first mixer 122, and the first filter 123 is coupled between the first mixer 122 and the first analog-to-digital converter 13. The first mixer 122 is also coupled to the first frequency divider 15. The first low-noise amplifier 121 receives the first radio frequency signal output from the first antenna 11, amplifies the first radio frequency signal, and transmits the amplified first radio frequency signal to the first mixer 122. The first mixer 122 receives the first frequency division signal output by the first frequency divider 15. The first mixer 122 mixes the first radio frequency signal with the first frequency division signal to obtain the first analog baseband signal, and transmits the first analog baseband signal to the first filter 123. The first filter 123 filters the first analog baseband signal and transmits the filtered first analog baseband signal to the first analog-to-digital converter 13.

[0091] The first low-noise amplifier 121 receives the second radio frequency signal output from the first antenna 11, amplifies the second radio frequency signal, and transmits the amplified second radio frequency signal to the first mixer 122. The first mixer 122 receives the second divided signal output from the first frequency divider 15, mixes the second radio frequency signal with the second divided signal to obtain a second analog baseband signal, and transmits the second analog baseband signal to the first filter 123. The first filter 123 filters the second analog baseband signal and transmits the filtered second analog baseband signal to the first analog-to-digital converter 13.

[0092] In the exemplary embodiment, both the first switch 21 and the second switch 22 are single-pole single-throw switches. The first switch 21 can be composed of a transistor or a MOSFET, and the second switch 22 can be composed of a transistor or a MOSFET. The first filter 123 can be a surface acoustic wave (SAW) filter.

[0093] Please see Figure 4 , Figure 4 for Figure 2 The diagram shows a second specific circuit structure of the receiver, where VAG is an abbreviation for Variable Gain Amplifier. Figure 4 The receiver 10 shown is Figure 3The difference in the receiver 10 shown is that the first signal receiving circuit 12 further includes a first variable gain amplifier 124.

[0094] Specifically, the first variable gain amplifier 124 is coupled between the first filter 123 and the first analog-to-digital converter 13. The first filter 123 outputs the filtered first analog baseband signal to the first variable gain amplifier 124, which amplifies the first analog baseband signal and outputs the amplified signal to the first analog-to-digital converter 13. The first filter 123 also outputs the filtered second analog baseband signal to the first variable gain amplifier 124, which amplifies the second analog baseband signal and outputs it to the first analog-to-digital converter 13.

[0095] Understandably, the first analog-to-digital converter 13 has a limited operating voltage range, requiring the received first analog baseband signal and second analog baseband signal to be within a preset voltage range. The first variable gain amplifier 124 is used to amplify the voltage of the first analog baseband signal and the voltage of the second analog baseband signal to the preset voltage range, and the amplification gain of the first variable gain amplifier 124 is adjustable.

[0096] Please see Figure 5 , Figure 5 for Figure 2 The diagram shows a third specific circuit structure of the receiver, where MN is an abbreviation for Matching Networks. Figure 5 The receiver 10 shown is Figure 3 The difference in the receiver 10 shown is that the receiver 10 also includes a first impedance matching network 19.

[0097] Specifically, the first impedance matching network 19 is coupled between the first antenna 11 and the first low-noise amplifier 121. The first impedance matching network 19 is used to make the impedance between the first antenna 11 and the first signal receiving circuit 12 matched, so as to reduce signal reflection and loss.

[0098] Please see Figure 6 , Figure 6 for Figure 2 The diagram shows the fourth specific circuit structure of the receiver. Figure 6 The receiver 10 shown is Figure 3 The difference in the receiver 10 shown is that the receiver 10 also includes a first amplifier 23.

[0099] Specifically, the first amplifier 23 is coupled between the first node N1 and the first frequency divider 15. The first amplifier 23 receives the first oscillation signal output from the first oscillator 16, amplifies the first oscillation signal, and outputs the amplified first oscillation signal to the first frequency divider 15. The first amplifier 23 also receives the second oscillation signal output from the second oscillator 17, amplifies the second oscillation signal, and outputs the amplified second oscillation signal to the first frequency divider 15.

[0100] Please see Figure 7 , Figure 7 for Figure 2 The diagram shows the fifth specific circuit structure of the receiver. Figure 7 The receiver 10 shown is Figure 3 The difference in the receiver 10 shown is that it also includes a first variable gain amplifier 124, a first impedance matching network 19, and a first amplifier 23. For a detailed description of the first variable gain amplifier 124, please refer to... Figure 4 The relevant descriptions of receiver 10 shown will not be repeated here. For a detailed description of the first impedance matching network 19, please refer to [link to relevant documentation]. Figure 5 The relevant descriptions of the receiver 10 shown will not be repeated here. For a detailed description of the first amplifier 23, please refer to [link to relevant documentation]. Figure 6 The relevant descriptions of the receiver 10 shown will not be repeated here.

[0101] Please see Figure 8 , Figure 8 This is a schematic diagram of a second functional structure of the receiver disclosed in this application. The difference between the receiver with the second functional structure and the receiver with the first functional structure is that the receiver 10 further includes a first controller 18.

[0102] Specifically, the first controller 18 is coupled to the first frequency divider 15, and the first controller 18 is used to output a first control signal to the first frequency divider 15. The first control signal is a pulse signal with a first potential and a second potential. The first potential is not equal to the second potential; that is, the first potential is greater than or less than the second potential. In this application, the example is always given with the first potential greater than the second potential.

[0103] The first frequency divider 15 divides the first oscillation signal or the second oscillation signal in response to a first control signal at a first potential. For example, when the first oscillator 16 outputs the first oscillation signal to the first frequency divider 15 through the first switch 21, the first frequency divider 15 divides the first oscillation signal in response to the first control signal at the first potential. When the second oscillator 17 outputs the second oscillation signal to the first frequency divider 15 through the second switch 22, the first frequency divider 15 divides the second oscillation signal in response to the first control signal at the first potential. The first frequency divider 15 is reset in response to the first control signal at the second potential, and the reset state of the first frequency divider 15 is between the frequency division of the second oscillation signal by the first frequency divider 15 and the frequency division of the first oscillation signal by the first frequency divider 15.

[0104] For the specific circuit structure of the receiver 10 with the second functional structure, please refer to [link / reference needed]. Figures 3 to 7 The relevant descriptions will not be repeated here.

[0105] Please see Figure 9 , Figure 9 This is a first timing diagram of the first control signal output by the first controller disclosed in an embodiment of this application. The first control signal Q1 includes a first frequency division stage t1, a second frequency division stage t2, a third frequency division stage t3, and a reset stage t5. In the first frequency division stage t1, the first antenna 11 receives a first electromagnetic wave signal, and the first controller 18 outputs the first control signal Q1 at a first potential to the first frequency divider 15. The first frequency divider 15 divides the first oscillation signal in response to the first control signal Q1 at the first potential. In the second frequency division stage t2 after the first frequency division stage t1, the first antenna 11 receives a second electromagnetic wave signal, and the first controller 18 outputs the first control signal Q1 at a first potential to the first frequency divider 15. The first frequency divider 15 divides the second oscillation signal in response to the first control signal Q1 at the first potential. In the third frequency division stage t3 after the second frequency division stage t2, the first antenna 11 receives the first electromagnetic wave signal, and the first controller 18 outputs the first control signal Q1 of the first potential to the first frequency divider 15. The first frequency divider 15 divides the first oscillation signal in response to the first control signal Q1 of the first potential.

[0106] That is, when receiver 10 receives the first electromagnetic wave signal (first frequency division stage t1), the second electromagnetic wave signal will occupy receiver 10 (second frequency division stage t2). After receiver 10 finishes receiving the second electromagnetic wave signal (after the second frequency division stage t2 ends), receiver 10 continues to receive the first electromagnetic wave signal (third frequency division stage t3).

[0107] In this embodiment, the reset of the first frequency divider 15 occurs between the first frequency divider 15's frequency division of the second oscillation signal and its frequency division of the first oscillation signal. This means that the first frequency divider 15 needs to be reset when switching from frequency division of the second oscillation signal to frequency division of the first oscillation signal. Specifically, during the reset phase t5 between the second frequency division phase t2 and the third frequency division phase t3, the first controller 18 outputs a first control signal Q1 at a second potential to the first frequency divider 15, and the first frequency divider 15 resets in response to the first control signal Q1 at the second potential. The reset can be understood as the first frequency divider 15 becoming inactive, effectively shutting down the first frequency divider 15.

[0108] Understandably, the mixing of the first radio frequency signal and the first frequency divider signal must be performed strictly according to the timing sequence; otherwise, the first analog baseband signal with the correct frequency cannot be obtained after mixing. Therefore, the timing sequence of the first frequency divider signal must be strictly guaranteed. Between switching from dividing the second oscillation signal to dividing the first oscillation signal, the first frequency divider 15 needs to be reset, and then the first frequency divider 15 should be controlled to divide the first oscillation signal according to the correct timing sequence.

[0109] Please see Figure 10 , Figure 10 This is a second timing diagram illustrating the first control signal output by the first controller disclosed in an embodiment of this application. The first control signal Q1 further includes a reset phase t4, which is located between the first frequency division phase t1 and the second frequency division phase t2. In the reset phase t4, the first controller 18 outputs the first control signal Q1 at a second potential to the first frequency divider 15, and the first frequency divider 15 resets in response to the first control signal Q1 at the second potential. The reset can be understood as the first frequency divider 15 not working, and the first frequency divider 15 being turned off.

[0110] Understandably, without a reset phase t4, the first frequency divider 15 would directly switch from dividing the first oscillation signal to dividing the second oscillation signal. In this case, the first oscillation signal would act as an interference signal, and starting from the second frequency division phase t2, the second frequency divider signal would have noise after dividing the second oscillation signal. Therefore, to eliminate the influence of the first oscillation signal, a reset phase t4 is set after the first frequency division phase t1 ends to turn off the first frequency divider 15 before starting the second frequency division phase t2.

[0111] It should be noted that the reset phase t4 is optional. Whether or not there is a reset phase t4, that is, whether the first frequency divider 15 is turned off from the first frequency division phase t1 to the second frequency division phase t2, does not affect the first frequency divider 15 from dividing the second oscillation signal, nor does it affect the first signal receiving circuit 12 from mixing the second radio frequency signal with the second frequency divided signal.

[0112] Please see Figure 11 , Figure 11 This is a schematic diagram of the third functional structure of the receiver disclosed in the embodiments of this application. The difference between the receiver with the third functional structure and the receiver with the second functional structure is that the receiver 10 with the third functional structure also includes a second antenna 31, a second signal receiving circuit 32, a second analog-to-digital converter 33, and a second frequency divider 35.

[0113] Specifically, the second signal receiving circuit 32 is coupled to the second antenna 31, the second analog-to-digital converter 33, and the second frequency divider 35, respectively. The second analog-to-digital converter 33 is also coupled to the baseband unit 14. A second node N2 exists between the second signal receiving circuit 32 and the second frequency divider 35, and a third node N3 exists between the first oscillator 16 and the first switch 21. The first controller 18 is coupled to the second node N2 between the second signal receiving circuit 32 and the second frequency divider 35, meaning the first controller 18 is coupled to both the second signal receiving circuit 32 and the second frequency divider 35. The second frequency divider 35 is also coupled to the third node N3 between the first oscillator 16 and the first switch 21, meaning the second frequency divider 35 is also coupled to both the first oscillator 16 and the first switch 21.

[0114] The second antenna 31 is used to receive the first electromagnetic wave signal, convert the first electromagnetic wave signal into a third radio frequency signal, and output the third radio frequency signal to the second signal receiving circuit 32. The third radio frequency signal is an analog electrical signal.

[0115] The first oscillator 16 generates a first oscillation signal and outputs it to the second frequency divider 35. The second frequency divider 35 divides the first oscillation signal to form a third frequency-divided signal and outputs the third frequency-divided signal to the second signal receiving circuit 32. Specifically, when the second antenna 31 receives the first electromagnetic wave signal, the second frequency divider 35 outputs the third frequency-divided signal (formed by dividing the first oscillation signal) to the second signal receiving circuit 32.

[0116] The second signal receiving circuit 32 mixes the third radio frequency signal with the third frequency divider signal to form a third analog baseband signal, and transmits the third analog baseband signal to the second analog-to-digital converter 33. The second analog-to-digital converter 33 receives the third analog baseband signal, converts the third analog baseband signal into a corresponding third digital baseband signal, and transmits the third digital baseband signal to the baseband unit 14.

[0117] In this embodiment, the second antenna 31 only receives the first electromagnetic wave signal. The second antenna 31 switches from receiving the first electromagnetic wave signal to receiving the second electromagnetic wave signal, and then switches back to receiving the first electromagnetic wave signal. That is, in the first frequency division stage t1, both the first frequency divider 15 and the second frequency divider 35 divide the first oscillation signal. In the reset stage t4, the first frequency divider 15 is turned off, and the second frequency divider 35 divides the first oscillation signal. In the second frequency division stage t2, the first frequency divider 15 divides the second oscillation signal, and the second frequency divider 35 divides the first oscillation signal. In the reset stage t5, the first frequency divider 15 is turned off, and the second frequency divider 35 divides the first oscillation signal. In the third frequency division stage t3, both the first frequency divider 15 and the second frequency divider 35 divide the first oscillation signal.

[0118] Understandably, the first electromagnetic wave signal is received simultaneously by two antennas, namely a first antenna 11 and a second antenna 31. The first oscillation signal is simultaneously divided by two frequency dividers, namely a first frequency divider 15 and a second frequency divider 35. This increases the rate at which the receiver 10 receives the first electromagnetic wave signal, saving time.

[0119] It should be noted that the third radio frequency signal has a relatively high frequency, making it difficult for the second signal receiving circuit 32 to filter the third radio frequency signal. Therefore, it is necessary to mix the third radio frequency signal with the third frequency divider signal to form a third analog baseband signal with a lower frequency. The second signal receiving circuit 32 also performs filtering on the third analog baseband signal.

[0120] It should be noted that you should refer to [link / reference]. Figure 12 , Figure 12 This is a timing diagram of the first oscillation signal and the third frequency-divided signal. The second frequency divider 35 divides the first oscillation signal LO into two third frequency-divided signals DIV. Both third frequency-divided signals DIV are output to the second signal receiving circuit 32. The two third frequency-divided signals DIV have the same frequency and are 90 degrees out of phase. The frequency of each third frequency-divided signal DIV is half the frequency of the first oscillation signal LO. The second frequency divider 35 outputs one of the two third frequency-divided signals DIV as the first trigger signal to the first controller 18.

[0121] The timing sequence of the first oscillation signal and the first frequency division signal is also as follows: Figure 12 As shown, the timing of the second oscillation signal and the second frequency division signal is also...

[0122] The second frequency divider 35 outputs the first oscillation signal after frequency division as the first trigger signal to the first controller 18. During the first frequency division stage t1 and the third frequency division stage t3, the first controller 18 responds to the first trigger signal by outputting a first control signal with a first potential.

[0123] Understandably, during the first frequency division phase t1 and the third frequency division phase t3, the first antenna 11 and the second antenna 31 simultaneously receive the first electromagnetic wave signal, requiring the first frequency divider 15 and the second frequency divider 35 to simultaneously divide the first oscillation signal. At the beginning of either the first frequency division phase t1 or the third frequency division phase t3, the second frequency divider 35 divides the first oscillation signal and transmits the divided first oscillation signal as the first trigger signal to the first controller 18. The first controller 18 responds to the first trigger signal by outputting a first control signal at a first potential. The first frequency divider 15 responds to the first control signal at the first potential by dividing the first oscillation signal, so that during the first frequency division phase t1 and the third frequency division phase t3, the first frequency divider 15 and the second frequency divider 35 simultaneously divide the first oscillation signal, thus ensuring that the first frequency-divided signal after the first frequency divider 15 divides the first oscillation signal and the third frequency-divided signal after the second frequency divider 35 divide the first oscillation signal are synchronized. It should be noted that the third frequency divider signal needs to be synchronized with the first frequency divider signal; otherwise, the first radio frequency signal will not be able to obtain the first analog baseband signal with the correct frequency after mixing with the first frequency divider signal.

[0124] Please see Figure 13 , Figure 13 for Figure 11 The diagram shows a first specific circuit structure of the receiver. The second signal receiving circuit 32 includes a second low-noise amplifier 321, a second mixer 322, and a second filter 323. The second low-noise amplifier 321 is coupled between the second antenna 31 and the second mixer 322, and the second filter 323 is coupled between the second mixer 322 and the second analog-to-digital converter 33. The second mixer 322 is also coupled to a second frequency divider 35. The second low-noise amplifier 321 receives the third radio frequency signal output from the second antenna 31, amplifies the third radio frequency signal, and transmits the amplified third radio frequency signal to the second mixer 322. The second mixer 322 receives the third frequency-divided signal transmitted by the second frequency divider 35, mixes the third radio frequency signal with the third frequency-divided signal to obtain a third analog baseband signal, and transmits the third analog baseband signal to the second filter 323. The second filter 323 filters the third analog baseband signal and transmits the filtered third analog baseband signal to the second analog-to-digital converter 33.

[0125] The first controller 18 includes a first multiplexer 181, a second multiplexer 182, and a first flip-flop 183. The first multiplexer 181 includes a first input terminal 181a, a second input terminal 181b, a first selection input terminal 181c, and a first output terminal 181d. The second multiplexer 182 includes a third input terminal 182a, a fourth input terminal 182b, a second selection input terminal 182c, and a second output terminal 182d. The first flip-flop 183 includes a first clock input terminal 183a, a first data input terminal 183b, and a first data output terminal 183c. The first input terminal 181a is coupled to the fourth node N4 and receives a Multiple-Receive-Multiple-Transmit (MIMO) signal. The second input terminal 181b receives a first enable signal EN1. The first selection input terminal 181c receives a first selection signal SEC1. The first output terminal 181d is coupled to the first data input terminal 183b. The first clock input terminal 183a is coupled to the second node N2 between the second frequency divider 35 and the second signal receiving circuit 32. The first data output terminal 183c is coupled to the third input terminal 182a. The fourth input terminal 182b receives the second enable signal EN2. The second selection input terminal 182c receives the second selection signal SEC2. The second output terminal 182d is coupled to the first frequency divider 15.

[0126] The second frequency divider 35 is also coupled to the fourth node N4, and the second frequency divider 35 receives multiple-in-multiple-out (MIMO) signals. The second frequency divider 35 divides the first oscillation signal in response to the MIMO signal at the first potential.

[0127] Among them, the multiple-in-multiple-out (MIMO) signal, the first enable signal EN1, the first selection signal SEC1, the second enable signal EN2, and the second selection signal SEC2 are all output by the digital baseband (DBB) processor. The signal output from the second output terminal 182d to the first frequency divider 15 is the first control signal Q1 output from the first controller 18 to the first frequency divider 15.

[0128] In this embodiment, the first multiplexer 181 selectively turns on the first input terminal 181a and the first output terminal 181d or the second input terminal 181b and the first output terminal 181d in response to the first selection signal SEC1. Specifically, when the first selection signal SEC1 is at the second potential, the first multiplexer 181 turns on the first input terminal 181a and the first output terminal 181d in response to the first selection signal SEC1, and the first output terminal 181d of the first multiplexer 181 outputs a multiple-input multiple-output (MIMO) signal to the first data input terminal 183b of the first flip-flop 183. When the first selection signal SEC1 is at the first potential, the first multiplexer 181 turns on the second input terminal 181b and the first output terminal 181d in response to the first selection signal SEC1, and the first output terminal 181d of the first multiplexer 181 outputs a second enable signal EN2 to the first data input terminal 183b of the first flip-flop 183.

[0129] The second multiplexer 182 selectively turns on the third input terminal 182a and the second output terminal 182d, or turns on the fourth input terminal 182b and the second output terminal 182d, in response to the second selection signal SEC2. Specifically, when the second selection signal SEC2 is at the second potential, the second multiplexer 182 turns on the third input terminal 182a and the second output terminal 182d in response to the second selection signal SEC2. When the second selection signal SEC2 is at the first potential, the second multiplexer 182 turns on the fourth input terminal 182b and the second output terminal 182d in response to the second selection signal SEC2, and the second output terminal 182d of the second multiplexer 182 outputs the second enable signal EN2 to the first frequency divider 15.

[0130] The first trigger 183 transmits the potential of the first data input terminal 183b to the first data output terminal 183c in response to a change in the potential of the first clock input terminal 183a. The potential of the first clock input terminal 183a is controlled by a first trigger signal. The change in the potential of the first clock input terminal 183a can be the instant when the potential of the first clock input terminal 183a changes from a first potential to a second potential, or the instant when the potential of the first clock input terminal 183a changes from a second potential to a first potential. In this embodiment, the example of the change in the potential of the first clock input terminal 183a being the instant when the potential of the first clock input terminal 183a changes from a first potential to a second potential is used for illustration.

[0131] Please see Figure 14 , Figure 14 for Figure 13 The diagram shows the timing of the signals received and output by the first controller. The first frequency division stage t1 includes a synchronization stage t11 and a switching preparation stage t12. The switching preparation stage t12 follows the synchronization stage t11, and the reset stage t4 follows the switching preparation stage t12.

[0132] Please see Figure 14 and Figure 15 , Figure 15 for Figure 13 The diagram shows the signal flow of the first controller during the synchronization phase. Figure 15 The dashed arrows in the diagram indicate the signal flow within the first controller 18 during the synchronization phase t11.

[0133] During the synchronization phase t11, the MIMO signal is at the first potential, the first enable signal EN1 is at the first potential, the first selection signal SEC1 is at the second potential, the second enable signal EN2 is at the second potential, and the second selection signal SEC2 is at the second potential. With the first selection signal SEC1 at the second potential, the first multiplexer 181 turns on the first input terminal 181a and the first output terminal 181d. The potentials of the first input terminal 181a, the first output terminal 181d, and the first data input terminal 183b are the same. The first flip-flop 183, in response to the change in the potential of the first clock input terminal 183a, transmits the potential of the first data input terminal 183b to the first data output terminal 183c. The potentials of the first data input terminal 183b and the first data output terminal 183c are the same as the potential of the third input terminal 182a. The second selection signal SEC2 is at the second potential. The second multiplexer 182 turns on the third input terminal 182a and the second output terminal 182d, and the potential of the third input terminal 182a is the same as the potential of the second output terminal 182d. That is, in the synchronization phase t11, the potential of the first control signal Q1 output by the first controller 18 is the same as the potential of the MIMO signal. Since the MIMO signal is at the first potential, the first controller 18 outputs the first control signal Q1 at the first potential to the first frequency divider 15.

[0134] During the synchronization phase t11, the second frequency divider 35 divides the first oscillation signal. The first frequency divider 15 outputs the divided third frequency signal as the first trigger signal to the first clock input terminal 183a of the first flip-flop 183, and the first data output terminal 183c of the first flip-flop 183 is at the first potential. The first data output terminal 183c, the third input terminal 182a, and the second output terminal 182d are connected, so the second output terminal 182d is at the first potential. The first switch 21 is turned on, and the first frequency divider 15 divides the first oscillation signal in response to the first control signal Q1 at the first potential.

[0135] Understandably, during the synchronization phase t11, while the second frequency divider 35 is dividing the first oscillation signal, the potential of the first potential MIMO signal is transmitted to the first frequency divider 15. The first frequency divider 15 then divides the first oscillation signal, so that the frequency division of the first oscillation signal by the first frequency divider 15 and the frequency division of the first oscillation signal by the second frequency divider 35 are performed synchronously. This helps to ensure that the third frequency division signal needs to be synchronized with the first frequency division signal.

[0136] Please see Figure 14 and Figure 16 , Figure 16 for Figure 13 The diagram shows the signal flow of the first controller during the switching preparation phase, the reset phase, and the third frequency division phase. Figure 16 The dashed arrows in the diagram indicate the signal flow within the first controller 18 during the switching preparation phase t12.

[0137] During the handover preparation phase t12, the MIMO (Multiple Receiver Multiple Transmitter) signal is at the first potential, the first enable signal EN1 is at the first potential, the first select signal SEC1 is at the first potential, the second enable signal EN2 is at the second potential, and the second select signal SEC2 is at the second potential. With the first select signal SEC1 at the first potential, the first multiplexer 181 turns on the second input terminal 181b and the first output terminal 181d. The potentials of the second input terminal 181b, the first output terminal 181d, and the first data input terminal 183b are the same. The first flip-flop 183, in response to a change in the potential of the first clock input terminal 183a, transmits the potential of the first data input terminal 183b to the first data output terminal 183c. The potentials of the first data input terminal 183b, the first data output terminal 183c, and the third input terminal 182a are the same. The second selection signal SEC2 is at the second potential. The second multiplexer 182 turns on the third input terminal 182a and the second output terminal 182d, and the potential of the third input terminal 182a is the same as the potential of the second output terminal 182d. That is, in the switching preparation stage t12, the potential of the first control signal Q1 output by the first controller 18 is the same as the potential of the first enable signal EN1. The first enable signal EN1 is at the first potential, so the first controller 18 outputs the first control signal Q1 at the first potential to the first frequency divider 15.

[0138] From the synchronization phase t11 to the switching preparation phase t12, the first multiplexer 181 switches from having its first input terminal 181a and first output terminal 181d connected to having its second input terminal 181b and first output terminal 181d connected. The potential of the first control signal Q1 output by the first controller 18 is the same as the potential of the first enable signal EN1. Both the first frequency divider 15 and the second frequency divider 35 divide the first oscillation signal.

[0139] Understandably, during the switching preparation phase t12, the first enable signal EN1 of the first potential is transmitted to the first frequency divider 15, causing the first frequency divider 15 to divide the first oscillation signal. In subsequent phases, the second frequency divider 35 will continue to perform frequency division, while the first frequency divider 15 needs to be turned off. Therefore, switching the first control signal Q1 of the first potential from being provided by MIMO to being provided by the first enable signal EN1 facilitates the easier shutdown of the first frequency divider 15 in subsequent phases.

[0140] Please see Figure 14 and Figure 17 , Figure 17 for Figure 13 The diagram shows the signal flow of the first controller during the reset phase and the second frequency division phase. Figure 17 The dashed arrows in the diagram indicate the signal flow within the first controller 18 during the reset phase t4.

[0141] During the reset phase t4, the MIMO signal is at the first potential, the first enable signal EN1 is at the second potential, the first select signal SEC1 is at the first potential, the second enable signal EN2 is at the second potential, and the second select signal SEC2 is at the first potential. With the first select signal SEC1 at the first potential, the first multiplexer 181 turns on the second input terminal 181b and the first output terminal 181d. The potentials of the second input terminal 181b, the first output terminal 181d, and the first data input terminal 183b are all the same. The first flip-flop 183, in response to the edge of the change in the potential of the first clock input terminal 183a, transmits the potential of the first data input terminal 183b to the first data output terminal 183c. The potential of the first data input terminal 183b is the same as the potential of the first data output terminal 183c and the potential of the third input terminal 182a. The second selection signal SEC2 is at the first potential. The second multiplexer 182 turns on the fourth input terminal 182b and the second output terminal 182d, and the potential of the fourth input terminal 182b is the same as the potential of the second output terminal 182d. That is, in the reset phase t4, the potential of the first control signal Q1 output by the first controller 18 is the same as the potential of the second enable signal EN2. The second enable signal EN2 is at the second potential, so the first controller 18 outputs the first control signal Q1 at the second potential to the first frequency divider 15.

[0142] From the switching preparation phase t12 to the reset phase t4, the potential of the second selection signal SEC2 switches from the second potential to the first potential. The second multiplexer 182 switches from being on at the third input terminal 182a and the second output terminal 182d to being on at the fourth input terminal 182b and the second output terminal 182d. The first controller 18 outputs the first control signal Q1, which is at the second potential, to the first frequency divider 15, thus turning off the first frequency divider 15. At the same time, the first switch 21 turns off, and the first enable signal EN1 switches from the first potential to the second potential.

[0143] Please see Figure 14 and Figure 17 , Figure 17 The dashed arrows in the diagram indicate the signal flow within the first controller 18 during the second frequency division phase t2.

[0144] In the second frequency division phase t2, the MIMO (Multiple Receiver Multiple Transmitter) signal is at the first potential, the first enable signal EN1 is at the second potential, the first selection signal SEC1 is at the first potential, the second enable signal EN2 is at the first potential, and the second selection signal SEC2 is at the first potential. With the first selection signal SEC1 at the first potential, the first multiplexer 181 turns on the second input terminal 181b and the first output terminal 181d. The potentials of the second input terminal 181b, the first output terminal 181d, and the first data input terminal 183b are all the same. The first flip-flop 183, in response to the change in the potential of the first clock input terminal 183a, transmits the potential of the first data input terminal 183b to the first data output terminal 183c. The potential of the first data input terminal 183b is the same as the potential of the first data output terminal 183c and the potential of the third input terminal 182a. When the second selection signal SEC2 is at the first potential, the second multiplexer 182 turns on the fourth input terminal 182b and the second output terminal 182d, making the potential of the fourth input terminal 182b the same as the potential of the second output terminal 182d. That is, during the reset phase t4, the potential of the first control signal Q1 output by the first controller 18 is the same as the potential of the second enable signal EN2. Since the second enable signal EN2 is at the first potential, the first controller 18 outputs the first control signal Q1 at the first potential to the first frequency divider 15. Similarly, during the second frequency division phase t2, the potential of the first control signal Q1 output by the first controller 18 is the same as the potential of the second enable signal EN2. Since the second enable signal EN1 is at the first potential, the first controller 18 outputs the first control signal Q1 at the first potential to the first frequency divider 15.

[0145] From the reset phase t4 to the second frequency division phase t2, the second enable signal EN2 switches from the second potential to the first potential, and the first controller 18 outputs the first control signal Q1 at the first potential to the first frequency divider 15. At the same time, the second switch 22 is turned on, and the first frequency divider 15 divides the second oscillation signal.

[0146] Please see Figure 14 and Figure 16 , Figure 16 The dashed arrows in the diagram indicate the signal flow within the first controller 18 during the reset phase t5.

[0147] During the reset phase t5, the MIMO signal is at the first potential, the first enable signal EN1 is at the second potential, the first select signal SEC1 is at the first potential, the second enable signal EN2 is at the second potential, and the second select signal SEC2 is at the second potential. With the first select signal SEC1 at the second potential, the first multiplexer 181 turns on the second input terminal 181b and the first output terminal 181d. The potentials of the second input terminal 181b, the first output terminal 181d, and the first data input terminal 183b are all the same. The first flip-flop 183, in response to the edge of the change in the potential of the first clock input terminal 183a, transmits the potential of the first data input terminal 183b to the first data output terminal 183c. The potential of the first data input terminal 183b is the same as the potential of the first data output terminal 183c and the potential of the third input terminal 182a. The second selection signal SEC2 is at the second potential. The second multiplexer 182 turns on the third input terminal 182a and the second output terminal 182d, and the potential of the third input terminal 182a is the same as the potential of the second output terminal 182d. That is, during the reset phase t5, the potential of the first control signal Q1 output by the first controller 18 is the same as the potential of the first enable signal EN1. The first enable signal EN1 is at the second potential, so the first controller 18 outputs the first control signal Q1 at the second potential to the first frequency divider 15.

[0148] From the second frequency division stage t2 to the reset stage t5, the second selection signal SEC2 switches from the first potential to the second potential. The second multiplexer 182 switches from turning on the fourth input terminal 182b and the second output terminal 182d to turning on the third input terminal 182a and the second output terminal 182d. The first controller 18 outputs the first control signal Q1, which is at the second potential, to the first frequency divider 15, and the first frequency divider 15 is turned off. At the same time, the second switch 22 is turned off.

[0149] Please see Figure 14 and Figure 16 , Figure 16 The dashed arrows in the diagram indicate the signal flow within the first controller 18 during the third frequency division phase t3.

[0150] In the third frequency division stage t3, the MIMO signal is at the first potential, the first enable signal EN1 is at the first potential, the first selection signal SEC1 is at the first potential, the second enable signal EN2 is at the second potential, and the second selection signal SEC2 is at the second potential. With the first selection signal SEC1 at the second potential, the first multiplexer 181 turns on the second input terminal 181b and the first output terminal 181d. The potentials of the second input terminal 181b, the first output terminal 181d, and the first data input terminal 183b are all the same. The first flip-flop 183, in response to the change in the potential of the first clock input terminal 183a, transmits the potential of the first data input terminal 183b to the first data output terminal 183c. The potential of the first data input terminal 183b is the same as the potential of the first data output terminal 183c and the potential of the third input terminal 182a. The second selection signal SEC2 is at the second potential. The second multiplexer 182 turns on the third input terminal 182a and the second output terminal 182d, and the potential of the third input terminal 182a is the same as the potential of the second output terminal 182d. That is, in the reset phase t5, the potential of the first control signal Q1 output by the first controller 18 is the same as the potential of the first enable signal EN1. Since the first enable signal EN1 is at the first potential, the first controller 18 outputs the first control signal Q1 at the first potential to the first frequency divider 15. That is, in the third frequency division phase t3, the potential of the first control signal Q1 output by the first controller 18 is the same as the potential of the first enable signal EN1. Since the first enable signal EN1 is at the first potential, the first controller 18 outputs the first control signal Q1 at the first potential to the first frequency divider 15.

[0151] From the reset phase t5 to the third frequency division phase t3, the first enable signal EN1 switches from the second potential to the first potential, and the first controller 18 outputs the first control signal Q1 at the first potential to the first frequency divider 15. At the same time, the second switch 22 is turned on, and the first frequency divider 15 divides the first oscillation signal.

[0152] Please see Figure 18 , Figure 18 for Figure 11 The diagram shows a second specific circuit structure of the receiver. Figure 18 The receiver shown is Figure 13 The differences between the receivers shown are as follows: receiver 10 also includes a first impedance matching network 19, a first amplifier 23, a second impedance matching network 39 and a second amplifier 34, the first signal receiving circuit 12 also includes a first variable gain amplifier 124, and the second signal receiving circuit 32 also includes a second variable gain amplifier 324.

[0153] Specifically, the first variable gain amplifier 124, the first impedance matching network 19, and the first amplifier 23 have been described above and will not be repeated here. It should be noted that the first variable gain amplifier 124 is optional; that is, the receiver 10 may or may not include the first variable gain amplifier 124. The first impedance matching network 19 is optional; that is, the receiver 10 may or may not include the first impedance matching network 19. The first amplifier 23 is optional; that is, the receiver 10 may or may not include the first amplifier 23.

[0154] In this embodiment, the second variable gain amplifier 324 is coupled between the second filter 323 and the second analog-to-digital converter 33. The second filter 323 outputs the filtered third analog baseband signal to the second variable gain amplifier 324, which amplifies the third analog baseband signal and outputs the amplified third analog baseband signal to the second analog-to-digital converter 33.

[0155] Understandably, the second analog-to-digital converter 33 has a limited operating voltage range, requiring the received third analog baseband signal to be within a preset voltage range. The second variable gain amplifier 324 is used to amplify the voltage of the third analog baseband signal to within the preset voltage range, and the gain of the second variable gain amplifier 324 is adjustable.

[0156] In this embodiment, the second impedance matching network 39 is coupled between the second antenna 31 and the second low-noise amplifier 321. The second impedance matching network 39 is used to make the impedance matching between the second antenna 31 and the second signal receiving circuit 32, so as to reduce signal reflection and loss.

[0157] In this embodiment, the second amplifier 34 is coupled between the third node N3 and the second frequency divider 35. The second amplifier 34 receives the first oscillation signal output by the first oscillator 16, amplifies the first oscillation signal, and outputs the amplified first oscillation signal to the second frequency divider 35.

[0158] It should be noted that the second variable gain amplifier 324 is optional, meaning that the receiver 10 may or may not include the second variable gain amplifier 324. The second impedance matching network 39 is optional, meaning that the receiver 10 may or may not include the second impedance matching network 39. The second amplifier 34 is optional, meaning that the receiver 10 may or may not include the second amplifier 34.

[0159] Please see Figure 19 , Figure 19This is a schematic diagram of the third functional structure of the receiver disclosed in this application. The receiver 10 with the third functional structure further includes a third antenna 41, a third signal receiving circuit 42, a third analog-to-digital converter 43, a third frequency divider 45, a third switch 51, and a fourth switch 52. For a description of the structural similarities between the receiver 10 with the first and second functional structures, please refer to the relevant descriptions of the receivers 10 with the first and second functional structures, which will not be repeated here.

[0160] Specifically, the third signal receiving circuit 42 is coupled to the third antenna 41, the third analog-to-digital converter 43, and the third frequency divider 45, respectively. The third analog-to-digital converter 43 is also coupled to the baseband unit 14. The third switch 51 is coupled between the third frequency divider 45 and the third node N3. The fourth switch 52 is coupled between the sixth node N6 between the third switch 51 and the third frequency divider 45, and between the fifth node N5 between the second switch 22 and the second oscillator 17. The third frequency divider 45 is also coupled to the seventh node N7 between the first controller 18 and the first frequency divider 15.

[0161] The third antenna 41 is used to receive the first electromagnetic wave signal, convert the first electromagnetic wave signal into a fourth radio frequency signal, and output the fourth radio frequency signal to the third signal receiving circuit 42. The third antenna 41 is also used to receive the second electromagnetic wave signal, convert the second electromagnetic wave signal into a fifth radio frequency signal, and output the fifth radio frequency signal to the third signal receiving circuit 42. Both the fourth and fifth radio frequency signals are analog electrical signals.

[0162] When the third switch 51 is on, the first oscillator 16 is coupled to the third frequency divider 45. When the third switch 51 is off, the first oscillator 16 is not coupled to the third frequency divider 45. When the fourth switch 52 is on, the second oscillator 17 is coupled to the third frequency divider 45. When the fourth switch 52 is off, the second oscillator 17 is not coupled to the third frequency divider 45. Note that the third switch 51 and the fourth switch 52 are not on simultaneously; that is, the third frequency divider 45 selectively couples with either the first oscillator 16 or the second oscillator 17.

[0163] The first oscillation signal generated by the first oscillator 16 is output to the third frequency divider 45. The third frequency divider 45 is used to divide the first oscillation signal to form a fourth frequency-divided signal, and then outputs the fourth frequency-divided signal to the third signal receiving circuit 42. The second oscillation signal generated by the second oscillator 17 is output to the third frequency divider 45. The third frequency divider 45 is used to divide the second oscillation signal to form a fifth frequency-divided signal, and then outputs the fifth frequency-divided signal to the third signal receiving circuit 42.

[0164] Specifically, when the third antenna 41 receives the first electromagnetic wave signal, the third frequency divider 45 outputs the fourth frequency-divided signal formed by dividing the first oscillation signal to the third signal receiving circuit 42. When the third antenna 41 receives the second electromagnetic wave signal, the third frequency divider 45 outputs the fifth frequency-divided signal formed by dividing the second oscillation signal to the third signal receiving circuit 42.

[0165] The third signal receiving circuit 42 mixes the fourth radio frequency signal with the fourth frequency divider signal to form a fourth analog baseband signal, and transmits the fourth analog baseband signal to the third analog-to-digital converter 43. The third analog-to-digital converter 43 converts the fourth analog baseband signal into a corresponding fourth digital baseband signal, and transmits the fourth digital baseband signal to the baseband unit 14.

[0166] The third signal receiving circuit 42 mixes the fifth radio frequency signal with the fifth frequency divider signal to form a fifth analog baseband signal, and transmits the fifth analog baseband signal to the third analog-to-digital converter 43. The third analog-to-digital converter 43 converts the fifth analog baseband signal into a corresponding fifth digital baseband signal, and transmits the fifth digital baseband signal to the baseband unit 14.

[0167] Understandably, in this application, a third signal receiving circuit 42 only needs to be equipped with a third frequency divider 45, which can switch between dividing the first oscillation signal and dividing the second oscillation signal, thereby reducing the finished product cost, the area occupied, and the power consumption.

[0168] In this embodiment of the application, the first controller 18 may also output a first control signal Q1 to the third frequency divider 45. Specifically, the first switch 21 and the third switch 51 are simultaneously turned on or off, and the second switch 22 and the fourth switch 52 are simultaneously turned on or off.

[0169] It should be noted that in the first frequency division phase t1, the first antenna 11 and the third antenna 41 simultaneously receive the first electromagnetic wave signal, the first switch 21 and the third switch 51 are simultaneously turned on, and the first frequency divider 15 and the third frequency divider 45 simultaneously perform frequency division processing on the first oscillation signal. In the reset phase t4, the first switch 21 and the third switch 51 are simultaneously turned off, and the first frequency divider 15 and the third frequency divider 45 are simultaneously turned off. In the second frequency division phase t2, the first antenna 11 and the third antenna 41 simultaneously receive the second electromagnetic wave signal, the second switch 22 and the fourth switch 52 are simultaneously turned on, and the first frequency divider 15 and the third frequency divider 45 simultaneously perform frequency division processing on the second oscillation signal. In the reset phase t5, the second switch 22 and the fourth switch 52 are simultaneously turned off, and the first frequency divider 15 and the third frequency divider 45 are simultaneously turned off. In the third frequency division stage t3, the first antenna 11 and the third antenna 41 simultaneously receive the first electromagnetic wave signal, the first switch 21 and the third switch 51 are simultaneously turned on, and the first frequency divider 15 and the third frequency divider 45 simultaneously perform frequency division processing on the first oscillation signal.

[0170] Please see Figure 20 , Figure 20 for Figure 19 The diagram shows the specific circuit structure of the receiver. Figure 20 The specific circuit of the receiver 10 shown is... Figure 18 For a description of the specific circuitry of the receiver 10 shown, where the structure is identical, please refer to [link to relevant documentation]. Figure 18 The relevant descriptions will not be repeated here.

[0171] Specifically, the third signal receiving circuit 42 includes a third low-noise amplifier 421, a third mixer 422, and a third filter 423. The third low-noise amplifier 421 is coupled between the third antenna 41 and the third mixer 422, and the third filter 423 is coupled between the third mixer 422 and the third analog-to-digital converter 43. The third mixer 422 is also coupled to a third frequency divider 45. The third low-noise amplifier 421 receives the fourth radio frequency signal output from the third antenna 41, amplifies the fourth radio frequency signal, and transmits the amplified fourth radio frequency signal to the third mixer 422. The third mixer 422 receives the fourth radio frequency signal, mixes the fourth radio frequency signal with the fourth frequency divider signal to obtain a fourth analog baseband signal, and transmits the fourth analog baseband signal to the third filter 423. The third filter 423 filters the fourth analog baseband signal and transmits the filtered fourth analog baseband signal to the third analog-to-digital converter 43.

[0172] The third low-noise amplifier 421 receives the fifth radio frequency signal output from the third antenna 41, amplifies the fifth radio frequency signal, and transmits the amplified fifth radio frequency signal to the third mixer 422. The third mixer 422 receives the fifth radio frequency signal, mixes the fifth radio frequency signal with the fifth frequency divider signal to obtain the fifth analog baseband signal, and transmits the fifth analog baseband signal to the third filter 423. The third filter 423 filters the fifth analog baseband signal and transmits the filtered fifth analog baseband signal to the third analog-to-digital converter 43.

[0173] In the exemplary embodiment, both the third switch 51 and the fourth switch 52 are single-pole single-throw switches. The third switch 51 can be composed of a transistor or a MOSFET, and the fourth switch 52 can be composed of a transistor or a MOSFET. The third filter 423 can be a surface acoustic wave (SAW) filter.

[0174] In one possible implementation, the third signal receiving circuit 42 further includes a third variable gain amplifier 424, which is coupled between the third filter 423 and the third analog-to-digital converter 43. The third variable gain amplifier 424 is used to amplify either the fourth analog baseband signal or the fifth analog baseband signal.

[0175] In one possible implementation, the receiver 10 further includes a third impedance matching network 49 coupled between the third antenna 41 and the third low-noise amplifier 421. The third impedance matching network 49 is used to achieve impedance matching between the third antenna 41 and the third signal receiving circuit 42 to reduce signal reflection and loss.

[0176] In one possible implementation, the receiver 10 further includes a third amplifier 46 coupled between the sixth node N6 and the third frequency divider 45. The third amplifier 46 is used to amplify either the first oscillation signal or the second oscillation signal.

[0177] It should be noted that the third variable gain amplifier 424 is optional, meaning that the receiver 10 may or may not include the third variable gain amplifier 424. The third impedance matching network 49 is optional, meaning that the receiver 10 may or may not include the third impedance matching network 49. The third amplifier 46 is optional, meaning that the receiver 10 may or may not include the third amplifier 46.

[0178] Please see Figure 21 , Figure 21 This is a schematic diagram of the fourth functional structure of the receiver disclosed in the embodiments of this application. Figure 21 The receiver shown is Figure 19 The difference in the receiver shown is that the third frequency divider 45 is not coupled to the seventh node N7 between the first controller 18 and the first frequency divider 15, but the third frequency divider 45 is coupled to the first controller 18. Figure 21 The receiver 10 shown is Figure 19 For a description of the structural similarities of the receiver 10 shown, please refer to [link / reference]. Figure 19 The relevant descriptions will not be repeated here.

[0179] Specifically, the first controller 18 outputs a second control signal to the third frequency divider 45. The second control signal is a pulse signal with a first potential and a second potential.

[0180] The third frequency divider 45 divides the first oscillation signal or the second oscillation signal in response to the second control signal at the first potential. For example, when the first oscillator 16 outputs the first oscillation signal to the third frequency divider 45, the third frequency divider 45 divides the first oscillation signal in response to the second control signal at the first potential. When the second oscillator 17 outputs the second oscillation signal to the third frequency divider 45, the third frequency divider 45 divides the second oscillation signal in response to the second control signal at the first potential. The third frequency divider 45 is reset in response to the second control signal at the second potential, and the reset state of the third frequency divider 45 is between the frequency division of the second oscillation signal and the frequency division of the first oscillation signal by the third frequency divider 45.

[0181] Please see Figure 22 , Figure 22 This is a timing diagram of the second control signal output by the first controller disclosed in an embodiment of this application. The second control signal Q2 also includes a first frequency division stage t1, a reset stage t4, a second frequency division stage t2, a reset stage t5, and a third frequency division stage t3. The reset stage t4 is optional; that is, the second control signal Q2 may or may not include the reset stage t4.

[0182] During the first frequency division phase t1, the second frequency division phase t2, and the third frequency division phase t3, the second control signal Q2 is at the first potential. During the reset phase t4 and the reset phase t5, the second control signal Q2 is at the second potential.

[0183] It should be noted that the difference between the second control signal Q2 and the first control signal Q1 lies in the duration of each stage of the second control signal Q2, which may be the same as or different from the duration of each stage of the first control signal Q1. For example, the duration of the first frequency division stage t1 of the second control signal Q2 may be the same as or different from the duration of the first frequency division stage t1 of the first control signal Q1, the duration of the second frequency division stage t2 of the second control signal Q2 may be the same as or different from the duration of the second frequency division stage t2 of the first control signal Q1, and the duration of the third frequency division stage t3 of the second control signal Q2 may be the same as or different from the duration of the third frequency division stage t3 of the first control signal Q1.

[0184] The operating timing of the first frequency divider 15 may be the same as or different from the operating timing of the third frequency divider 45. The turn-on timing of the first switch 21 may be the same as or different from the turn-on timing of the third switch 51. The turn-on timing of the second switch 22 may be the same as or different from the turn-on timing of the fourth switch 52.

[0185] Please see Figure 23 , Figure 23 for Figure 21 The diagram shows the specific circuit structure of the receiver. Figure 23 The receiver 10 shown is Figure 20 The difference in the receiver 10 shown is that the first controller 18 also includes a third multiplexer 184.

[0186] Specifically, the third multiplexer 184 includes a fifth input terminal 184a, a sixth input terminal 184b, a third selection input terminal 184c, and a third output terminal 184d. The fifth input terminal 184a is coupled to the third input terminal 182a, the sixth input terminal 184b receives the third enable signal EN3, the third selection input terminal 184c receives the third selection signal SEC3, and the third output terminal 184d is coupled to the third frequency divider 45.

[0187] Please see Figure 24 , Figure 24 for Figure 23 The diagram shows the timing sequence of the signals received and output by the first controller. Figure 24 The second enable signal EN2 and the second select signal SEC2 are not shown.

[0188] In this embodiment, the third multiplexer 184 selectively turns on the fifth input terminal 184a and the third output terminal 184d or the sixth input terminal 184b and the third output terminal 184d in response to the third selection signal SEC3. Specifically, when the third selection signal SEC3 is at the second potential, the third multiplexer 184 turns on the fifth input terminal 184a and the third output terminal 184d. When the third selection signal SEC3 is at the first potential, the third multiplexer 184 turns on the sixth input terminal 184b and the third output terminal 184d, and the third output terminal 184d of the third multiplexer 184 outputs the third enable signal EN3 to the third frequency divider 45.

[0189] The first multiplexer 181, the first trigger 183, and the third multiplexer 184 are combined. Figure 24 For a description of the timing diagram shown, please refer to the combination of the first multiplexer 181, the first flip-flop 183, and the second multiplexer 182. Figure 14 The relevant descriptions of the timing diagrams shown will not be repeated here.

[0190] Please see Figure 25 , Figure 25 This is a schematic diagram of the fifth functional structure of the receiver disclosed in the embodiments of this application. The difference between the receiver 10 with the fifth functional structure and the receiver 10 with the third functional structure is that the receiver 10 with the fifth functional structure also includes a second controller 48.

[0191] Specifically, the second controller 48 is coupled to the eighth node N8 between the first frequency divider 15 and the first signal receiving circuit 12, and the second controller 48 is also coupled to the third frequency divider 45. The second controller 48 outputs a third control signal Q3 to the third frequency divider 45.

[0192] Please see Figure 26 , Figure 26 This is a timing diagram of the third control signal output by the second controller disclosed in an embodiment of this application. The third control signal Q3 also includes a first frequency division stage t1, a reset stage t4, a second frequency division stage t2, a reset stage t5, and a third frequency division stage t3. The reset stage t4 is optional; that is, the third control signal Q3 may or may not include the reset stage t4.

[0193] Specifically, the second controller 48 outputs a third control signal Q3 to the third frequency divider 45. The third control signal Q3 is a pulse signal with a first potential and a second potential.

[0194] The third frequency divider 45 divides the first oscillation signal or the second oscillation signal in response to the third control signal Q3 at the first potential. For example, when the first oscillator 16 outputs the first oscillation signal to the third frequency divider 45, the third frequency divider 45 divides the first oscillation signal in response to the third control signal Q3 at the first potential. When the second oscillator 17 outputs the second oscillation signal to the third frequency divider 45, the third frequency divider 45 divides the second oscillation signal in response to the third control signal Q3 at the first potential. The third frequency divider 45 is reset in response to the third control signal Q3 at the second potential, and the reset of the third frequency divider 45 is between the frequency division of the second oscillation signal and the frequency division of the first oscillation signal by the third frequency divider 45.

[0195] During the first frequency division phase t1, the second frequency division phase t2, and the third frequency division phase t3, the third control signal Q3 is at the first potential. During the reset phase t4 and the reset phase t5, the third control signal Q3 is at the second potential.

[0196] In this embodiment of the application, the first frequency divider 15 outputs the frequency-divided signal of the first oscillation signal as the second trigger signal to the second controller 48. In the first frequency division stage t1 and the third frequency division stage t3, the second controller 48 responds to the second trigger signal and outputs the first control signal Q1 at the first potential. The third frequency divider 45 responds to the third control signal Q3 at the first potential and divides the first oscillation signal.

[0197] During the second frequency division stage t2, the second controller 48 outputs a third control signal Q3 at the first potential to the third frequency divider 45, and the third frequency divider 45 divides the second oscillation signal in response to the third control signal Q3 at the first potential.

[0198] During the reset phase t4, the third frequency divider 45 is reset in response to the third control signal Q3 at the second potential.

[0199] During the reset phase t5, the third frequency divider 45 is reset in response to the third control signal Q3 of the second potential. The reset of the third frequency divider 45 is between the frequency division of the second oscillation signal by the third frequency divider 45 and the frequency division of the first oscillation signal by the third frequency divider 45.

[0200] Understandably, the first electromagnetic wave signal is received simultaneously by multiple antennas, namely the first antenna 11 and the third antenna 41, or the first antenna 11, the second antenna 31, and the third antenna 41. The first oscillation signal is simultaneously divided by multiple frequency dividers, namely the first frequency divider 15 and the third frequency divider 45, or the first frequency divider 15, the second frequency divider 35, and the third frequency divider 45. This increases the rate at which the receiver 10 receives the first electromagnetic wave signal and saves time. Furthermore, during the first frequency division stage t1 and the third frequency division stage t3, the first antenna 11 and the third antenna 41 simultaneously receive the first electromagnetic wave signal, requiring the first frequency divider 15 and the third frequency divider 45 to simultaneously divide the first oscillation signal. At the start of either the first frequency division phase t1 or the third frequency division phase t3, the first frequency divider 15 divides the first oscillation signal, transmitting the divided first oscillation signal as a second trigger signal to the second controller 48. The second controller 48, in response to the second trigger signal, outputs a third control signal Q3 at a first potential. The second frequency divider 48, in response to the third control signal Q3 at the first potential, divides the first oscillation signal, ensuring that in both the first and third frequency division phases t1 and t3, the first frequency divider 15 and the third frequency divider 45 simultaneously divide the first oscillation signal. Consequently, the fourth frequency-divided signal obtained by the third frequency divider 45 is synchronized with the first frequency-divided signal obtained by the first frequency divider 15. The fourth frequency-divided signal needs to be synchronized with the first frequency-divided signal; otherwise, the fourth RF signal and the fourth frequency-divided signal will mix, resulting in an incorrect fourth analog baseband signal.

[0201] Understandably, the third frequency divider 45 is reset in response to the third control signal Q3 at the second potential. The reset of the third frequency divider 45 occurs between its division of the second oscillation signal and its division of the first oscillation signal. The mixing of the fourth RF signal and the fourth divided signal must be performed strictly according to the timing sequence; otherwise, the fourth analog baseband signal with the correct frequency cannot be obtained after mixing. Therefore, the timing of the fourth divided signal must be strictly guaranteed. Between switching from dividing the second oscillation signal to dividing the first oscillation signal, the third frequency divider 45 needs to be reset, and then the third frequency divider 45 is controlled to divide the first oscillation signal according to the correct timing sequence.

[0202] Please see Figure 27 and Figure 28 , Figure 27 for Figure 25 The diagram shows the specific circuit structure of the receiver. Figure 28 for Figure 25The diagram shows the timing of the signals received and output by the second controller. The second controller 48 includes a fourth multiplexer 481, a fifth multiplexer 482, and a second flip-flop 483. The fourth multiplexer 481 includes a seventh input terminal 481a, an eighth input terminal 481b, a fourth selection input terminal 481c, and a fourth output terminal 481d. The fifth multiplexer 482 includes a ninth input terminal 482a, a tenth input terminal 482b, a fifth selection input terminal 482c, and a fifth output terminal 482d. The second flip-flop 483 includes a second clock input terminal 483a, a second data input terminal 483b, and a second data output terminal 483c. The seventh input terminal 481a receives a Multiple-Receive-Multiple-Transmit (MIMO) signal. The eighth input terminal 481b receives a fourth enable signal EN4. The fourth selection input terminal 481c receives a fourth selection signal SEC4. The fourth output terminal 481d is coupled to the second data input terminal 483b. The second clock input terminal 483a is coupled to the eighth node N8 between the first frequency divider 15 and the first signal receiving circuit 12. The second data output terminal 483c is coupled to the ninth input terminal 482a. The tenth input terminal 482b receives the fifth enable signal EN5. The fifth select input terminal 482c receives the fifth select signal SEC5. The fifth output terminal 482d is coupled to the third frequency divider 45.

[0203] In this embodiment, the fourth multiplexer 481 selectively turns on the seventh input terminal 481a and the fourth output terminal 481d or the eighth input terminal 481b and the fourth output terminal 481d in response to the fourth selection signal SEC4. Specifically, when the fourth selection signal SEC4 is at the second potential, the fourth multiplexer 481 turns on the seventh input terminal 481a and the fourth output terminal 481d, and the fourth output terminal 481d of the fourth multiplexer 481 outputs a multiple-input multiple-output (MIMO) signal to the second data input terminal 483b of the second flip-flop 483. When the fourth selection signal SEC1 is at the first potential, the fourth multiplexer 481 turns on the eighth input terminal 481b and the fourth output terminal 481d, and the fourth output terminal 481d of the fourth multiplexer 481 outputs a fourth enable signal EN1 to the second data input terminal 483b of the second flip-flop 483.

[0204] The fifth multiplexer 482 responds to the fifth selection signal SEC4 by selectively turning on either the ninth input terminal 482a and the fifth output terminal 482d, or the tenth input terminal 482b and the fifth output terminal 482d. Specifically, when the fifth selection signal SEC5 is at the second potential, the fifth multiplexer 482 turns on the ninth input terminal 482a and the fifth output terminal 482d. When the fifth selection signal SEC5 is at the first potential, the fifth multiplexer 482 turns on the tenth input terminal 482b and the fifth output terminal 482d, and the fifth output terminal 482d of the fifth multiplexer 482 outputs the fifth enable signal EN5 to the third frequency divider 45.

[0205] The second flip-flop 483 transmits the potential of the second data input terminal 483b to the second data output terminal 483c in response to the change in the potential of the second clock input terminal 483a. The potential of the first clock input terminal 183a is controlled by the third frequency divider signal.

[0206] The fourth multiplexer 481, the second trigger 483, and the fifth multiplexer 482 are combined Figure 28 For a description of the timing diagram shown, please refer to the combination of the first multiplexer 181, the first flip-flop 183, and the second multiplexer 182. Figure 14 The relevant descriptions of the timing diagrams shown will not be repeated here.

[0207] In summary, the electronic device 1 provided in this application embodiment includes a receiver 10. The receiver 10 includes a first signal receiving circuit 12, a first frequency divider 15, a first oscillator 16, a second oscillator 17, a first switch 21, and a second switch 22. The first signal receiving circuit 12 is coupled to the first frequency divider 15. The first switch 21 is coupled to both the first frequency divider 15 and the first oscillator 16. The second switch 22 is coupled to the node between the first frequency divider 15 and the first switch 21, as well as to the second oscillator 17. The first switch 21 and the second switch 22 are not simultaneously turned on. The first oscillator 16 is used to output a first oscillation signal to the first frequency divider 15. The second oscillator 17 is used to output a second oscillation signal to the first frequency divider 15. The first frequency divider 15 is used to divide the first oscillation signal or the second oscillation signal, and output the divided signal to the first signal receiving circuit 12.

[0208] Understandably, when the first signal receiving circuit 12 receives the first radio frequency signal corresponding to the Wi-Fi signal, the first frequency divider 15 divides the first oscillation signal. When the first signal receiving circuit 12 receives the second radio frequency signal corresponding to the BT signal, the first frequency divider 15 divides the second oscillation signal. The first frequency divider 15 is selectively coupled to the first oscillator 16 or the second oscillator 17, allowing the first frequency divider 15 to switch back and forth between dividing the first oscillation signal and dividing the second oscillation signal. When the first frequency divider 15 is receiving the first radio frequency signal, the second radio frequency signal preempts the first frequency divider 15, before the first radio frequency signal has been fully received. After the first frequency divider 15 finishes receiving the second radio frequency signal, the first frequency divider 15 continues to receive the first radio frequency signal. Therefore, it is not necessary to retransmit the first radio frequency signal, thereby improving the efficiency of receiving the first radio frequency signal.

[0209] Furthermore, if a first signal receiving circuit 12 requires two frequency dividers—one to divide the first oscillation signal and the other to divide the second oscillation signal—two frequency dividers would occupy more area. Additionally, when dividing the second oscillation signal, it's necessary to continue dividing the first oscillation signal, which increases power consumption. For example, for a 2G receiver, an additional frequency divider would add 10mA of power consumption, and for a 5G receiver, multiple frequency dividers would add an additional 20mA of power consumption. Therefore, in this application, a first signal receiving circuit 12 only needs one first frequency divider 15, which can switch between dividing the first oscillation signal and dividing the second oscillation signal, reducing finished product cost, occupied area, and power consumption.

[0210] It should be understood that the application of this application is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims. Those skilled in the art will understand that implementing all or part of the processes of the above embodiments, and making equivalent changes according to the claims of this application, still falls within the scope of this application.

Claims

1. A receiver, characterized in that, The system includes a first signal receiving circuit, a first frequency divider, a first oscillator, a second oscillator, a first switch, and a second switch. The first signal receiving circuit is coupled to the first frequency divider. The first switch is coupled to both the first frequency divider and the first oscillator. The second switch is coupled to the node between the first frequency divider and the first switch, as well as to the second oscillator. The first switch and the second switch are not simultaneously turned on. The first oscillator is used to output a first oscillation signal to the first frequency divider through the first switch, and the second oscillator is used to output a second oscillation signal to the first frequency divider through the second switch. The first frequency divider is used to divide the first oscillation signal or the second oscillation signal by frequency, and output the divided signal to the first signal receiving circuit.

2. The receiver as described in claim 1, characterized in that, The receiver further includes a first controller coupled to the first frequency divider. The first controller is used to output a first control signal to the first frequency divider. The first frequency divider responds to the first control signal at a first potential to divide the first oscillation signal or the second oscillation signal.

3. The receiver as described in claim 2, characterized in that, The first frequency divider is reset in response to the first control signal at the second potential. The reset of the first frequency divider is between the first frequency divider dividing the second oscillation signal and the first frequency divider dividing the first oscillation signal. The first potential is greater than or less than the second potential.

4. The receiver as described in claim 3, characterized in that, The first control signal includes a first frequency division stage, a second frequency division stage, a third frequency division stage, and a reset stage, wherein the first frequency division stage, the second frequency division stage, the reset stage, and the third frequency division stage are arranged sequentially in time order; In the first frequency division stage, the first frequency divider divides the first oscillation signal in response to the first control signal at the first potential; in the second frequency division stage, the first frequency divider divides the second oscillation signal in response to the first control signal at the first potential; in the reset stage, the first frequency divider resets in response to the first control signal at the second potential; in the third frequency division stage, the first frequency divider divides the first oscillation signal in response to the first control signal at the first potential.

5. The receiver as described in claim 4, characterized in that, The first control signal further includes a reset phase, which is located between the first frequency division phase and the second frequency division phase; During the reset phase, the first frequency divider is reset in response to the first control signal at the second potential.

6. The receiver as described in claim 5, characterized in that, The receiver further includes a second signal receiving circuit and a second frequency divider. The second signal receiving circuit is coupled to the second frequency divider. The second frequency divider is also coupled to the node between the first oscillator and the first switch. The first controller is also coupled to the node between the second signal receiving circuit and the second frequency divider. The first frequency divider is used to divide the first oscillation signal and output the divided signal to the first signal receiving circuit. The second frequency divider is used to output the divided signal of the first oscillation signal as a first trigger signal to the first controller. In the first frequency division stage and the third frequency division stage, the first controller responds to the first trigger signal and outputs the first control signal at the first potential to the first frequency divider.

7. The receiver as claimed in claim 6, characterized in that, The first controller includes a first multiplexer, a second multiplexer, and a first flip-flop. The first multiplexer includes a first input terminal, a second input terminal, a first selection input terminal, and a first output terminal. The second multiplexer includes a third input terminal, a fourth input terminal, a second selection input terminal, and a second output terminal. The first flip-flop includes a first clock input terminal, a first data input terminal, and a first data output terminal. The first input terminal receives a multiple-transmit multiple-receive signal, the second input terminal receives a first enable signal, the first selection input terminal receives a first selection signal, the first output terminal is coupled to the first data input terminal, the first clock input terminal is coupled to the node between the second frequency divider and the second signal receiving circuit, the first data output terminal is coupled to the third input terminal, the fourth input terminal receives a second enable signal, the second selection input terminal receives a second selection signal, and the second output terminal is coupled to the first frequency divider. The first multiplexer selectively turns on the first input terminal and the first output terminal or the second input terminal and the first output terminal in response to the first selection signal. The second multiplexer selectively turns on the third input terminal and the second output terminal or the fourth input terminal and the second output terminal in response to the second selection signal. The first trigger transmits the potential of the first data input terminal to the first data output terminal in response to the change edge of the potential of the first clock input terminal.

8. The receiver as claimed in claim 7, characterized in that, The first frequency division phase includes a synchronization phase and a handover preparation phase. The handover preparation phase occurs after the synchronization phase, and the reset phase occurs after the handover preparation phase. During the synchronization phase, the multiple-receive-multiple-transmit signal is a first potential, the first enable signal is a first potential, the first selection signal is a second potential, the second selection signal is a second potential, the first multiplexer connects the first input terminal and the first output terminal, the first trigger responds to the change edge of the potential of the first clock input terminal to transmit the potential of the first data input terminal to the first data output terminal, the second multiplexer connects the third input terminal and the second output terminal, and the first controller outputs the first control signal at the first potential to the first frequency divider.

9. The receiver as claimed in claim 8, characterized in that, During the switching preparation phase, the first enable signal is a first potential, the first selection signal is a first potential, the second selection signal is a second potential, the first multiplexer connects the second input terminal to the first output terminal, the first trigger responds to the change edge of the potential of the first clock input terminal to transmit the potential of the first data input terminal to the first data output terminal, the second multiplexer connects the third input terminal to the second output terminal, and the first controller outputs the first control signal at the first potential to the first frequency divider.

10. The receiver as claimed in claim 7, characterized in that, During the reset phase, the second enable signal is at a second potential, the second selection signal is at a first potential, the second multiplexer connects the fourth input terminal to the second output terminal, and the first controller outputs the first control signal at the second potential to the first frequency divider.

11. The receiver as claimed in claim 7, characterized in that, During the second frequency division phase, the second enable signal is at the first potential, the second selection signal is at the first potential, the second multiplexer connects the fourth input terminal to the second output terminal, and the first controller outputs the first control signal at the first potential to the first frequency divider.

12. The receiver as claimed in claim 7, characterized in that, During the reset phase, the first enable signal is at a second potential, the first selection signal is at a first potential, the second selection signal is at a second potential, the first multiplexer connects the second input terminal to the first output terminal, the first trigger responds to the change edge of the potential at the first clock input terminal to transmit the potential at the first data input terminal to the first data output terminal, the second multiplexer connects the third input terminal to the second output terminal, and the first controller outputs the first control signal at the second potential to the first frequency divider.

13. The receiver as claimed in claim 7, characterized in that, In the third frequency division stage, the first enable signal is a first potential, the first selection signal is a first potential, the second selection signal is a second potential, the first multiplexer connects the second input terminal to the first output terminal, the first trigger responds to the change edge of the potential of the first clock input terminal to transmit the potential of the first data input terminal to the first data output terminal, the second multiplexer connects the third input terminal to the second output terminal, and the first controller outputs the first control signal at the first potential to the first frequency divider.

14. The receiver according to any one of claims 4-13, characterized in that, The receiver further includes a third signal receiving circuit, a third frequency divider, a third switch, a fourth switch, and a second controller. The third frequency divider is coupled to the second controller and the third switch. The third switch is also coupled to the node between the first oscillator and the first switch. The fourth switch is coupled to the node between the third frequency divider and the third switch, and the node between the second switch and the second oscillator. The second controller is also coupled to the node between the first frequency divider and the first signal receiving circuit. The first frequency divider divides the first oscillation signal into a second trigger signal and outputs it to the second controller. During the first frequency division stage and the third frequency division stage, the second controller responds to the second trigger signal and outputs the third control signal at a first potential to the third frequency divider. The third frequency divider responds to the third control signal at the first potential and divides the first oscillation signal into a second frequency. During the second frequency division phase, the second controller outputs the third control signal at the first potential to the third frequency divider, and the third frequency divider divides the second oscillation signal in response to the third control signal at the first potential.

15. The receiver as claimed in claim 14, characterized in that, The third frequency divider is reset in response to the third control signal at the second potential, and the reset of the third frequency divider is between the frequency division of the second oscillation signal by the third frequency divider and the frequency division of the first oscillation signal by the third frequency divider.

16. An electronic device, characterized in that, It includes a processor and a receiver as described in any one of claims 1-15, wherein the processor is coupled to the receiver.

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