M-lvds receiver circuit and electronic device

Abstract

The application discloses an M-LVDS receiver circuit and electronic equipment, comprising: a working mode selection signal, a level conversion circuit unit, a preamplifier unit, an output amplifier unit and an idle detection filter circuit unit, one input end VA of the level conversion circuit unit is connected with one signal line of an M-LVDS bus, another input end VB of the level conversion circuit unit is connected with another signal line of the M-LVDS bus, the level conversion circuit unit converts the input end VA and the input end VB into signals INA and INB respectively, and the signals INA and INB are connected with input signal ends of the preamplifier unit respectively. The application has faster response speed, is beneficial to improving data transmission rate and is suitable for high-speed bus transmission scenes. The receiver circuit of the application is compatible with TYPE1 and TYPE2 working modes and has a built-in bus idle detection function.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to an M-LVDS receiver circuit and electronic device. Background Technology

[0002] M-LVDS, short for Multipoint-Low-Voltage Differential Signaling, aims to extend point-to-point LVDS to solve multipoint application problems. The M-LVDS protocol includes two operating modes: TYPE1 and TYPE2. To ensure system stability and efficiency, it is essential to monitor the M-LVDS bus occupancy status in real time, especially accurately detecting periods of bus idleness, in order to schedule new transmission requests or trigger low-power control strategies.

[0003] A circuit is required that is compatible with M-LVDS TYPE1 and TYPE2 operating modes and has a bus idle detection function. Summary of the Invention

[0004] Therefore, it is necessary to provide an M-LVDS receiver circuit and electronic device that is compatible with M-LVDS TYPE1 and TYPE2 operating modes and has a bus idle detection function.

[0005] To achieve the above objectives, the present invention provides an M-LVDS receiver circuit, comprising: a working mode selection signal, a level conversion circuit unit, a preamplifier unit, an output amplifier unit, and an idle detection filter circuit unit. One input terminal VA of the level conversion circuit unit is connected to a signal line of the M-LVDS bus, and the other input terminal VB of the level conversion circuit unit is connected to another signal line of the M-LVDS bus. The level conversion circuit unit converts input terminals VA and VB into signals INA and INB, respectively. Signals INA and INB are respectively connected to the input signal terminals of the preamplifier unit. The output signal of the preamplifier unit includes signal V. OBP_TYP1 V OBP_TYP2 V OBN V OAP V OAN_TYP1 V OAN_TYP2 V OBN and V OAP V OBP_TYP1 and V OAN_TYP1 V OBP_TYP1 and V OAN_TYP1Each pair consists of a symmetrical differential signal with a different voltage range between them. The differential component of each differential signal pair is equal to the differential voltage of the M-LVDS bus. Multiple output signal terminals of the preamplifier unit are connected to the input signal terminals of the output amplifier unit. The operating mode selection signal is connected to the output amplifier unit. The output amplifier unit is used to select one channel of signal V when the operating mode selection signal is TYPE1. OBP_TYP1 and V OBN The comparison and output signal OUT_TYP and another selection signal V are used. OAN_TYP1 and V OAP The comparison and output signal OUT_TYP2 are used by the output amplifier unit to select one channel signal V when the operating mode selection signal is TYPE2. OBP_TYP2 and V OBN The comparison and output of OUT_TYP and another selection signal V are performed. OAN_TYP2 and V OAP The comparison and output signal OUT_TYP2 are used; the output of the output amplifier unit is output to the idle detection filter circuit unit, and the idle detection filter circuit unit outputs the bus idle status indication signal IDLE_N according to the received signal.

[0006] Further, the preamplifier unit includes switches N1-N9 and resistors R1-R6. The gate of switch N1 is connected to its drain, bias current terminal IB1, and gate of switch N2. The drain of switch N2 is connected to the sources of switch N3 and switch N4. The gate of switch N3 is connected to signal INA, and the gate of switch N4 is connected to signal INB. The drain of switch N3 is connected to one end of resistor R1 and the gate of switch N5. The drain of switch N4 is connected to one end of resistor R2 and the gate of switch N6. The source of switch N5 is connected to signal V. OAN_TYP2 One end of resistor R3 is connected, and the source of switching transistor N6 is connected to signal V. OBP_TYP2 One end of resistor R4 is connected to the signal V, and the other end of resistor R3 is connected to the signal V. OAN_TYP1 One end of resistor R5 is connected to the signal V. OBN The other end of resistor R4 is connected to the drain of switching transistor N8, and the other end of resistor R4 is connected to signal V. OBP_TYP1 One end of resistor R6 is connected to the signal V. OAPThe gate of switch N8 is connected to the drain of switch N9. The gate of switch N8 is connected to the gate of switch N9, the gate of switch N7, the drain of switch N7, and the bias current terminal IB2. The sources of switch N1, switch N2, switch N7, switch N8, and switch N9 are grounded. The other end of resistor R1, the other end of resistor R2, the drain of switch N5, and the drain of switch N6 are connected to the power supply VDD. Resistors R3 and R4 have the same resistance value, and resistors R5 and R6 have the same resistance value.

[0007] Furthermore, the output amplifier unit includes two secondary amplifiers, AMP1 and AMP2; when the operating mode selection signal is TYPE1, the secondary amplifier AMP1 outputs signal V... OBP_TYP1 and V OBN Comparison and output, secondary amplifier AMP2 compares the signal V. OAN_TYP1 and V OAP The comparison and output are performed; when the operating mode selection signal is TYPE2, the secondary amplifier AMP1 of the output amplifier unit compares and outputs the signal V. OBP_TYP2 and V OBN Comparison and output, secondary amplifier AMP2 compares the signal V. OAN_TYP2 and V OAP Compare and output.

[0008] Furthermore, the secondary amplifier includes a second-stage pre-amplifier circuit and a rail-to-rail amplifier circuit. The second-stage pre-amplifier circuit amplifies the received signal a second time, and the rail-to-rail amplifier circuit then processes the signal to output the rail-to-rail signal OUT.

[0009] Furthermore, the second-stage pre-amplifier circuit includes switches N11-N18, resistors R11 and R12. The gate of switch N11 is connected to a comparator signal input terminal INP, and the gate of switch N12 is connected to another comparator signal input terminal INN. The source of switch N11 is connected to the source of switch N12 and the drain of switch N14. The gate of switch N14 is connected to the gate of switch N13, the drain of switch N13, the gate of switch N17, the gate of switch N18, and the bias current terminal IB3. The drain of switch N11 and one end of resistor R11 are connected to the gate of switch N15. The drain of switch N12 and one end of resistor R12 are connected to the gate of switch N16. The source of switch N15 is connected to the intermediate comparator signal V. OP The source of switch N16 is connected to the drain of switch N17, and the source of switch N16 is connected to the intermediate comparison signal V. ONThe source of switching transistor N13 is connected to the drain of switching transistor N18. The sources of switching transistors N13, N14, N17, and N18 are grounded. The other ends of resistors R11 and R12, the drains of switching transistors N15 and N16 are connected to the power supply VDD. One comparison signal input terminal INP and another comparison signal input terminal INN are connected to the comparison signal from the previous stage. The intermediate comparison signal V... OP Compare with intermediate signal V ON Connect to the rail-to-rail amplifier circuit.

[0010] Furthermore, the rail-to-rail amplifier circuit includes switching transistors N19-N27, with the gate of switching transistor N19 connected to the intermediate comparison signal V. OP The gate of the switching transistor N20 is connected to the intermediate comparison signal V. ON The connections are as follows: the drain of switch N19 is connected to the drain of switch N22, the gate of switch N22, and the gate of switch N21; the drain of switch N21 is connected to the drain of switch N25, the gate of switch N25, and the gate of switch N26; the drain of switch N20 is connected to the drain of switch N23, the gate of switch N23, and the gate of switch N24; and the drain of switch N24 is connected to the drain of switch N26. Connect the signal output terminal OUT. The source of switch N19 is connected to the source of switch N20 and the drain of switch N27. The gate of switch N27 is connected to the bias current terminal IB3. The sources of switch N25, N26 and N27 are grounded. The sources of switch N21, N22, N23 and N24 are connected to the power supply VDD. The intermediate comparison signal V... OP Compare with intermediate signal V ON It is connected to the second-stage pre-amplifier circuit, and the signal output terminal OUT serves as the output terminal of the secondary amplifier.

[0011] Furthermore, the output amplifier unit includes a transmission gate, the control terminal of which is connected to the operating mode selection signal, and the transmission gate is used to select the signal.

[0012] Furthermore, the idle detection filter circuit includes a first NOR gate, a filter capacitor, and a NOT gate. The two input terminals of the first NOR gate are respectively connected to the signal OUT_TYP and the signal OUT_TYP2. The output terminal of the first NOR gate is connected to one end of the filter capacitor and the input terminal of the NOT gate. The other end of the filter capacitor is grounded. The output terminal of the NOT gate outputs the bus idle status indication signal IDLE_N.

[0013] Furthermore, it also includes a latch and a multiplexer. The two inputs of the latch are connected to signals OUT_TYP and OUT_TYP2, respectively. The output of the latch, OUT_TYP1, is connected to one input of the multiplexer. The other input of the multiplexer is connected to signal OUT_TYP2. The selection control terminal of the multiplexer is connected to the working mode selection signal. The output of the multiplexer outputs signal RX_OUT.

[0014] The present invention provides an electronic device, including an M-LVDS bus signal, an M-LVDS receiver circuit, and a bus idle state indication signal. The M-LVDS bus signal includes a pair of differential transmission signals. The M-LVDS receiver circuit is an M-LVDS receiver circuit as described in any one of the present invention. The differential signal input terminal of the M-LVDS receiver circuit is respectively connected to the pair of differential transmission signals of the M-LVDS bus signal, and the output terminal of the M-LVDS receiver circuit is connected to the bus idle state indication signal.

[0015] The above technical solution has the following advantages, unlike existing technologies:

[0016] (1) The receiver circuit of the present invention is compatible with TYPE1 and TYPE2 operating modes, and can flexibly cope with different usage scenarios, thus having higher applicability. The receiver circuit of the present invention controls the selection signal of the output amplifier unit through the operating mode selection signal, thereby changing the operating mode of the circuit, so that the receiver circuit can flexibly switch between TYPE1 and TYPE2 modes.

[0017] (2) The receiver circuit of this invention has a built-in bus idle detection function, which is applicable to both TYP1 and TYP2 operating modes and can accurately identify the bus idle state. The receiver circuit of this invention detects the differential signal of the bus through a preamplifier unit and an output amplifier unit. The circuit specifically uses two channels to compare and output the signal respectively (e.g., two secondary amplifiers can be used). In conjunction with the preamplifier, the bus differential voltage can be compared with the positive and negative threshold voltages of the receiver, which can not only realize data transmission, but also detect the bus idle state. In both TYPE1 and TYPE2 operating modes, the receiver can accurately identify the bus idle state and output a stable indication signal.

[0018] (3) The receiver circuit of the present invention has a fast idle detection function response speed, which is beneficial to shorten the M-LVDS bus polling time and improve the data transmission rate. The present invention directly uses a preamplifier + 2-way comparison (the comparison can be a secondary amplifier) ​​and output to determine whether the bus is in an idle state. There is no need to add an additional detection circuit. The detection time is not limited by the system clock frequency. Under the existing mature process, nanosecond-level detection delay can be easily achieved, which can effectively shorten the bus polling time and thus improve the bus data transmission rate.

[0019] (4) The receiver circuit structure of the present invention is simple and easy to implement. It only uses one preamplifier and two comparators, as well as a small number of logic devices and resistors and capacitors, which can be easily integrated into the chip. It has strong process versatility and can also be implemented on the PCB using discrete devices. Attached Figure Description

[0020] Figure 1 This is a circuit schematic diagram of one embodiment of the present invention;

[0021] Figure 2 This is a circuit schematic diagram of one embodiment of the present invention;

[0022] Figure 3 This is a circuit schematic diagram of one embodiment of the present invention. Detailed Implementation

[0023] To explain in detail the technical content, structural features, objectives, and effects of the technical solution, the following description is provided in conjunction with specific embodiments and accompanying drawings.

[0024] In this document, the term "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The term "embodiment" appearing in various places throughout the specification does not necessarily refer to the same embodiment, nor does it specifically limit its independence or connection with other embodiments. In principle, in this application, as long as there are no technical contradictions or conflicts, the technical features mentioned in each embodiment can be combined in any way to form corresponding implementable technical solutions.

[0025] Unless otherwise defined, the technical terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the use of related terms herein is merely for the purpose of describing particular embodiments and is not intended to limit this application.

[0026] In the description of this application, the term "and / or" is used to describe the logical relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A exists, B exists, and A and B exist simultaneously. Additionally, the character " / " in this document generally indicates that the preceding and following objects have an "or" logical relationship.

[0027] In this application, terms such as “first” and “second” are used only to distinguish one entity or operation from another, and do not necessarily require or imply any actual quantity, hierarchy or order relationship between these entities or operations.

[0028] Unless otherwise specified, the use of terms such as “comprising,” “including,” “having,” or other similar expressions in this application is intended to cover non-exclusive inclusion, which does not exclude the presence of additional elements in a process, method, or product that includes the stated elements, such that a process, method, or product that includes a list of elements may include not only those defined elements but also other elements not expressly listed, or elements inherent to such a process, method, or product.

[0029] Similar to the interpretation in the Patent Examination Guidelines, in this application, expressions such as "greater than," "less than," and "exceeding" are understood to exclude the stated number; expressions such as "above," "below," and "within" are understood to include the stated number. Furthermore, in the description of the embodiments in this application, "multiple" means two or more (including two), and similar expressions related to "multiple" are also interpreted in this way, such as "multiple groups" and "multiple times," unless otherwise explicitly specified.

[0030] In the description of the embodiments of this application, the space-related expressions used, such as "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "vertical," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential," indicate the orientation or positional relationship based on the orientation or positional relationship shown in the specific embodiments or drawings. They are only for the purpose of describing the specific embodiments of this application or for the reader's understanding, and do not indicate or imply that the device or component referred to must have a specific position, a specific orientation, or be constructed or operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0031] Unless otherwise expressly specified or limited, the terms "installation," "connection," "linking," "fixing," and "setting," as used in the description of the embodiments of this application, should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral setting; it can be a mechanical connection, an electrical connection, or a communication connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal connection of two components or the interaction between two components. For those skilled in the art to which this application pertains, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0032] Please see Figures 1 to 3 This invention provides an M-LVDS receiver circuit, comprising: a working mode selection signal, a level conversion circuit unit, a preamplifier unit, an output amplifier unit, and an idle detection filter circuit unit. One input terminal VA of the level conversion circuit unit is connected to a signal line of the M-LVDS bus, and another input terminal VB of the level conversion circuit unit is connected to another signal line of the M-LVDS bus. The level conversion circuit unit converts input terminals VA and VB into signals INA and INB, respectively. Signals INA and INB are respectively connected to the input signal terminals of the preamplifier unit. The output signal of the preamplifier unit includes signal V. OBP_TYP1 V OBP_TYP2 V OBN V OAP V OAN_TYP1 V OAN_TYP2 V OBN and V OAP V OBP_TYP1 and V OAN_TYP1 V OBP_TYP1 and V OAN_TYP1 Each pair consists of a symmetrical differential signal with a different voltage range between them. The differential component of each differential signal pair is equal to the differential voltage of the M-LVDS bus. Multiple output signal terminals of the preamplifier unit are connected to the input signal terminals of the output amplifier unit. The operating mode selection signal is connected to the output amplifier unit. The output amplifier unit is used to select one channel of signal V when the operating mode selection signal is TYPE1. OBP_TYP1 and V OBN The comparison and output signal OUT_TYP and another selection signal V are used. OAN_TYP1 and V OAP The comparison and output signal OUT_TYP2 are used by the output amplifier unit to select one channel signal V when the operating mode selection signal is TYPE2. OBP_TYP2 and V OBN The comparison and output of OUT_TYP and another selection signal V are performed. OAN_TYP2and V OAP The comparison and output signal OUT_TYP2 are used; the output of the output amplifier unit is output to the idle detection filter circuit unit, and the idle detection filter circuit unit outputs the bus idle status indication signal IDLE_N according to the received signal.

[0033] It should be noted that, in the textual description, signal V OBP_TYP1 V OBP_TYP2 V OBN V OAP V OAN_TYP1 V OAN_TYP2 The specific signal names are displayed using subscripts, while the attached diagram shows the full signal in magnification for easier reference. Please refer to the diagram for details. The operating mode selection signal indicates different operating modes; for example, a high level indicates TYPE1 operating mode, and a low level indicates TYPE2 operating mode. The level shifting circuit is used to shift the level. Because the M-LVDS protocol specifies a wide input level range (-1.4~3.8V), the M-LVDS bus signals VA and VB need to be processed by the level shifting circuit to shift the common-mode level to the input range allowed by the pre-amplifier circuit, ensuring the pre-amplifier functions properly. The pre-amplifier unit initially amplifies the differential signal amplitude. The amplified signal is then divided into three groups of differential signals, V... OBP_TYP1 V OBP_TYP2 V OBN V OAP V OAN_TYP1 V OAN_TYP2 Each pair has a different voltage, thus satisfying the voltage requirements of different modes TYPE1 and TYPE2 of the M-LVDS protocol standard. The output amplifier unit selects different signals for comparison and output in different operating modes, realizing two-channel signal output. The two signal outputs are sent to the idle detection filter circuit unit. If both channels are low, the idle detection filter circuit unit processes the signal and outputs an idle indicator signal IDLE_N=0, indicating that the bus is in an idle state. Otherwise, it outputs IDLE_N=1, indicating that the bus is in a normal operating state.

[0034] The receiver circuit of the above embodiment is compatible with both TYPE1 and TYPE2 operating modes, flexibly adapting to different usage scenarios and offering greater applicability. In this embodiment, the receiver circuit controls the selection signal of the output amplifier unit through a working mode selection signal, thereby changing the circuit's operating mode and allowing the receiver circuit to flexibly switch between TYPE1 and TYPE2 modes. It also features a built-in bus idle detection function, applicable to both TYPE1 and TYPE2 operating modes, accurately identifying the bus idle state. This embodiment's receiver circuit detects the differential signal of the bus through a preamplifier unit and an output amplifier unit. The output amplifier, in conjunction with the preamplifier, implements a window comparator function to detect the bus idle state. The circuit specifically employs two separate channels for signal comparison and output (e.g., two secondary amplifiers), which, in conjunction with the preamplifier, can compare the bus differential voltage with the receiver's positive and negative threshold voltages, enabling both data transmission and bus idle state detection. In both TYPE1 and TYPE2 operating modes, the receiver can accurately identify the bus idle state and output a stable indication signal.

[0035] As an optional embodiment, such as Figure 2 As shown, the preamplifier unit includes switches N1-N9 and resistors R1-R6. The gate of switch N1 is connected to its drain, bias current terminal IB1, and gate of switch N2. The drain of switch N2 is connected to the sources of switch N3 and switch N4. The gate of switch N3 is connected to signal INA, and the gate of switch N4 is connected to signal INB. The drain of switch N3 is connected to one end of resistor R1 and the gate of switch N5. The drain of switch N4 is connected to one end of resistor R2 and the gate of switch N6. The source of switch N5 is connected to signal V. OAN_TYP2 One end of resistor R3 is connected, and the source of switching transistor N6 is connected to signal V. OBP_TYP2 One end of resistor R4 is connected to the signal V, and the other end of resistor R3 is connected to the signal V. OAN_TYP1 One end of resistor R5 is connected to the signal V. OBN The other end of resistor R4 is connected to the drain of switching transistor N8, and the other end of resistor R4 is connected to signal V. OBP_TYP1 One end of resistor R6 is connected to the signal V. OAP The gate of switch N8 is connected to the drain of switch N9. The gate of switch N8 is connected to the gate of switch N9, the gate of switch N7, the drain of switch N7, and the bias current terminal IB2. The sources of switch N1, switch N2, switch N7, switch N8, and switch N9 are grounded. The other end of resistor R1, the other end of resistor R2, the drain of switch N5, and the drain of switch N6 are connected to the power supply VDD. Resistors R3 and R4 have the same resistance value, and resistors R5 and R6 have the same resistance value.

[0036] Figure 2 The operation of the intermediate preamplifier unit is as follows: where R3=R4, R5=R6, and the currents in the two resistor branches are equal, then V OBN and V OAP Given a pair of symmetrical differential signals, the amplification factor of V can be adjusted by designing the preamplifier unit. OAP - V OBN =V id =V A -V B (Vid is the bus differential voltage). Similarly, V OBP_TYP1 and V OAN_TYP1 V OBP_TYP1 and V OAN_TYP1 These are also a pair of symmetrical differential signals, each with a differential component equal to the bus differential voltage. Taking the threshold voltage generation principle of the TYPE1 receiver as an example, it can be seen from the circuit structure that V OAN_TYP1 V OBP_TYP1 Differential voltage V of the bus id The relationship between them is as follows:

[0037] Equation (1)

[0038] Equation (2)

[0039] In the above formula, V R5 V R6 These are the voltage drops across resistors R5 and R6, respectively, and:

[0040] Equation (3)

[0041] From the above relationship, it can be seen that when the bus differential voltage reaches V R5 At that time, V OAP With V OAN_TYP1 Achieving balance; when the bus differential voltage reaches -V R5 At that time, V OBN With V OBP_TYP1 To achieve equilibrium, the threshold voltage of the TYPE1 receiver is ±V. R5 This threshold voltage also serves as the total idle detection window voltage.

[0042] Similarly, the forward threshold voltage of the TYPE2 receiver is equal to the sum of the voltage drops across resistors R3 and R5, V. R3 +V R5 This threshold voltage also serves as the positive window voltage for idle detection of the TYPE2 receiver, and the negative window voltage for idle detection is -(V). R3 +V R5 ).Depend on Figure 2It can be seen that the expression for the forward threshold voltage of the TYPE2 receiver is as follows:

[0043] Equation (4)

[0044] Therefore, by reasonably setting the resistance values ​​and circuit bias current in the preamplifier unit, where the circuit bias current IB2 controls the current in the branches of resistors R3, R5, R4, and R6, different voltages can be obtained by multiplying different currents by different resistances, thus generating the TYPE1 and TYPE2 receiver threshold voltages that conform to the M-LVDS protocol standard. Moreover, the circuit structure of this embodiment is simple.

[0045] The bias current terminal is used to connect to an external bias current control signal. Figure 2 In this circuit, bias current terminals IB1 and IB2 represent the bias currents for the first and second stages of the preamplifier, respectively. The bias current IB1, along with the width-to-length ratio of the input differential pair switches N3 and N4, determines the transconductance gm of the preamplifier (when the input differential pair is operating in the saturation region). Given other circuit parameters, increasing the bias current IB1 can increase the transconductance gm, thereby improving the circuit gain and bandwidth, but it also increases power consumption. Therefore, a reasonable bias current IB1 must be set by comprehensively considering the preamplifier's gain, bandwidth, and power consumption requirements. Furthermore, the values ​​of the bias current IB1 and resistors R1 and R2 affect the common-mode level of the output signal. Therefore, when designing the bias current IB1 and R1 and R2, it is also necessary to ensure that the common-mode level of the output signal is within the allowable input range of the secondary amplifier.

[0046] according to Figure 2 It is known that the value of the bias current IB2 will affect the voltage drop across resistors R3 to R6, thus affecting the receiver's threshold voltage. Therefore, the bias current IB2 and the resistance values ​​of resistors R3 to R6 need to be set appropriately to generate the TYPE1 and TYPE2 receiver threshold voltages that conform to the M-LVDS protocol standard.

[0047] In some embodiments, the output amplifier unit includes two secondary amplifiers, AMP1 and AMP2; when the operating mode selection signal is TYPE1, the secondary amplifier AMP1 responds to signal V. OBP_TYP1 and V OBN Comparison and output, secondary amplifier AMP2 compares the signal V. OAN_TYP1 and V OAP The comparison and output are performed; when the operating mode selection signal is TYPE2, the secondary amplifier AMP1 of the output amplifier unit compares and outputs the signal V. OBP_TYP2 and V OBN Comparison and output, secondary amplifier AMP2 compares the signal V. OAN_TYP2 and V OAPThe system performs comparison and output. Specifically, one comparison and output is achieved through secondary amplifier AMP1, and the other through secondary amplifier AMP2. This simple structure achieves two comparison and output channels in different operating modes using two secondary amplifiers.

[0048] Furthermore, such as Figure 3 As shown, the secondary amplifier includes a second-stage pre-amplifier circuit and a rail-to-rail amplifier circuit. The second-stage pre-amplifier circuit amplifies the received signal a second time, and the rail-to-rail amplifier circuit then processes the signal to output the rail-to-rail signal OUT. This second-stage pre-amplifier circuit amplifies the signal that has already been processed by the previous stage, further increasing the amplitude of the signal input to the rail-to-rail amplifier circuit. The subsequent rail-to-rail amplifier circuit does not need to perform all the amplification on its own; instead, the second-stage pre-amplifier circuit undertakes part of the amplification, thus enabling the entire secondary amplifier to achieve a higher overall amplification.

[0049] As an example, such as Figure 3 As shown, the second-stage pre-amplifier circuit includes switches N11-N18, resistors R11 and R12. The gate of switch N11 is connected to a comparator signal input terminal INP, and the gate of switch N12 is connected to another comparator signal input terminal INN. The source of switch N11 is connected to the source of switch N12 and the drain of switch N14. The gate of switch N14 is connected to the gate of switch N13, the drain of switch N13, the gate of switch N17, the gate of switch N18, and the bias current terminal IB3. The drain of switch N11 and one end of resistor R11 are connected to the gate of switch N15. The drain of switch N12 and one end of resistor R12 are connected to the gate of switch N16. The source of switch N15 is connected to the intermediate comparator signal V. OP The source of switch N16 is connected to the drain of switch N17, and the source of switch N16 is connected to the intermediate comparison signal V. ON The source of switching transistor N13 is connected to the drain of switching transistor N18. The sources of switching transistors N13, N14, N17, and N18 are grounded. The other ends of resistors R11 and R12, the drains of switching transistors N15 and N16 are connected to the power supply VDD. One comparison signal input terminal INP and another comparison signal input terminal INN are connected to the comparison signal from the previous stage. The intermediate comparison signal V... OP Compare with intermediate signal V ONIt is connected to a rail-to-rail amplifier circuit. Signal VOP is the amplified signal of signal INP, and signal VON is the amplified signal of signal INN. Signal amplification can be achieved using simple switching transistors and resistors, resulting in a simple structure. The bias current terminal IB3 is the bias current for the secondary amplifier circuits AMP1 and AMP2. Similar to the preamplifier circuit, the magnitude of this bias current directly affects the transconductance of AMP1 and AMP2, thus affecting the circuit gain and bandwidth. Therefore, a reasonable bias current IB3 must be set according to the design requirements.

[0050] As an example, such as Figure 3 As shown, the rail-to-rail amplifier circuit includes switching transistors N19-N27. The gate of switching transistor N19 is connected to the intermediate comparison signal V. OP The gate of the switching transistor N20 is connected to the intermediate comparison signal V. ON The connections are as follows: the drain of switch N19 is connected to the drain of switch N22, the gate of switch N22, and the gate of switch N21; the drain of switch N21 is connected to the drain of switch N25, the gate of switch N25, and the gate of switch N26; the drain of switch N20 is connected to the drain of switch N23, the gate of switch N23, and the gate of switch N24; and the drain of switch N24 is connected to the drain of switch N26. Connect the signal output terminal OUT. The source of switch N19 is connected to the source of switch N20 and the drain of switch N27. The gate of switch N27 is connected to the bias current terminal IB3. The sources of switch N25, N26 and N27 are grounded. The sources of switch N21, N22, N23 and N24 are connected to the power supply VDD. The intermediate comparison signal V... OP Compare with intermediate signal V ON Connected to the second-stage pre-amplifier circuit, the signal output terminal OUT serves as the output terminal of the secondary amplifier. This embodiment can realize a rail-to-rail amplifier circuit with a simple switching transistor, resulting in a simple structure.

[0051] In some embodiments, the output amplifier unit includes a transmission gate, the control terminal of which is connected to an operating mode selection signal. The transmission gate is used to select the signal. That is, by controlling the transmission gate, different signals can be connected to one comparator or another, thereby enabling the selection of different signals for comparison in different operating modes. Figure 1 As shown, it includes transmission gates TG1-TG4. When TYP_SEL=1, the receiver circuit operates in TYPE1 mode. At this time, transmission gates TG1 and TG3 are open, and V... OBP =V OBP_TYP1 V OAN =V OAN_TYP1 At this time, the 1-channel selection signal V OBP_TYP1 and VOBN The comparison and output signal OUT_TYP and another selection signal V are used. OAN_TYP1 and V OAP The comparison and output signal OUT_TYP2 are performed. When TYP_SEL=0, the receiver operates in TYPE2 mode. At this time, transmission gates TG2 and TG4 are open, and V... OBP =V OBP_TYP2 V OAN =V OAN_TYP2 At this time, the 1-channel selection signal V OBP_TYP2 and V OBN The comparison and output of OUT_TYP and another selection signal V are performed. OAN_TYP2 and V OAP Compare and output signal OUT_TYP2.

[0052] Furthermore, the idle detection filtering circuit includes a first NOR gate, a filter capacitor, and a NOT gate. The two inputs of the first NOR gate are connected to signals OUT_TYP and OUT_TYP2, respectively. The output of the first NOR gate is connected to one end of the filter capacitor and the input of the NOT gate. The other end of the filter capacitor is grounded. The output of the NOT gate outputs the bus idle state indication signal IDLE_N. When the circuit operates in TYPE1 mode, if the bus differential voltage is within the bus idle detection window voltage, signals OUT_TYP and OUT_TYP2 simultaneously output low levels. After processing by the filtering circuit, the idle indication signal IDLE_N=0 is output (the filtering circuit filters out glitches to prevent the IDLE_N signal from erroneously flipping), indicating that the bus is in an idle state; otherwise, IDLE_N=1 is output, indicating that the bus is in a normal operating state. Similarly, when the circuit operates in TYPE2 mode, if the bus differential voltage is within the bus idle detection window voltage, OUT_TYP and OUT_TYP2 simultaneously output low levels, causing IDLE_N to flip to a low level, indicating that the bus is in an idle state; otherwise, IDLE_N=1 is output. Therefore, the receiver circuit of this design uses a combination of a preamplifier and two secondary amplifiers, which not only realizes the bus data transmission function, but also the idle detection function.

[0053] Furthermore, it also includes a latch and a multiplexer. The two inputs of the latch are connected to signals OUT_TYP and OUT_TYP2, respectively. The output of the latch, OUT_TYP1, is connected to one input of the multiplexer, and the other input of the multiplexer is connected to signal OUT_TYP2. The selection control terminal of the multiplexer is connected to the operating mode selection signal, and the output of the multiplexer is the signal RX_OUT. The latch can be constructed from two NOR gates, such as... Figure 1 As shown. When the operating mode selection signal is in TYPE1 mode, there is V.OBP =V OBP_TYP1 V OAN =V OAN_TYP1 The multiplexer MUX1 selects channel OUT_TYP1 as the output. When the bus differential voltage V... id When the voltage is less than the negative threshold voltage of the TYPE1 receiver, OUT_TYP is high, and OUT_TYP2 is low. After processing by the SR latch, the TYP1 mode output signal OUT_TYP1 is low, therefore RX_OUT = OUT_TYP1 = 0. When the bus differential voltage V id When the voltage exceeds the positive threshold voltage of the TYPE1 receiver, OUT_TYP2 is high, and OUT_TYP is low, therefore RX_OUT = OUT_TYP1 = 1. This occurs when the operating mode selection signal is in TYPE2 mode. At this time, V... OBP =V OBP_TYP2 V OAN =V OAN_TYP2 The multiplexer MUX1 selects channel 0, OUT_TYP2, for output. When the bus differential voltage V... id When the voltage is greater than the receiver's forward threshold voltage (TYPE2), OUT_TYP2 is high, and RX_OUT = OUT_TYP2 is also high. Otherwise, the output RX_OUT is low. This allows the receiver circuit output to be configured for different operating modes based on the selector signal.

[0054] When the above embodiments are combined into one embodiment, its circuit operation principle is as follows: When the operating mode selection signal TYP_SEL=1, the receiver circuit operates in TYPE1 mode. At this time, transmission gates TG1 and TG3 are open, and V... OBP =V OBP_TYP1 V OAN =V OAN_TYP1 The multiplexer MUX1 selects channel OUT_TYP1 as the output. When the bus differential voltage V... id Less than the negative threshold voltage of the TYPE1 receiver - V R5 (V) R5 When the expression is shown in equation (3), the output OUT_TYP of the secondary amplifier AMP1 is high, and the output signal OUT_TYP2 of the secondary amplifier AMP2 is low. After processing by the SR latch, the output signal OUT_TYP1 of the TYP1 mode is low. Therefore, RX_OUT = OUT_TYP1 = 0. When the bus differential voltage V id The positive threshold voltage V of the TYPE1 receiver is greater than R5When the secondary amplifier AMP2 outputs OUT_TYP2 at a high level, the secondary amplifier AMP1 outputs OUT_TYP at a low level, therefore RX_OUT = OUT_TYP1 = 1.

[0055] When TYP_SEL=0, the receiver operates in TYPE2 mode. At this time, transmission gates TG2 and TG4 are open, and V... OBP =V OBP_TYP2 V OAN =V OAN_TYP2 The multiplexer MUX1 selects channel 0, OUT_TYP2, for output. When the bus differential voltage V... id Greater than the positive threshold voltage V of the TYPE2 receiver R3 +V R5 When (see equation (4)), the secondary amplifier AMP2 output OUT_TYP2 is at a high level, and at this time RX_OUT=OUT_TYP2 is at a high level; otherwise, the output RX_OUT is at a low level.

[0056] One implementation of secondary amplifiers AMP1 and AMP2 is as follows: Figure 3 As shown, the internal circuit includes a second-stage pre-amplifier circuit and a rail-to-rail amplifier circuit. The second-stage pre-amplifier circuit amplifies the signal output from the pre-amplifier a second time, and finally outputs the rail-to-rail signal OUT after processing by the rail-to-rail amplifier circuit.

[0057] The receiver circuit of this invention has a bus idle detection function. The preamplifier and secondary amplifiers AMP1 and AMP2 in this receiver circuit can be combined to form an equivalent window comparator. The preamplifier and secondary amplifier AMP1 work together to compare the bus differential voltage with the receiver's negative threshold voltage, outputting OUT_TYP as the negative window voltage detection result. The preamplifier and secondary amplifier AMP2 work together to compare the bus differential voltage with the receiver's positive threshold voltage, outputting OUT_TYP2 as the positive window voltage detection result. The bus idle detection principle is as follows: When the circuit operates in TYPE1 mode, the bus idle detection window voltage is ±V. R5 If the bus differential voltage is -V R5 <V id <V R5 If the secondary amplifiers AMP1 and AMP2 simultaneously output a low level, the output idle indicator signal IDLE_N=0 (the filter circuit removes glitches and prevents the IDLE_N signal from erroneously toggling) will be processed by the filter circuit, indicating that the bus is in an idle state; otherwise, IDLE_N=1 will be output, indicating that the bus is in a normal operating state. Similarly, when the circuit is operating in TYPE2 mode, the bus idle detection window voltage is ±(V R3 +V R5If the bus differential voltage is -(V) R3 +V R5 ) < V id <V R3 +V R5 At this time, AMP1 and AMP2 simultaneously output a low level, causing IDLE_N to toggle to a low level, indicating that the bus is in an idle state; otherwise, IDLE_N=1 is output. Therefore, the receiver circuit of this design uses a combination of a preamplifier and two secondary amplifiers, which not only realizes the bus data transmission function, but also the idle detection function.

[0058] This invention provides an electronic device comprising an M-LVDS bus signal, an M-LVDS receiver circuit, and a bus idle state indication signal. The M-LVDS bus signal includes a pair of differential transmission signals. The M-LVDS receiver circuit is as described in any one of claims 1 to 9. The differential signal input terminal of the M-LVDS receiver circuit is connected to the pair of differential transmission signals of the M-LVDS bus signal, and the output terminal of the M-LVDS receiver circuit is connected to the bus idle state indication signal. The electronic device of this invention uses the M-LVDS receiver circuit of this invention, is compatible with TYPE1 and TYPE2 operating modes, and has a built-in bus idle detection function. The receiver circuit of this invention has a simple structure and is easy to implement.

[0059] It should be noted that although the above embodiments have been described herein, this does not limit the scope of patent protection of the present invention. Therefore, any changes and modifications made to the embodiments described herein based on the innovative concept of the present invention, or equivalent structural or procedural transformations made using the content of the present invention's specification and drawings, directly or indirectly applying the above technical solutions to other related technical fields, are all included within the scope of patent protection of the present invention.

Claims

1. An M-LVDS receiver circuit, characterized in that, include: The system includes a working mode selection signal, a level conversion circuit unit, a preamplifier unit, an output amplifier unit, and an idle detection filter circuit unit. One input terminal VA of the level conversion circuit unit is connected to a signal line of the M-LVDS bus, and the other input terminal VB is connected to another signal line of the M-LVDS bus. The level conversion circuit unit converts input terminals VA and VB into signals INA and INB, respectively. Signals INA and INB are connected to the input signal terminals of the preamplifier unit. The output signal of the preamplifier unit includes signal V. OBP_TYP1 V OBP_TYP2 V OBN V OAP V OAN_TYP1 V OAN_TYP2 V OBN and V OAP V OBP_TYP1 and V OAN_TYP1 V OBP_TYP1 and V OAN_TYP1 Each pair consists of a symmetrical differential signal with a different voltage range between them. The differential component of each differential signal pair is equal to the differential voltage of the M-LVDS bus. Multiple output signal terminals of the preamplifier unit are connected to the input signal terminals of the output amplifier unit. The operating mode selection signal is connected to the output amplifier unit. The output amplifier unit is used to select one channel of signal V when the operating mode selection signal is TYPE1. OBP_TYP1 and V OBN The comparison and output signal OUT_TYP and another selection signal V are used. OAN_TYP1 and V OAP The comparison and output signal OUT_TYP2 are used by the output amplifier unit to select one channel signal V when the operating mode selection signal is TYPE2. OBP_TYP2 and V OBN The comparison and output of OUT_TYP and another selection signal V are performed. OAN_TYP2 and V OAP The comparison and output signal OUT_TYP2 are used; the output of the output amplifier unit is output to the idle detection filter circuit unit, and the idle detection filter circuit unit outputs the bus idle status indication signal IDLE_N according to the received signal.

2. The M-LVDS receiver circuit according to claim 1, characterized in that: The preamplifier unit includes switches N1-N9 and resistors R1-R6. The gate of switch N1 is connected to its drain, bias current terminal IB1, and the gate of switch N2. The drain of switch N2 is connected to the source of switch N3 and the source of switch N4. The gate of switch N3 is connected to signal INA, and the gate of switch N4 is connected to signal INB. The drain of switch N3 is connected to one end of resistor R1 and the gate of switch N5. The drain of switch N4 is connected to one end of resistor R2 and the gate of switch N6. The source of switch N5 is connected to signal V. OAN_TYP2 One end of resistor R3 is connected, and the source of switching transistor N6 is connected to signal V. OBP_TYP2 One end of resistor R4 is connected to the signal V, and the other end of resistor R3 is connected to the signal V. OAN_TYP1 One end of resistor R5 is connected to the signal V. OBN The other end of resistor R4 is connected to the drain of switching transistor N8, and the other end of resistor R4 is connected to signal V. OBP_TYP1 One end of resistor R6 is connected to the signal V. OAP The gate of switch N8 is connected to the drain of switch N9. The gate of switch N8 is connected to the gate of switch N9, the gate of switch N7, the drain of switch N7, and the bias current terminal IB2. The sources of switch N1, switch N2, switch N7, switch N8, and switch N9 are grounded. The other end of resistor R1, the other end of resistor R2, the drain of switch N5, and the drain of switch N6 are connected to the power supply VDD. Resistors R3 and R4 have the same resistance value, and resistors R5 and R6 have the same resistance value.

3. The M-LVDS receiver circuit according to claim 1, characterized in that: The output amplifier unit includes two secondary amplifiers, AMP1 and AMP2; when the operating mode selection signal is TYPE1, the secondary amplifier AMP1 outputs signal V. OBP_TYP1 and V OBN Comparison and output, secondary amplifier AMP2 compares the signal V. OAN_TYP1 and V OAP The comparison and output are performed; when the operating mode selection signal is TYPE2, the secondary amplifier AMP1 of the output amplifier unit compares and outputs the signal V. OBP_TYP2 and V OBN Comparison and output, secondary amplifier AMP2 compares the signal V. OAN_TYP2 and V OAP Compare and output.

4. The M-LVDS receiver circuit according to claim 3, characterized in that: The secondary amplifier includes a second-stage pre-amplifier circuit and a rail-to-rail amplifier circuit. The second-stage pre-amplifier circuit amplifies the received signal a second time, and the rail-to-rail amplifier circuit then processes the signal to output the rail-to-rail signal OUT.

5. The M-LVDS receiver circuit according to claim 4, characterized in that: The second-stage pre-amplifier circuit includes switches N11-N18, resistors R11 and R12. The gate of switch N11 is connected to a comparator signal input terminal INP, and the gate of switch N12 is connected to another comparator signal input terminal INN. The source of switch N11 is connected to the source of switch N12 and the drain of switch N14. The gate of switch N14 is connected to the gate of switch N13, the drain of switch N13, the gate of switch N17, the gate of switch N18, and the bias current terminal IB3. The drain of switch N11 and one end of resistor R11 are connected to the gate of switch N15. The drain of switch N12 and one end of resistor R12 are connected to the gate of switch N16. The source of switch N15 is connected to the intermediate comparator signal V. OP The source of switch N16 is connected to the drain of switch N17, and the source of switch N16 is connected to the intermediate comparison signal V. ON The source of switching transistor N13 is connected to the drain of switching transistor N18. The sources of switching transistors N13, N14, N17, and N18 are grounded. The other ends of resistors R11 and R12, the drains of switching transistors N15 and N16 are connected to the power supply VDD. One comparison signal input terminal INP and another comparison signal input terminal INN are connected to the comparison signal from the previous stage. The intermediate comparison signal V... OP Compare with intermediate signal V ON Connect to the rail-to-rail amplifier circuit.

6. The M-LVDS receiver circuit according to claim 4, characterized in that: The rail-to-rail amplifier circuit includes switching transistors N19-N27, with the gate of switching transistor N19 connected to the intermediate comparison signal V. OP The gate of the switching transistor N20 is connected to the intermediate comparison signal V. ON The connections are as follows: the drain of switch N19 is connected to the drain of switch N22, the gate of switch N22, and the gate of switch N21; the drain of switch N21 is connected to the drain of switch N25, the gate of switch N25, and the gate of switch N26; the drain of switch N20 is connected to the drain of switch N23, the gate of switch N23, and the gate of switch N24; and the drain of switch N24 is connected to the drain of switch N26. Connect the signal output terminal OUT. The source of switch N19 is connected to the source of switch N20 and the drain of switch N27. The gate of switch N27 is connected to the bias current terminal IB3. The sources of switch N25, N26 and N27 are grounded. The sources of switch N21, N22, N23 and N24 are connected to the power supply VDD. The intermediate comparison signal V... OP Compare with intermediate signal V ON It is connected to the second-stage pre-amplifier circuit, and the signal output terminal OUT serves as the output terminal of the secondary amplifier.

7. The M-LVDS receiver circuit according to claim 1, characterized in that: The output amplifier unit includes a transmission gate, the control terminal of which is connected to the operating mode selection signal. The transmission gate is used to select the signal.

8. The M-LVDS receiver circuit according to claim 1, characterized in that: The idle detection filter circuit includes a first NOR gate, a filter capacitor, and a NOT gate. The two inputs of the first NOR gate are connected to signals OUT_TYP and OUT_TYP2, respectively. The output of the first NOR gate is connected to one end of the filter capacitor and the input of the NOT gate. The other end of the filter capacitor is grounded. The output of the NOT gate outputs the bus idle status indication signal IDLE_N.

9. An M-LVDS receiver circuit according to claim 1, characterized in that: It also includes a latch and a multiplexer. The two inputs of the latch are connected to the signals OUT_TYP and OUT_TYP2, respectively. The output of the latch, OUT_TYP1, is connected to one input of the multiplexer. The other input of the multiplexer is connected to the signal OUT_TYP2. The selection control terminal of the multiplexer is connected to the working mode selection signal. The output of the multiplexer is the output signal RX_OUT.

10. An electronic device, characterized in that: The device includes an M-LVDS bus signal, an M-LVDS receiver circuit, and a bus idle state indication signal. The M-LVDS bus signal includes a pair of differential transmission signals. The M-LVDS receiver circuit is the M-LVDS receiver circuit as described in any one of claims 1 to 9. The differential signal input terminal of the M-LVDS receiver circuit is connected to the pair of differential transmission signals of the M-LVDS bus signal, and the output terminal of the M-LVDS receiver circuit is connected to the bus idle state indication signal.

Images