A single board and network device

Abstract

The embodiment of the application provides a single board and network equipment, comprising a serial transceiver, the serial transceiver comprises a hybrid circuit, and the hybrid circuit comprises a sending circuit and a receiving circuit.The sending circuit is used for sending a first data signal to a data transmission channel, and the data transmission channel is used for data transmission between the single board and a peer single board.The receiving circuit is used for receiving transmission data from the data transmission channel and eliminating the first data signal from the sending circuit, and the transmission data comprises a second data signal from the peer single board, and the second data signal is transmitted in the data transmission channel at the same time as the first data signal.

Description

Technical Field

[0001] This application relates to the field of computers, and more particularly to a single-board computer and a network device. Background Technology

[0002] Parallel buses and serial buses are two different data transmission methods. A parallel bus is a bus structure that transmits multiple data bits simultaneously through multiple data lines. While parallel buses can increase bandwidth by increasing bus width and clock speed, they still have many limitations, such as the need for clock coordination, strict setup and hold times between data and clock signals, and crosstalk between signals. Serial buses overcome the shortcomings of parallel buses, increasing data transmission rates by several orders of magnitude. In network communication equipment, high-speed serial buses are typically used for data transmission to improve the utilization of physical links, increase equipment capacity, and reduce design complexity.

[0003] The high-speed serial bus used for internal communication in current network devices can only achieve unidirectional transmission, that is, the signal is transmitted unidirectionally on only one physical channel, and the transmitter (TX) and receiver (RX) on the same board work on different physical channels.

[0004] As networks develop, the required capacity of network devices is increasing, but the speed and configurable number of unidirectional high-speed serial buses have reached their limits, which is not conducive to increasing device capacity. Summary of the Invention

[0005] This application provides a single-board computer and a network device that can communicate via a high-speed serial bus with simultaneous bidirectional transmission, thereby increasing device capacity.

[0006] This application provides a single-board unit including a serial transceiver. The serial transceiver includes a hybrid circuit, which includes a transmitting circuit and a receiving circuit. The transmitting circuit is used to transmit a first data signal to a data transmission channel, which is used for data transmission between the single-board unit and a peer single-board unit. The receiving circuit is used to receive transmitted data from the data transmission channel and eliminate the first data signal from the transmitting circuit. The transmitted data includes a second data signal from the peer single-board unit, and the second data signal and the first data signal are transmitted simultaneously on the data transmission channel.

[0007] In this solution, the serial transceiver of the single board includes a transmitting circuit and a receiving circuit. The transmitting circuit is used to send local data to the data transmission channel, and the receiving circuit is used to receive data transmitted on the data transmission channel. It can also eliminate local data from the transmitting circuit, so that it can correctly receive data transmitted on the data transmission channel while sending local data. It supports simultaneous data transmission and reception, enabling single boards to communicate through a high-speed serial bus with simultaneous bidirectional transmission, thereby improving device capacity.

[0008] In one possible implementation, the transmitted data also includes an echo signal of the first data signal, and the serial transceiver also includes an analog echo canceller (AEC) used to cancel the echo signal of the first data signal in the transmitted data.

[0009] In this scheme, the serial transceiver is also equipped with AEC (Automatic Echo Control) to eliminate echo signals of local data in the analog domain and improve communication quality.

[0010] In one possible implementation, the serial transceiver also includes an analog front end (AFE) module, with an analog front end (AEC) configured at the front end of the AFE.

[0011] In this solution, AEC is set at the front end of AFE, which can achieve better echo cancellation effect and improve communication quality in some specific scenarios.

[0012] In one possible implementation, the serial transceiver also includes an AFE, with an AEC configured at the back end of the AFE.

[0013] In this solution, AEC is set at the back end of AFE, which can achieve better echo cancellation effect and improve communication quality in some specific scenarios.

[0014] In one possible implementation, the hybrid circuit is an actively driven replication circuit.

[0015] In one possible implementation, the hybrid circuit is an inverter combined with a linear resistor circuit.

[0016] In one possible implementation, the hybrid circuit is a passive resistor-transconductance hybrid circuit.

[0017] In one possible implementation, the serial transceiver also includes a digital echo canceller (DEC), which is used to eliminate the echo signal of the first data signal in the transmitted data.

[0018] In this scheme, the serial transceiver is also equipped with a DEC (Digital Echo Control) to eliminate the echo signal of the first data signal in the digital domain and improve communication quality.

[0019] A second aspect of this application provides a network device including a first board and a second board, which communicate via a data transmission channel. The first board has a first serial transceiver, and the second board has a second serial transceiver. The first serial transceiver includes a first hybrid circuit, which includes a first transmitting circuit and a first receiving circuit. The second serial transceiver includes a second hybrid circuit, which includes a second transmitting circuit and a second receiving circuit. The first transmitting circuit transmits a first data signal to the data transmission channel. The second transmitting circuit transmits a second data signal to the data transmission channel, and the first and second data signals are transmitted simultaneously on the data transmission channel. The first receiving circuit receives first transmitted data from the data transmission channel and cancels the first data signal from the first transmitting circuit; the first transmitted data includes the second data signal. The second receiving circuit receives second transmitted data from the data transmission channel and cancels the second data signal from the second transmitting circuit; the second transmitted data includes the first data signal.

[0020] In this solution, the serial transceiver on the single board of the network device includes a transmitting circuit and a receiving circuit. The transmitting circuit is used to send local data to the data transmission channel, and the receiving circuit is used to receive data transmitted on the data transmission channel. It can also eliminate local data from the transmitting circuit, so that it can correctly receive data transmitted on the data transmission channel while sending local data. It supports simultaneous data transmission and reception, enabling the network device to communicate through a high-speed serial bus with simultaneous bidirectional transmission, thereby increasing the device capacity.

[0021] In one possible implementation, the first transmitted data further includes an echo signal of the first data signal, and the second transmitted data further includes an echo signal of the second data signal. The first serial transceiver further includes a first AEC (Active Electronic Control), and the second serial transceiver further includes a second AEC. The first AEC is used to cancel the echo signal of the first data signal in the first transmitted data, and the second AEC is used to cancel the echo signal of the second data signal in the first transmitted data.

[0022] In this solution, the serial transceiver on the single board is also equipped with AEC, which eliminates the echo signal of the local data in the analog domain and improves the communication quality.

[0023] In one possible implementation, the first serial transceiver further includes a first AFE, the second serial transceiver further includes a second AFE, the first AEC is configured at the front end of the first AFE, and the second AEC is configured at the front end of the second AFE.

[0024] In one possible implementation, the first serial transceiver further includes a first AFE, the second serial transceiver further includes a second AFE, the first AEC is located at the back end of the first AFE, and the second AEC is located at the back end of the second AFE.

[0025] In one possible implementation, the first hybrid circuit and the second hybrid circuit are active drive replication circuits.

[0026] In one possible implementation, the first hybrid circuit and the second hybrid circuit are inverters combined with linear resistor circuits.

[0027] In one possible implementation, the first hybrid circuit and the second hybrid circuit are resistance-transconductance passive hybrid circuits.

[0028] In one possible implementation, the first serial transceiver further includes a first DEC, and the second serial transceiver further includes a second DEC. The first DEC is used to eliminate the echo signal of the first data signal in the first transmitted data, and the second DEC is used to eliminate the echo signal of the second data signal in the second transmitted data.

[0029] In this solution, the serial transceiver on the single board is also equipped with DEC, which eliminates the echo signal of the local data in the digital domain and improves the communication quality.

[0030] In one possible implementation, the first board is the master board, and the second board is the slave board. The first data signal carries a clock signal. The second board is used to recover the clock signal from the first data signal and use the clock signal as a clock reference.

[0031] In this solution, clock synchronization is achieved through an embedded clock, eliminating the need for a separate clock line and saving pin and wiring resources.

[0032] In one possible implementation, the network device further includes an external clock module that sends clock signals to the first board and the second board, so that the first board and the second board use the clock signals as a clock reference.

[0033] In this solution, the external clock module provides a stable clock signal, reducing synchronization errors, and the clock signal is transmitted through a dedicated line to reduce interference.

[0034] A third aspect of this application provides a network device including the single board described in the first aspect. Attached Figure Description

[0035] Figure 1 This is a schematic diagram illustrating parallel and serial transmission.

[0036] Figure 2 A schematic diagram illustrating communication between network communication devices via a serial bus;

[0037] Figure 3a This is a schematic diagram of network communication devices communicating via a high-speed serial bus with unidirectional transmission.

[0038] Figure 3b A schematic diagram of a single-board communication via a high-speed serial bus with simultaneous bidirectional transmission provided in an embodiment of this application;

[0039] Figure 4 A schematic diagram of a hybrid circuit provided in an embodiment of this application;

[0040] Figure 5 A schematic diagram of a hybrid circuit provided in an embodiment of this application;

[0041] Figure 6 A schematic diagram of a hybrid circuit provided in an embodiment of this application;

[0042] Figure 7 A schematic diagram of a serial transceiver provided in an embodiment of this application;

[0043] Figure 8 Another schematic diagram of a serial transceiver provided in an embodiment of this application;

[0044] Figure 9 Another schematic diagram of a serial transceiver provided in an embodiment of this application;

[0045] Figure 10 Another schematic diagram of a single-board communication via a high-speed serial bus with simultaneous bidirectional transmission provided in an embodiment of this application;

[0046] Figure 11 Another schematic diagram of a single-board communication via a high-speed serial bus with simultaneous bidirectional transmission provided in an embodiment of this application;

[0047] Figure 12 Another schematic diagram of a single-board communication via a high-speed serial bus with simultaneous bidirectional transmission provided in an embodiment of this application;

[0048] Figure 13 Another schematic diagram of a single-board communication via a high-speed serial bus with simultaneous bidirectional transmission provided in an embodiment of this application;

[0049] Figure 14 Another schematic diagram of a single-board communication via a high-speed serial bus with simultaneous bidirectional transmission provided in an embodiment of this application;

[0050] Figure 15 A schematic diagram of a network device provided in an embodiment of this application;

[0051] Figure 16A schematic diagram illustrating clock synchronization of a network device provided in this application embodiment;

[0052] Figure 17 Another schematic diagram illustrating clock synchronization of a network device provided in this application embodiment;

[0053] Figure 18 Another schematic diagram of the network device provided in the embodiments of this application;

[0054] Figure 19 A schematic diagram illustrating clock synchronization of a network device provided in this application embodiment;

[0055] Figure 20 Another schematic diagram illustrating clock synchronization of a network device provided in an embodiment of this application. Detailed Implementation

[0056] The embodiments of this application are described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. As those skilled in the art will understand, with the development of technology and the emergence of new scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0057] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0058] To facilitate understanding of this application, the relevant concepts involved in this application will be introduced below:

[0059] Driver: Generally refers to hardware circuits or chips used to enhance signals or optimize communication. They can be used to compensate for signal attenuation during transmission (especially in long-distance communication), match devices with different voltage domains (such as communication between 3.3V and 5V devices), prevent noise or transient voltage on the bus from damaging sensitive devices, improve the load capacity of the bus, and support more devices in parallel.

[0060] Transconductance amplifier: It is a special type of amplifier in electronic circuits. Its core function is to convert the input voltage into the output current, that is, the output current is proportional to the input voltage.

[0061] Inverter: It is the most basic component in digital logic circuits. Its core function is to invert the logic state of the input signal.

[0062] Differential signal lines: Differential signal lines include positive signal lines and negative signal lines. The signals on the positive signal line (e.g., Tx+) and the negative signal line (e.g., Tx-) do not individually represent the data "1" or "0", but rather represent the data through the voltage difference between them. Specifically, the signals on the positive and negative signal lines are out of phase, and their voltage difference is used to represent the actual data value. Assuming the positive signal line is Tx+ and the negative signal line is Tx-, the voltage difference (ΔV) between them is used to represent the data: Data "1": The voltage of the positive signal line is higher than the voltage of the negative signal line, i.e., ΔV>0. Data "0": The voltage of the positive signal line is lower than the voltage of the negative signal line, i.e., ΔV<0.

[0063] Clock signal: A clock signal is a periodic signal, typically represented as a square wave (alternating high and low levels). Its periodic changes provide a reference for digital circuits, enabling the various parts of the circuit to work in coordination. The main function of the clock signal is synchronization. In digital circuits, the clock signal is used to control the timing of data transmission, storage, and processing.

[0064] Clock recovery refers to the process in digital communication systems where the receiving end recovers a clock signal synchronized with the transmitting end based on the received signal. Its core objective is to eliminate clock asynchrony problems caused by factors such as clock skew and jitter, ensuring the accuracy and stability of data transmission.

[0065] Please see Figure 1 Parallel buses can transmit multiple bits of data simultaneously. They have multiple data lines, each transmitting one bit of data, allowing a complete byte, word, or wider data unit to be transmitted at the same time. For example, a 32-bit parallel bus can transmit 32 bits of data simultaneously, like having 32 parallel channels, each transmitting one bit of data, greatly improving data transmission efficiency. Parallel buses require more physical wiring. Taking a common 32-bit parallel bus as an example, at least 32 data lines are needed to transmit data, in addition to address lines, control lines, and other lines to complete the communication process. Early memory buses on computer motherboards were parallel, with multiple pins for data transmission. The large number of these pins made the connection between the motherboard and the memory modules relatively complex.

[0066] Parallel buses can theoretically achieve very high transmission speeds because they transmit multiple bits of data simultaneously. For example, a 32-bit parallel bus with a clock frequency of 100MHz has a theoretical bandwidth of 32 × 100MHz = 3.2 Gbit / s. However, in practical applications, parallel buses are affected by various factors, such as signal interference and timing synchronization issues. Because multiple data lines transmit data simultaneously, signals between different data lines may interfere with each other, leading to data transmission errors. Furthermore, ensuring that data on multiple data lines arrives at the receiving end simultaneously requires precise timing control, which is difficult to achieve at high speeds. Therefore, the actual transmission speed of a parallel bus is often lower than its theoretical value.

[0067] Serial buses transmit data bit by bit. In serial communication, data is sent or received one bit at a time sequentially on a single communication line. For example, an 8-bit byte of data will be transmitted first, with the most significant bit (or least significant bit) sent first, followed by the remaining bits in sequence until the entire byte is transmitted. Serial buses typically require fewer physical lines. For instance, a simple serial communication link might only need one data line (for unidirectional transmission) and one clock line (for synchronous data transmission). Taking the RS-232 serial communication interface as an example, it primarily uses a small number of pins to achieve communication between devices, including transmit data lines, receive data lines, and ground.

[0068] In network communication equipment, high-speed serial buses are typically used for data transmission to improve physical link utilization, increase device capacity, and reduce design complexity. For example, please refer to... Figure 2 The network communication device consists of two boards (board 1 and board 2), each with multiple network processors. These processors are responsible for processing network data packets and performing operations such as routing, forwarding, and filtering. The network processors on the two boards are interconnected via a high-speed serial bus to enable high-speed data transmission and exchange.

[0069] Please see Figure 3a Existing high-speed serial buses in network communication equipment can only achieve unidirectional transmission. A single board needs to have transmitters (TX) and receivers (RX) operating on different physical channels to achieve simultaneous data transmission and reception via two high-speed serial buses in different directions. With the increase in network capacity and speed, the speed and number of unidirectional high-speed serial buses within network communication equipment have become bottlenecks. Speed ​​improvements can only be achieved by increasing the modulation depth or frequency of the electrical signals, which places increasingly higher demands on the design of passive links and active circuits, making it increasingly difficult to implement and hindering further increases in the capacity of network communication equipment.

[0070] Assume that the number of high-speed serial buses in the communication equipment is N, and the baud rate of the electrical signal on each high-speed serial bus is T (T = 2 × fN, where fN is the Nyquist frequency or fundamental frequency of the signal) Baud / s, and the modulation depth of the serial electrical signal is m. If the high-speed serial bus can only transmit in one direction, then the equipment capacity of the communication equipment is N × T × m bps = 2 × N × fN × mbps. If the high-speed serial bus can transmit in both directions simultaneously, then the equipment capacity of the communication equipment is N × T × m bps = 4 × N × fN × m bps. It is easy to see that using a bidirectional serial bus can significantly improve the equipment capacity of the communication equipment.

[0071] This application provides a single-board embodiment; please refer to [link / reference]. Figure 3b These single boards can communicate with each other via a high-speed serial bus that transmits bidirectionally at the same time. The high-speed serial bus uses single-ended signal lines or differential signal lines.

[0072] This type of board is equipped with a serial transceiver, which includes a hybrid circuit comprising a transmitting circuit and a receiving circuit. The transmitting circuit transmits local data to the peer board via a data transmission channel; the receiving circuit receives transmitted data from the data transmission channel simultaneously with the transmitting circuit's transmission of local data. The transmitted data includes peer data from the peer board and echo signals of the local data. When the transmitting circuit sends local data to the data transmission channel, it also sends local data to the receiving circuit. The receiving circuit further eliminates the local data from the transmitting circuit, thereby ensuring correct reception of transmitted data from the data transmission channel.

[0073] The hybrid circuit described above can be implemented in several different ways, which will be introduced below:

[0074] I. Active Driven Replication Circuit

[0075] Please see Figure 4 The aforementioned hybrid circuit can specifically be an active drive replication circuit, which includes driver 401, driver 402, resistor 403, resistor 404, and differential amplifier 405. The data signal to be transmitted is input to driver 401 and driver 402 respectively. Driver 401 amplifies the data signal and outputs the main data signal; driver 402 amplifies the data signal and outputs the secondary data signal.

[0076] Driver 401 and resistor 403 constitute a transmitting circuit. The main data signal output by driver 401 is sent to the data transmission channel after passing through resistor 403, thereby transmitting to the other end's board. Driver 402, resistor 404, and differential amplifier 405 constitute a receiving circuit. The secondary data signal output by driver 402 is input to differential amplifier 405 after passing through resistor 404. In addition, the main data signal passing through resistor 403 is also input to differential amplifier 405. Since the two signals are highly matched, the difference approaches zero, so the main data signal and the secondary data signal are eliminated. At the same time, the data transmitted on the data transmission channel is also transmitted to differential amplifier 405 for further processing.

[0077] II. Resistance-Transconductance Passive Hybrid Circuit

[0078] Please see Figure 5 The aforementioned hybrid circuit can specifically be a resistor-transconductance passive hybrid circuit, which specifically includes a driver 501, a resistor 502, a transconductance amplifier 503, and a transconductance amplifier 504.

[0079] Driver 501 and resistor 502 constitute the transmitting circuit. The data signal to be transmitted is input to driver 501, which amplifies the data signal. The amplified data signal is then sent to the data transmission channel after passing through resistor 502, thereby being transmitted to the board at the other end. Resistor 502, transconductance amplifier 503, and transconductance amplifier 504 constitute the receiving circuit. The data signal output from driver 501 and the transmitted data on the data transmission channel are mixed in the receiving circuit. By adjusting the amplification factor and resistance value of transimpedance amplifier 503 and transconductance amplifier 504, the data signal is eliminated, ensuring correct reception of transmitted data.

[0080] III. Inverter combined with linear resistor circuit

[0081] Please see Figure 6 The aforementioned hybrid circuit can specifically be an inverter combined with a linear resistor circuit. This circuit specifically includes driver 601, driver 602, resistor 603, resistor 604, resistor 605, inverter 606, and resistor 607. The data signal to be transmitted is input to driver 601 and driver 602 respectively. Driver 601 amplifies the data signal and outputs the main data signal; driver 602 amplifies the data signal and outputs the secondary data signal.

[0082] Driver 601 and resistor 603 constitute the transmitting circuit. The main data signal is sent to the data transmission channel after passing through resistor 603, and thus transmitted to the single board at the other end. Driver 602, resistor 604, resistor 605, inverter 606, and resistor 607 constitute the receiving circuit. Resistors 604, 605, 606, and inverter 607 form a voltage adder. The main data signal, the secondary data signal, and the transmitted data on the data transmission channel passing through resistor 604 enter this voltage adder, which cancels out the main data signal and the secondary data signal.

[0083] Please see Figure 7 , Figure 7 The simplified schematic diagram of the aforementioned serial transceiver shows that the hybrid circuit 701 can simultaneously send data signals to the data transmission channel and correctly receive transmitted data on the data transmission channel, performing subsequent processing. The serial transceiver also includes post-processing circuitry connected to the receiving circuit, including an AFE module 702, an ADC module 703, and an EQ 704. The AFE module 702 is responsible for amplifying, filtering, and impedance matching the input signal. The processed analog signal enters the ADC module 703 for sampling, quantization, and encoding, converting it into a digital signal. The digital signal enters the EQ 704 for frequency response adjustment, adaptive equalization, and phase correction, ultimately obtaining the desired peer data.

[0084] Please see Figure 8 In one possible implementation, the serial transceiver may further include an AEC module 705. The AEC module 705 uses an adaptive filtering algorithm to estimate the echo path and generates an estimated signal that is the opposite of the echo signal, thereby eliminating the echo signal of the local data in the transmitted data in the analog domain. The AEC module 705 may be located at the front end or the back end of the AFE module 702.

[0085] Please see Figure 9 In one possible implementation, the serial transceiver may further include a DEC module 706, which may be integrated with the EQ 704. The DEC module 706 uses an adaptive filtering algorithm to estimate the echo path and generates an estimated signal that is the opposite of the echo signal, thereby eliminating the echo signal of the local data in the transmitted data in the digital domain.

[0086] The aforementioned board, based on the hybrid circuitry in the serial transceiver, can simultaneously receive and transmit data. Based on this, a bidirectional high-speed serial bus can be constructed, including boards at both ends and a data transmission channel connecting the two boards. The two boards are those described above.

[0087] Please see Figure 10 , Figure 10 This is a schematic diagram of simultaneous bidirectional high-speed serial bus communication between single boards in an embodiment of this application. The two single boards at both ends are referred to as single board 1 and single board 2, respectively.

[0088] The serial transceiver on board 1 includes a hybrid circuit 1001, an AFE module 1002, an AEC module 1003, an ADC module 1004, an equalizer (EQ) 1005, and a DEC module 1006. The serial transceiver on board 2 includes a hybrid circuit 1101, an AFE module 1102, an AEC module 1103, an ADC module 1104, an EQ 1105, and a DEC module 1106.

[0089] The data to be sent on board 1 is denoted as data signal 1, and the data to be sent on board 2 is denoted as data signal 2. Data signal 1 is sent to the data transmission channel through the mixing circuit 1001, and data signal 2 is sent to the data transmission channel through the mixing circuit 1101. Data signal 1 and data signal 2 are transmitted simultaneously on the physical signal, that is, the serial transceiver on board 1 and the serial transceiver on board 2 simultaneously send data to the other end.

[0090] The hybrid circuit 1001 includes a transmitting circuit and a receiving circuit. The transmitting circuit sends a data signal 1 to a data transmission channel. The receiving circuit receives the data signal 1 from the transmitting circuit and the transmitted data 1 from the data transmission channel, the transmitted data 1 including a data signal 2 and an echo signal of the data signal 1. The receiving circuit cancels the data signal 1 from the transmitting circuit, thereby ensuring correct reception of the transmitted data 1 on the data transmission channel.

[0091] AFE module 1002 performs amplification, filtering, and impedance matching on the transmitted data 1.

[0092] The AEC module 1003 uses an adaptive filtering algorithm to estimate the echo path and generate an estimated signal that is the opposite of the echo signal, thereby eliminating the echo signal of data signal 1 in the analog domain.

[0093] The ADC module 1004 converts the transmitted signal 1 into a digital signal.

[0094] EQ1005 performs frequency response adjustment, adaptive equalization, and phase correction on transmitted signal 1.

[0095] DEC module 1006 uses an adaptive filtering algorithm to estimate the echo path and generate an estimated signal that is the opposite of the echo signal, thereby eliminating the echo signal of data signal 1 in the digital domain.

[0096] After the above processing, board 1 can obtain data signal 2 from board 2.

[0097] The hybrid circuit 1101 includes a transmitting circuit and a receiving circuit. The transmitting circuit sends data signal 2 to a data transmission channel. The receiving circuit receives data signal 2 from the transmitting circuit and transmitted data 2 from the data transmission channel, the transmitted data 2 including data signal 1 and an echo signal of data signal 2. The receiving circuit cancels data signal 2 from the transmitting circuit, thereby ensuring correct reception of transmitted data 2 on the data transmission channel.

[0098] AFE module 1102 performs amplification, filtering, and impedance matching on the transmitted data 2.

[0099] AEC module 1103 uses an adaptive filtering algorithm to estimate the echo path and generate an estimated signal that is the opposite of the echo signal, thereby eliminating the echo signal of data signal 2 in the analog domain.

[0100] The ADC module 1104 converts the transmitted signal 2 into a digital signal.

[0101] EQ1105 performs frequency response adjustment, adaptive equalization, and phase correction on the transmitted signal 2.

[0102] DEC module 1106 uses an adaptive filtering algorithm to estimate the echo path and generate an estimated signal that is the opposite of the echo signal, thereby eliminating the echo signal of data signal 2 in the digital domain.

[0103] After the above processing, board 2 can obtain data signal 1 from board 1.

[0104] Please see Figure 11 , Figure 11 This is another schematic diagram illustrating simultaneous bidirectional high-speed serial bus communication between single boards according to an embodiment of this application. Figure 10 The difference is that, Figure 10 The AEC modules are all located at the back end of the AEF modules, while Figure 11 The AEC module is located at the front of the AEF module, and the rest... Figure 11 and Figure 10 The same applies to the examples described above, and will not be elaborated upon here.

[0105] Please see Figure 12 The following uses a hybrid circuit as an example. Figure 4 Taking the structure shown as an example, a more detailed explanation will be provided:

[0106] The hybrid circuit on board 1 includes driver 1201, driver 1202, resistor 1203, resistor 1204 and differential amplifier 1205. In addition, board 1 also includes AEC module 1206, AFE module 1207, ADC module 1208, EQ 1209 and DEC module 1210.

[0107] Data signal 1 from board 1 is input to driver 1201 and driver 1202 respectively. Driver 1201 amplifies the data signal and outputs the main data signal; driver 1202 amplifies the data signal and outputs the secondary data signal. Driver 1201 and resistor 1203 constitute a transmitting circuit. The main data signal output by driver 1201 is sent to the data transmission channel after passing through resistor 1203. Driver 1202, resistor 1204, and differential amplifier 1205 constitute a receiving circuit. The secondary data signal output by driver 1202 is input to differential amplifier 1205 after passing through resistor 1204. In addition, the main data signal after passing through resistor 1203 is also input to differential amplifier 1205. Since the two signals are highly matched and the difference approaches zero, the main data signal and the secondary data signal are eliminated.

[0108] Data signal 2 from board 2 is input to driver 1301 and driver 1302 respectively. Driver 1301 amplifies the data signal and outputs the main data signal; driver 1302 amplifies the data signal and outputs the secondary data signal. Driver 1301 and resistor 1303 constitute a transmitting circuit. The main data signal output by driver 1301 is sent to the data transmission channel after passing through resistor 1303. Driver 1302, resistor 1304, and differential amplifier 1305 constitute a receiving circuit. The secondary data signal output by driver 1302 is input to differential amplifier 1305 after passing through resistor 1304. In addition, the main data signal after passing through resistor 1303 is also input to differential amplifier 1305. Since the two signals are highly matched and the difference approaches zero, the main data signal and the secondary data signal are eliminated.

[0109] While data signal 1 is being sent to the data transmission channel, transmitted data 1 on the data transmission channel is being transmitted to differential amplifier 1205. Transmitted data 1 includes the echo signal of data signal 1 and data signal 2.

[0110] The AEC module 1206 uses an adaptive filtering algorithm to estimate the echo path and generate an estimated signal that is the opposite of the echo signal, thereby eliminating the echo signal of data signal 1 in the analog domain.

[0111] AFE module 1207 performs amplification, filtering, and impedance matching on the transmitted data 1.

[0112] The ADC module 1208 converts the transmitted signal 1 into a digital signal.

[0113] EQ1209 performs frequency response adjustment, adaptive equalization, and phase correction on transmitted signal 1.

[0114] DEC module 1210 uses an adaptive filtering algorithm to estimate the echo path and generates an estimated signal that is the opposite of the echo signal, thereby eliminating the echo signal of data signal 1 in the digital domain.

[0115] After the above processing, board 1 can obtain data signal 2 from board 2.

[0116] While data signal 2 is being sent to the data transmission channel, transmitted data 2 on the data transmission channel is being transmitted to differential amplifier 1305. Transmitted data 2 includes the echo signal of data signal 2 and data signal 1.

[0117] The AEC module 1306 uses an adaptive filtering algorithm to estimate the echo path and generate an estimated signal that is the opposite of the echo signal, thereby eliminating the echo signal of data signal 2 in the analog domain.

[0118] AFE module 1307 performs amplification, filtering, and impedance matching on the transmitted data 2.

[0119] The ADC module 1308 converts the transmitted signal 2 into a digital signal.

[0120] The EQ1309 performs frequency response adjustment, adaptive equalization, and phase correction on the transmitted signal 2.

[0121] DEC module 1310 uses an adaptive filtering algorithm to estimate the echo path and generate an estimated signal that is the opposite of the echo signal, thereby eliminating the echo signal of data signal 2 in the digital domain.

[0122] After the above processing, board 2 can obtain data signal 1 from board 1.

[0123] Please see Figure 13 The following uses a hybrid circuit as an example. Figure 5 Taking the structure shown as an example, a more detailed explanation will be provided:

[0124] The hybrid circuit on the serial transceiver of board 1 includes a driver 1401, a resistor 1402, a transimpedance amplifier 1403, and a transimpedance amplifier 1404. Additionally, the serial transceiver of board 1 also includes an AEC module 1405, an AFE module 1406, an ADC module 1407, an EQ module 1408, and a DEC module 1409. Driver 1401 and resistor 1402 constitute the transmitting circuit. Data signal 1 from board 1 is input to driver 1401, which amplifies data signal 1. The amplified data signal 1 is then transmitted to the data transmission channel after passing through resistor 1402.

[0125] The hybrid circuit on the serial transceiver of board 2 includes driver 1501, resistor 1502, transimpedance amplifier 1503, and transimpedance amplifier 1504. Additionally, the serial transceiver of board 2 also includes AEC module 1505, AFE module 1506, ADC module 1507, EQ 1508, and DEC module 1509. Driver 1501 and resistor 1502 constitute the transmitting circuit. Data signal 2 from board 2 is input to driver 1501, which amplifies data signal 2. The amplified data signal 2 is then transmitted to the data transmission channel after passing through resistor 1502.

[0126] Resistor 1402, transconductance amplifier 1403, and transconductance amplifier 1404 constitute the receiving circuit. The data signal 1 output by driver 1403 and the transmitted data 1 on the data transmission channel are mixed in the receiving circuit. By adjusting the amplification factor and resistance value of transimpedance amplifier 1403 and transconductance amplifier 1404, the data signal 1 is eliminated, ensuring that the transmitted data 1 is correctly received. The transmitted data 1 includes the echo signal of data signal 1 and the data signal 2 from board 2.

[0127] Resistor 1502, transconductance amplifier 1503, and transconductance amplifier 1504 constitute the receiving circuit. The data signal 2 output by driver 1503 and the transmitted data 2 on the data transmission channel are mixed in the receiving circuit. By adjusting the amplification factor and resistance value of transimpedance amplifier 1503 and transconductance amplifier 1504, the data signal 2 is eliminated to ensure the correct reception of transmitted data 2. Transmitted data 2 includes the echo signal of data signal 2 and data signal 1 from board 1.

[0128] The AEC module 1405 uses an adaptive filtering algorithm to estimate the echo path and generate an estimated signal that is the opposite of the echo signal, thereby eliminating the echo signal of data signal 1 in the analog domain.

[0129] AFE module 1406 performs amplification, filtering, and impedance matching on the transmitted data 1.

[0130] The ADC module 1407 converts the transmitted signal 1 into a digital signal.

[0131] EQ1408 performs frequency response adjustment, adaptive equalization, and phase correction on transmitted signal 1.

[0132] DEC module 1409 uses an adaptive filtering algorithm to estimate the echo path and generate an estimated signal that is the opposite of the echo signal, thereby eliminating the echo signal of data signal 1 in the digital domain.

[0133] After the above processing, board 1 can obtain data signal 2 from board 2.

[0134] The AEC module 1505 uses an adaptive filtering algorithm to estimate the echo path and generate an estimated signal that is the opposite of the echo signal, thereby eliminating the echo signal of data signal 2 in the analog domain.

[0135] The AFE module 1506 amplifies, filters, and performs impedance matching on the transmitted data 2.

[0136] The ADC module 1507 converts the transmitted signal 2 into a digital signal.

[0137] The EQ1508 performs frequency response adjustment, adaptive equalization, and phase correction on the transmitted signal 2.

[0138] DEC module 1509 uses an adaptive filtering algorithm to estimate the echo path and generate an estimated signal that is the opposite of the echo signal, thereby eliminating the echo signal of data signal 2 in the digital domain.

[0139] After the above processing, board 2 can obtain data signal 1 from board 1.

[0140] Please see Figure 14 The following uses a hybrid circuit as an example. Figure 6 Taking the structure shown as an example, a more detailed explanation will be provided:

[0141] The hybrid circuit on the serial transceiver of board 1 includes driver 1601, driver 1602, resistor 1603, resistor 1604, resistor 1605, inverter 1606, and resistor 1607. In addition, the serial transceiver of board 1 also includes AEC module 1608, AFE module 1609, ADC module 1610, EQ 1611, and DEC module 1612.

[0142] The hybrid circuit on the serial transceiver of board 2 includes driver 1701, driver 1702, resistor 1703, resistor 1704, resistor 1705, inverter 1706, and resistor 1707. In addition, the serial transceiver of board 2 also includes AEC module 1708, AFE module 1709, ADC module 1710, EQ 1711, and DEC module 1712.

[0143] Driver 1601 and resistor 1603 constitute a transmitting circuit. Data signal 1 of board 1 is input to driver 1601 and driver 1602 respectively. Driver 1601 amplifies data signal 1 and outputs main data signal. The main data signal is sent to the data transmission channel after passing through resistor 1603. Driver 1602 amplifies data signal 1 and outputs secondary data signal.

[0144] Driver 1701 and resistor 1703 constitute a transmitting circuit. Data signal 2 of board 2 is input to driver 1701 and driver 1702 respectively. Driver 1701 amplifies data signal 2 and outputs main data signal. The main data signal is sent to the data transmission channel after passing through resistor 1703. Driver 1702 amplifies data signal 2 and outputs secondary data signal.

[0145] Driver 1602, resistors 1604 and 1605, inverter 1606 and resistor 1607 constitute the receiving circuit. Resistors 1604, 1605, 1606 and inverter 1607 constitute a voltage adder. The main data signal, the secondary data signal and the transmitted data 1 on the data transmission channel enter the voltage adder. The voltage adder eliminates the main data signal and the secondary data signal to ensure the correct reception of the transmitted data 1. The transmitted data 1 includes the echo signal of data signal 1 and data signal 2 from board 2.

[0146] Driver 1702, resistors 1704 and 1705, inverter 1706 and resistor 1707 constitute the receiving circuit. Resistors 1704, 1705, 1706 and inverter 1707 constitute a voltage adder. The main data signal, the secondary data signal and the transmitted data 2 on the data transmission channel enter the voltage adder. The voltage adder eliminates the main data signal and the secondary data signal to ensure the correct reception of the transmitted data 2. The transmitted data 2 includes the echo signal of the data signal 2 and the data signal 1 from the board 1.

[0147] The AEC module 1608 uses an adaptive filtering algorithm to estimate the echo path and generate an estimated signal that is the opposite of the echo signal, thereby eliminating the echo signal of data signal 1 in the analog domain.

[0148] The AFE module 1609 amplifies, filters, and performs impedance matching on the transmitted data 1.

[0149] The ADC module 1610 converts the transmitted signal 1 into a digital signal.

[0150] EQ1611 performs frequency response adjustment, adaptive equalization, and phase correction on transmitted signal 1.

[0151] DEC module 1612 uses an adaptive filtering algorithm to estimate the echo path and generate an estimated signal that is the opposite of the echo signal, thereby eliminating the echo signal of data signal 1 in the digital domain.

[0152] After the above processing, board 1 can obtain data signal 2 from board 2.

[0153] The AEC module 1708 uses an adaptive filtering algorithm to estimate the echo path and generate an estimated signal that is the opposite of the echo signal, thereby eliminating the echo signal of data signal 2 in the analog domain.

[0154] The AFE module 1709 amplifies, filters, and performs impedance matching on the transmitted data 2.

[0155] The ADC module 1710 converts the transmitted signal 2 into a digital signal.

[0156] EQ1711 performs frequency response adjustment, adaptive equalization, and phase correction on the transmitted signal 2.

[0157] DEC module 1712 uses an adaptive filtering algorithm to estimate the echo path and generate an estimated signal that is the opposite of the echo signal, thereby eliminating the echo signal of data signal 2 in the digital domain.

[0158] After the above processing, board 2 can obtain data signal 1 from board 1.

[0159] In the foregoing embodiments, the ADC module used can be a high-performance ADC module, including but not limited to high-bandwidth ADC modules, low-noise ADC modules, and low-power ADC modules. The echo cancellation algorithm can employ zero-forcing algorithm, least mean squares (LMS) algorithm, normalized least mean squares (NLMS) algorithm, normalized subband adaptive filter (NSAF) algorithm, frequency domain adaptive filter (FDAF) algorithm, etc.

[0160] Please see Figure 15 This application provides a network device that includes the aforementioned single board 1 and single board 2, which communicate via a high-speed serial bus with simultaneous bidirectional transmission, thereby increasing the device capacity.

[0161] Please see Figure 16 In one possible implementation, the network device also includes an external clock module, and board 1 and board 2 can receive the clock signal sent by the external clock module and use it as a clock reference.

[0162] Commonly used external clock modules include crystal oscillators, which can provide high-precision clock signals and are suitable for scenarios with high clock accuracy requirements; atomic clocks, such as rubidium clocks or cesium clocks, which provide extremely high clock accuracy and stability, but are more expensive and are usually used in high-precision measurement or communication systems; and oven-controlled crystal oscillators, which improve clock accuracy through temperature compensation technology and are suitable for environments sensitive to temperature changes.

[0163] The output of the external clock module needs to be connected to the clock input pins of the two boards via a suitable transmission line (such as a coaxial cable or microstrip line). Ensure impedance matching and signal integrity of the transmission line to reduce signal loss and interference during transmission. After receiving the clock signal from the external clock module, the clock input pins of the two boards will send it to their internal clock circuits for processing.

[0164] The two boards process the received external clock signal and use it as a reference clock signal to synchronize the various modules and subsystems within the board. For example, in a digital communication system, the reference clock signal is used to synchronize data transmission and reception, ensuring correct data transmission.

[0165] The reference clock signal is distributed to each module within the board through a clock distribution network (such as a clock tree) to ensure that all modules use the same clock frequency and phase. Simultaneously, two boards can also be synchronized via clock signals to enable cross-board collaborative operation.

[0166] Please see Figure 17 In one possible implementation, one of the boards 1 and 2 is a master board and the other is a slave board (e.g., board 1 is the master board and board 2 is the slave board). The master board sends a clock signal in the data signal to the slave board through the data transmission channel. The slave board can recover the clock signal from the data signal and use it as a clock reference.

[0167] Please see Figure 18 This application also provides a network device, which includes the single board provided in this application. For example, one network device includes the aforementioned single board 1, and another network device includes single board 2. Single board 1 and single board 2 communicate through a high-speed serial bus with simultaneous bidirectional transmission.

[0168] Please see Figure 19 In one possible implementation, the aforementioned single board 1 and single board 2 can receive clock signals sent by an external clock module and use them as clock references.

[0169] Please see Figure 20 In one possible implementation, one of the boards 1 and 2 is a master board and the other is a slave board (e.g., board 1 is the master board and board 2 is the slave board). The master board sends a clock signal in the data signal to the slave board through the data transmission channel. The slave board can recover the clock signal from the data signal and use it as a clock reference.

[0170] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection between apparatuses or units through some interfaces, and may be electrical, mechanical, or other forms.

[0171] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0172] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0173] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

Claims

1. A single-board unit, characterized in that, Includes serial transceivers; The serial transceiver includes a hybrid circuit, which includes a transmitting circuit and a receiving circuit. The transmitting circuit is used to send the first data signal to the data transmission channel, which is used for data transmission between the single board and the peer single board. The receiving circuit is used to receive transmitted data from the data transmission channel and eliminate the first data signal from the transmitting circuit. The transmitted data includes a second data signal from the peer board, and the second data signal and the first data signal are transmitted simultaneously in the data transmission channel.

2. The single board according to claim 1, characterized in that, The transmitted data also includes the echo signal of the first data signal; The serial transceiver also includes an analog echo canceller (AEC). The AEC is used to eliminate the echo signal of the first data signal in the transmitted data.

3. The single board according to claim 2, characterized in that, The serial transceiver also includes an analog front-end module (AFE), with the analog front-end module (AEC) located at the front end of the AFE.

4. The single board according to claim 2, characterized in that, The serial transceiver also includes an analog front-end module (AFE), with the analog front-end module (AEC) located at the back end of the AFE.

5. The single board according to any one of claims 1 to 4, characterized in that, The hybrid circuit is an active driven replication circuit.

6. The single board according to any one of claims 1 to 4, characterized in that, The hybrid circuit is an inverter combined with a linear resistor circuit.

7. The single board according to any one of claims 1 to 4, characterized in that, The hybrid circuit is a passive resistance-transconductance hybrid circuit.

8. The single board according to any one of claims 2 to 4, characterized in that, The serial transceiver also includes a digital echo canceller (DEC) for eliminating the echo signal of the first data signal in the transmitted data.

9. A network device, characterized in that, It includes a first board and a second board, which communicate with each other through a data transmission channel. The first board is equipped with a first serial transceiver, and the second board is equipped with a second serial transceiver. The first serial transceiver includes a first hybrid circuit, which includes a first transmitting circuit and a first receiving circuit; the second serial transceiver includes a second hybrid circuit, which includes a second transmitting circuit and a second receiving circuit. The first transmitting circuit is used to transmit a first data signal to the data transmission channel; The second transmitting circuit is used to transmit a second data signal to the data transmission channel, wherein the first data signal and the second data signal are transmitted simultaneously in the data transmission channel; The first receiving circuit is configured to receive first transmitted data from the data transmission channel and eliminate the first data signal from the first transmitting circuit, wherein the first transmitted data includes the second data signal; The second receiving circuit is configured to receive second transmitted data from the data transmission channel and eliminate the second data signal from the second transmitting circuit, wherein the second transmitted data includes the first data signal.

10. The network device according to claim 9, characterized in that, The first transmitted data also includes the echo signal of the first data signal, and the second transmitted data also includes the echo signal of the second data signal; The first serial transceiver further includes a first analog echo canceller (AEC), and the second serial transceiver further includes a second AEC. The first AEC is used to eliminate the echo signal of the first data signal in the first transmitted data; The second AEC is used to eliminate the echo signal of the second data signal in the first transmitted data.

11. The network device according to claim 10, characterized in that, The first serial transceiver further includes a first analog front-end module (AFE), and the second serial transceiver further includes a second AFE. The first AFE is located at the front end of the first AFE, and the second AFE is located at the front end of the second AFE.

12. The network device according to claim 10, characterized in that, The first serial transceiver further includes a first AFE, and the second serial transceiver further includes a second AFE. The first AEC is located at the back end of the first AFE, and the second AEC is located at the back end of the second AFE.

13. The network device according to any one of claims 9 to 12, characterized in that, The first hybrid circuit and the second hybrid circuit are active drive replication circuits.

14. The network device according to any one of claims 9 to 12, characterized in that, The first hybrid circuit and the second hybrid circuit are inverters combined with linear resistor circuits.

15. The network device according to any one of claims 9 to 12, characterized in that, The first hybrid circuit and the second hybrid circuit are resistance-transconductance passive hybrid circuits.

16. The network device according to claim 12, characterized in that, The first serial transceiver further includes a first digital echo canceller (DEC), and the second serial transceiver further includes a second DEC. The first DEC is used to cancel the echo signal of the first data signal in the first transmitted data, and the second DEC is used to cancel the echo signal of the second data signal in the second transmitted data.

17. The network device according to any one of claims 9 to 16, characterized in that, The first board is the master board, the second board is the slave board, and the first data signal carries a clock signal. The second board is used to recover the clock signal from the first data signal and use the clock signal as a clock reference.

18. The network device according to any one of claims 9 to 16, characterized in that, The network device further includes an external clock module, which sends clock signals to the first board and the second board so that the first board and the second board use the clock signals as a clock reference.

19. The network device according to any one of claims 9 to 18, characterized in that, The data transmission channel is either a differential channel or a single-ended channel.

20. A network device, characterized in that, Includes the single board as described in any one of claims 1 to 8.

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