An FPGA prototype verification system and verification method of a power carrier communication chip

Abstract

The application mainly relates to an FPGA prototype verification system of a power carrier communication chip, which comprises a digital front-end transceiving unit, a digital-to-analog / analog-to-digital conversion unit, a received symbol processing unit, a sending rate adaptation unit and a receiving rate adaptation unit. In the sending path, the output of the digital front-end transceiving unit is sent to the digital-to-analog conversion unit after frequency increasing by the sending rate adaptation unit; in the receiving path, the output of the analog-to-digital conversion unit is processed by the digital front-end transceiving unit and then sent to the received symbol processing unit after frequency decreasing by the receiving rate adaptation unit. The receiving rate adaptation unit supports multi-channel synchronous processing, and when a synchronous start signal is detected in any channel, all channels are triggered to carry out frequency decreasing processing. The application realizes full-function and high-performance prototype verification of a higher working rate target chip, and high-quality verification is achieved at a lower hardware cost.

Description

Technical Field

[0001] This invention relates to the field of power line carrier communication technology, and specifically to an FPGA prototype verification system and verification method for a power line carrier communication chip. Background Technology

[0002] The new generation of low-voltage power line broadband carrier communication (taking China Southern Power Grid PLC2.0 as an example) adopts Turbo code-based channel encoding and decoding technology at its physical layer. Compared with the previous generation, PLC2.0 mainly adds the following functions: support for Orthogonal Frequency Division Multiple Access (OFDMA), support for Multiple-Input Multiple-Output (MIMO) technology, and support for a bitloading table. At the same time, the number of physical layer input / output ports of PLC2.0 has increased to three, and the overall number of logic gates in the chip has nearly doubled.

[0003] As chip complexity increases, the number of combinational logic gates also increases dramatically. To ensure the real-time performance of OFDM symbol processing, chips implemented in ASICs need to employ more advanced process technologies, such as 40nm or more, to reduce the risk of setup time violations. According to relevant process library documentation, the typical symbol clock frequency for the PLC2.0 carrier physical layer in ASIC implementations needs to reach or exceed 380MHz.

[0004] However, in the early FPGA prototyping stage of chip development, due to the limited internal wiring resources and relatively outdated process technology (typically 14nm and above) of mainstream FPGA platforms, their highest operating frequency (FMax) under such large-scale complex logic can usually only reach about 100MHz. Because of the huge frequency gap between the ASIC target operating frequency and the FPGA hardware limit frequency, if the FPGA verification design is not modified, synthesis tools are prone to generating numerous setup time violations during timing analysis, thus making it impossible to complete the functional and performance verification of the next-generation PLC2.0 chip.

[0005] To overcome the limitations of FPGA hardware resources, traditional prototyping methods typically employ a "system-wide frequency reduction" strategy. This involves uniformly reducing all logic clocks within the FPGA to below 100MHz to ensure timing convergence. However, this simplistic and crude system-level frequency reduction introduces several new problems: First, the data rate from the FPGA port output to the analog-to-digital / digital-to-analog converter (ADC / DAC) is severely reduced, causing a complete mismatch between the actual transmit / receive performance of the verification system and the chip's true performance under protocol requirements, failing to reflect the chip's true operating state. Second, when verifying MIMO multi-channel communication, simple overall frequency reduction cannot guarantee the alignment and synchronization of high-speed multiple signals during processing, easily leading to data loss or symbol misalignment due to clock phase deviations between channels. Finally, when verifying different frequency bands or scenarios, traditional frequency reduction often requires repeated modifications to the FPGA's cross-clock domain RTL code, resulting in slow verification version iterations and severely hindering the chip development cycle.

[0006] Therefore, how to achieve accurate and efficient prototype verification of next-generation high-frequency carrier chips while minimizing RTL code modifications, and ensure the synchronization and reliability of MIMO multi-channel signal processing, while supporting ordinary FPGA hardware resources, is a key technical problem that urgently needs to be solved in this field.

[0007] It should be noted that the information disclosed in the background section above is only for understanding the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0008] The technical problem to be solved by this invention is: "How to overcome the technical bottleneck of the mismatch between the hardware processing speed of the verification platform and the working speed of the physical layer of the communication chip, and realize the full-function prototype verification of the high-speed multi-channel carrier communication chip."

[0009] The technical solution adopted in this application to solve the above-mentioned technical problems is as follows.

[0010] This application provides an FPGA prototype verification system for a power line carrier communication chip, comprising: Digital front-end transceiver unit, digital-to-analog converter unit, analog-to-digital converter unit, receive symbol processing unit, transmit rate adaptation unit, and receive rate adaptation unit; In the transmission path, the transmission output of the digital front-end transceiver unit is connected to the digital-to-analog converter unit through the transmission rate adaptation unit. The transmission rate adaptation unit is used to upsample the transmission data output by the digital front-end transceiver unit and then output it to the digital-to-analog converter unit. In the receiving path, the receiving output of the analog-to-digital converter is connected to the receiving input of the digital front-end transceiver unit. The receiving output of the digital front-end transceiver unit is connected to the receiving symbol processing unit through the receiving rate adaptation unit. The receiving rate adaptation unit is used to receive the receiving processing data and the corresponding synchronization start signal output by the digital front-end transceiver unit, and output the receiving processing data to the receiving symbol processing unit after frequency down-conversion processing. The receive rate adaptation unit supports multi-channel synchronous processing, which is used to trigger down-frequency processing of the received data of all channels when a synchronization start signal of any channel in the receive path is detected.

[0011] In some embodiments, the transmission rate adaptation unit includes a first dual-port storage unit and a first control unit. The first control unit is used to control the first dual-port storage unit to write data at a slow clock frequency and read data at a fast clock frequency.

[0012] In some embodiments, the receive rate adaptation unit includes a second dual-port storage unit and a second control unit. The second control unit is used to control the second dual-port storage unit to write data at a fast clock frequency and read data at a slow clock frequency. The second control unit is also used to record the write address of the synchronization start signal in the second dual-port storage unit and backtrack a predetermined number of symbol lengths based on the write address to determine the read start address.

[0013] In some embodiments, multi-channel synchronization processing includes 3-channel synchronization processing in MIMO mode. When the receive rate adaptation unit detects the synchronization start signal of any one of the 3 channels, it triggers all 3 channels to perform down-frequency processing on the received data.

[0014] In some embodiments, the digital front-end transceiver unit also outputs a synchronization success pulse signal and a peak count value to the receive rate adaptation unit, and the receive rate adaptation unit is further used to output the synchronization start signal, the synchronization success pulse signal and the peak count value after uniformly reducing their speed.

[0015] In some embodiments, the FPGA prototype verification system for the power line carrier communication chip further includes a filter bandwidth switching unit. The filter bandwidth switching unit is used to generate a filter bandwidth switching interrupt signal when a synchronization success pulse signal before speed reduction is detected; and to synchronize the reception completion flag across clock domains to the first reception clock domain when a reception completion flag corresponding to the second reception clock domain is detected, so as to clear the filter bandwidth switching state in the filter bandwidth switching unit.

[0016] In some embodiments, the system further includes an MCU interactive buffer unit, a transceiver decoding unit, and a transmit symbol processing unit; the MCU interactive buffer unit is connected to the transceiver decoding unit, the transceiver decoding unit is connected to the transmit symbol processing unit, and the transmit symbol processing unit is connected to the transmit input of the digital front-end transceiver unit; the receive symbol processing unit is also connected to the transceiver decoding unit, and the transceiver decoding unit is also connected to the MCU interactive buffer unit.

[0017] In some embodiments, the transceiver decoding unit includes a scrambling submodule, a Turbo-coded interleaving submodule, and a channel interleaving submodule; For the transmission path: when the data input to the transceiver decoding unit is frame control data, the frame control data bypasses the scrambling submodule and is processed sequentially through the Turbo coding interleaving submodule and the channel interleaving submodule; when the data input to the transceiver decoding unit is payload data, the payload data is processed sequentially through the scrambling submodule, the Turbo coding interleaving submodule and the channel interleaving submodule. For the receiving path: when the data decoded by the transceiver decoding unit is frame control data, the frame control data is processed sequentially through the channel deinterleaving submodule and the Turbo decoding submodule, and then sent to the MCU interactive buffer unit; when the data decoded by the transceiver decoding unit is payload data, the payload data is processed sequentially through the channel deinterleaving submodule, the Turbo decoding submodule and the descrambling submodule, and then sent to the MCU interactive buffer unit.

[0018] In some embodiments, the down-frequency processing performed by the receive rate adaptation unit includes: reducing the rate of the received processing data output by the digital front-end transceiver unit to 1 / 4 or 1 / 8; the up-frequency processing performed by the transmit rate adaptation unit includes: increasing the rate of the transmit data output by the digital front-end transceiver unit to twice the normal rate.

[0019] In some embodiments, a verification method is also provided that utilizes the FPGA prototype verification system of the power line carrier communication chip of the present invention, comprising the following steps: In the transmission path, the transmission data output by the digital front-end transceiver unit is upsampled by the transmission rate adaptation unit and then transmitted to the digital-to-analog converter unit. In the receiving path, the digital signal converted by the analog-to-digital converter is input to the digital front-end transceiver unit; the receiving rate adaptation unit receives the receiving processing data and the corresponding synchronization start signal output by the digital front-end transceiver unit, and outputs the receiving processing data to the receiving symbol processing unit after frequency down-conversion processing. In the multi-channel synchronous processing mode supported by the receiving rate adaptation unit, the synchronization start signal of any channel in the receiving path is detected, and when the synchronization start signal is detected, the receiving processing data of all channels is triggered to perform down-frequency processing.

[0020] The present invention has the following beneficial effects: First, this invention sets up a transmission rate adaptation unit, which receives transmitted data from the digital front-end transceiver unit and performs up-frequency processing. By increasing the data rate before digital-to-analog conversion, the analog signal output by the digital-to-analog conversion unit can reach a higher frequency required for the operation of the chip's physical layer. This overcomes the bottleneck of the limited maximum operating frequency of the logic inside the FPGA platform and achieves the effect of verifying high-speed transmission function on ordinary FPGA hardware. Secondly, by setting up a receive rate adaptation unit, which receives the received processing data and corresponding synchronization start signal from the digital front-end transceiver unit and performs frequency reduction processing, the high-speed received data stream is slowed down before entering the subsequent complex receive symbol processing unit. This significantly reduces the timing pressure on subsequent processing modules and effectively avoids establishment time violations caused by high-frequency processing in the receive path, ensuring the stability and correctness of the receive link. Furthermore, the receive rate adaptation unit has multi-channel synchronous processing capabilities. By monitoring the synchronization start signal of any channel, it triggers all channels to perform frequency reduction processing. This mechanism ensures that in multi-channel (such as MIMO) application scenarios, the data of each channel can maintain phase alignment and synchronous processing, preventing data loss or processing errors caused by slight delay differences in signals of each channel, and ensuring the complete verification of multi-channel functions.

[0021] Ultimately, the aforementioned transmit rate adaptation unit, receive rate adaptation unit, and their multi-channel synchronous processing functions, along with the digital front-end transceiver unit, digital-to-analog converter, analog-to-digital converter, and receive symbol processing unit, cooperate and coordinate to form a complete rate adaptation prototype verification architecture. This architecture, by introducing configurable rate conversion nodes at key locations in the transmit and receive paths, successfully achieves full-function, high-performance prototype verification of target chips with higher operating speeds on an FPGA verification platform with limited processing capabilities, achieving the goal of completing high-quality verification at a lower hardware cost.

[0022] Other beneficial effects of the present invention will be further described below. Attached Figure Description

[0023] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 This is an overall architecture diagram of the next-generation power line carrier communication chip FPGA prototype verification system according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the composition and synchronization position of the HPLC leader symbols in an embodiment of the present invention, showing the leader frame structure of the SYNCP and SYNCM segments; Figure 3 This is a schematic diagram of the transmission rate adaptation unit (transmission upsampling module) in an embodiment of the present invention, including a dual-port RAM 1024K×36_2p and corresponding transmission clock A and B control interfaces; Figure 4 This is a schematic diagram of the receiving rate adaptation unit (receiving down-frequency module) in an embodiment of the present invention, including a dual-port RAM 1024K×64_2p, a synchronization start / success input, and a filter bandwidth switching flag output interface; Figure 5 This is a schematic diagram of the key timing waveforms when the transmission rate adaptation unit performs transmission upsampling processing in an embodiment of the present invention. It shows in detail the timing correspondence between transmission clocks 1 and 2, transmission enable, RAM write / read address and data. Detailed Implementation

[0024] The embodiments of the present invention will be described in detail below. It should be emphasized that the following description is merely exemplary and not intended to limit the scope and application of the present invention.

[0025] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of the present invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0026] In existing FPGA prototyping, the frequency limits of the hardware platform often limit the verification process. Simply using system-level frequency reduction to circumvent timing violations frequently leads to inaccurate protocol performance verification and, in MIMO multi-channel scenarios, data loss is easily caused by phase asynchrony between channels. These problems arise because existing solutions fail to recognize that the low-speed processing logic within the system and the communication interface of the external physical layer can be functionally decoupled using independent rate adaptation units. Based on this understanding, this invention abandons the conventional thinking of frequency reduction and constructs a verification system that separates high and low speed clock domains: In the transmission path, the "transmission rate adaptation unit" performs "frequency up-processing" on the "transmitted data" output by the "digital front-end transceiver unit" to ensure that the signal output to the "digital-to-analog converter unit" meets the high-frequency requirements of the protocol; In the reception path, the "reception rate adaptation unit" receives the "synchronization start signal" and immediately links all channels to perform "frequency down-processing" on the "received processing data" when the signal is triggered on any channel. Thus, while ensuring that the FPGA's internal logic operates at a low frequency and can be stably synthesized, accurate and efficient verification of multi-channel high-speed carrier communication chips is achieved.

[0027] The technical solution of the present invention will be described in detail below.

[0028] In some embodiments, the FPGA prototype verification system for the power line carrier communication chip of the present invention includes a digital front-end transceiver unit, a digital-to-analog converter (DAC), an analog-to-digital converter (ADC), a receive symbol processing unit, a transmit rate adaptation unit, and a receive rate adaptation unit. In the transmit path, the transmit output of the digital front-end transceiver unit is connected to the DAC via the transmit rate adaptation unit. In the receive path, the receive output of the ADC is connected to the receive input of the digital front-end transceiver unit, and the receive output of the digital front-end transceiver unit is connected to the receive symbol processing unit via the receive rate adaptation unit. Furthermore, the receive rate adaptation unit supports multi-channel synchronous processing.

[0029] When the transmit path is operational, the digital pre-amplifier transceiver unit processes the transmit data and outputs it to the transmit rate adaptation unit. The transmit rate adaptation unit then upscales the transmit data output from the digital pre-amplifier transceiver unit and outputs it to the digital-to-analog converter unit, thereby decoupling the low-speed processing clock domain inside the FPGA from the high-speed output rate of the external interface. When the receive path is operational, the analog-to-digital converter unit converts the external analog signal into a digital signal and inputs it to the receive input of the digital pre-amplifier transceiver unit. The digital pre-amplifier transceiver unit processes the signal and outputs the processed receive data and the corresponding synchronization start signal to the receive rate adaptation unit. The receive rate adaptation unit receives the processed data and the synchronization start signal, downscales the processed receive data, and outputs it to the receive symbol processing unit. Simultaneously, the receive rate adaptation unit continuously monitors the status of each channel in the receive path. Once it detects the synchronization start signal of any channel in the receive path, it immediately triggers all channels to simultaneously perform downscale processing on their processed receive data.

[0030] It is understood that by arranging transmission rate adaptation units and reception rate adaptation units on the transmission path and reception path respectively, the present invention enables the FPGA core logic module to operate at a lower clock frequency to avoid setup time violations. Under the premise of ensuring timing convergence, rate matching is achieved only at the external port through frequency upsampling and downsampling, ensuring the protocol consistency of the carrier signal. At the same time, the reception rate adaptation unit effectively eliminates the loss and misalignment of multiple data paths that may be caused by the phase difference of signal arrival between different physical channels by the linkage detection and synchronous downsampling of the multi-channel synchronization start signal.

[0031] In some embodiments, the transmit rate adaptation unit and the receive rate adaptation unit can be implemented using first-in-first-out (FIFO) memory or asynchronous dual-port memory, depending on the actual situation. The up-frequency and down-frequency ratios can also be adaptively adjusted according to different protocols. Multi-channel synchronous processing is not physically limited to 3-channel MIMO scenarios, but can also be extended to 2-channel or 4-channel synchronous processing scenarios. Furthermore, its linkage triggering method can be either real-time response using hardware logic or mode switching through configuration registers.

[0032] In some embodiments, the transmission rate adaptation unit is further described. Exemplarily, the transmission rate adaptation unit includes a first dual-port storage unit and a first control unit. The first control unit is connected to the write port and read port of the first dual-port storage unit, respectively. During transmission path operation, the transmission data output by the digital front-end transceiver unit is sent to the first dual-port storage unit. The first control unit controls the first dual-port storage unit to write data at a slow clock frequency. After the data buffer is complete, the first control unit switches the control logic to read the buffered transmission data in the first dual-port storage unit at a fast clock frequency, thereby achieving physical upsampling of the transmission data through the difference between the read and write clock frequencies.

[0033] It is understood that, through the cooperation of the first dual-port storage unit and the first control unit, the transmission rate adaptation unit of the present invention can utilize the inherent asynchronous read and write port characteristics of the dual-port memory to stably and efficiently transmit transmission data from the low-speed core clock domain of the FPGA to the high-speed external interface clock domain without adding complex handshake signals.

[0034] In some embodiments, the first dual-port storage unit may be composed of block random access memory (BRAM) or distributed random access memory (DRAM) embedded inside the FPGA; the ratio between the slow clock frequency and the fast clock frequency of the first control unit is not limited to 2 times, but can also be set to 4 times or 8 times according to different communication carrier frequency band requirements. This ratio is mainly changed in real time through the register configuration in the first control unit.

[0035] In some embodiments, the receive rate adaptation unit is further described. Exemplarily, the receive rate adaptation unit includes a second dual-port storage unit and a second control unit. The second control unit is connected to the write port and read port of the second dual-port storage unit, and has address recording and calculation functions. During receive path operation, the received processing data output by the digital front-end transceiver unit and the corresponding synchronization start signal enter the receive rate adaptation unit. The second control unit controls the second dual-port storage unit to write data at a fast clock frequency. During data writing, the second control unit detects and records the write address of the synchronization start signal in the second dual-port storage unit in real time. When downclocking is required, the second control unit uses this write address as a reference to backtrack a predetermined number of symbol lengths (e.g., backtracking 13 OFDM symbol lengths according to the protocol preamble structure) to determine the read start address, and controls the second dual-port storage unit to start reading data at a slow clock frequency based on this read start address.

[0036] It is understood that by recording the write address of the synchronization start signal and backtracking based on it, the present invention can accurately locate the start position of the valid data frame, prevent the frame header data from being incomplete or truncated due to down-frequency extraction, and ensure that the receiving symbol processing unit obtains a complete and aligned data block.

[0037] In some embodiments, the "predetermined number of symbol lengths" for backtracking by the second control unit can be configured according to the frame preamble structure of different communication protocols, for example, adjusted to backtrack a different number of preamble symbols in non-baseband mode; the second dual-port storage unit can also be replaced by an external asynchronous memory or an internal FIFO combined with an address pointer.

[0038] In some embodiments, the multi-channel synchronization processing is further described. For example, multi-channel synchronization processing specifically covers three-channel synchronization processing in MIMO mode. The input port of the receive rate adaptation unit simultaneously corresponds to the received processing data of the three channels and the synchronization start signals of the three channels. When the verification system is in MIMO receive mode, the receive rate adaptation unit monitors the data input of its three channels in real time. For example, when the first channel captures a valid preamble signal and triggers the synchronization start signal before the second and third channels, the receive rate adaptation unit, after detecting the synchronization start signal of that channel, immediately uses this event as a global trigger command, simultaneously triggering the synchronous down-frequency processing of the received processing data of all three channels.

[0039] It is understood that, in the scenario of MIMO multi-antenna reception, even if there is a time difference in signal arrival caused by spatial propagation delay in the three physical channels, the present invention can ensure that the data of all channels are synchronously down-frequencyd within the same time window, thereby ensuring the phase alignment accuracy of subsequent MIMO channel estimation and symbol processing.

[0040] It should be noted that the number of channels can be expanded to 2 or 4 depending on the actual FPGA prototype verification platform or the change in communication standard. The above "3 channels" is a typical application under the PLC2.0 standard, which corresponds to the number of physical layer input ports.

[0041] In some embodiments, the signal transmission between the digital front-end transceiver unit and the receive rate adaptation unit is further described. Exemplarily, in addition to transmitting received processing data and a synchronization start signal, the digital front-end transceiver unit also outputs a synchronization success pulse signal and a peak count value to the receive rate adaptation unit. During synchronization detection, the digital front-end transceiver unit not only outputs the original received processing data and the synchronization start signal, but also, after successfully completing synchronization positioning, sends a synchronization success pulse signal and a relevant peak count value indicating the strength of the received signal to the receive rate adaptation unit. Upon receiving the above signals, the receive rate adaptation unit uniformly reduces the speed of the synchronization start signal, the synchronization success pulse signal, and the peak count value within the same down-frequency processing cycle and synchronously outputs them to the subsequent receive symbol processing unit.

[0042] It is understood that the present invention uniformly reduces the speed of the synchronization start, synchronization success pulse and peak count value, which can ensure that the data packets obtained by the subsequent modules and the accompanying control status information maintain strict consistency on the time axis, avoid the loss of control signal pulses or state misalignment caused by the frequency domain change due to speed reduction, and improve the reliability of the verification process.

[0043] It should be noted that the control signal for the unified speed reduction output is not limited to the three types mentioned above, and may also include other auxiliary measurement signals such as channel energy indication and phase offset indication.

[0044] In some embodiments, the FPGA prototype verification system for the power line carrier communication chip further includes a filter bandwidth switching unit, which is connected to the corresponding signal output terminal of the receive rate adaptation unit. During system operation, the filter bandwidth switching unit continuously monitors the synchronization success pulse signal before the rate reduction. Once this signal is detected, a filter bandwidth switching interrupt signal is immediately generated and sent to the software for processing. The software completes the bandwidth switching in the interrupt service routine. During reception, when the system detects the reception completion flag corresponding to the second receive clock domain (low-speed domain), it indicates that the reception task of the current frame has ended. At this time, the reception completion flag needs to be synchronized across clock domains to the first receive clock domain (high-speed domain) to clear the filter bandwidth switching state currently stored in the filter bandwidth switching unit, so that the receive filter is restored to the initial maximum bandwidth state, waiting for subsequent signal processing.

[0045] It is understood that the present invention achieves dynamic management of the receiving filter through the above settings. During data frame reception, the bandwidth is switched by interruption to ensure anti-interference capability. After the frame reception ends, the bandwidth status is automatically reset without additional manual reset or complex clock domain control, thus avoiding interference with the reception of subsequent communication frames due to bandwidth error switching.

[0046] In some embodiments, the triggering condition for generating the filter bandwidth switching interrupt signal can be, in addition to detecting a synchronization success pulse signal, the detection of a specific preamble or protocol indicator bit of a specified frame type; the triggering signal for clearing can be either detecting a reception completion flag or forcibly clearing it after the timeout timer expires.

[0047] In some embodiments, the FPGA prototype verification system for the power line carrier communication chip further includes an MCU interactive buffer unit, a transceiver decoding unit, and a transmit symbol processing unit. The MCU interactive buffer unit is connected to the transceiver decoding unit; the transceiver decoding unit is connected to the transmit symbol processing unit; the transmit symbol processing unit is connected to the transmit input of the digital front-end transceiver unit; simultaneously, the receive symbol processing unit is also connected to the transceiver decoding unit, and the transceiver decoding unit is also connected to the MCU interactive buffer unit.

[0048] In the complete transmission verification process, control commands from the external MCU and the data to be transmitted are first buffered in the MCU interaction buffer unit, then sent to the transceiver decoding unit for channel coding. The encoded data enters the transmit symbol processing unit for OFDM symbol-level processing, and finally is sent to the digital front-end transceiver unit for pre-processing and output through the transmit rate adaptation unit. In the receive verification process, the data after symbol processing by the receive symbol processing unit is sent to the transceiver decoding unit for channel decoding. The decoded data is finally sent back to the MCU interaction buffer unit for the external MCU to read.

[0049] It is understood that by connecting the MCU interactive buffer, transceiver decoding and symbol processing unit at the system front end to the digital front-end transceiver unit, the present invention constructs a complete closed-loop path from the data source to the physical layer front end, enabling the prototype verification system to directly run the full protocol stack functions of the chip from the application layer to the physical layer on the FPGA hardware without external software simulation, thus greatly improving the comprehensiveness of the verification.

[0050] In some embodiments, the MCU interactive buffer unit, transceiver decoding unit, and transmit symbol processing unit can be implemented using an integrated single-chip processing core or functional module, and are not necessarily limited to physically separated modules.

[0051] In some embodiments, the transceiver decoding unit specifically includes a scrambling submodule, a Turbo coding interleaving submodule, a channel interleaving submodule, a channel deinterleaving submodule, a Turbo decoding submodule, and a descrambling submodule. During transmission, if the data input to the transceiver decoding unit is frame control data, then the frame control data bypasses the scrambling submodule and is directly encoded sequentially through the Turbo coding interleaving submodule and the channel interleaving submodule; if the data input to the transceiver decoding unit is payload data, then the payload data is encoded sequentially through the scrambling submodule, the Turbo coding interleaving submodule, and the channel interleaving submodule. During the receiving path, when the data decoded by the transceiver decoding unit is frame control data, the frame control data is processed sequentially by the channel deinterleaving submodule and the Turbo decoding submodule, and then directly sent to the MCU interactive buffer unit without passing through the descrambling submodule. When the data decoded by the transceiver decoding unit is payload data, the payload data is processed sequentially by the channel deinterleaving submodule, the Turbo decoding submodule, and finally by the descrambling submodule before being sent to the MCU interactive buffer unit.

[0052] It is understood that the present invention implements different bypass or scrambling / descrambling processing paths for frame control data and payload data, accurately simulating the chip's requirements for different encoding / decoding and scrambling strategies for frame headers and payloads in physical layer protocol processing, so that the output results of the prototype verification system have extremely high protocol consistency.

[0053] In some embodiments, bypassing the scrambling or descrambling submodule can be achieved by setting a multiplexer in the data path and switching it in conjunction with the frame type flags for transmission / reception.

[0054] In some embodiments, the rate of the received processing data output by the digital front-end transceiver unit is down-frequencyed to 1 / 4 or 1 / 8; the up-frequency processing performed by the transmit rate adaptation unit includes: up-frequencying the transmit data output by the digital front-end transceiver unit to twice the original rate. In actual system operation, depending on the carrier center frequency, the down-frequency processing performed by the receive rate adaptation unit can reduce the rate of the received processing data output by the digital front-end transceiver unit to 1 / 4 or 1 / 8 of the original rate. For example, in non-baseband mode, the ADC sampling clock is 100MHz, and the data rate input to the receive rate adaptation unit is down-frequencyed to 1 / 4 of the original frequency (i.e., 25MHz) to adapt to the internal low-speed logic. In the transmit path, the up-frequency processing performed by the transmit rate adaptation unit can up-frequency the transmit data output by the digital front-end transceiver unit to twice the original rate, for example, increasing the internal 25MHz data rate to 50MHz to match the DAC's working sampling requirements.

[0055] It is understood that by setting specific up / down frequency parameters (such as 1 / 4, 1 / 8, and 2 times), the system can accurately adapt to the two typical signal transmission scenarios of baseband and non-baseband in China Southern Power Grid PLC2.0, providing a standardized configuration reference for different test cases of carrier chips.

[0056] It should be noted that the ratio of up-clocking to down-clocking is not limited to the values ​​mentioned above. When the external physical layer protocol requirements change, other up-clocking and down-clocking ratios (such as 4x up-clocking or 1 / 16 down-clocking) can be configured in the register.

[0057] In some embodiments, a verification method implementing the aforementioned system is also provided. This method relies on the FPGA prototype verification system for the aforementioned power line carrier communication chip. Exemplarily, the specific workflow of this verification method is as follows: Regarding the transmission path step, in this step, the transmission data output from the digital front-end transceiver unit is up-frequency processed by the transmission rate adaptation unit and then transmitted to the digital-to-analog converter unit, thus balancing the internal low-speed synthesis logic with the external high-speed transmission requirements. Regarding the reception path step, in this step, the digital signal converted by the analog-to-digital converter unit is input to the digital front-end transceiver unit; subsequently, the reception processing data output from the digital front-end transceiver unit and the corresponding synchronization start signal are received through the reception rate adaptation unit, and the reception processing data is down-frequency processed and output to the reception symbol processing unit. Regarding the multi-channel synchronization processing step, in the multi-channel synchronization processing mode supported by the reception rate adaptation unit, the synchronization start signal of any channel in the reception path is detected in real time. Once the synchronization start signal of any channel is detected, the reception processing data of all channels are immediately triggered to simultaneously perform down-frequency processing.

[0058] It is understood that by constructing independent up-frequency and down-frequency processing flows, this invention achieves seamless connection between the slow logic inside the FPGA prototype verification platform and the high-speed communication of the external interface from the perspective of operation steps. In particular, through the dynamic detection and linkage triggering of the multi-channel synchronization processing steps, it ensures that the MIMO multi-channel receiver has extremely high synchronization alignment accuracy during the down-frequency process, thereby realizing comprehensive and reliable verification of high-frequency multi-channel carrier communication chips on ordinary FPGA hardware.

[0059] In some embodiments, the up-frequency processing and down-frequency processing in the verification method can be implemented using a software-programmable lookup table method or a hardware multiplier-accumulator. The detection of the synchronization start signal can also be achieved by configuring the synchronization matching threshold under different protocols to adapt to the frequency band configuration of different carrier test scenarios.

[0060] The present application will be further described below with reference to the accompanying drawings and specific embodiments.

[0061] It should be noted that the specific terms such as "module," "domain," "interleaving," and "decoding" in the following description, as well as specific examples such as "RAM1024K×36_2p," "RAM1024K×64_2p," and "13 OFDM symbol lengths," are intended to provide illustrative examples of the present invention. Those skilled in the art will understand that the above specific terms and implementation structures should not be construed as limiting the corresponding concepts of "unit," "storage unit," "frequency," "symbol length," and "processing" in the present invention. For example, the "transmit up-frequency module" and "receive down-frequency module" in this embodiment are specific implementations of the "transmit rate adaptation unit" and "receive rate adaptation unit" in the present invention; the "digital front-end transceiver module," "receive OFDM symbol processing module," "transmit OFDM symbol processing module," "transmit / receive decoding module," and "MCU and transceiver subsystem interaction buffer" respectively correspond to the "digital front-end transceiver unit," "receive symbol processing unit," "transmit symbol processing unit," "transmit / receive decoding unit," and "MCU interaction buffer unit" in the present invention. "Multi-channel linkage synchronous processing" is also only one execution method of "multi-channel synchronous processing" in this embodiment.

[0062] Similarly, in this embodiment, the first dual-port storage unit and the second dual-port storage unit can be implemented using dual-port RAM of type "RAM1024K×36_2p" and "RAM1024K×64_2p" respectively; the slow clock frequency and the fast clock frequency can be implemented in the form of "transmit clock 1 (receive clock B)" and "transmit clock 2 (receive clock A)" respectively in terms of specific timing, and the specific clock frequency should be determined according to the actual verification mode (such as baseband / non-baseband); the predetermined number of symbol lengths in this embodiment is exemplarily implemented using the length of 13 OFDM symbols for backtracking.

[0063] The specific forms, structures, frequency values, number of symbols, and specific names described above are merely illustrative examples. After reading this application, those skilled in the art can fully implement alternative methods without departing from the concept of this invention, using other names, other hardware architectures, other storage depths, other clock frequency allocations, or other numbers of symbol lengths that have the same or equivalent functions. All such alternative implementation methods fall within the protection scope of this invention.

[0064] Example 1: System Overall Architecture and Basic Function Verification This embodiment provides an FPGA prototype verification system for a power line carrier communication chip. The system includes: a digital front-end transceiver unit, a digital-to-analog converter unit, an analog-to-digital converter unit, a receive symbol processing unit, a transmit rate adaptation unit, and a receive rate adaptation unit.

[0065] In the transmission path, the transmit output of the digital front-end transceiver unit is connected to the digital-to-analog converter unit via a transmit rate adaptation unit. The transmit rate adaptation unit is used to upsample the transmit data output from the digital front-end transceiver unit before outputting it to the digital-to-analog converter unit. In the receiving path, the receiving output of the analog-to-digital converter is connected to the receiving input of the digital front-end transceiver unit, and the receiving output of the digital front-end transceiver unit is connected to the receiving symbol processing unit through the receiving rate adaptation unit. The receiving rate adaptation unit is used to receive the received processing data and the corresponding synchronization start signal output by the digital front-end transceiver unit, and outputs the received processing data to the receiving symbol processing unit after down-frequency processing.

[0066] In chip transmit mode, the bitstream output by the digital front-end transceiver module bypasses the transmit upsampling module and is directly transmitted to the analog-to-digital / digital-to-analog converter module. When the system is in FPGA prototype verification transmit mode, the bitstream generated by the digital front-end transceiver module is first rate-adapted by the transmit upsampling module before being transmitted to the analog-to-digital / digital-to-analog converter module. In chip receive mode, the signal processed by the digital front-end transceiver module is directly passed to the receive OFDM symbol processing module for preamble averaging and other subsequent operations. In FPGA prototype verification receive mode, the signal processed by the digital front-end transceiver module must first be processed by the receive downsampling module before being sent to the receive OFDM symbol processing module.

[0067] The receive rate adaptation unit supports multi-channel synchronous processing. Specifically, when a synchronization start signal of any channel (e.g., phase A, phase B, or phase C in MIMO mode) is detected in the receive path, it triggers down-frequency processing of the received data of all three channels, ensuring the synchronization and consistency of the multi-channel data.

[0068] The connection relationship and high / low speed domain isolation principle in this embodiment like Figure 1 The system architecture diagram shown can be divided into two clock domains: high and low. The digital front-end transceiver unit (DFE) operates at a slow clock speed to ensure that the FPGA's internal routing time meets the setup time requirements. On the transmit path, the transmit rate adaptation unit (transmit upsampling module) buffers the transmit data from the slow domain into a dual-port memory and reads it out at twice the rate in the fast transmit clock domain, delivering it to the digital-to-analog converter (DAC). On the receive path, the high-speed data stream converted by the analog-to-digital converter (ADC) first enters the receive rate adaptation unit (receive downsampling module), which writes the received data into the dual-port memory. When the synchronization start signal of any channel is captured, the corresponding RAM write address is calculated and the duration of 13 OFDM symbols is traced back (e.g., ...). Figure 2The preamble frame structure shown is followed by data and associated control signals that are uniformly reduced in speed (1 / 4 or 1 / 8) under a slow receive clock domain and delivered to the subsequent OFDM symbol processing module. This decoupled architecture enables full-function verification of high-frequency physical layer protocol signals on a low-frequency FPGA hardware platform.

[0069] Example 2: Complete signal processing flow of the transmitting and receiving ends This embodiment details the complete data flow steps between the transmitting and receiving ends during system operation. In this embodiment, the system also includes an MCU interactive buffer unit, a transceiver decoding unit, and a transmit symbol processing unit; the MCU interactive buffer unit is connected to the transceiver decoding unit, the transceiver decoding unit is connected to the transmit symbol processing unit, and the transmit symbol processing unit is connected to the transmit input of the digital front-end transceiver unit; the receive symbol processing unit is also connected to the transceiver decoding unit, and the transceiver decoding unit is also connected to the MCU interactive buffer unit.

[0070] (a) Processing flow at the sending end At the transmitting end, the carrier transmission steps include: configuring parameters and writing the frame control and payload of the carrier to be transmitted into the transmission buffer; Step S1: When the input data is frame control data, the frame control data bypasses the scrambling submodule and is processed sequentially through the Turbo coding interleaving submodule and the channel interleaving submodule. Step S2: When the input data is payload data, the payload data is processed sequentially through the scrambling submodule, the Turbo coding interleaving submodule, and the channel interleaving submodule. Step S3: After the transceiver encoding and decoding module completes the encoding of the frame control or payload data, it outputs the data to the transmit OFDM symbol processing module for further processing. Step S4: The bit stream processed by the OFDM symbol processing module will be transmitted to the digital front-end transceiver module; Step S5: In chip transmission mode, the code stream output by the digital front-end transceiver module will bypass the upsampling module and be directly transmitted to the analog-to-digital / digital-to-analog converter module. Step S6: When the system is in the FPGA prototype verification sending state, the code stream generated by the digital front-end transceiver module will first be rate-adapted by the sending up-frequency module and finally transmitted to the analog-to-digital / digital-to-analog converter module.

[0071] (Note: S1 and S2 cannot be performed simultaneously, and S5 and S6 cannot be established simultaneously; after the carrier transmission code stream passes through the analog-to-digital / digital-to-analog conversion module, it can be transmitted to the receiving end via coaxial cable.) More specifically, the instant delivery workflow is as follows: 1) After configuring parameters such as transmission bandwidth and channel, write the frame control information and payload data to be transmitted into the interaction buffer between the MCU and the transceiver subsystem; 2) Frame control data skips the scrambling submodule and sequentially completes Turbo coding, channel interleaving, EPIS interleaving, ROBO interleaving (A / B / C phase), bit-loading ROBO interleaving, and mapping control; 3) The data enters the OFDM symbol processing module and sequentially performs processing such as RAM1 buffering, inverse fast Fourier transform (IFFT), RAM2 buffering, MIMO spatial mapping, adding cyclic prefix (CP) and windowing (A / B / C phases), and transmission buffering (A / B / C phases); 4) Data enters the digital front-end transceiver module (A / B / C phases) to complete operations such as symbol splicing; 5) Data enters the transmission upsampling module (A / B / C phases), and after frequency multiplication, it is output to the coaxial cable by the analog-to-digital / digital-to-analog converter module (A / B / C phases).

[0072] (II) Receiving end processing flow At the receiving end, the carrier reception steps include: Step S7: The analog-to-digital / digital-to-analog converter module converts the analog signal input from the coaxial cable into a digital signal and transmits it to the digital front-end transceiver module. Step S8: In chip receiving mode, the signal processed by the digital front-end transceiver module is passed directly to the OFDM symbol processing module to perform subsequent operations such as preamble averaging filtering. Step S9: In FPGA prototype verification receiving mode, the signal processed by the digital front-end transceiver module needs to be processed by the receiving down-frequency module before being sent to the receiving OFDM symbol processing module to perform subsequent operations such as preamble averaging filtering. Step S10: The data output by the OFDM symbol processing module is transmitted to the transceiver decoding module to complete subsequent processing such as demapping; Step S11: When the data decoded by the transceiver decoding unit is frame control data, it is directly sent to the interaction buffer between the MCU and the transceiver subsystem after channel deinterleaving and Turbo decoding. Step S12: When the data obtained by the transceiver decoding unit is payload data, it needs to be processed by the descrambling submodule after channel deinterleaving, Turbo decoding, and then sent to the interactive buffer between the MCU and the transceiver subsystem.

[0073] More specifically, the receiving workflow is as follows: 1) After configuring parameters such as receiving bandwidth and receiving channel, the carrier signal is transmitted from the analog-to-digital / digital-to-analog converter module (A / B / C phase) to the digital front-end transceiver module (A / B / C phase). 2) After the digital front-end transceiver module (A / B / C phase) completes synchronization detection and other operations in sequence, it inputs the carrier signal and related control signals to the receiving down-frequency module (A / B / C phase). 3) Within the OFDM symbol processing module, the data is processed sequentially through the receive buffer, interactive FIFO, preamble filter, and TF signal-to-noise ratio estimation submodule. 4) If MIMO channel estimation is used, the data after A / B / C phase filtering enters the MIMO signal estimation submodule; if SISO channel estimation is used, the relevant data passes through symbol processing, RAM3 buffer, and SISO signal estimation submodule in sequence. 5) If the output is SISO channel estimation, the symbol-processed data is directly passed to the EPIS deinterleaving, ROBO deinterleaving, and Bit-loading ROBO deinterleaving modules. If the output is MIMO channel estimation, demapping must be completed before EPIS deinterleaving. Subsequently, the data sequentially undergoes channel deinterleaving, Turbo decoding, scrambling (note: this process does not apply to frame control data), OFDM symbol calculation, PFH decoding, and CRC check. Finally, the data is written into the interactive buffer between the MCU and the transceiver subsystem, thus completing the frequency downsampling reception process.

[0074] Example 3: Specific circuit implementation and parameter control of the upsampling module This embodiment describes a preferred hardware implementation structure for the transmission rate adaptation unit. For example... Figure 3 As shown, the transmission rate adaptation unit includes a first dual-port storage unit and a first control unit. The first dual-port storage unit can be a dual-port RAM memory with a specification of 1024K×36. The first control unit is used to control the memory to write data at a slow clock frequency (e.g., transmit clock 1, used for protocol layer logic) and read data at a fast clock frequency (e.g., transmit clock 2, used for DAC interface).

[0075] No new state machine is needed for the upsampling transmission section. After enabling tx_en_1x, the address is written after the rising edge and incremented to wr_max in each transmission clock cycle 1. The value of wr_max is latched on the falling edge of enabling tx_en_1x. The output enable tx_en_2x is set high after the falling edge of tx_en_1x, and the address ram_rd_addr is read and incremented by 1 in each transmission clock cycle 2. When ram_rd_addr increments to the latched value of wr_max, tx_en_2x is cleared and the ABC3 phase data ram_dout has been transmitted. Figure 5A schematic diagram of the transmission upsampling timing is shown, illustrating the relationship between each signal (transmission clock 1, transmission clock 2, tx_en_1x, tx_en_2x, ram_wr_addr, ram_din, ram_rd_addr, ram_dout) and its state (idle, preamble, frame control, training frame, payload).

[0076] In this embodiment, the actual write and read frequencies of the transmit upsampling module are configured according to the current verification mode. In baseband mode, transmit clock 1 is 12.5MHz and transmit clock 2 is 25MHz; in non-baseband mode, transmit clock 1 is 25MHz and transmit clock 2 is 50MHz. The carrier frequency is uniformly upsampled in both baseband and non-baseband modes. In baseband mode, the transmit fast clock is 25MHz and the DAC operates at 50MHz; in non-baseband mode, the transmit fast clock is 50MHz and the DAC operating clock is 100MHz, thus meeting the Nyquist sampling requirements.

[0077] Regarding the configuration of the transmit RAM storage depth, the actual theoretical depth should be configured to 1460K (the theoretical maximum depth for baseband data is...). 725,716: 13*1024+12*(1024+458)+12*(1024+264)+16*(1024+264)+511*(1024+264)+2*(458-264)=725716; (For non-baseband, multiply by 2, the maximum is approximately 1450K). This embodiment uses a 1024K specification, mainly to balance FPGA synthesis speed and meet most verification scenarios.

[0078] Example 4: Specific circuit implementation of the receiver down-conversion module, multi-channel linkage and bandwidth switching mechanism This embodiment describes the hardware implementation structure of the receiving rate adaptation unit and its multi-channel linkage logic.

[0079] like Figure 4 As shown, the receive rate adaptation unit includes a second dual-port storage section and a second control section. The second dual-port storage section can be a dual-port RAM memory with a specification of 1024K×64. The second control section is used to control the memory to write data at a fast clock frequency (e.g., receive clock A, determined by the ADC input, such as 100MHz) and read data at a slow clock frequency (e.g., receive clock B, used for subsequent OFDM processing modules, such as 25MHz / 50MHz).

[0080] (a) Synchronous positioning and speed reduction processing like Figure 2As shown, a typical preamble frame for next-generation power line carrier consists of 13 OFDM symbols (SYNCP and SYNCM segments). During normal reception, the receiver detects the synchronization start signal in the SYNCP segment and the synchronization success signal in the second SYNCM segment.

[0081] The new generation power line carrier receiver downsampling module works in conjunction with the digital front-end transceiver module to achieve synchronization detection. All input data is written into the dual-port RAM in the receiver downsampling module based on the receive clock A domain. The system records the RAM write address corresponding to the synchronization start signal and uses this address as a reference to trace back 13 OFDM symbols to determine the RAM read start address. Regarding data rate conversion, every two receive clock A cycles correspond to one valid original input data flag at the input end; the output end can be configured to have one valid output data flag every eight or sixteen receive clock A cycles. Similarly, output data, synchronization start, synchronization success, and related peak count values ​​are all uniformly downsampled to 1 / 4 or 1 / 8 of the original data rate before being output sequentially. The second control unit records the write address of the synchronization start signal in the second dual-port storage unit and uses this write address as a reference to trace back a predetermined number (e.g., 13) of symbols to determine the read start address.

[0082] (ii) MIMO multi-channel linkage and synchronization processing The receiver rate adaptation unit supports multi-channel synchronous processing, i.e., 3-channel synchronous processing in MIMO mode. Considering that there are a maximum of 3 channels of 12-bit input data and 3 channels of synchronization start signals in MIMO mode, when the synchronization start signal of any one channel (phase A, phase B, or phase C) is detected, the system immediately calculates the corresponding RAM write address and starts the speed reduction output mechanism of control signals and data signals to prevent data loss.

[0083] In a specific configuration, if the MIMO multiple signals have undergone delay alignment calibration at the physical layer (analog front end or digital front end) before entering the receiving down-frequency module, then in order to further ensure timing, down-frequency can be started as soon as a synchronization start signal is detected in any of the A / B / C phases; the subsequent digital front-end transceiver module can align the data of each channel according to information such as the number of synchronization segments to prevent data loss or processing errors caused by slight delay differences in the signals of each channel.

[0084] (iii) Cross-clock domain coordination of filter bandwidth switching The preamble, training frame, and payload receiver filter bandwidth of the next-generation carrier require switching. Upon detecting a successful synchronization pulse signal before speed reduction, the system generates a switching interrupt flag and automatically switches to the receiver software, which switches the filter to the new bandwidth at the first symbol of the training frame. When the receiver completion flag corresponding to receiver clock B (low-speed domain) is detected, the system first synchronizes this flag across clock domains to receiver clock A (high-speed domain), then clears the filter bandwidth switching flag, restoring the filter to its maximum bandwidth state.

[0085] To avoid delayed filter bandwidth switching due to frequency downsampling, the software uses the maximum bandwidth after power-on reset. To address the instability between old and new bandwidths, the number of carrier symbols is generally limited to no more than three. The new Southern Power Grid protocol recommends against using corresponding symbols for channel estimation, which will not affect other functions.

[0086] (iv) Receiver speed and clock configuration In baseband mode, receive clock A is 100MHz and receive clock B is 50MHz; in non-baseband mode, receive clock A is 100MHz and receive clock B is 100MHz. The receiver ADC operates at 50MHz in baseband mode and 100MHz in non-baseband mode. The receive rate adaptation unit can downclock the input data rate to 1 / 4 or 1 / 8 of the original rate to match the subsequent OFDM symbol processing module and the target operating rate.

[0087] The background section of this invention may include background information about the problems or environment in which the invention is being developed, and is not necessarily a description of prior art. Therefore, the content included in the background section does not constitute an admission of prior art by the applicant.

[0088] The above description provides a further detailed explanation of the present invention in conjunction with specific / preferred embodiments, and it should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various substitutions or modifications can be made to these described embodiments without departing from the concept of the present invention, and all such substitutions or modifications should be considered within the scope of protection of the present invention. In the description of this specification, the reference to terms such as "an embodiment," "some embodiments," "preferred embodiment," "example," "specific example," or "some examples," etc., indicates that the specific features, structures, materials, or characteristics described in connection with that embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any suitable manner in one or more embodiments or examples. Without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification and the features of different embodiments or examples. Although the embodiments of the present invention and their advantages have been described in detail, it should be understood that various changes, substitutions, and modifications can be made herein without departing from the scope of protection of the patent application.

Claims

1. An FPGA prototype verification system for a power line carrier communication chip, characterized in that, include: Digital front-end transceiver unit, digital-to-analog converter unit, analog-to-digital converter unit, receive symbol processing unit, transmit rate adaptation unit, and receive rate adaptation unit; In the transmission path, the transmission output terminal of the digital front-end transceiver unit is connected to the digital-to-analog converter unit through the transmission rate adaptation unit. The transmission rate adaptation unit is used to upsample the transmission data output by the digital front-end transceiver unit and then output it to the digital-to-analog converter unit. In the receiving path, the receiving output of the analog-to-digital conversion unit is connected to the receiving input of the digital front-end transceiver unit. The receiving output of the digital front-end transceiver unit is connected to the receiving symbol processing unit through the receiving rate adaptation unit. The receiving rate adaptation unit is used to receive the receiving processing data and the corresponding synchronization start signal output by the digital front-end transceiver unit, and output the receiving processing data to the receiving symbol processing unit after frequency down-processing. The receiving rate adaptation unit supports multi-channel synchronous processing and is used to trigger the frequency reduction processing of the receiving processing data of all channels when a synchronization start signal of any channel in the receiving path is detected.

2. The FPGA prototype verification system for power line carrier communication chips according to claim 1, characterized in that, The transmission rate adaptation unit includes a first dual-port storage unit and a first control unit. The first control unit is used to control the first dual-port storage unit to write data at a slow clock frequency and read data at a fast clock frequency.

3. The FPGA prototype verification system for power line carrier communication chips according to claim 1, characterized in that, The receiving rate adaptation unit includes a second dual-port storage unit and a second control unit. The second control unit is used to control the second dual-port storage unit to write data at a fast clock frequency and read data at a slow clock frequency. The second control unit is also used to record the write address of the synchronization start signal in the second dual-port storage unit, and to determine the read start address by backtracking a predetermined number of symbols based on the write address.

4. The FPGA prototype verification system for power line carrier communication chips according to claim 1, characterized in that, The multi-channel synchronization processing includes 3-channel synchronization processing in MIMO mode. When the receiving rate adaptation unit detects the synchronization start signal of any one of the 3 channels, it triggers all 3 channels to perform the down-frequency processing.

5. The FPGA prototype verification system for power line carrier communication chips according to claim 1, characterized in that, The digital front-end transceiver unit also outputs a synchronization success pulse signal and a peak count value to the receiving rate adaptation unit. The receiving rate adaptation unit is also used to uniformly reduce the speed of the synchronization start signal, the synchronization success pulse signal and the peak count value before outputting them.

6. The FPGA prototype verification system for power line carrier communication chips according to claim 5, characterized in that, The FPGA prototype verification system for the power line carrier communication chip also includes a filter bandwidth switching unit. The filter bandwidth switching unit is used to generate a filter bandwidth switching interrupt signal when the synchronization success pulse signal before the speed reduction is detected; and when the reception completion flag corresponding to the second receiving clock domain is detected, the reception completion flag is synchronized across clock domains to the first receiving clock domain to clear the filter bandwidth switching state in the filter bandwidth switching unit.

7. The FPGA prototype verification system for power line carrier communication chips according to claim 1, characterized in that, It also includes an MCU interactive buffer unit, a transceiver decoding unit, and a transmit symbol processing unit; the MCU interactive buffer unit is connected to the transceiver decoding unit, the transceiver decoding unit is connected to the transmit symbol processing unit, and the transmit symbol processing unit is connected to the transmit input terminal of the digital front-end transceiver unit; the receive symbol processing unit is also connected to the transceiver decoding unit, and the transceiver decoding unit is also connected to the MCU interactive buffer unit.

8. The FPGA prototype verification system for the power line carrier communication chip according to claim 7, characterized in that, The transceiver decoding unit includes a scrambling submodule, a Turbo-coded interleaving submodule, and a channel interleaving submodule; For the transmission path: when the data input to the transceiver decoding unit is frame control data, the frame control data bypasses the scrambling submodule and is processed sequentially through the Turbo coding interleaving submodule and the channel interleaving submodule; when the data input to the transceiver decoding unit is payload data, the payload data is processed sequentially through the scrambling submodule, the Turbo coding interleaving submodule and the channel interleaving submodule. For the receiving path: when the data decoded by the transceiver decoding unit is frame control data, the frame control data is processed sequentially by the channel deinterleaving submodule and the Turbo decoding submodule, and then sent to the MCU interactive buffer unit; when the data decoded by the transceiver decoding unit is payload data, the payload data is processed sequentially by the channel deinterleaving submodule, the Turbo decoding submodule and the descrambling submodule, and then sent to the MCU interactive buffer unit.

9. The FPGA prototype verification system for power line carrier communication chips according to claim 1, characterized in that, The down-frequency processing performed by the receiving rate adaptation unit includes: reducing the rate of the received processing data output by the digital front-end transceiver unit to 1 / 4 or 1 / 8; the up-frequency processing performed by the transmitting rate adaptation unit includes: increasing the rate of the transmitting data output by the digital front-end transceiver unit to twice the normal rate.

10. A verification method implemented using an FPGA prototype verification system based on the power line carrier communication chip according to any one of claims 1 to 9, characterized in that, Includes the following steps: In the transmission path, the transmission data output by the digital front-end transceiver unit is upsampled by the transmission rate adaptation unit and then transmitted to the digital-to-analog converter unit. In the receiving path, the digital signal converted by the analog-to-digital converter is input to the digital front-end transceiver unit; the receiving rate adaptation unit receives the receiving processing data and the corresponding synchronization start signal output by the digital front-end transceiver unit, and outputs the receiving processing data to the receiving symbol processing unit after frequency down-processing. In the multi-channel synchronous processing mode supported by the receiving rate adaptation unit, the synchronization start signal of any channel in the receiving path is detected, and when the synchronization start signal is detected, the receiving processing data of all channels is triggered to perform the down-frequency processing.

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