Integrated radio frequency switching circuit with single pole multi throw switch

Abstract

An integrated radio frequency switching circuit includes a radio frequency (RF) input / output (RFIO) configured to be operatively coupled to a plurality of RF paths. A wireless local area network (WLAN) transmit path includes a power amplifier and a WLAN power amplifier matching network circuit that are operatively coupled to the RFIO without a switch. An inductor in the WLAN power amplifier matching network is shunted to ground in all modes of operation for electrostatic discharge (ESD) protection of the RFIO. A personal area network (PAN) transmit path includes two power amplifiers with different power levels that are both operatively coupled to the RFIO through a series switch. A WLAN / PAN signal receive path includes a low noise amplifier (LNA) and an LNA matching network coupled to the RFIO. The series switch and LNA matching network are controlled to enable a plurality of transmit and receive modes of operation.

Description

Technical Field

[0001] This embodiment generally relates to radio frequency (RF) communication, and more specifically to an RF switch for transmitting and receiving RF signals. Background Technology

[0002] Radio frequency (RF) communication is crucial to modern wireless technology, enabling a wide range of applications, including cellular networks (e.g., 4G, 5G), Wi-Fi, Bluetooth, satellite systems, and radar. Wireless communication systems rely on transmitting and receiving electromagnetic signals across a broad range of frequencies, power levels, and protocols. For example, wireless communication systems are expected to provide multiple different services within a single platform, such as access to cellular networks, wireless local area networks (WLANs) (e.g., Wi-Fi), and personal area networks (PANs) (e.g., Bluetooth).

[0003] The ever-increasing demand for high data rates, low latency, and multi-band operation has driven the complexity of RF systems, requiring sophisticated front-end architectures to manage the RF path between antennas, amplifiers, filters, and transceivers. At the heart of the RF front-end architecture is the switching circuitry, which bootstraps and controls the RF signals. RF switches enable functions such as antenna multiplexing, band selection, and transmit / receive (T / R) isolation, allowing a single device to provide a communication system.

[0004] Existing RF switching solutions face challenges, including trade-offs between insertion loss, isolation, switching speed, and power handling. Therefore, innovation in RF switch design and integration is crucial for improving the performance, efficiency, and scalability of RF communication systems to meet the evolving needs of next-generation wireless technologies. Summary of the Invention

[0005] This summary is provided to introduce, in a simplified form, the selection of concepts further described in the detailed description below. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

[0006] One innovative aspect of the subject matter of this disclosure can be implemented in an integrated radio frequency switching circuit. The integrated radio frequency switching circuit includes: a radio frequency input / output (RFIO) node; a first power amplifier for transmitting a personal area network (PAN) signal at a first power level; and a second power amplifier for transmitting the PAN signal at a second power level, wherein both the first and second power amplifiers are operatively coupled to the RFIO node via a first switch. Additionally, the integrated radio frequency switching circuit includes: a WLAN power amplifier matching network circuit operatively coupled to the RFIO node without a switch, and a third power amplifier for transmitting the wireless local area network (WLAN) signal. The WLAN power amplifier matching network circuit includes a first inductor coupled to the RFIO node and shunt to ground for electrostatic discharge (ESD) protection of the RFIO node. The integrated radio frequency switching circuit further includes: a low-noise amplifier for receiving the WLAN signal and the PAN signal, operatively coupled to the RFIO node.

[0007] Another innovative aspect of the subject matter of this disclosure can be implemented in a method for sharing an integrated radio frequency input / output (RFIO) node in a radio frequency switching circuit. The method includes: during a first PAN transmit operation mode, operatively coupling a first power amplifier to the RFIO node via a first switch and transmitting a Personal Area Network (PAN) signal at a first power level; and during a second PAN transmit operation mode, operatively coupling a second power amplifier to the RFIO node via the first switch and transmitting the PAN signal at a second power level. The method further includes: during a WLAN transmit operation mode, operatively coupling a third power amplifier and a power amplifier matching network circuit to the RFIO node without a switch and transmitting a Wireless Local Area Network (WLAN) signal. The power amplifier matching network circuit includes a first inductor coupled to the RFIO node and shunt to ground for electrostatic discharge (ESD) protection of the RFIO node during all operation modes. The method further includes: during a WLAN / PAN receive operation mode, operatively coupling a low-noise amplifier to the RFIO node without a switch and receiving either a WLAN signal or a PAN signal.

[0008] Another innovative aspect of the subject matter of this disclosure can be implemented in an integrated radio frequency switching circuit comprising: a radio frequency input / output (RFIO) node configured to be operatively coupled to a first human local area network (PAN) transmit path, a second PAN transmit path, a wireless local area network (WLAN) transmit path, and a WLAN and PAN receive path. The integrated RF switching circuit includes: a first power amplifier for transmitting a PAN signal at a first power level along the first PAN transmit path during a first PAN transmit operation mode; and a second power amplifier for transmitting the PAN signal at a second power level along the second PAN transmit path during a second PAN transmit operation mode. A first switch is coupled between both the first and second power amplifiers and the RFIO node and is controlled to operatively couple both the first and second power amplifiers to the RFIO node during both the first and second PAN transmit operation modes. The integrated RF switching circuit further includes: a third power amplifier for transmitting a wireless local area network (WLAN) signal along the WLAN transmit path during a WLAN transmit operation mode; and a WLAN power amplifier matching network circuit coupled between the third power amplifier and the RFIO node along the WLAN transmit path. The third power amplifier and the WLAN power amplifier matching network circuit are operatively coupled to the RFIO node without switching. The WLAN power amplifier matching network circuit includes a first inductor coupled to the RFIO node and shunt to ground for electrostatic discharge (ESD) protection of the RFIO node during all operating modes. The integrated RF switching circuit further includes a low-noise amplifier operatively coupled to the RFIO node for receiving WLAN or PAN signals along the WLAN and PAN receive paths during WLAN / PAN receive operating modes. Attached Figure Description

[0009] This exemplary embodiment is illustrated by way of example and is not intended to be limited to the figures in the accompanying drawings.

[0010] Figure 1 A block diagram showing an example of a radio frequency (RF) front-end architecture.

[0011] Figure 2 A block diagram of an RF front-end architecture is shown, which includes a front-end module with an integrated transmit / receive switch.

[0012] Figure 3A This diagram illustrates an RF single-pole multi-throw transmit / receive switch according to some implementations, which connects four RF paths to a single RF input / output (RFIO) node of a front-end module.

[0013] Figure 3B , 3C The diagram shows a 3D representation of the RF single-pole multi-throw transmit / receive switch in different operating modes according to some implementations.

[0014] Figure 4 This is a flowchart illustrating an example of a method for sharing an integrated radio frequency switching circuit with RFIO nodes according to some implementations. Detailed Implementation

[0015] In the following description, numerous specific details, such as examples of specific components, circuits, and processes, are set forth to provide a thorough understanding of this disclosure. As used herein, the term “coupling” means direct coupling or coupling through one or more intermediate components or circuits. Furthermore, specific terms and / or details are set forth in the following description and for purposes of explanation to provide a thorough understanding of exemplary embodiments. However, it will be apparent to those skilled in the art that these specific details may not be required to practice the exemplary embodiments. In other instances, well-known circuits and devices are illustrated in block diagram form to avoid obscuring this disclosure. Any signal provided on various buses as described herein may be time-division multiplexed with other signals and provided via one or more common buses. Additionally, interconnections between circuit elements or software blocks may be shown as buses or single-signal lines. Each bus may alternatively be a single-signal line, and each single-signal line may alternatively be a bus, and a single line or bus may represent any one or more of a multitude of physical or logical mechanisms for communication between components. Exemplary embodiments are not intended to be construed as limited to the specific examples described herein, but are intended to be construed as including all embodiments as defined by the appended claims within their scope.

[0016] As discussed in this paper, radio frequency (RF) switches are used to bootstrap and control RF signals for transmission and reception within the front-end architecture. Systems involving a large number of RF paths may require multiple RF switches combined to accommodate the number of RF paths. However, using multiple RF switches increases cost and may require several RF input / output (RFIO) nodes in the front-end module. RF switches typically include series switches in the RF transmit path, which reduces the efficiency of the power amplifier, resulting in losses during transmit mode. Additionally, RFIOs need to be protected against electrostatic discharge (ESD) events, which is difficult without compromising RF performance.

[0017] The implementation of the subject matter described herein includes integrated RF switching circuitry that provides multiple (e.g., four) RF paths to the RFIO node while minimizing switching losses and simplifying ESD design. As discussed herein, the switching circuitry includes a Wireless Local Area Network (WLAN) transmit path that is operatively coupled to the RFIO node without a series switch to avoid losses during WLAN transmission. The WLAN transmit path includes a WLAN power amplifier and a WLAN power amplifier matching network with an inductor shunt to ground for ESD protection of the RFIO node in all operating modes. High-power and low-power Personal Area Network (PAN) transmit paths include power amplifiers operating at different power levels, both coupled to the RFIO node via a series switch that operatively couples the PAN transmit path to the RFIO node during PAN transmission and isolates the PAN transmit path under other conditions. Additionally, a receive path for WLAN and PAN signals includes a low-noise amplifier coupled to the RFIO node. The RFIO node can be coupled to a shunt capacitor array in a low-noise amplifier matching network, wherein the shunt capacitor array includes variable capacitors that are tuned for different operating modes of the RFIO node. Switches in the low-noise amplifier matching network can be additionally controlled to protect the low-noise amplifier during transmit operation mode and to be controlled for input matching during receive operation mode.

[0018] Figure 1 A block diagram of a radio frequency (RF) front-end architecture 100 is shown. The RF front-end architecture 100 is illustrated as having a front-end module 110, external transmit / receive switch circuits 120 and 130, a duplexer 140, and an antenna 150.

[0019] Front-end module 110 is illustrated as including multiple radio frequency (RF) application-specific integrated circuits (ASICs) coupled to amplifier circuitry. The RF ASICs may be configured to implement mixer circuitry, oscillators, and input / output filters to generate a complex baseband signal from an RF signal received via antenna 150, and from the complex baseband signal to generate an RF signal for transmission on antenna 150. As illustrated, front-end module 110 may include RF ASICs 162 and 164 for transmitting and receiving Wireless Wide Area Network (WWAN) RF signals (e.g., for fifth-generation (5G) or sixth-generation (6G) New Radio (NR) standards), respectively, with RF ASICs 162 and 164 coupled to power amplifier (PA) 163 and low-noise amplifier (LNA) 165, respectively. Power amplifier 163 and LNA 165 for WWAN RF signals are connected to antenna 150 via external transmit / receive switching circuitry 120 and duplexer 140.

[0020] The front-end module 110 may additionally include RF ASICs for wireless local area network (WLAN) signals (e.g., based on the IEEE 802.11 standard (including IEEE 802.11ax, commonly referred to as WiFi, or other protocols) and RF ASICs for personal local area network (PAN) signals (e.g., based on Bluetooth®, Zigbee, ultra-wideband (UWB), near field communication (NFC), etc.). For example, as illustrated, the front-end module 110 may include RF ASICs 172 and 174 for transmitting and receiving PAN RF signals (e.g., Bluetooth RF signals at 2.4 GHz), and may additionally include RF ASICs 182 and 184 for transmitting and receiving WLAN RF signals (e.g., WiFi RF signals at 2.4 GHz), although other frequencies and protocols may be used. RF ASICs 172 and 182, used for transmitting PAN and WLAN signals respectively, are both coupled to power amplifiers 192 and 194 (e.g., via switch 193), and RF ASIC 172 for PAN signals is further coupled to power amplifier 196. For example, power amplifiers 194 and 196 can be used to selectively transmit PAN signals at relatively high power (H) or low power (L), respectively. RF ASICs 174 and 184, used for receiving PAN and WLAN signals respectively, are both coupled to receive signals via LNA 198.

[0021] Power amplifiers 192, 194, and 196, and LNA 198 are connected to antenna 150 via external transmit / receive switching circuitry 130 and duplexer 140. External transmit / receive switching circuitry 130 includes two single-pole double-throw (SP2T) switches 132 and 134, which are connected to front-end module 110 via three radio frequency input / output (RFIO) pins or nodes. The first SP2T switch 132 is connected to power amplifiers 192 and LNA 198 via two separate RFIO pins. The second SP2T switch 134 is connected to power amplifiers 194 and 196 via a single RFIO pin and is further connected to the first SP2T switch 132 and duplexer 140.

[0022] As can be seen, using two separate SP2T switches for the external transmit / receive switch circuit 130 for WLAN and PAN signals increases cost. Furthermore, the front-end module 110 requires three RFIO nodes to communicate with the external transmit / receive switch circuit 130.

[0023] In some front-end modules, an RF single-pole double-throw transmit / receive switch can connect a single RFIO node to both a power amplifier and a low-noise amplifier via a matching network circuit and a series switch (e.g., Figure 1The power amplifier 192 and low-noise amplifier 198 are shown in the diagram. However, using a series switch between the power amplifier and the RFIO node reduces the efficiency of the power amplifier, resulting in losses when in transmit mode.

[0024] Additionally, RFIO nodes must be connected to electrostatic discharge (ESD) circuitry to dissipate or shunt the energy of discharges or withstand current and voltage levels. Typically, the ESD circuitry for an RFIO node needs to withstand 2kV for the Human Body Model (HBM) and 500V for the Charged Device Model (CDM). Generally, for example, the DC path should be less than 2 ohms to withstand 2kV HBM ESD. However, implementing ESD circuitry is challenging when the output power at the RFIO node is high (such as in the case of transmitting WLAN signals with a peak output voltage Vp > 7V). In some implementations, for example, the ESD circuitry may include diode shunts, but this impacts RF performance, particularly in high-output-power transmission modes. For example, common-cathode common-gate amplifiers may be used in multiple stages, resulting in high output voltage swings during transmission. During transmission (e.g., for WLAN signals), the RFIO node must withstand high signal voltage swings and requires low parasitic capacitance. If an ESD diode device is designed to withstand high signal voltage swings, it will generate even higher parasitic capacitance. Accordingly, using ESD diode devices for transmission in ESD circuits will reduce RF performance.

[0025] Furthermore, if more than two RF paths are desired (such as WLAN transmit, WLAN receive, PAN transmit, and PAN receive), using a single-pole double-throw switch in the front-end module is insufficient.

[0026] Accordingly, an integrated single-pole multi-throw transmit / receive RF switch is desirable for accommodating more than two RF paths using only a single RFIO node.

[0027] Figure 2 A block diagram of a radio frequency (RF) front-end architecture 200 is shown, which includes a front-end module 210 having integrated transmit / receive switches 220 and 230 connected to a duplexer 240 and an antenna 250. The integrated transmit / receive switch 230 is a single-pole multi-throw transmit / receive switch 230 connected to the antenna 250 via a single RFIO node, according to the implementation discussed herein. The front-end module 210 may be coupled to one or more processors 202 configured to control the operation of the front-end module 210, including various operating modes of the transmit / receive switch 230 as discussed herein.

[0028] Similar to Figure 1The front-end module 110 and front-end module 210 illustrated in the figure include multiple RF ASICs. In some implementations, front-end module 210 may include RF ASICs 262 and 264 for transmitting and receiving WWAN RF signals (e.g., for 5G or 6G NR standards), respectively, with RF ASICs 262 and 264 coupled to power amplifier 263 and low-noise amplifier 265, respectively. Power amplifier 263 and low-noise amplifier 265 are connected to antenna 250 via integrated single-pole double-throw switch 220 and duplexer 240. It should be understood that in some implementations, front-end module 210 may not include RF ASIC 262 or 264, or may include additional or other types of RF ASICs connected to antenna 250 in a manner similar to RF ASIC 262 or 264.

[0029] Additionally, the front-end module 210 may include RF ASICs 272 and 282 for transmitting PAN signals and WLAN signals, respectively. RF ASICs 272 and 282 are similar to... Figure 1 The front-end module 110 illustrated includes RF ASICs 172 and 182, and the front-end module 210 may include RF ASICs 274 and 284 for receiving PAN signals and WLAN signals, respectively, similar to RF ASICs 174 and 184 in front-end module 110. RF ASICs 272 and 282 for transmitting PAN signals and WLAN signals, respectively, are both coupled to power amplifiers 292 and 294 (e.g., via switch 293), and RF ASIC 272 for PAN signals is further coupled to power amplifier 296. For example, power amplifiers 294 and 296 may be used to selectively transmit PAN signals at relatively high power (H) or low power (L), respectively. RF ASICs 274 and 284 for receiving PAN signals and WLAN signals, respectively, are both coupled to receive signals via LNA 298.

[0030] Power amplifiers 292, 294, and 296, as well as LNA 298, are all connected to an integrated single-pole multi-throw transmit / receive switch 230, which is connected to antenna 250 via a single RFIO node 212 of front-end module 210. Therefore, the integrated transmit / receive switch 230 comprises only a single switch (as shown in the image). Figure 1 The two switches used in the middle are opposite), and only a single RFIO node is required (as in...). Figure 1 The three opposites used in the text).

[0031] In addition to using a single RFIO node to share more than two RF paths, as discussed above, the RF switch should also minimize switching losses in the most critical path of the WLAN transmit power amplifier (e.g., by eliminating series switches between the WLAN transmit power amplifier and the RFIO node). Furthermore, the RF switch should be used to simplify the ESD design for protecting the RFIO node.

[0032] Figure 3A The diagram illustrates an RF single-pole multi-throw (SPMWP) transmit / receive switch 300 according to some implementations, which connects four RF paths to an RFIO node 310 of a front-end module. For example, the four RF paths connected to the RFIO node 310 may include a WLAN transmit path, a PAN high-power transmit path, a PAN low-power transmit path, and a WLAN / PAN receive path. Figure 3B , 3C The 3D diagrams show the switches in various operating modes (including WLAN transmission mode, high-power and low-power PAN transmission modes, and WLAN / PAN reception mode).

[0033] As illustrated, switch 300 includes a first power amplifier 320 connected to RFIO node 310 via power amplifier matching network circuitry 322. The first power amplifier 320 has the highest output power among all RF paths connected to RFIO node 310. For example, the first power amplifier 320 can be used for WLAN signals and is sometimes referred to herein as WLAN power amplifier 320. To minimize losses, WLAN power amplifier 320 is connected to RFIO node 310 without a series switch (e.g., WLAN power amplifier 320 with WLAN power amplifier matching network circuitry 322 is directly connected to RFIO node 310 without an intermediate series switch).

[0034] The WLAN power amplifier matching network circuit 322 includes a transformer 324 with inductors L1 and L2, with the secondary inductor L2 connected to the RFIO node 310 and shunt to ground. The inductor L2 in the WLAN power amplifier matching network circuit 322 serves as an ESD circuit for the RFIO node 310 in all operating modes of the switch 300 (e.g., during WLAN transmit, PAN high-power transmit, PAN low-power transmit, and WLAN / PAN receive).

[0035] Switch 300 includes a second power amplifier 330 and a third power amplifier 340, both of which are connected to RFIO node 310 via a series switch SW1 (such as a MOSFET). The series switch SW1 can be closed during PAN signal transmission via the second power amplifier 330 or the third power amplifier 340, and otherwise open during other operating modes of switch 300 (e.g., during WLAN transmission or WLAN / PAN reception). Both the second power amplifier 330 and the third power amplifier 340 are used to transmit signals with a power level lower than that of the first power amplifier 320. The second power amplifier 330 can transmit at a lower power than the third power amplifier 340. For example, the second and third power amplifiers 330 and 340 can be used for PAN signals and are sometimes referred to herein as PAN low (L) power amplifier 330 and PAN high (H) power amplifier 340.

[0036] The PAN low-power amplifier 330 can be connected to a series switch SW1 via a PAN power amplifier matching network circuit 332. The PAN power amplifier matching network circuit 332 includes a transformer 334 with inductors L3 and L4, while the secondary inductor L4 is connected to the RFIO node 310 via the series switch SW1 and shunt to ground. The PAN high-power amplifier 340 can be connected to the series switch SW1 via a capacitor 342. During transmission using the PAN high-power amplifier 340, shunt inductors L4 and L2 from the WLAN power amplifier matching network circuit 322 are used for output matching.

[0037] Switch 300 further includes a low-noise amplifier 350, which is connected to RFIO node 310 via capacitor C1 and LNA matching network circuit 352. The output terminals of the low-noise amplifier 350 can be connected (e.g., to transformer 360) to enable differential output from a single output. LNA matching network circuit 352 includes transformer 354, which includes inductors L5 and L6, a variable capacitor C2 connected between inductors L5 and L6 and between capacitor C1 and ground, and a switch SW2 (e.g., a MOSFET) connected between inductors L5 and L6. Switch SW1 is closed during WLAN transmission by WLAN power amplifier 320 or PAN transmission by PAN low-power amplifier 330 or PAN high-power amplifier 340, and is open during WLAN / PAN reception by low-noise amplifier 350.

[0038] Therefore, RFIO node 310 is connected to a shunt capacitor array including capacitor C1 and variable capacitor C2. The variable capacitor C2 can be adjusted for various operating modes of switch 300 based on the equivalent capacitance of C1 and C2 in series (i.e., The variable capacitor C2 can be tuned to a specific level such that the capacitor array (i.e., capacitors C1 and C2 in series) is used as a power amplifier balun resonant shunt capacitor during WLAN transmission by the WLAN power amplifier 320. The variable capacitor C2 can also be tuned to a specific level such that the capacitor array (i.e., capacitors C1 and C2 in series) is optimized for output matching during PAN transmission by the PAN low-power amplifier 330 or the PAN high-power amplifier 332. The variable capacitor C2 can be turned off such that the capacitor array (i.e., capacitor C1) is used as an AC coupling capacitor during WLAN / PAN reception by the low-noise amplifier 350.

[0039] Therefore, by configuring switches SW1 and SW2 and the variable capacitor C2, switch 300 can be configured for different operating modes. For example, Table 1 summarizes various configurations of switch 300 for different operating modes, including WLAN transmission (WLAN Tx), high-power PAN transmission (PAN H Tx), low-power PAN transmission (PAN L Tx), and WLAN / PAN reception (WLAN / PAN Rx). In Table 1, the C2 value MAX indicates the maximum capacitance, X1 and X2 are different values ​​based on PAN Tx matching, and 0 indicates no capacitance or minimum capacitance.

[0040] Figure 3B The diagram shows switch 300 in WLAN transmission mode. (As shown in...) Figure 3B As illustrated in the diagram and indicated in Table 1, in WLAN transmit mode, the inductor L2 shunt to ground provides ESD protection for RFIO node 310. Switch SW1 is open, protecting PAN power amplifiers 330 and 340. Additionally, switch SW2 is closed (short-circuited) to protect low-noise amplifier 350. Variable capacitor C2 is set to its maximum capacitance to maximize attenuation of power from WLAN power amplifier 320 during transmission (e.g., operating as a shunt capacitor for the power amplifier balun resonant).

[0041] Figure 3C The diagram shows switch 300 in PAN H or PAN L transmission mode. (As shown in...) Figure 3CAs illustrated in the diagram and indicated in Table 1, in PAN transmit mode, inductor L2, shunt to ground, provides ESD protection for RFIO node 310. Switch SW1 is closed to connect PAN power amplifiers 330 and 340 to RFIO node 310. Thus, PAN low-power amplifier 330 and PAN high-power amplifier 340 share the same output and good performance. Additionally, inductors L3 and L4 protect PAN low-power amplifier 330 during transmit by PAN high-power amplifier 340. Similarly, inductors L1 and L2 protect WLAN power amplifier 320 during transmit by PAN high-power amplifier 340 (or PAN low-power amplifier 330). Switch SW2 is closed (short-circuited) to protect low-noise amplifier 350. Variable capacitor C2 is tuned to X1 or X2 to optimize output matching of PAN low-power amplifier 330 and PAN high-power amplifier 340 during transmit (e.g., operating as a matching shunt capacitor).

[0042] Figure 3D The diagram shows switch 300 in WLAN or PAN receive mode. Figure 3D As illustrated in the diagram and indicated in Table 1, in WLAN or PAN receive mode, inductor L2 shunt to ground provides ESD protection for RFIO node 310. Switch SW1 is open, isolating PAN power amplifiers 330 and 340. Switch SW2 is open, and variable capacitor C2 is cut off, making LNA input matching based on inductor L2, capacitor C1, and inductors L5 and L6. Thus, the capacitor array operates as AC coupling capacitors in WLAN or PAN receive mode.

[0043] Figure 4 This is a flowchart illustrating an example of a method 400 that uses a shared integrated RF switching circuit with RF input / output (RFIO) nodes according to some implementation. For example, the integrated RF switching circuit could be... Figure 3A , 3B The switch 300 illustrated in 3C and 3D diagrams can be used in front-end modules, such as in... Figure 2 The diagram shows the front-end modules used in the front-end architecture 200.

[0044] like Figure 4 As illustrated, during the first PAN transmit operation mode (510), the first power amplifier is operatively coupled to the RFIO node via a first switch and transmits a Personal Area Network (PAN) signal (e.g., as shown by...) at a first power level. Figure 3C The power amplifier 330 and switch SW1 are illustrated in the diagram.

[0045] During the second PAN transmit operation mode (520), the second power amplifier is operatively coupled to the RFIO node via the first switch and transmits a PAN signal at the second power level (e.g., as by...). Figure 3C The power amplifier 340 and switch SW1 are illustrated in the diagram.

[0046] During WLAN transmit operation mode (530), the third power amplifier and power amplifier matching network circuitry are operatively coupled to the RFIO node without switching and transmit wireless local area network (WLAN) signals (e.g., as provided by...). Figure 3B The power amplifier 320 and WLAN power amplifier matching network circuit 322 are illustrated in the diagram. Additionally, the power amplifier matching network circuit includes a first inductor coupled to the RFIO node and shunt to ground for electrostatic discharge (ESD) protection of the RFIO node during all operating modes (e.g., as per [reference to...]). Figures 3A-3D As discussed and illustrated by inductor L2).

[0047] During WLAN / PAN receive operation mode (540), the low-noise amplifier is operatively coupled to the RFIO node without switching and receives WLAN or PAN signals (e.g., as provided by...). Figure 3D (As illustrated in the diagram of the low-noise amplifier 350).

[0048] In some implementations, the low-noise amplifier is operatively coupled to the RFIO node via a low-noise amplifier matching network circuit, which includes a capacitor array having a first capacitor coupled to the RFIO node and a variable capacitor coupled between the first capacitor and ground (e.g., as provided by...). Figure 3A (As illustrated by capacitors C1 and C2 in the diagram). The method may further include: tuning the variable capacitor to attenuate the power of the low-noise amplifier during the first PAN transmit operation mode, the second PAN transmit operation mode, and the WLAN transmit operation mode; and the variable capacitor may be turned off during the WLAN / PAN receive operation mode (e.g., as per the description of...). Figures 3A-3D As discussed in Table 1).

[0049] In some implementations, the capacitor array can be used as a power amplifier balun resonant shunt capacitor during WLAN transmit operation mode (e.g., as per [reference]). Figure 3A and 3B As discussed.

[0050] In some implementations, the capacitor array can be used as a matching shunt capacitor during the first PAN transmit operation mode and the second PAN transmit operation mode (e.g., as per [reference]). Figure 3A and3C As discussed.

[0051] In some implementations, the capacitor array can be used as an AC coupling capacitor during WLAN / PAN receive operation mode (e.g., as per [reference]). Figure 3A and 3D As discussed.

[0052] In some implementations, the low-noise amplifier matching network circuit may further include a second switch, which may be positioned between two inductors (e.g., as provided by...). Figure 3A (As illustrated by switch SW2 in the diagram). The method may further include: during the first PAN transmit operation mode, the second PAN transmit operation mode, and the WLAN transmit operation mode, closing the second switch to protect the low-noise amplifier (e.g., as per the diagram regarding...). Figure 3A , 3B As discussed in 3C). The method may further include disconnecting the switch during WLAN / PAN receive operation mode (e.g., as discussed in...). Figure 3A and 3D (as discussed in Table 1).

[0053] In some implementations, the method may include: during a first PAN transmit operation mode and a second PAN transmit operation mode, closing a first switch to operatively couple the first and second power amplifiers to an RFIO node; and during a WLAN transmit operation mode and a WLAN / PAN receive operation mode, opening the first switch to protect the first and second power amplifiers (e.g., as per [reference to...]). Figure 3A , 3B (As discussed in 3C and 3D and switch SW1 in Table 1).

[0054] In some implementations, the first power amplifier can be operatively coupled to the RFIO node via a PAN power amplifier matching network circuit, which includes a second inductor coupled to the second power amplifier and the first switch and shunt to ground to protect the first power amplifier during the second PAN transmit operation mode (e.g., as per [reference]). Figure 3A and 3C (As discussed in the inductor L4).

[0055] Those skilled in the art will recognize that information and signals can be represented using any of a wide variety of different techniques and arts. For example, data, instructions, commands, information, signals, bits, symbols, and chips, which can be referenced throughout the description above, can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0056] Furthermore, those skilled in the art will recognize that the various illustrative logic blocks, modules, circuits, and algorithmic steps described in conjunction with the aspects disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this hardware-software interchangeability, various illustrative components, blocks, modules, circuits, and steps have been generally described above in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as causing a departure from the scope of this disclosure.

[0057] The various illustrative logic blocks, modules, and circuits described in conjunction with the embodiments disclosed herein may be implemented or performed using a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0058] The methods, sequences, or algorithms described in conjunction with the aspects disclosed herein may be implemented directly in hardware, in a software module executed by a processor, or in a combination of both. The software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Alternatively, the storage medium may be integrated with the processor.

[0059] In the foregoing description, embodiments have been described with reference to specific examples thereof. However, it will be apparent that various modifications and changes may be made therein without departing from the broader scope of this disclosure as set forth in the appended claims. Accordingly, the description and drawings are to be viewed in an illustrative rather than a limiting sense.

Claims

1. An integrated radio frequency switching circuit, comprising: Radio frequency input / output (RFIO) node; A first power amplifier is used to transmit a personal area network (PAN) signal at a first power level; A second power amplifier is used to transmit the PAN signal at a second power level, wherein both the first power amplifier and the second power amplifier are operatively coupled to the RFIO node via a first switch; A WLAN power amplifier matching network circuit and a third power amplifier for transmitting Wireless Local Area Network (WLAN) signals are operably coupled to the RFIO node without switching. The WLAN power amplifier matching network circuit includes a first inductor coupled to the RFIO node and shunt to ground for electrostatic discharge (ESD) protection of the RFIO node. A low-noise amplifier for receiving WLAN and PAN signals is operatively coupled to the RFIO node.

2. The integrated radio frequency switching circuit as described in claim 1, wherein, The low-noise amplifier is operatively coupled to the RFIO node via a low-noise amplifier matching network circuit, which includes a capacitor array comprising a first capacitor coupled to the RFIO node and a variable capacitor coupled between the first capacitor and ground. The variable capacitor is tuned to attenuate the power to the low-noise amplifier during the transmission of the WLAN signal by the third power amplifier, the transmission of the PAN signal by the first power amplifier at the first power level, and the transmission of the PAN signal by the second power amplifier at the second power level, and is in a cut-off state during the reception of the WLAN signal and the reception of the PAN signal by the low-noise amplifier.

3. The integrated radio frequency switching circuit as described in claim 2, wherein, The capacitor array is used as a power amplifier balun resonant shunt capacitor during the transmission of the WLAN signal by the third power amplifier.

4. The integrated radio frequency switching circuit as described in claim 2, wherein, The capacitor array serves as a matching shunt capacitor during the transmission of the PAN signal by the first power amplifier at the first power level and during the transmission of the PAN signal by the second power amplifier at the second power level.

5. The integrated radio frequency switching circuit as described in claim 2, wherein, The capacitor array is used as an AC coupling capacitor during the reception of the WLAN signal by the low-noise amplifier and during the reception of the PAN signal by the low-noise amplifier.

6. The integrated radio frequency switching circuit as described in claim 2, wherein, The low-noise amplifier matching network circuit further includes a second switch that closes during the period when the first power amplifier transmits the PAN signal at the first power level, during the period when the second power amplifier transmits the PAN signal at the second power level, and during the period when the third power amplifier transmits the WLAN signal, to protect the low-noise amplifier.

7. The integrated radio frequency switching circuit as described in claim 6, wherein, The second switch is open during the period when the WLAN signal is received by the low-noise amplifier and during the period when the PAN signal is received by the low-noise amplifier.

8. The integrated radio frequency switching circuit as described in claim 1, wherein, The first switch is closed during the period when the PAN signal is transmitted by the first power amplifier at the first power level and during the period when the PAN signal is transmitted by the second power amplifier at the second power level, and the first switch is open during the period when the WLAN signal is transmitted by the third power amplifier, during the period when the WLAN signal is received by the low noise amplifier, and during the period when the PAN signal is received by the low noise amplifier.

9. The integrated radio frequency switching circuit as described in claim 1, wherein, The first power amplifier is operatively coupled to the RFIO node via a PAN power amplifier matching network circuit, wherein the PAN power amplifier matching network circuit includes a second inductor that is coupled to the second power amplifier and the first switch and shunt to ground.

10. A method for sharing a radio frequency input / output (RFIO) node in an integrated radio frequency switching circuit, comprising: During the first PAN transmit operation mode, a first power amplifier is operatively coupled to the RFIO node via a first switch and transmits a Personal Area Network (PAN) signal at a first power level; During the second PAN transmit operation mode, the second power amplifier is operatively coupled to the RFIO node via the first switch and the PAN signal is transmitted at the second power level; During WLAN transmit operation mode, a third power amplifier and a power amplifier matching network circuit are operatively coupled to the RFIO node without switching and transmit wireless local area network (WLAN) signals, wherein the power amplifier matching network circuit includes a first inductor coupled to the RFIO node and shunt to ground for electrostatic discharge (ESD) protection of the RFIO node during all operating modes. as well as During WLAN / PAN receive operation mode, a low-noise amplifier is operatively coupled to the RFIO node without switching and receives WLAN or PAN signals.

11. The method of claim 10, wherein, The low-noise amplifier is operatively coupled to the RFIO node via a low-noise amplifier matching network circuit, the low-noise amplifier matching network circuit including a capacitor array, the capacitor array including a first capacitor coupled to the RFIO node and a variable capacitor coupled between the first capacitor and ground, the method further comprising: tuning the variable capacitor to attenuate the power to the low-noise amplifier during a first PAN transmit operation mode, a second PAN transmit operation mode and the WLAN transmit operation mode; and tuning the variable capacitor to a cut-off state during the WLAN / PAN receive operation mode.

12. The method of claim 11, wherein, The capacitor array is used as a power amplifier balun resonant shunt capacitor during the WLAN transmit operation mode.

13. The method of claim 11, wherein, The capacitor array is used as a matching shunt capacitor during the first PAN transmit operation mode and the second PAN transmit operation mode.

14. The method of claim 11, wherein, The capacitor array is used as an AC coupling capacitor during the WLAN / PAN receive operation mode.

15. The method of claim 11, wherein, The low-noise amplifier matching network circuit further includes a second switch, and the method further includes: closing the second switch to protect the low-noise amplifier during the first PAN transmission operation mode, the second PAN transmission operation mode, and the WLAN transmission operation mode.

16. The method of claim 15, further comprising disconnecting the second switch during the WLAN / PAN receive operation mode.

17. The method of claim 10, further comprising: During the first PAN transmit operation mode and the second PAN transmit operation mode, the first switch is closed to operatively couple the first power amplifier and the second power amplifier to the RFIO node; Furthermore, during the WLAN transmit operation mode and the WLAN / PAN receive operation mode, the first switch is disconnected to protect the first power amplifier and the second power amplifier.

18. The method of claim 10, wherein, The first power amplifier is operatively coupled to the RFIO node via a PAN power amplifier matching network circuit, wherein the PAN power amplifier matching network circuit includes a second inductor coupled to the second power amplifier and the first switch and shunt to ground to protect the first power amplifier during the second PAN transmit operation mode.

19. An integrated radio frequency switching circuit, comprising: Radio frequency input / output (RFIO) nodes configured to be operatively coupled to a first human local area network (PAN) transmit path, a second PAN transmit path, a wireless local area network (WLAN) transmit path, and WLAN and PAN receive paths; A first power amplifier is used to transmit a PAN signal at a first power level along the first PAN transmission path during a first PAN transmission operation mode. A second power amplifier is used to transmit the PAN signal at a second power level along the second PAN transmission path during the second PAN transmission operation mode; A first switch is coupled between both the first power amplifier and the second power amplifier and the RFIO node. The first switch is controlled to operatively couple both the first power amplifier and the second power amplifier to the RFIO node during the first PAN transmit operation mode and the second PAN transmit operation mode. A third power amplifier is used to transmit wireless local area network (WLAN) signals along the WLAN transmission path during WLAN transmission operation mode; A WLAN power amplifier matching network circuit is coupled along the WLAN transmit path between the third power amplifier and the RFIO node, wherein the third power amplifier and the WLAN power amplifier matching network circuit are operatively coupled to the RFIO node without switching, and wherein the WLAN power amplifier matching network circuit includes a first inductor coupled to the RFIO node and shunt to ground for electrostatic discharge (ESD) protection of the RFIO node during all operating modes; and A low-noise amplifier, operatively coupled to the RFIO node, is used to receive WLAN or PAN signals along the WLAN and PAN receive paths during WLAN / PAN receive operation mode.

20. The integrated radio frequency switching circuit as described in claim 19, wherein, The low-noise amplifier is operatively coupled to the RFIO node via a low-noise amplifier matching network circuit, which includes a capacitor array having a first capacitor coupled to the RFIO node and a variable capacitor coupled between the first capacitor and ground. The variable capacitor is tuned to attenuate the power to the low-noise amplifier during the first PAN transmit operation mode, the second PAN transmit operation mode, and the WLAN transmit operation mode, and is in a cut-off state during the WLAN / PAN receive operation mode.

Images