Satellite data computing power control system and method

Abstract

The application provides a satellite data computing power control system and method, comprising: a baseband beam control link configured to provide a satellite-borne data stream through a single satellite controllable beam; a comprehensive electronic board card configured to provide computing power required by the satellite-borne data stream to the baseband beam control link; and a management and control board card configured to allocate computing power between the comprehensive electronic board card and the baseband beam control link.

Description

Technical Field

[0001] This invention relates to the field of aerospace technology, and in particular to an onboard data computing power control system and method. Background Technology

[0002] Traditional GEO high-throughput satellites and first-generation LEO communication constellations are limited by the computing power ceiling of onboard baseband processors. The controllable beam size of a single satellite is generally at the level of tens of beams, and beam scheduling algorithms are mainly completed by the baseband processor itself. The number of beams is limited by: ① The real-time computing power of the onboard baseband processor (FPGA or DSP) is insufficient to support the weight update and interference coordination calculations at the level of hundreds of beams; ② There is a lack of high-bandwidth, low-latency, deterministic data paths for beam scheduling decision data, beam weight data, and beam measurement feedback data between the baseband, integrated electronics, and payload data streams; ③ Traditional integrated electronics boards are only configured with gigabit Ethernet, which cannot carry the large-scale data streams generated by onboard processing at the level of hundreds of beams; ④ Onboard computing power is distributed between the baseband and integrated electronics domains, making coordinated scheduling impossible. Summary of the Invention

[0003] The purpose of this invention is to provide an on-board data computing power control system and method to solve the problem that the controllable beam of a single satellite in the existing communication constellation baseband beam control link is limited by the computing power of the on-board baseband processor.

[0004] To solve the above-mentioned technical problems, the present invention provides an on-board data computing power control system, comprising: The baseband beam control link is configured to provide onboard data streams via a single-satellite controllable beam; The integrated electronic board is configured to provide the computing power required to supply the onboard data stream to the baseband beam control link; and The control board is configured to distribute computing power between the integrated electronic board and the baseband beam control link.

[0005] Optionally, in the aforementioned on-board data computing power control system, the integrated electronic board includes: The first service computing power board is configured to form an integrated storage and computing power structure between the multi-core CPU, FPGA coprocessor, and onboard storage unit via a high-speed inter-chip bus, providing low-latency closed-loop access within the board for beam weights and / or channel measurement intermediate results; and The second business computing power board is configured to accelerate the inference of the beam scheduling AI model through the heterogeneous acceleration computing power module, so as to integrate AI beam management with traditional beam scheduling.

[0006] Optionally, in the aforementioned on-board data computing power control system, the control board includes: The mainframe small core is configured to perform space service management and attitude and orbit control via real-time CPU. The host CPU core is configured to manage the autonomous operation and computing power scheduling of the control board through real-time CPU. The backup small core is configured as a cold backup for the main small core, and the backup large core is configured as a cold backup for the main large core. The control board is connected to the high-speed switching board via gigabit Ethernet and analog switch cross-backup, and is connected to the PCIe topology of the first service computing power board and the second service computing power board via PCIe bus; The collaborative scheduling includes using a computing power collaborative scheduler software module to uniformly address the ports of the high-speed switching board, the multi-core CPU and FPGA coprocessor and onboard storage unit of the first service computing power board, and the heterogeneous acceleration computing power modules of the second service computing power board, so as to provide a unified computing power view for baseband beam control.

[0007] Optionally, in the aforementioned on-board data computing power control system, the multi-core CPU and FPGA coprocessor include a CPU with 16 or more cores, a main frequency of not less than 2.1 GHz, and support for virtualization, and an FPGA coprocessor including at least 693,120 logic units. The onboard storage unit includes an SSD with a capacity of 2TB or more and a PCIe to M.2 NVMe converter, and DDR4 memory with a capacity of not less than 32GB; The CPU of the first service computing power board is simultaneously connected to the FPGA coprocessor and SSD via the PCIe 3.0×4 bus. The intermediate results generated by the FPGA calculation include the beam weight matrix, FFT results, and channel estimation matrix. The intermediate results generated by the FPGA calculation are directly written to the SSD through the CPU to form an integrated storage and computing power structure. The integrated storage and computing power structure is used for high-bandwidth closed-loop access to matrix data at the hundred-beam level. The FPGA coprocessor acts as a hardware accelerator for beam weight calculation, offloading FFT and matrix multiplication into hardware. The multi-core CPU is also used for the serial decision-making logic and exception handling of beam scheduling.

[0008] Optionally, in the on-board data computing power control system, the first service computing power board further includes a beam weight coprocessing software module; The beam weight coprocessing software module includes: The FPGA coprocessor acceleration module is configured to offload FFT, matrix multiplication, and correlation operations into hardware. The multi-core CPU beam weight calculation task module is configured to perform serial decision logic and exception handling for beam scheduling. The SSD beam weight data access module is configured to provide a Btrfs file system, simultaneous recording and playback, and RAID to persistently store the weight matrix at the hundred-beam level, channel measurement data, and intermediate beam scheduling results. The compute-storage integrated data path module is configured to transfer the FPGA computation results from the multi-core CPU beam weight calculation task module to the SSD beam weight data access module via the PCIe 3.0×4 shared bus for low-latency closed-loop access.

[0009] Optionally, in the aforementioned on-board data computing power control system, the second service computing power board includes a heterogeneous acceleration computing power module consisting of a CPU with 16 or more cores, a main frequency of not less than 2.1GHz, a CPU that supports virtualization, a GPU / NPU module, and a capacity of not less than 32GB DDR4 memory. The heterogeneous acceleration computing power module accelerates the inference of the AI ​​model for beam scheduling and runs in parallel with the traditional beam scheduling algorithm of the first service computing power board, so that the control board can perform fusion decision-making between the first service computing power board and the first service computing power board to allocate beam scheduling computing power. The AI ​​models mentioned include reinforcement learning-based beam selection models, inter-beam interference prediction models, and / or beam hopping models.

[0010] Optionally, in the aforementioned on-board data computing power control system, the second service computing power board further includes a beam scheduling AI inference software module; The beam scheduling AI inference software module includes: The AI ​​model inference engine is configured to run AI models based on TensorRT and ONNX Runtime. The AI ​​model is configured to provide the AI ​​model inference engine with a beam selection reinforcement learning model, an inter-beam interference prediction model, and / or a beam hopping model. The inference result feedback module is configured to go up to the high-speed switching board via 10GBASE-KR, and then be forwarded by the high-speed switching board to the control board for fusion decision.

[0011] Optionally, in the aforementioned on-board data computing power control system, the high-speed switching board, the first service computing power board, and the second service computing power board are interconnected with the baseband processing unit through at least four 10GBASE-KR high-speed serial buses of 10Gbps each, to form a computing power supply channel for the baseband beam control link. The computing power supply channel is used to transmit beam weights, channel status, beam scheduling commands, beam measurement feedback, and beam frequency hopping command data streams. The high-speed switching board exposes the baseband beam control data port on the baseband side and distributes the data stream to the management board, the first service computing power board, and the second service computing power board through the onboard switching matrix on the integrated electronic side.

[0012] Optionally, in the aforementioned on-board data computing power control system, the control board further includes a computing power collaborative scheduler software module; The computing power collaborative scheduler software module includes: The resource unified addressing module is configured to uniformly address the heterogeneous acceleration computing power of high-speed switching board ports, first service computing power board, and second service computing power board to form a computing power resource pool. The beam control task mapping module is configured to dynamically select the optimal computing node from the FPGA coprocessor of the first service computing power board, the multi-core CPU of the first service computing power board, and the heterogeneous acceleration computing power of the second service computing power board according to the computing power requirements of the baseband side beam control task. The computing power requirements mentioned above include weight calculation tasks, FFT tasks, and / or AI inference tasks; The beam control data stream scheduling module is configured to transmit a hundred-beam weighted data stream between the high-speed switching board, the first service computing power board, and / or the second service computing power board based on the priority queue, PCIe bandwidth allocation, and DDR QoS mechanism of the high-speed switching board. The AI ​​inference and traditional scheduling fusion adjudication module is configured to fuse and adjudicate the AI ​​inference results of the second service computing power board and the traditional scheduling results of the first service computing power board, and output the final beam control command.

[0013] The present invention also provides a method for controlling on-board data computing power, comprising: Onboard data streams are provided by a single-satellite controllable beam via a baseband beam control link; The integrated electronic board provides the computing power required for the onboard data stream to the baseband beam control link; and The computing power is allocated between the integrated electronic board and the baseband beam control link by the control board.

[0014] In the on-board data computing power control system and method provided by this invention, the computing power required for the on-board data stream is provided to the baseband beam control link through the integrated electronic board, which improves the single-satellite controllable beam capability of the baseband beam control link. It realizes the high-bandwidth data exchange brought about by sinking the board-level heterogeneous computing power of the satellite integrated electronics to the on-board baseband beam control link. Furthermore, the control board allocates computing power between the integrated electronic board and the baseband beam control link, which also improves the collaborative scheduling of computing power between the board of the satellite integrated electronics and the on-board baseband beam control link.

[0015] The inventors of this invention discovered through research that, with the evolution of low-Earth orbit constellations and high-throughput satellites, the number of beams per satellite has been increasing towards "hundreds" or even "thousands," which has become an industry consensus. However, the data flow of hundreds of beams, such as weight updates, channel measurements, inter-beam interference coordination, and beam frequency hopping, far exceeds the processing limits of traditional baseband self-closed loops. At the same time, satellite integrated electronics (especially service computing boards) already possess mature computing power such as domestically produced multi-core CPUs, FPGA coprocessors, heterogeneous acceleration computing power (such as GPUs / NPUs), onboard large-capacity storage, and gigabit / ten-gigabit Ethernet interfaces. However, the traditional architecture has not pushed the integrated electronic computing power down to the baseband beam control loop, only undertaking the traditional functions of "satellite service + attitude and orbit control + application services," resulting in significant idle computing power.

[0016] Currently disclosed prior art closely related to this invention includes: Existing technology 1 discloses a spaceborne heterogeneous computing system integrating CPU, FPGA and NPU modules, which achieves high computing power environment and low power consumption through triple redundant storage, dynamic scheduling and distributed network architecture; however, this solution focuses on the construction of the spaceborne heterogeneous computing platform itself and does not involve the coordinated scheduling of heterogeneous computing power and baseband beam control link.

[0017] Existing technology 2 discloses a beam scheduling algorithm based on equal division of the field of view, interference avoidance distance, and dynamic allocation of the starting position of the frequency band resource block; however, this scheme belongs to the algorithm level and does not solve the problem of high-bandwidth data path and computing power supply required for the algorithm to run.

[0018] Existing technology 3 discloses an intelligent beam management method based on AI / ML models for beam scanning, RACH usage, and beam switching; however, this solution focuses on AI beam selection on the ground base station side and does not involve the coordination of onboard integrated electronic computing power and baseband beam control.

[0019] A foreign commercial satellite operator has disclosed an on-board AI computer solution for a Ka-band high-throughput satellite (FPGA for beam scheduling + heterogeneous AI accelerator for AI inference, total satellite power 200W). The solution discloses an on-board intelligent processing architecture based on FPGA for beam scheduling and heterogeneous AI accelerator for inference. However, the solution deploys the on-board computing power as an external "AI computer" independently, without deep integration with the baseband and integrated electronic board-level data exchange system.

[0020] In summary, the existing technology has three core problems: First, the on-board computing power and baseband beam control are physically separated and cannot work together; second, the data exchange bandwidth (gigabit level) between boards is insufficient to support data streams of hundreds of beams; third, the beam scheduling algorithm is not designed in an end-to-end collaborative manner with the underlying computing power supply and data path, which limits the expansion of beam size.

[0021] This invention proposes a cross-functional approach between satellite integrated electronics and onboard baseband processing. Specifically, it presents a high-bandwidth data exchange and computing power collaborative scheduling system and method for commercial low-Earth orbit communication and internet satellites, designed to integrate the board-level heterogeneous computing power of satellite integrated electronics into the onboard baseband beam control link. Specifically, it involves a board-based computing power scheduling architecture based on an onboard integrated electronics board-based platform (consisting of high-speed switching boards, control boards, service computing power boards 1 and 2 interconnected via a unified backplane). By incorporating the board-level heterogeneous computing power of integrated electronics (multi-core CPU computing power + FPGA co-processing computing power + heterogeneous acceleration computing power + onboard large-capacity storage) into the baseband beam control loop, and cooperating with the high-bandwidth data channel exposed to the baseband side by the high-speed switching boards, the controllable beam size of a single satellite is increased from the tens of beams level of traditional baseband self-closed loops to the hundreds of beams level, thereby improving the overall communication capability of the satellite. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the overall architecture of the on-board data computing power control system in one embodiment of the present invention; Figure 2 This is a schematic diagram of the high-speed switching board port allocation and baseband beam control data channel of the on-board data computing power control system in one embodiment of the present invention; Figure 3 This is a schematic diagram of the unified resource addressing and task mapping of the on-board data computing power control system management board as the "computing power collaborative scheduling center" in one embodiment of the present invention; Figure 4 This is a schematic diagram of the integrated storage and computing power structure of the on-board data computing power control system business computing power board 1 in one embodiment of the present invention; Figure 5 This is a schematic diagram of the three-party collaborative working sequence of the on-board data computing power control system "high-bandwidth data exchange + computing power collaborative scheduling + baseband beam control" in one embodiment of the present invention; Figure 6 This is a schematic diagram of the complete closed loop of the on-board data computing power control system with hundred-beam weight data flow in one embodiment of the present invention; Figure 7 This is a schematic diagram of the beam scheduling AI inference and traditional scheduling fusion decision process of the on-board data computing power control system in one embodiment of the present invention. Detailed Implementation

[0023] In this invention, the various embodiments are merely intended to illustrate the solutions of the invention and should not be construed as limiting.

[0024] It should also be noted that within the scope of this invention, the terms "same", "equal", and "equal to" do not mean that the two values ​​are absolutely equal, but allow for a certain reasonable error. In other words, the terms also cover "substantially the same", "substantially equal", and "substantially equal to".

[0025] Furthermore, the numbering of the steps in the methods of the present invention does not limit the execution order of the method steps. Unless otherwise specified, the method steps may be executed in different orders.

[0026] In this invention, the modules of the system according to the invention can be implemented using software, hardware, firmware, or a combination thereof. When a module is implemented using software, its function can be implemented through computer program flow. For example, the module can be implemented using code segments (such as code segments in languages ​​like C and C++) stored in a storage device (such as a hard disk, memory, etc.), wherein the corresponding function of the module can be implemented when the code segment is executed by a processor. When a module is implemented using hardware, its function can be implemented by setting a corresponding hardware structure. For example, the module's function can be implemented by hardware programming a programmable device such as a field-programmable gate array (FPGA), or by designing an application-specific integrated circuit (ASIC) that includes multiple transistors, resistors, capacitors, and other electronic devices. When a module is implemented using firmware, the module's function can be written into a read-only memory such as an EPROM or EEPROM in the form of program code, and the corresponding function of the module can be implemented when the program code is executed by a processor. In addition, some functions of the module may need to be implemented by separate hardware or by working in cooperation with the hardware. For example, the detection function is implemented by a corresponding sensor (such as a proximity sensor, accelerometer, gyroscope, etc.), the signal transmission function is implemented by a corresponding communication device (such as a Bluetooth device, infrared communication device, baseband communication device, Wi-Fi communication device, etc.), the output function is implemented by a corresponding output device (such as a display, speaker, etc.), and so on.

[0027] The on-board data computing power control system and method proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0028] The technical problem this invention aims to solve is: how to integrate the heterogeneous computing power of satellite integrated electronics (multi-core CPU computing power + FPGA coprocessing computing power + heterogeneous acceleration computing power + onboard large-capacity storage) into the baseband beam control link in an end-to-end deterministic scheduling manner, thereby increasing the controllable beam size of a single satellite from the tens of beams level of traditional baseband self-closed loop to the hundreds of beams level; at the same time, through the integrated computing-storage data path design, massive amounts of data such as hundreds of beams-level weights, channel measurements, and intermediate beam scheduling results are completed in a closed loop within the computing power domain, significantly reducing cross-domain transmission latency and bandwidth pressure.

[0029] Specifically, the following five sub-problems need to be solved: First, the bandwidth for data exchange between integrated electronic boards has been increased from gigabit level to 10 gigabit level (single port ≥ 10Gbps, whole board switching capacity ≥ 50Gbps), providing the underlying path for hundred-beam weighted data streams; Second, the baseband and integrated electronic computing power are uniformly addressed and scheduled, with the control board serving as the central hub for collaborative scheduling. Third, the business computing power board 1 provides low-latency closed-loop access to beam weights / channel measurement intermediate results through a computing-storage integrated structure of "multi-core CPU + FPGA coprocessor + onboard large-capacity storage" (shared through a high-speed inter-chip bus); Fourth, the beam weight calculation is offloaded to hardware via the FPGA coprocessor (such as FFT, matrix operation, and channel estimation), and the multi-core CPU focuses on scheduling decisions and exception handling. Fifth, accelerate the inference of beam scheduling AI models (such as reinforcement learning beam selection models) through the heterogeneous acceleration computing power (such as GPU / NPU) of the business computing power board 2, so as to realize the integration of AI beam management and traditional beam scheduling.

[0030] The purpose of this invention is to provide an on-board data computing power control system and method to solve the problem that the controllable beam of a single satellite in the existing communication constellation baseband beam control link is limited by the computing power of the on-board baseband processor.

[0031] To achieve the above objectives, the present invention provides an onboard data computing power control system and method, comprising: a baseband beam control link configured to provide onboard data streams via a single-satellite controllable beam; an integrated electronic board configured to provide the computing power required for the onboard data streams to the baseband beam control link; and a management board configured to allocate computing power between the integrated electronic board and the baseband beam control link.

[0032] Figure 1 The overall architecture of the on-board data computing power control system according to an embodiment of the present invention is shown, such as... Figure 1As shown, embodiments of the present invention propose a high-bandwidth data exchange and computing power collaborative scheduling method and system for on-board intelligent baseband processing, deployed on a board-based hardware platform of satellite integrated electronics, consisting of high-speed exchange boards, control boards, and first service computing power boards (such as...). Figure 1 The business computing power board 1 and the second business computing power board (as shown) are shown. Figure 1 The business computing power board 2 shown is interconnected through a unified backplane bus (high-speed signal connector + low-speed signal connector). Figure 2 This invention illustrates the high-speed switching board port allocation and baseband beam control data channel of an onboard data computing power control system according to an embodiment of the present invention, wherein: In one embodiment of the present invention, the high-speed switching board adopts a dual-core architecture of domestically produced high-logic-capacity FPGA + domestically produced MCU. The FPGA has a built-in bidirectional switching capacity of ≥50Gbps (≥4 10GBASE-SR external optical ports + ≥4 10GBASE-KR internal electrical ports + ≥2 Gigabit Ethernet internal electrical ports), and is interconnected with the service computing power board 1 / 2 and the management board through GTH high-speed SERDES. The MCU is responsible for power-on control, task scheduling, power monitoring and master / slave switching. The high-speed switching board exposes a dedicated port for "baseband beam control data channel", which carries the bidirectional beam control data stream of baseband ↔ integrated electronics (including beam weights, channel state information, beam scheduling commands, beam measurement feedback, beam frequency hopping commands, etc.).

[0033] In one embodiment of the present invention, the control board adopts a big.LITTLE heterogeneous architecture (primary + backup cold backup). The primary small core is a domestically produced hard real-time CPU (≤10us interrupt response), responsible for satellite management and attitude and orbit control; the big core is a domestically produced high-real-time CPU, responsible for autonomous management and computing power collaborative scheduling. The control board, as the "collaborative scheduling hub" of the present invention, is connected to the high-speed switching board via Gigabit Ethernet (with cross-backup via analog switches) and to the PCIe topology of the service computing power board 1 / 2 via PCIe bus. The control board runs the "computing power collaborative scheduler" software module, which uniformly addresses the ports of the high-speed switching board, the multi-core CPU / FPGA / heterogeneous accelerated computing power / onboard large-capacity storage resources of the service computing power board 1 / 2, providing a unified computing power view for baseband beam control.

[0034] In one embodiment of the present invention, the service computing power board 1 adopts a "computing-storage integrated" architecture consisting of a domestic multi-core CPU (≥16 cores, main frequency ≥2.1GHz, supporting virtualization) + a domestic FPGA coprocessor (≥693120 logic units) + an onboard large-capacity SSD (≥2TB, PCIe to M.2 NVMe) + a large-capacity DDR4 memory (≥32GB). It is the computing-storage integrated carrier unit for "beam weight / channel measurement data" of the present invention. Figure 4This invention illustrates an embodiment of the onboard data computing power control system's service computing power board 1, featuring an integrated storage and computing power structure. A domestically produced multi-core CPU simultaneously connects to an FPGA coprocessor and an onboard large-capacity SSD via a PCIe 3.0×4 bus (32Gbps). Intermediate results generated by the FPGA computation (such as beam weight matrices, FFT results, and channel estimation matrices) can be directly written to the SSD via the CPU, eliminating the need for external network transmission. This constitutes a "computing-storage integrated" structure within the board (a storage and computing power integrated structure), particularly suitable for high-bandwidth closed-loop access to large-scale matrix data at the hundred-beam level. The FPGA acts as a hardware accelerator for beam weight computation, offloading FFT, matrix multiplication, and correlation operations. The multi-core CPU focuses on the serial decision-making logic and exception handling for beam scheduling.

[0035] In one embodiment of the present invention, the service computing power board 2 adopts an architecture of domestic multi-core CPU (≥16 cores, main frequency ≥2GHz, supporting virtualization) + heterogeneous accelerated computing power (such as GPU / NPU module, ≥230TOPS INT8) + large-capacity DDR4 memory (≥32GB), and is the carrier unit of the "beam scheduling AI inference" of the present invention. The heterogeneous accelerated computing power accelerates the inference of the AI ​​model of beam scheduling (such as the beam selection model based on reinforcement learning, the inter-beam interference prediction model, and the beam frequency hopping model), and runs in parallel with the traditional beam scheduling algorithm of the service computing power board 1, and is dynamically decided by the control board.

[0036] In one embodiment of the present invention, the high-speed switching board and service computing power board 1 / 2 are interconnected with the baseband processing unit via ≥4 10GBASE-KR high-speed serial buses (10Gbps each), serving as "computing power supply channels" for the baseband beam control link, carrying data streams such as beam weights, channel states, beam scheduling commands, beam measurement feedback, and beam frequency hopping commands. The high-speed switching board exposes a "baseband beam control data port" to the baseband side, and distributes data to the management board (gigabit), service computing power board 1 (10 gigabit), and service computing power board 2 (10 gigabit) through an onboard switching matrix to the integrated electronics side.

[0037] In one embodiment of the present invention, the "computing power collaborative scheduler" software module running on the control board includes: ① a resource unified addressing module, which abstracts the high-speed switching board port, the multi-core CPU / FPGA / SSD of service computing power board 1, and the multi-core CPU / heterogeneous accelerated computing power of service computing power board 2 into a unified resource pool; ② a beam control task mapping module, which dynamically selects the optimal computing power node among the FPGA coprocessing of service computing power board 1, the multi-core CPU of service computing power board 1, and the heterogeneous accelerated computing power of service computing power board 2 according to the computing power requirements of the baseband side beam control task (such as weight calculation task, FFT task, AI inference task); ③ a beam control data flow scheduling module, which ensures high bandwidth, deterministic, and low latency transmission of the hundred-beam weight data flow between the high-speed switching board and service computing power board 1 / 2 through mechanisms such as priority queues, PCIe bandwidth allocation, and DDR QoS of the high-speed switching board; ④ an AI inference and traditional scheduling fusion adjudication module, which compares the AI ​​inference results of service computing power board 2 with those of service computing power board 1. The traditional scheduling results are fused and adjudicated to output the final beam control command. Figure 3 This invention illustrates the unified resource addressing and task mapping of the on-board data computing power control system management board as a "computing power collaborative scheduling hub" in one embodiment of the present invention. Figure 5 The diagram illustrates the timing sequence of the three-way collaborative operation of the on-board data computing power control system, which integrates "high-bandwidth data exchange, computing power collaborative scheduling, and baseband beam control," in one embodiment of the present invention.

[0038] In one embodiment of the present invention, the service computing board 1 runs a "beam weight coprocessing" software module, including: ① an FPGA coprocessing acceleration module, which offloads FFT, matrix multiplication, correlation operations, etc. into hardware; ② a multi-core CPU beam weight calculation task module; ③ an onboard large-capacity SSD beam weight data storage module, which supports Btrfs file system, simultaneous recording and playback, and RAID, and persistently stores the weight matrix at the hundred-beam level, channel measurement data, and intermediate beam scheduling results; ④ an integrated computing-storage data path module, which realizes low-latency closed-loop access within the board (avoiding cross-board network transmission) of FPGA calculation results → multi-core CPU → SSD through a PCIe 3.0×4 shared bus.

[0039] In one embodiment of the present invention, the service computing power board 2 runs a "beam scheduling AI inference" software module, including: ① an AI model inference engine (based on TensorRT, ONNX Runtime, etc.); ② a beam selection reinforcement learning model, an inter-beam interference prediction model, and a beam frequency hopping model; ③ an inference result feedback module, which uplinks to the high-speed switching board via 10GBASE-KR, and is then forwarded by the high-speed switching board to the control board for fusion decision.

[0040] In one embodiment of the present invention, the domestic multi-core CPU of the service computing power board can be replaced with any other domestic multi-core CPU that meets the performance requirements; the domestic FPGA coprocessor of service computing power board 1 can be replaced with any other domestic FPGA that meets the performance requirements; the heterogeneous acceleration computing power of service computing power board 2 can be replaced with any domestic AI inference accelerator card that meets the performance requirements; the domestic FPGA of the high-speed switching board can be replaced with any other FPGA or dedicated switching chip with a switching capacity of ≥50Gbps; and the big.LITTLE cores of the control board can be replaced with any other domestic heterogeneous CPU that meets the hard real-time / strong real-time requirements. The "computing power collaborative scheduler" software module can be replaced with other centralized or distributed scheduling implementations; the "computing-storage integration" structure can be extended to business computing power board 2, and also to other extended business computing power boards; this invention can be extended to various on-board baseband processing scenarios such as Ka / Ku / Q / V arbitrary frequency bands, inter-satellite laser links, and user gateway stations; this invention can support expansion of more than 100 beams (such as 200 beams, 500 beams), only requiring expansion of the number of business computing power boards (extension slots have been reserved on the backplane); the beam scheduling AI model can be replaced with other AI models, such as beam interference prediction based on graph neural networks, beam frequency hopping prediction based on Transformer, etc.

[0041] Compared with the prior art, the present invention has the following beneficial effects: First, the high-bandwidth data exchange capability (≥50Gbps) and heterogeneous computing power (multi-core CPU + FPGA + heterogeneous acceleration computing power + onboard large-capacity storage) of satellite integrated electronics are brought down to the baseband beam control link, increasing the number of controllable beams per satellite from the tens of beams level of traditional baseband self-closed loop to the hundreds of beams level (e.g., from 64 beams to 128 beams or even 192 beams), in line with industry trends such as low-Earth orbit constellations / high-throughput satellites / 6G massive MIMO; Second, through the "multi-core CPU + onboard large-capacity SSD" computing-storage integrated structure of the business computing power board 1 (via PCIe 3.0×4 shared bus), the weight matrix at the hundred-beam level, channel measurement data, and intermediate beam scheduling results are stored and retrieved in a closed loop within the computing power domain, which significantly reduces cross-domain transmission latency (from milliseconds to microseconds) and bandwidth pressure (avoiding long-term occupation of 10 Gigabit ports). Third, by offloading the hardware of FFT, matrix multiplication and correlation operations through the FPGA coprocessor, the single beam weight update delay is reduced by more than 10 times, making real-time weight update at the hundred-beam level possible. Fourth, by accelerating the inference of the beam scheduling AI model through the heterogeneous acceleration computing power of the business computing power board 2, the AI ​​beam management (reinforcement learning beam selection, inter-beam interference prediction, beam frequency hopping) and traditional beam scheduling can run in parallel, with dynamic decision-making by the control board, thereby improving the level of intelligence of beam scheduling. Fifth, by exposing the "baseband beam control data port" to the baseband side through high-speed switching boards, the interconnection bandwidth between integrated electronics and baseband is increased from gigabit level to 10 gigabit level, and a single port can carry more than 4 times the beam weight data stream; Sixth, the control board acts as the "coordinated scheduling hub," uniformly addressing the ports of high-speed switching boards, half of the computing power of service computing boards, and onboard storage resources, thereby avoiding idle computing power and improving the overall satellite resource utilization efficiency. 7. This invention is compatible with the existing spaceborne integrated electronic board architecture, reusing the hardware platform of high-speed switching board, service computing power board 1 / 2, and control board, and only adding software modules ("computing power collaborative scheduler", "beam weight co-processing", "beam scheduling AI inference"), without the need for hardware redesign, which significantly reduces engineering costs; 8. This invention supports scalability of more than 100 beams. The backplane has reserved expansion slots, which can expand the number of service computing power boards as needed, and further expand the controllable beam scale of a single satellite to 200 beams or even 500 beams, in sync with the evolution path of high-throughput satellites and 6Gmassive MIMO.

[0042] Embodiments of the present invention also provide a method for controlling onboard data computing power, comprising: providing onboard data streams via a single-satellite controllable beam of a baseband beam control link; providing computing power required for the onboard data streams to the baseband beam control link via an integrated electronic board; and allocating computing power between the integrated electronic board and the baseband beam control link via a control board.

[0043] The on-board data computing power control system proposed in the embodiments of the present invention is deployed on a spaceborne integrated electronic board hardware platform and is implemented according to the following steps: I. Hardware platform setup; The first step is to deploy a high-speed switching board (domestic high logic capacity FPGA + domestic MCU + domestic PHY chip + DDR memory + optical module), connect to the baseband processing unit (baseband beam control data channel) through ≥4 10GBASE-SR optical ports, connect to the service computing power board 1 / 2 through ≥4 10GBASE-KR electrical ports, and connect to the management and control board through ≥2 gigabit Ethernet electrical ports. The second step is to deploy a management board host (domestic small-core CPU + domestic large-core CPU + domestic FPGA + MRAM radiation-resistant storage + onboard SSD + CAN-FD controller + analog switch), which is connected to the gigabit network port of the high-speed switching board through one 1000Base-T channel via two-stage analog switches, and connected to the PCIe topology of half of the service computing power board through PCIe 3.0×4 via multiple MUX switches. At the same time, a backup management board is deployed as a cold backup. The third step is to deploy the business computing power board 1 (domestic multi-core CPU + domestic FPGA coprocessor + onboard large-capacity SSD (M.2 NVMe, PCIe 3.0×4 adapter) + large-capacity DDR4 memory + 3 NOR FLASH chips + 2 Gigabit Ethernet ports + PCIe 3.0×4 bus interface), which realizes the "computing-storage integration" of "multi-core CPU + FPGA coprocessor + onboard large-capacity SSD" through the PCIe 3.0×4 shared bus; The fourth step is to deploy the business computing power board 2 (domestic multi-core CPU + heterogeneous acceleration computing power module + large-capacity DDR4 memory + 3 NOR FLASH chips + 2 gigabit Ethernet ports + PCIe 3.0 × 4 bus interface). The fifth step involves interconnecting the high-speed switching board, control board, service computing board 1, and service computing board 2 via a unified backplane bus (high-speed signal connector + low-speed signal connector) to form a complete high-bandwidth data exchange and computing power collaborative scheduling system.

[0044] II. Software Module Deployment; The sixth step is to deploy the "computing power collaborative scheduler" software module (running on a large-core real-time operating system) on the control board, including a resource unified addressing module, a beam control task mapping module, a beam control data flow scheduling module, and an AI inference and traditional scheduling fusion adjudication module. Step 7: Deploy the "beam weight coprocessing" software module (running on a multi-core domestic CPU operating system) on the business computing power board 1, including the FPGA coprocessing acceleration module, the multi-core CPU beam weight calculation task module, the onboard large-capacity SSD beam weight data storage and retrieval module, and the computing-storage integrated data path module. Step 8: Deploy the "Beam Scheduling AI Inference" software module (running on a multi-core domestic CPU operating system) on the business computing power board 2, including the AI ​​model inference engine, beam selection reinforcement learning model, inter-beam interference prediction model, beam frequency hopping model, and inference result feedback module. Step 9: Configure a dedicated port for the "baseband beam control data channel" (occupying part of the port in the 10G-SR) in the high-speed switching board FPGA, and configure the beam control data stream priority queue, DDR QoS, and PCIe bandwidth allocation strategy. Step 10: After the entire satellite is powered on in orbit, the small core hard real-time operating system of the control board starts and runs the satellite service software and attitude and orbit control software; the large core strong real-time operating system starts the "computing power collaborative scheduler"; the service computing power board 1 / 2 starts its respective software modules; the high-speed switching board MCU controls the FPGA to power on and complete the configuration loading.

[0045] III. Hundred-beam baseband beam control process; In the eleventh step, the baseband processing unit sends a hundred-beam-level beam weight update request (including target beam ID set, beam weight matrix, and channel state information) to the high-speed switching board through the 10G BASE-SR baseband beam control data channel, requesting a bandwidth of approximately 8 Gbps (hundred-beam level). Step 12: The high-speed switching board FPGA receives the request and forwards it to the PCIe 3.0×4 interface (32 Gbps bandwidth) of the service computing power board 1 according to the priority queue configured on the management board (beam control data stream has the highest priority). At the same time, it sends a task notification to the gigabit network port of the management board. Step 13: The control board's "computing power co-scheduler" distributes the task (weight calculation / FFT / AI inference) to the optimal computing power node among the FPGA coprocessor (FFT / matrix multiplication / related operations) of business computing power board 1, the multi-core CPU (beam scheduling serial decision) of business computing power board 1, and the heterogeneous accelerated computing power (AI inference) of business computing power board 2, based on the request content (weight calculation / FFT / AI inference). Step 14: The FPGA coprocessor of the business computing board 1 completes hardware acceleration tasks such as FFT, matrix multiplication, and related operations (the update latency of the hundred-beam weight is about 1 ms). The calculation results are directly written to the onboard large-capacity SSD through the PCIe 3.0×4 shared bus via the multi-core CPU (avoiding cross-board network transmission), forming a "computing-storage integration" structure within the single board. In step 15, the multi-core CPU of service computing board 1 completes the serial decision-making of beam scheduling (such as beam priority sorting and beam collision detection), and the heterogeneous accelerated computing power of service computing board 2 completes the inference of beam scheduling AI model (such as reinforcement learning beam selection, inter-beam interference prediction, and beam frequency hopping). The two results are uplinked to the high-speed switching board through 10G BASE-KR. Step 16: The high-speed switching board FPGA forwards the two results (traditional scheduling result + AI inference result) to the management board via gigabit network port; Step 17: The "AI inference and traditional scheduling fusion adjudication module" of the control board's "computing power collaborative scheduler" fuses and adjudicates the two results, and outputs the final beam control command. Figure 7 This paper illustrates the beam scheduling AI inference and traditional scheduling fusion decision process of an on-board data computing power control system according to an embodiment of the present invention.

[0046] Step 18: The final beam control command passes through the management board → high-speed switching board → 10G BASE-SR baseband beam control data channel → baseband processing unit to complete the closed loop of the hundred-beam level beam weight update. Figure 6 This illustrates a complete closed loop of the onboard data computing power control system with 100-beam weighted data flow in one embodiment of the present invention.

[0047] In the above process, the hundred-beam weight data stream forms a complete closed loop between the baseband, high-speed switching board, service computing board 1 / 2, and control board; the "computing-storage integration" structure (PCIe 3.0×4 shared bus) inside the service computing board 1 allows the FPGA calculation results to be directly written to the SSD without external network transmission; the "computing power coordination scheduler" of the control board uniformly addresses the ports of the high-speed switching board, the computing power of the service computing board 1 / 2, and the onboard storage resources, avoiding idle computing power.

[0048] Through this invention, the controllable beam size of a single satellite can be increased from the tens of beams level of traditional baseband self-closed loop to the hundreds of beams level (e.g., from 64 beams to 128 beams or even 192 beams), and the overall satellite beam control capability can be improved by 2-3 times.

[0049] The innovative aspects of this invention include at least: First, based on the board-based integrated spaceborne electronic architecture of "high-speed switching board (domestic FPGA, ≥50Gbps switching capacity) + control board (big and small core heterogeneous) + service computing power board 1 (multi-core CPU + FPGA coprocessor + onboard large-capacity SSD computing-storage integration) + service computing power board 2 (multi-core CPU + heterogeneous acceleration computing power)", the computing power of the integrated electronics is pushed down to the baseband beam control link, increasing the scale of controllable beams of a single satellite from tens of beams to hundreds of beams. Second, the service computing power board 1 based on the PCIe 3.0×4 shared bus has a "computing-storage integration" structure (FPGA coprocessor + onboard large-capacity SSD sharing a multi-core CPU PCIe bus) to realize low-latency closed-loop access of the hundred-beam weight data stream within the computing power domain (avoiding cross-domain network transmission). Third, based on the resource unified addressing and beam control task mapping mechanism of the "computing power collaborative scheduler" of the control board, the high-speed switching board port and the multi-core CPU / FPGA / heterogeneous acceleration computing power / SSD computing power of the service computing power board 1 / 2 are abstracted into a unified resource pool, providing end-to-end deterministic scheduling for baseband beam control. Fourth, based on the high-bandwidth port configuration of multiple 10GBASE-SR, multiple 10GBASE-KR, and multiple gigabit Ethernet ports of the high-speed switching board, the "baseband beam control data port" is exposed on the baseband side, which increases the interconnection bandwidth between the integrated electronics and the baseband from gigabit level to 10 gigabit level. Fifth, a fusion decision mechanism based on beam scheduling AI inference and traditional FPGA + multi-core CPU scheduling based on the heterogeneous acceleration computing power of the business computing power board 2, the control board dynamically decides the AI ​​inference results and traditional scheduling results, and outputs the final beam control command; Sixth, based on the unified backplane bus (high-speed signal connector + low-speed signal connector), the board-level scalability is provided. The backplane has reserved expansion slots to support scalability of more than 100 beams (200 / 500 beams), which is in sync with the evolution path of high-throughput satellites and 6G massive MIMO. 7. Based on the design of the scheduler operating environment of the control board with big and small cores heterogeneous (small cores running star service / attitude and orbit control in hard real time + big cores running computing power collaborative scheduler in strong real time), the hard real-time control (≤10us interrupt response) and strong real-time computing power scheduling (millisecond-level task mapping) are decoupled to avoid the scheduler preempting star service / attitude and orbit control resources.

[0050] The embodiments of the present invention also include: Autonomous management includes relying on an integrated electronic platform and using onboard autonomous management software to achieve autonomous perception of satellite status, autonomous task scheduling, autonomous resource allocation, and autonomous fault diagnosis and handling. Under limited ground intervention, it enables the coordinated operation of the entire satellite platform and payloads, constructs an onboard "autonomous control center," and enhances the satellite's on-orbit survivability and mission efficiency.

[0051] The serial decision-making logic of beam scheduling includes the beam scheduling unit completing resource conflict detection, resource allocation decision, beam command generation and resource status update for each beam requirement in the order of the task queue, and starting the next task only after completing the entire process decision for a single task.

[0052] Btrfs is a modern file system native to the Linux kernel based on the B-tree File System and copy-on-write mechanism. It integrates subvolumes, instantaneous snapshots, data verification and self-healing, transparent compression, and multi-device storage pool capabilities. It provides stronger data fault tolerance and flexible storage management capabilities without the need for additional volume management components, making it suitable for unattended spaceborne embedded storage systems that require on-orbit data backup.

[0053] RAID is a redundant array of multiple solid-state drives (SSDs). It improves read and write bandwidth through striping and defends against single-disk hardware failures through mirroring / verification mechanisms. Due to the limitations of SSD garbage collection and reconstruction IO pressure characteristics, solid-state storage generally prioritizes RAID1 / RAID10 and uses RAID5 / RAID6 with caution or prohibits its use. RAID only solves the problem of entire disk failure and cannot detect flash bit flips. It usually needs to be used in conjunction with a file system with data verification capabilities.

[0054] TensorRT and ONNX Runtime: TensorRT is NVIDIA's deep learning inference optimization engine for GPU platforms. It optimizes trained models through computation graph fusion, operator tuning, and precision quantization, reducing computational and memory overhead and significantly lowering inference latency. It is suitable for AI tasks such as target detection and image recognition in spaceborne intelligent payloads, and only supports the NVIDIA GPU ecosystem. The model inference engine is strongly tied to the hardware architecture. ONNX Runtime is a cross-platform deep learning inference framework based on the open ONNX model format. It adopts a pluggable execution provider architecture and can run inference on CPUs, GPUs, and various AI accelerators. It balances deployment versatility with hardware acceleration capabilities, making it suitable for iterative development across multiple hardware platforms. However, its native performance on NVIDIA GPUs is weaker than TensorRT.

[0055] 10GBASE-KR is a single-channel 10Gbps backplane Ethernet physical layer standard defined by IEEE 802.3ap. It adopts 64B / 66B encoding, 10.3125Gbaud serial transmission, and has a built-in link training and auto-negotiation mechanism. It is compatible with high-speed differential interconnects of PCB backplanes with connectors and is widely used for large data transmission between VPX chassis and spaceborne integrated electronic boards.

[0056] While some embodiments of the present invention have been described in this application, those skilled in the art will understand that these embodiments are merely illustrative. Numerous variations, alternatives, and improvements will arise in those skilled in the art under the teachings of this invention without departing from its scope. The appended claims are intended to define the scope of the invention and thereby cover the methods and structures within the scope of the claims themselves and their equivalents in power conversion.

Claims

1. A satellite data computing power control system, characterized in that, include: The baseband beam control link is configured to provide onboard data streams via a single-satellite controllable beam; The integrated electronic board is configured to provide the computing power required to supply the onboard data stream to the baseband beam control link; as well as The control board is configured to distribute computing power between the integrated electronic board and the baseband beam control link.

2. The on-board data computing power control system as described in claim 1, characterized in that, The integrated electronic board includes: The first service computing power board is configured to form an integrated storage and computing power structure between the multi-core CPU, FPGA coprocessor, and onboard storage unit via a high-speed inter-chip bus, providing low-latency closed-loop access within the board for beam weights and / or channel measurement intermediate results; and The second business computing power board is configured to accelerate the inference of the beam scheduling AI model through the heterogeneous acceleration computing power module, so as to integrate AI beam management with traditional beam scheduling.

3. The on-board data computing power control system as described in claim 2, characterized in that, The control board includes: The mainframe small core is configured to perform space service management and attitude and orbit control via real-time CPU. The host CPU core is configured to manage the autonomous operation of control boards¹ and coordinate computing power scheduling through real-time CPU. The backup small core is configured as a cold backup for the main small core, and the backup large core is configured as a cold backup for the main large core. The control board is connected to the high-speed switching board via gigabit Ethernet and analog switch cross-backup, and is connected to the PCIe topology of the first service computing power board and the second service computing power board via PCIe bus; The collaborative scheduling includes using a computing power collaborative scheduler software module to uniformly address the ports of the high-speed switching board, the multi-core CPU and FPGA coprocessor and onboard storage unit of the first service computing power board, and the heterogeneous acceleration computing power modules of the second service computing power board, so as to provide a unified computing power view for baseband beam control.

4. The on-board data computing power control system as described in claim 2, characterized in that, The multi-core CPU and FPGA coprocessor include a CPU with 16 or more cores, a main frequency of not less than 2.1 GHz, and support for virtualization, and an FPGA coprocessor including at least 693,120 logic units; The onboard storage unit includes an SSD with a capacity of 2TB or more and a PCIe to M.2 NVMe converter, and DDR4 memory with a capacity of not less than 32GB; The CPU of the first service computing power board is simultaneously connected to the FPGA coprocessor and SSD via the PCIe 3.0×4 bus. The intermediate results generated by the FPGA calculation include the beam weight matrix, FFT results, and channel estimation matrix. The intermediate results generated by the FPGA calculation are directly written to the SSD through the CPU to form an integrated storage and computing power structure. The integrated storage and computing power structure is used for high-bandwidth closed-loop access to matrix data at the hundred-beam level. The FPGA coprocessor acts as a hardware accelerator for beam weight calculation, offloading FFT and matrix multiplication into hardware. The multi-core CPU is also used for the serial decision-making logic and exception handling of beam scheduling.

5. The on-board data computing power control system as described in claim 4, characterized in that, The first service computing power board also includes a beam weight coprocessing software module; The beam weight coprocessing software module includes: The FPGA coprocessor acceleration module is configured to offload FFT, matrix multiplication, and correlation operations into hardware. The multi-core CPU beam weight calculation task module is configured to perform serial decision logic² and exception handling for beam scheduling. The SSD beamweight data access module is configured to provide Btrfs³ file system, simultaneous recording and playback, and RAID. 4 This allows for the persistent storage of weight matrices at the hundred-beam level, channel measurement data, and intermediate beam scheduling results. The compute-storage integrated data path module is configured to transfer the FPGA computation results from the multi-core CPU beam weight calculation task module to the SSD beam weight data access module via the PCIe 3.0×4 shared bus for low-latency closed-loop access.

6. The on-board data computing power control system as described in claim 2, characterized in that, The second service computing power board includes a heterogeneous acceleration computing power module consisting of a CPU with more than 16 cores, a main frequency of not less than 2.1GHz, a virtualization-supporting CPU, a GPU / NPU module, and a capacity of not less than 32GB DDR4 memory; The heterogeneous acceleration computing power module accelerates the inference of the AI ​​model for beam scheduling and runs in parallel with the traditional beam scheduling algorithm of the first service computing power board, so that the control board can perform fusion decision-making between the first service computing power board and the first service computing power board to allocate beam scheduling computing power. The AI ​​models mentioned include reinforcement learning-based beam selection models, inter-beam interference prediction models, and / or beam hopping models.

7. The on-board data computing power control system as described in claim 6, characterized in that, The second service computing board also includes a beam scheduling AI inference software module; The beam scheduling AI inference software module includes: The AI ​​model inference engine is configured to be based on TensorRT and ONNX Runtime. 5 Running AI models; The AI ​​model is configured to provide the AI ​​model inference engine with a beam selection reinforcement learning model, an inter-beam interference prediction model, and / or a beam hopping model. The inference result return module is configured to use 10GBASE-KR. 6 The data is sent to the high-speed switching board, which then forwards it to the control board for fusion and adjudication.

8. The on-board data computing power control system as described in claim 2, characterized in that, The high-speed switching board, the first service computing board, and the second service computing board are interconnected with the baseband processing unit through a 10GBASE-KR high-speed serial bus with at least four 10Gbps channels, forming a computing power supply channel for the baseband beam control link. The computing power supply channel is used to transmit beam weights, channel status, beam scheduling commands, beam measurement feedback, and beam frequency hopping command data streams. The high-speed switching board exposes the baseband beam control data port on the baseband side and distributes the data stream to the management board, the first service computing power board, and the second service computing power board through the onboard switching matrix on the integrated electronic side.

9. The on-board data computing power control system as described in claim 2, characterized in that, The control board also includes a computing power collaborative scheduler software module; The computing power collaborative scheduler software module includes: The resource unified addressing module is configured to uniformly address the heterogeneous acceleration computing power of high-speed switching board ports, first service computing power board, and second service computing power board to form a computing power resource pool. The beam control task mapping module is configured to dynamically select the optimal computing node from the FPGA coprocessor of the first service computing power board, the multi-core CPU of the first service computing power board, and the heterogeneous acceleration computing power of the second service computing power board according to the computing power requirements of the baseband side beam control task. The computing power requirements mentioned above include weight calculation tasks, FFT tasks, and / or AI inference tasks; The beam control data stream scheduling module is configured to transmit a hundred-beam weighted data stream between the high-speed switching board, the first service computing power board, and / or the second service computing power board based on the priority queue, PCIe bandwidth allocation, and DDR QoS mechanism of the high-speed switching board. The AI ​​inference and traditional scheduling fusion adjudication module is configured to fuse and adjudicate the AI ​​inference results of the second service computing power board and the traditional scheduling results of the first service computing power board, and output the final beam control command.

10. A method for controlling on-board data computing power, characterized in that, include: Onboard data streams are provided by a single-satellite controllable beam via a baseband beam control link; The integrated electronic board provides the computing power required for the onboard data stream to the baseband beam control link; as well as The computing power is allocated between the integrated electronic board and the baseband beam control link by the control board.

Images