Method for adjusting signal amplitude, electro-optical modulator, readable storage medium and computer program product

Abstract

The embodiment of the application provides a signal amplitude adjusting method, an electro-optical modulator, a readable storage medium and a computer program product. The method is applied to the electro-optical modulator, and the electro-optical modulator comprises a driving circuit. The driving circuit comprises a plurality of slice circuits. The method comprises the following steps: adjusting the output logic of a target slice circuit in the plurality of slice circuits through at least one lookup table (LUT) circuit in the target slice circuit, so as to adjust the output level of a multi-amplitude signal input into the electro-optical modulator, thereby compensating for the nonlinear effect in the electro-optical conversion process and improving the signal integrity. The problem that an electro-optical transmitter in the prior art cannot effectively process a signal introducing nonlinearities in the electro-optical conversion is solved.

Description

Technical Field

[0001] This application relates to the field of communications, and more specifically, to a method for adjusting signal amplitude, an electro-optic modulator, a readable storage medium, and a computer program product. Background Technology

[0002] With the rapid development of applications such as cloud computing, big data, and artificial intelligence, the computing and storage demands of data centers are increasing dramatically, and the bandwidth requirements for interconnection between data centers are also constantly rising. Traditional copper cable transmission can no longer meet the demands of modern data centers for high bandwidth and low latency, especially in long-distance, high-speed connections, where the transmission speed and signal attenuation of copper cables limit their application. In contrast, optical fiber offers higher bandwidth, lower latency, and longer transmission distances, making optical modules the ideal choice for data center interconnection and large-scale data transmission. To meet this demand, optical modules, as key components for data transmission, have become an indispensable technical part of data center networks. In optical modules, the drive circuit and modulator of the optical transmitter are key components, working together to generate and transmit the modulated signal. The quality of the modulated signal generated by the drive circuit directly affects the performance of the entire optical module.

[0003] Traditional electro-optic transmitters employ a linear analog amplification architecture, cascading multiple amplifier circuits to increase the swing of the input signal, ultimately meeting the swing requirements of the optical modulator. While this approach can linearly amplify the input signal, it cannot effectively process the nonlinearities introduced by electro-optic conversion. Summary of the Invention

[0004] This application provides a signal amplitude adjustment method, an electro-optic modulator, a readable storage medium, and a computer program product to at least solve the problem in the related art that electro-optic transmitters cannot effectively process signals introduced by electro-optic conversion that are nonlinear.

[0005] According to one embodiment of this application, a method for adjusting signal amplitude is provided, applied to an electro-optic modulator, the electro-optic modulator including a driving circuit, the driving circuit including multiple slice circuits, the method comprising:

[0006] The output logic of the target slice circuit is adjusted by at least one lookup table (LUT) circuit in the target slice circuit among the plurality of slice circuits to adjust the output level of the multi-amplitude signal input to the electro-optic modulator.

[0007] According to another embodiment of this application, an electro-optic modulator is provided, including a driving circuit, the driving circuit including a plurality of slice circuits;

[0008] The target slice circuit among the plurality of slice circuits is used to adjust the output logic of the target slice circuit through at least one lookup table (LUT) circuit in the target slice circuit to adjust the output level of the multi-amplitude signal input to the electro-optic modulator.

[0009] According to yet another embodiment of this application, a computer-readable storage medium is also provided, wherein a computer program is stored therein, and the computer program is configured to perform the steps in any of the above method embodiments when it is run.

[0010] According to yet another embodiment of this application, an electronic device is also provided, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0011] According to yet another embodiment of this application, a computer program product is also provided, including a computer program that, when executed by a processor, implements the steps in any of the above method embodiments.

[0012] In this embodiment, by using the output logic of the LUT control slice, the amplitude of the output signal is adjusted, thereby compensating for the nonlinear effects in the electro-optic conversion process and improving signal integrity. This solves the problem in related technologies where electro-optic transmitters cannot effectively process signals introduced by electro-optic conversion. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of a LUT-based multi-amplitude electro-optic modulator architecture according to an embodiment of this application;

[0014] Figure 2 This is a flowchart of a signal amplitude adjustment method according to an embodiment of this application;

[0015] Figure 3 This is a schematic diagram of a single slice circuit according to an embodiment of this application;

[0016] Figure 4 This is a schematic diagram of the internal structure of a single slice NRZ circuit (4-channel mux) according to an embodiment of this application;

[0017] Figure 5 This is a waveform diagram without any equalization processing according to an embodiment of this application;

[0018] Figure 6 This is a waveform diagram of equalization processing for FFE according to an embodiment of this application;

[0019] Figure 7This is a waveform diagram illustrating the equalization processing of rising edges according to an embodiment of this application.

[0020] Figure 8 This is a waveform diagram illustrating equalization processing of the falling edge according to an embodiment of this application.

[0021] Figure 9 This is a digital logic block diagram of a multi-amplitude electro-optic modulator based on a lookup table, according to an embodiment of this application.

[0022] Figure 10 This is a structural block diagram of an electro-optic modulator according to an embodiment of this application;

[0023] Figure 11 This is a structural block diagram of an electronic device according to an embodiment of this application. Detailed Implementation

[0024] The embodiments of this application will be described in detail below with reference to the accompanying drawings and examples.

[0025] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0026] To achieve higher data transmission rates, a combination of multi-amplitude modulation (MPM) and optical interconnects is considered to overcome this challenge. For example, 4-level pulse amplitude modulation (PAM4) uses four different signal levels for data transmission (0 / 1 / 2 / 3), with each symbol period representing 2 bits of logic information (Most Significant Bit (MSB) and Least Significant Bit (LSB)). Therefore, to achieve the same bit rate, PAM4 signals require only half the baud rate and half the bandwidth of non-return-to-zero (NRZ) signals, leading to its increasingly widespread application. However, to obtain a good eye diagram, PAM4 modulation demands higher driver linearity compared to NRZ modulation. Compared to traditional electrical transmitters, PAM4-modulated electro-optical transmitters not only need to meet their own linearity requirements but also require compensation for the nonlinearity in the process of converting electrical signals to optical signals.

[0027] Traditional electro-optic transmitters employ a linear analog amplification architecture, cascading multiple amplifier circuits to increase the swing of the input signal, ultimately meeting the swing requirements of the optical modulator. While this approach linearly amplifies the input signal, it struggles to effectively process the nonlinearities introduced by electro-optic conversion. This issue is less pronounced in NRZ modulation, but in multi-amplitude modulation, such as PAM4 modulation, the nonlinearity leads to inconsistent rise and fall times in the eye diagram, as well as inconsistent eye heights (eye opening sizes) among the three eyes (the three eye regions formed by level changes in the PAM4 signal). These factors severely impact the multi-amplitude electro-optic modulation driver.

[0028] To address the aforementioned technical problems, this application proposes a method for adjusting the signal amplitude of an electro-optic modulator. The driving circuit of the electro-optic modulator adopts a sliced ​​architecture, meaning it can be divided into multiple circuits with identical structures but different weights. Each circuit is called a slice, and the output of a single slice is controlled by its internal LUT (Low-Level Transformer). The final output is obtained by synthesizing multiple slices. By utilizing the LUT within the slice to control the rising and falling edges of the signal, the nonlinearity introduced by the electro-optic conversion is compensated, improving signal integrity. This solves the problem in related technologies where electro-optic transmitters cannot effectively process signals with nonlinearity introduced by electro-optic conversion.

[0029] The following describes the terms used in the embodiments of this application:

[0030] Non-Return-to-Zero (NRZ):

[0031] NRZ is the most basic binary signal encoding method. The signal maintains a constant level within a bit period, either high (representing 1) or low (representing 0). NRZ signals are simple and intuitive, but in high-speed communication, their fixed level can lead to DC offset and signal attenuation effects, and make it difficult to extract the clock signal at the receiving end.

[0032] Most significant bit (MSB) and least significant bit (LSB):

[0033] MSB and LSB represent the most significant bit and least significant bit in a binary number, respectively, and they are the basic units that constitute a binary number. In multilevel modulation, such as four-level pulse amplitude modulation (PAM4), more than one bit of information can be transmitted within each modulation symbol period, and the combination of MSB and LSB is used to represent different signal levels.

[0034] PAM4:

[0035] PAM4 is a four-level pulse amplitude modulation technique where each symbol period can represent 2 bits of information. PAM4 uses four different voltage levels (typically represented as 0 / 1 / 2 / 3) to transmit data, where 0 and 1 correspond to the low and high levels in NRZ, while 2 and 3 are additional intermediate levels. In PAM4, the combination of the MSB and LSB determines the specific signal level transmitted: for example, "00" corresponds to level 0, "01" to level 1 / 3, "10" to level 2 / 3, and "11" to level 1.

[0036] The relationship between PAM4 and NRZ:

[0037] PAM4 is a multi-level modulation based on NRZ signals. In PAM4, the original data stream is divided into high-order bits (MSB) and low-order bits (LSB) NRZ data streams, which are then amplified and modulated by different driving circuits (such as slicing circuits with different weights) and finally synthesized to form the PAM4 signal. Therefore, PAM4 can be seen as an extension of NRZ signals, combining high-level and low-level NRZ signals to generate more complex signal levels and improve data transmission efficiency.

[0038] The roles of MSB and LSB in PAM4:

[0039] In PAM4, one symbol cycle can transmit two bits of information, represented by the MSB and LSB. The MSB determines which "high" level (0 or 1) the signal is at, while the LSB determines whether it is at a specific level of 0, 1 / 3, 2 / 3, or 1. This combination of MSB and LSB allows PAM4 to double the amount of information per symbol cycle without increasing bandwidth, thereby increasing the data transmission rate.

[0040] MSB and LSB play an encoding role in the conversion of NRZ signals to PAM4 signals. Compared with NRZ, PAM4 improves the efficiency of data transmission by introducing additional signal levels.

[0041] Figure 1 This is a schematic diagram of a LUT-based multi-amplitude electro-optic modulator architecture according to an embodiment of this application. This embodiment can operate in... Figure 1 On the electro-optic modulator architecture shown, such as Figure 1 As shown, the electro-optic modulator may include: a clock and data recovery (CDR) module and a drive circuit.

[0042] The CDR module can be used to convert the high-order modulation signal PAM4 into an NRZ signal so that nonlinear equalization processing can be performed on the NRZ signal.

[0043] The driving circuit consists of multiple slice circuits with identical structures but different driving capabilities. Each slice circuit is pre-configured with corresponding weights; for example, there are 3 MSB slices and 3 LSB slices, with the MSB slices configured with weights of 8, 4, and 2, and the LSB slices configured with weights of 4, 2, and 1. These 6 slices, through the current of the output circuit, can directly synthesize a 112G PAM4 signal. In this embodiment, by adjusting the activation state of the MSB or LSB slice weights, the level of each signal state can be finely controlled to optimize signal quality and transmission performance.

[0044] Each slice circuit may include a retiming circuit, a lookup table circuit, a MUX circuit, and an output stage circuit.

[0045] The retiming circuit can be used to receive multiple NRZ signals transmitted by the CDR module, sample the multiple NRZ signals, and align them according to the clock to obtain the processed multiple NRZ signals.

[0046] The lookup table circuit can be used to control each slice circuit through an off-chip configuration control word. Based on the NRZ signal input to the lookup table, it searches for the corresponding NRZ output signal and controls the activation state of the preset weight of the corresponding slice based on the NRZ output signal.

[0047] The MUX circuit can be used to synthesize multiple NRZ signals output by the lookup table circuit into a single full-rate signal.

[0048] The output stage circuit can be used to amplify a single full-rate signal.

[0049] For example, such as Figure 1 As shown, the front end of the electro-optic modulator can receive 112Gbps PAM4 differential signals. PAM4 stands for four-level pulse amplitude modulation, meaning that 2 bits of information can be transmitted per symbol period.

[0050] The received PAM4 signal can first enter the CDR module. The CDR module can be used to extract the clock signal from the signal and recover the data stream, while converting the PAM4 signal into an NRZ signal for subsequent circuit processing. In this embodiment, the CDR module can decompose the 112Gbps PAM4 signal into multiple 56Gbps NRZ signals, and further decompose each 56Gbps NRZ signal to obtain multiple 14Gbps NRZ signals to adapt to the processing of the sliced ​​drive circuit.

[0051] The driving circuit is connected to the sliced ​​driving circuit of the CDR module. The sliced ​​driving circuit consists of multiple sub-circuits (i.e., slices) with different driving capabilities but identical structures. The driving capability of each slice can be determined by its corresponding pre-configured weight; the higher the weight, the higher the driving capability. Each slice receives the NRZ signal and performs logic control and signal encoding according to its internal lookup table. By changing the LUT content of the slice, the amplitude and shape of the signal can be precisely controlled to compensate for the nonlinear effects in the electro-optical conversion process.

[0052] The output signals from multiple slices are combined. In the output stage circuit, these signals are synthesized into a high-speed PAM4 signal, which ultimately drives the electro-optic modulator. The output stage circuit is responsible for signal amplification and shaping, ensuring that the signal has sufficient amplitude and the correct shape to effectively drive the modulator.

[0053] In this embodiment, the LUT circuit can control the output state of each slice circuit according to the code pattern (combination of MSB and LSB) of the input signal through predefined output rules. These rules can be dynamically adjusted to adapt to the needs of signal transmission. For example, to address nonlinearity issues related to rising or falling edges, the LUT circuit can be configured to output different levels or voltages under specific code pattern combinations, thereby ensuring that the final PAM4 signal has the correct eye height and rise / fall times.

[0054] This embodiment provides a method for adjusting the signal amplitude operating on the aforementioned electro-optic modulator. Figure 2 This is a flowchart of a signal amplitude adjustment method according to an embodiment of this application, applied to an electro-optic modulator. The electro-optic modulator includes a driving circuit, which includes multiple slice circuits, such as... Figure 2 As shown, the process includes the following steps:

[0055] Step S201: Adjust the output logic of the target slice circuit by using at least one lookup table (LUT) circuit in the target slice circuit among the plurality of slice circuits to adjust the output level of the multi-amplitude signal input to the electro-optic modulator.

[0056] For example, the driving circuit of this application embodiment may include multiple slice circuits, each slice circuit may include at least one LUT circuit, and each LUT circuit in the slice circuit can independently control the output logic of the slice circuit.

[0057] In one exemplary embodiment, the electro-optic modulator further includes a clock and data recovery (CDR) module, and the method further includes:

[0058] The input multi-amplitude signal is decomposed into multiple low-speed signals by the CDR module, and at least one of the multiple low-speed signals is input to the target slicing circuit; wherein, each LUT circuit of the target slicing circuit is used to adjust the output code pattern of one low-speed signal.

[0059] For example, in this application embodiment, the low-speed signal is a signal with a rate lower than that of the multiple amplitude signals. For instance, the CDR module can decompose the 112Gbps PAM4 signal input to the electro-optic modulator into two 56Gbps NRZ signals, and further decompose each 56Gbps NRZ signal to obtain multiple 14Gbps NRZ signals for input to the drive circuit connected to the CDR module.

[0060] In one exemplary embodiment, each of the plurality of slice circuits further includes at least one retiming circuit, each of the retiming circuits being connected to a LUT circuit, and the method further includes:

[0061] The retiming circuit receives the low-speed signal input from the CDR module, samples the low-speed signal and aligns it according to the clock to obtain the processed low-speed signal, and inputs the processed low-speed signal into the corresponding LUT circuit.

[0062] In one exemplary embodiment, each of the plurality of slice circuits further includes a multiplexed MUX circuit, and after adjusting the output logic of the target slice circuit, it further includes:

[0063] The MUX circuit combines the low-speed signals output by all LUT circuits in the target slice circuit into a single high-speed signal.

[0064] As an example, each slice circuit may sequentially include one or more retiming circuits, one or more LUT circuits, a multiplexed MUX circuit, an output stage circuit, etc. The output of each retiming circuit can be connected to the input of a LUT circuit, the output of at least one LUT circuit can be connected to the input of a MUX circuit, and the input of the MUX circuit can be connected to the input of the output stage circuit.

[0065] For example, Figure 3 This is a schematic diagram of a single slice circuit according to an embodiment of this application, such as... Figure 3 In the single slice circuit shown, a retiming circuit is connected to a LUT circuit. The signal can be input from the retiming circuit, output from the LUT circuit to the MUX circuit, and integrated by the MUX circuit before finally reaching the output stage circuit.

[0066] The retiming circuit adjusts the signal timing to ensure time alignment during subsequent processing. The LUT circuit, located after the retiming circuit, adjusts the signal logic according to pre-configured rules, achieving signal encoding equalization and nonlinearity compensation. The MUX circuit integrates the processed signals, combining multiple low-speed signals into a single high-speed signal. For example, the MUX circuit can receive the LUT output signal and combine it into an NRZ signal. The output stage circuit amplifies the integrated signal to provide sufficient drive capability to control the electro-optic modulator. The output stage circuit ensures the signal has sufficient amplitude and energy for electro-optic conversion.

[0067] For example, Figure 4 This is a schematic diagram of the internal structure of a single slice NRZ circuit (4-way mux) according to an embodiment of this application, as shown below. Figure 4 The single slice shown contains four independent retiming circuits and four corresponding LUT circuits, meaning that each input signal has its own independent timing adjustment and logic processing path.

[0068] exist Figure 4 In this system, each NRZ signal has a dedicated retiming circuit to adjust the timing, and then the signal enters an independent LUT for logic encoding and equalization. Signal processing is more detailed and independent, and the characteristics and quality of each signal can be optimized individually. Figure 4 The MUX circuit shown can receive four output signals, each of which has undergone its own retiming and LUT processing. The MUX circuit can be used to combine the four signals into a single high-speed NRZ signal. Figure 3 In contrast, the MUX here needs to process four signals that have already undergone independent coding and equalization.

[0069] Figure 4 In the individual slices shown, signals are processed independently within each slice and then integrated. The processing of each signal is independent, and they are then synthesized via a MUX circuit. This architecture allows for customized processing of different signals to meet the needs of nonlinear compensation, while simultaneously achieving signal rate enhancement and quality optimization through integration.

[0070] Figure 3 In this process, the signal is processed through a shared retiming circuit and a LUT. Figure 4 In this system, each signal has its own independent retiming circuit and LUT, further increasing the circuit's flexibility and the independence of signal processing. Figure 3 In this circuit, the signal after the LUT can be directly integrated into the MUX circuit. Figure 4 In this process, each signal is first processed independently in the LUT before being integrated into the MUX.

[0071] In this embodiment, by using the output logic of the LUT control slice, the amplitude of the output signal is adjusted, thereby compensating for the nonlinear effects in the electro-optic conversion process and improving signal integrity. This solves the problem in related technologies where electro-optic transmitters cannot effectively process signals introduced by electro-optic conversion that are nonlinear.

[0072] In one exemplary embodiment, adjusting the output logic of the target slice circuit through at least one lookup table (LUT) circuit in the target slice circuit among the plurality of slice circuits includes:

[0073] For each low-speed signal input to the target slice circuit, the output logic of the target slice circuit is adjusted according to the input code pattern of the low-speed signal through the corresponding LUT circuit of the target slice circuit, thereby adjusting the output code pattern of the low-speed signal.

[0074] In one exemplary embodiment, adjusting the output logic of the target slice circuit and the output code pattern of the low-speed signal by adjusting the corresponding LUT circuit of the target slice circuit according to the input code pattern of the low-speed signal includes:

[0075] The LUT circuit determines the output code corresponding to the current input code of the low-speed signal based on the current input code of the low-speed signal, the output code of the low-speed signal at the previous moment, and the preset LUT logic.

[0076] In one exemplary embodiment, the LUT logic includes at least one of the following: LUT logic without equalization, LUT logic with FFE equalization, LUT logic with rising edge equalization, and LUT logic with falling edge equalization.

[0077] For example, the driving circuit adopts a sliced ​​architecture. For instance, the MSB has three slices with weights of X8, X4, and X2, meaning the driving capabilities are X8, X4, and X2 respectively. The three slices have the same input, and the output is controlled by a lookup table. The logic of the lookup table can be determined by the control word. Taking the lookup table circuit of the MSB sliced ​​circuit as an example, the input of each lookup table is the current input code MBS[n] and the output code MSB[n-1] from the previous time step, i.e., the code of two adjacent bits. The following provides an exemplary description of the LUT logic in various scenarios of the MSB sliced ​​circuit:

[0078] 1) Without any load balancing, the lookup table logic can be as shown in Table 1:

[0079] Table 1

[0080] MSB[n] MSB[n-1] Output 0 0 0 0 1 0 1 0 1 1 1 1

[0081] Figure 5 This is a waveform diagram without any equalization processing according to an embodiment of this application, such as... Figure 5 As shown, the input waveform diagram shows the original signal state without any signal processing; the output part of the waveform diagram without any equalization processing is the signal that is directly output by the output stage circuit after the signal enters the slicing circuit, passes through the lookup table, but is not compensated or adjusted in any way.

[0082] 2) Perform feedforward equalization (FFE) for equalization processing. The lookup table logic is shown in Table 2, which involves inverting the signal and delaying it by 1 bit:

[0083] Table 2

[0084] MSB[n] MSB[n-1] Output 0 0 1 0 1 0 1 0 1 1 1 0

[0085] In the design of high-speed electro-optic modulators, the use of FFE (Free-Form Equalization) technology can significantly improve signal integrity and transmission efficiency. It is applicable to long-distance transmission and multi-level modulation, such as PAM4. FFE equalization can improve the rising and falling edges of the signal by compensating for inter-symbol interference and signal attenuation, resulting in higher signal quality at the receiver.

[0086] Figure 6 This is a waveform diagram illustrating the equalization process performed using FFE according to an embodiment of this application, as shown below. Figure 6 As shown, the input waveform represents the original signal state. When FFE equalization is applied, the output waveform displays the compensated signal state. FFE equalization uses lookup table logic to predict signal transitions and strengthen or weaken the output at signal edges to compensate for ISI effects. For example, whenever the signal transitions from low to high, the FFE-equalized signal exhibits a faster rising edge, thereby reducing the impact of ISI, increasing the eye diagram opening, and making the signal easier to decode at the receiver.

[0087] 3) Perform equalization processing on rising edges. The lookup table logic can be shown in Table 3:

[0088] Table 3

[0089] MSB[n] MSB[n-1] Output 0 0 1 0 1 1 1 0 1 1 1 0

[0090] As can be seen from Table 3, when MSB changes from 0 to 1 (i.e. rising edge), the output is set to 1 regardless of whether the previous MSB value is 0 or 1, in order to enhance the rising edge of the signal; while when MSB[n] = 1 and MSB[n-1] = 1, the output is set to 0. This is usually to avoid unnecessary signal fluctuations, but it can also be adjusted according to specific design requirements. Sometimes, the output in this case is even set to 1 to achieve more stable signal transmission.

[0091] Figure 7 This is a waveform diagram illustrating the equalization processing of the rising edge according to an embodiment of this application, such as... Figure 7 As shown, the input waveform represents the original signal state, while the output waveform shows the signal state after equalization processing for the rising edge. When the signal transitions from level 0 (MSB is 0) to level 1 or level 2 / 3 (MSB is 1), the rising edge of the signal is accelerated due to the control of the LUT, reducing the influence of ISI. This results in a larger opening in the eye diagram during signal rise, more consistent eye height, and more accurate signal recognition.

[0092] 4) Perform equalization processing on the falling edge. The lookup table logic can be shown in Table 4:

[0093] Table 4

[0094] MSB[n] MSB[n-1] Output 0 0 1 0 1 0 1 0 1 1 1 1

[0095] As shown in Table 4, when the signal drops from level 1 to level 0 (i.e., the falling edge), the output is set to 0, even if the current value of the input signal is 0. Conversely, if both the current and previous values ​​of the signal are 0, the output is set to 1. This logic helps to accelerate the falling edge of the signal, reduce the ISI effect, and improve the signal's falling characteristics, especially for transitions from higher to lower levels.

[0096] Figure 8 This is a waveform diagram illustrating the equalization processing of the falling edge according to an embodiment of this application, as shown below. Figure 8 As shown, the input waveform represents the original signal state, while the output waveform illustrates the characteristics of the signal after falling-edge equalization (LUT). The purpose of LUT is to optimize the signal's falling-edge characteristics through LUT logic. With falling-edge equalization, the falling edge becomes steeper and faster as the signal transitions from a higher to a lower level, which helps reduce the effects of ISI and improve signal integrity.

[0097] In one exemplary embodiment, each of the plurality of slice circuits corresponds to a weight for indicating the driving capability of the slice circuit, and the logic for adjusting the output of the target slice circuit includes:

[0098] Based on the mapping relationship between the code pattern of the high-speed signal output by the MUX circuit, the preset output code pattern, and the slice weight, the activation state of the weight of the target slice circuit corresponding to the code pattern of the high-speed signal is adjusted by the LUT circuit of the target slice circuit, so as to adjust the output logic of the target slice circuit.

[0099] In one exemplary embodiment, it further includes:

[0100] The LUT circuit of the target slice circuit calculates a weighted value of the output level of the target slice circuit based on the activation state of the weights of the target slice circuit and the level of the high-speed signal of the target slice circuit, so as to adjust the output level of the multi-amplitude signal input to the electro-optic modulator.

[0101] As an example, taking the output PAM4 signal as an example, each slice receives 4 MSB signals and 4 LSB signals. The 2-bit data composed of the MSB and LSB signals has four possibilities: "00, 01, 10, 11". Assume the driver circuit has 6 slice circuits: 3 MSB slices and 3 LSB slices. The weights of the MSB slices (M1, M2, M3) are "x8, x4, x2" respectively, and their input logic is shown in Table 5, i.e., MSB output; the weights of the LSB slices (L1, L2, L3) are "x4, x2, x1" respectively, and their input logic is shown in Table 5, i.e., LSB output. This weighting ratio results in 2 / 3 outputting MSB signals and 1 / 3 outputting LSB signals, ultimately outputting a PAM4 signal.

[0102] Table 5

[0103]

[0104] As shown in Table 5, when both the MSB and LSB output codes are "0", it indicates that the PAM4 signal is at its lowest level, 0. Neither the MSB nor LSB slices produce output, therefore the weighted sum is 0. This means the output signal is at a low level, distinguishing it from other levels.

[0105] When the MSB output code is "0" and the LSB output code is "1", it indicates that the PAM4 signal is at a low level, but higher than 0, such as 1 / 3 level. At this time, the LSB slices (L1, L2, L3) are active, while the MSB slices are inactive. The weights are summed to 4+2+1=7, which determines the amplitude of the 1 / 3 level.

[0106] When the MSB output code is "1" and the LSB output code is "0", it indicates that the signal is at a high level, but below the highest level of 1, such as 2 / 3 level. At this time, the MSB slices (M1, M2, M3) are active, with a weighted sum of 8 + 4 + 2 = 14, while the LSB slices are inactive, with a weight of 0. The weighted sum of 14 determines the amplitude of the 2 / 3 level.

[0107] When both the MSB and LSB outputs are "1", it indicates that the signal is at its highest level. At this time, both MSB and LSB slicing are active, and the weighted sum is 21 (8+4+2+4+2+1), which is the highest weighted sum among all levels, ensuring the maximum amplitude of the 1 level in the signal.

[0108] The formula for PAM4 signal output can be:

[0109] The output level of the PAM4 signal = (8*M1 + 4*M2 + 2*M3) + (4*L1 + 2*L2 + 1*L3)

[0110] For each PAM4 level, the weight ratio of the MSB and LSB slices is fixed, but the actual output level can be adjusted by controlling the output logic of each slice. For example, to perform non-linear compensation on level 2 / 3 and improve its eye height, the weight of the MSB slice can be appropriately reduced and the weight of the LSB slice increased, making the weighted sum of the outputs larger, but not exceeding the weighted value of 21 for level 1, ensuring clear boundaries between signal levels.

[0111] The following example further illustrates the process of weight balancing of the slice circuit based on the lookup table circuit in this application embodiment:

[0112] For example, referring to Table 1, the weights of the 6 slices, MSB and LSB, are as follows: MSB: M1 = 8, M2 = 4, M3 = 2; LSB: L1 = 4, L2 = 2, L3 = 1; the output level of the PAM4 signal = (8*M1 + 4*M2 + 2*M3) + (4*L1 + 2*L2 + 1*L3).

[0113] Suppose we need to enlarge the uppermost eye in the PAM4 signal eye diagram, we can change the MSB encoding of level 2 / 3. Since level 2 / 3 only depends on MSB (as shown in Table 1, MSB=1, LSB=0), we can adjust the combination of MSB units to reduce its output:

[0114] Original level 2 / 3: M1=1, M2=1, M3=1, i.e., the sum of weights: 8+4+2=14

[0115] Adjust the output logic of the lookup table:

[0116] For example, only activate a portion of the MSB slices: M1 = 1 (activated), M2 = 1 (activated), M3 = 0 (not activated), that is, the sum of weights: 8 + 4 = 12.

[0117] Result: The weighting value of level 2 / 3 decreased from 14 to 12.

[0118] The lookup table-based control process in this application embodiment can control the state of each signal individually, such as equalizing the edges to compensate for the nonlinearity of photoelectric conversion. The equalization intensity can be determined by the slice intensity. For example, slices X8 and X4 of the MSB are not processed, slice X2 of the LSB is processed with rising edge equalization, slice X1 is processed with falling edge equalization, and so on.

[0119] It should be noted that the above adjustment process is only a weight adjustment method to make the uppermost eye in the eye diagram larger. Those skilled in the art can adjust the activation state of the weight of any slice according to the actual situation to achieve the adjustment of eye height. This application embodiment does not limit this.

[0120] The following example further illustrates the process of modulating multi-amplitude signals based on a lookup table according to the embodiments of this application:

[0121] For example, Figure 9 This is a digital logic block diagram of a multi-amplitude electro-optic modulator based on a lookup table, according to an embodiment of this application, such as... Figure 9 As shown, suppose there is a 112Gbps PAM4 signal to be modulated, which can have four different levels (0, 1 / 3, 2 / 3, 1) in each symbol period, representing 2 bits of information. Assume that 6 slicing circuits are used, 3 for MSB signal processing and 3 for LSB signal processing, with MSB slice weights of X8, X4, and X2, and LSB slice weights of X4, X2, and X1.

[0122] A 112Gbps PAM4 differential signal is input to the electro-optic modulator. The PAM4 signal can be represented as 2 bits of data per unit time, with the high-order bit being the MSB signal and the low-order bit being the LSB signal. In this case, it can also be regarded as a PAM4 signal, which is decomposed into two NRZ signals.

[0123] The input 112Gbps PAM4 signal first passes through a CDR module. The CDR decomposes the 112Gbps PAM4 multi-amplitude signal into eight 14Gbps NRZ signals (i.e., four MSB signals and four LSB signals), reducing the rate of each signal to 14Gbps, which is one-quarter of the original signal rate. The four MSB signals can be simultaneously input into three MSB slices, and the four LSB signals can be simultaneously input into three LSB slices. For example, the MSB signals are fed into three slices, each with a different weight (M1=8, M2=4, M3=2). These slices undergo nonlinear compensation through internal LUT circuitry, adjusting the signal amplitude and rise / fall times. Similarly, the LSB signals are also fed into three slices, with weights L1=4, L2=2, and L3=1. LUTs also perform nonlinear compensation on the LSB slices.

[0124] Each 14Gbps NRZ signal enters the corresponding slice circuit. In each slice circuit, the signal passes through a retiming module to ensure accurate timing for subsequent processing.

[0125] Next, the 14Gbps NRZ signal processed by the retiming module enters the LUT circuit. The LUT circuit can output the adjusted signal level according to the input code pattern (e.g., MSB[n] and MSB[n-1], LSB[n] and LSB[n-1], etc.) and the configured control word.

[0126] The output signal of the LUT circuit passes through the MUX circuit, which combines four 14Gbps signals into one 56Gbps NRZ signal. Simultaneously, it can synthesize signals according to the weights of each slice. For example, after the MSB and LSB signals are combined by the MUX, their current outputs are synthesized to generate the final PAM4 signal. The current synthesis follows the rules of MSB and LSB slice weights, i.e., PAM4 output level = (8M1 + 4M2 + 2M3) + (4L1 + 2L2 + 1L3).

[0127] Each MSB slice can include four lookup table circuits, each of which can adjust the output code of an MSB signal according to the lookup table content. The MUX circuit in each MSB slice can synthesize the four MSB signals, which have been adjusted by the four lookup table circuits respectively, into a single MSB signal. By adjusting the activation state of the weights of the MSB slices, the output level of the synthesized MSB signal can be further finely controlled.

[0128] Each LSB slice can include four lookup table circuits. Each lookup table circuit can adjust the output code of an LSB signal according to the lookup table content. The MUX circuit in each LSB slice can synthesize the four LSB signals, which have been adjusted by the four lookup table circuits respectively, into one LSB signal. By adjusting the activation state of the weights of the LSB slices, the output level of the synthesized LSB signal can be further finely controlled.

[0129] The MSB and LSB signals output after adjusting the slice weights can be combined to obtain a modulated 112Gbps PAM4 signal. The six signals output from the MSB and LSB slicing circuits can be synthesized in the final MUX circuit according to the weight ratio to form a 112Gbps PAM4 signal.

[0130] The output stage circuit further amplifies the synthesized PAM4 signal, providing sufficient drive current or voltage to drive the optical modulator.

[0131] In this embodiment, the nonlinearity of the electro-optic modulator can be compensated by combining a sliced ​​driving circuit and LUT control, thereby improving signal integrity. The driving circuit, through a sliced ​​design, allows for independent LUT control of each slice, enabling precise control of the signal output. This embodiment can drive multi-amplitude modulation, such as PAM4 and PAM6. By controlling the weights of the MSB and LSB slices, signals with multiple different levels can be output, thereby increasing the data transmission rate without increasing bandwidth.

[0132] In this embodiment, using a LUT to perform nonlinear equalization on the signal can effectively address the nonlinear effects during the electro-optic conversion process, ensuring that the signal quality is not affected. By adjusting the control logic of the LUT, the rising edge, falling edge, or eye level of the signal can be flexibly optimized to adapt to different transmission environments and modulation formats.

[0133] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0134] This embodiment also provides an electro-optic modulator for implementing the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that implements a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0135] Figure 10 This is a structural block diagram of an electro-optic modulator according to an embodiment of this application, such as... Figure 10 As shown, the electro-optic modulator includes a driving circuit 10, which includes a plurality of slice circuits 101.

[0136] The target slice circuit 101 among the plurality of slice circuits is used to adjust the output logic of the target slice circuit 101 through at least one lookup table (LUT) circuit 1011 in the target slice circuit 101 to adjust the output level of the multi-amplitude signal input to the electro-optic modulator.

[0137] In one exemplary embodiment, the electro-optic modulator further includes:

[0138] The CDR module is used to decompose the input multi-amplitude signal into multiple low-speed signals, and input at least one of the multiple low-speed signals into the target slicing circuit; wherein, each LUT circuit of the target slicing circuit is used to adjust the output code pattern of one low-speed signal.

[0139] In one exemplary embodiment, the target slicing circuit is configured to, for each low-speed signal input to the target slicing circuit, adjust the output logic of the target slicing circuit according to the input code pattern of the low-speed signal through a corresponding LUT circuit, thereby adjusting the output code pattern of the low-speed signal.

[0140] In one exemplary embodiment, the LUT circuit is configured to determine the output code corresponding to the current input code of the low-speed signal based on the current input code of the low-speed signal, the output code of the low-speed signal at the previous moment, and a preset LUT logic.

[0141] In one exemplary embodiment, the LUT logic includes at least one of the following: LUT logic without equalization, LUT logic with FFE equalization, LUT logic with rising edge equalization, and LUT logic with falling edge equalization.

[0142] In one exemplary embodiment, each of the plurality of slice circuits further includes:

[0143] The MUX circuit is used to combine the low-speed signals output by all LUT circuits in the target slice circuit into a single high-speed signal.

[0144] In one exemplary embodiment, each of the plurality of slice circuits corresponds to a weight for indicating the driving capability of the slice circuit.

[0145] The target slicing circuit is used to adjust the activation state of the weights of the target slicing circuit corresponding to the code pattern of the high-speed signal output by the MUX circuit, the preset output code pattern and the slicing weight mapping relationship, through the LUT circuit of the target slicing circuit, so as to adjust the output logic of the target slicing circuit.

[0146] In one exemplary embodiment, the target slicing circuit is further configured to calculate a weighted value of the output level of the target slicing circuit through the LUT circuit of the target slicing circuit based on the activation state of the weights of the target slicing circuit and the level of the high-speed signal of the target slicing circuit, so as to adjust the output level of the multi-amplitude signal input to the electro-optic modulator.

[0147] In one exemplary embodiment, each of the plurality of slice circuits further includes at least one retiming circuit, and each of the retiming circuits is connected to a LUT circuit.

[0148] The retiming circuit is used to receive the low-speed signal input by the CDR module, sample the low-speed signal and align it according to the clock to obtain the processed low-speed signal, and input the processed low-speed signal into the corresponding LUT circuit.

[0149] It should be noted that the above modules can be implemented by software or hardware. For the latter, they can be implemented in the following ways, but are not limited to: all the above modules are located in the same processor; or, the above modules are located in different processors in any combination.

[0150] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above method embodiments when run.

[0151] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0152] Figure 11 This is a structural block diagram of an electronic device according to an embodiment of this application, such as... Figure 11 As shown, embodiments of this application also provide an electronic device 110, including a memory 1101 and a processor 1102. The memory 1101 stores a computer program, and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0153] In one exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0154] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0155] Embodiments of this application also provide a computer program product, including a computer program that, when executed by a processor, implements the steps in any of the above method embodiments.

[0156] Obviously, those skilled in the art should understand that the modules or steps of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented here, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, this application is not limited to any particular combination of hardware and software.

[0157] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A method for adjusting signal amplitude, characterized in that, The method, applied to an electro-optic modulator including a driving circuit comprising multiple slice circuits, includes: The output logic of the target slice circuit is adjusted by at least one lookup table (LUT) circuit in the target slice circuit among the plurality of slice circuits to adjust the output level of the multi-amplitude signal input to the electro-optic modulator.

2. The method according to claim 1, characterized in that, The electro-optic modulator further includes a clock and data recovery (CDR) module, and the method further includes: The input multi-amplitude signal is decomposed into multiple low-speed signals by the CDR module, and at least one of the multiple low-speed signals is input to the target slicing circuit; wherein, each LUT circuit of the target slicing circuit is used to adjust the output code pattern of one low-speed signal.

3. The method according to claim 2, characterized in that, The step of adjusting the output logic of the target slice circuit through at least one lookup table (LUT) circuit in the target slice circuit among the plurality of slice circuits includes: For each low-speed signal input to the target slice circuit, the output logic of the target slice circuit is adjusted according to the input code pattern of the low-speed signal through the corresponding LUT circuit of the target slice circuit, thereby adjusting the output code pattern of the low-speed signal.

4. The method according to claim 3, characterized in that, The step of adjusting the output code pattern of the low-speed signal by adjusting the output logic of the target slice circuit through the corresponding LUT circuit of the target slice circuit according to the input code pattern of the low-speed signal includes: The LUT circuit determines the output code corresponding to the current input code of the low-speed signal based on the current input code of the low-speed signal, the output code of the low-speed signal at the previous moment, and the preset LUT logic.

5. The method according to claim 4, characterized in that, The LUT logic includes at least one of the following: LUT logic without equalization, LUT logic with FFE equalization, LUT logic with rising edge equalization, and LUT logic with falling edge equalization.

6. The method according to claim 3, characterized in that, Each of the plurality of slice circuits further includes a multiplexed MUX circuit, and after adjusting the output logic of the target slice circuit, it further includes: The MUX circuit combines the low-speed signals output by all LUT circuits in the target slice circuit into a single high-speed signal.

7. The method according to claim 6, characterized in that, Each of the plurality of slice circuits corresponds to a weight used to indicate the driving capability of the slice circuit, and the logic for adjusting the output of the target slice circuit includes: Based on the mapping relationship between the code pattern of the high-speed signal output by the MUX circuit, the preset output code pattern, and the slice weight, the activation state of the weight of the target slice circuit corresponding to the code pattern of the high-speed signal is adjusted by the LUT circuit of the target slice circuit, so as to adjust the output logic of the target slice circuit.

8. The method according to claim 7, characterized in that, Also includes: The LUT circuit of the target slice circuit calculates a weighted value of the output level of the target slice circuit based on the activation state of the weights of the target slice circuit and the level of the high-speed signal of the target slice circuit, so as to adjust the output level of the multi-amplitude signal input to the electro-optic modulator.

9. The method according to claim 2, characterized in that, Each of the plurality of slice circuits further includes at least one retiming circuit, each of the retiming circuits being connected to a LUT circuit, the method further including: The retiming circuit receives the low-speed signal input from the CDR module, samples the low-speed signal and aligns it according to the clock to obtain the processed low-speed signal, and inputs the processed low-speed signal into the corresponding LUT circuit.

10. An electro-optic modulator, characterized in that, Includes a driving circuit, which includes multiple slice circuits; The target slice circuit among the plurality of slice circuits is used to adjust the output logic of the target slice circuit through at least one lookup table (LUT) circuit in the target slice circuit to adjust the output level of the multi-amplitude signal input to the electro-optic modulator.

11. The electro-optic modulator according to claim 10, characterized in that, The electro-optic modulator also includes: The CDR module is used to decompose the input multi-amplitude signal into multiple low-speed signals, and input at least one of the multiple low-speed signals into the target slicing circuit; wherein, each LUT circuit of the target slicing circuit is used to adjust the output code pattern of one low-speed signal.

12. The electro-optic modulator according to claim 11, characterized in that, The target slicing circuit is used to adjust the output logic of the target slicing circuit according to the input code pattern of each low-speed signal input to the target slicing circuit, thereby adjusting the output code pattern of the low-speed signal through the corresponding LUT circuit.

13. The electro-optic modulator according to claim 12, characterized in that, The LUT circuit is used to determine the output code corresponding to the current input code of the low-speed signal based on the current input code of the low-speed signal, the output code of the low-speed signal at the previous moment, and the preset LUT logic.

14. The electro-optic modulator according to claim 13, characterized in that, The LUT logic includes at least one of the following: LUT logic without equalization, LUT logic with FFE equalization, LUT logic with rising edge equalization, and LUT logic with falling edge equalization.

15. The electro-optic modulator according to claim 12, characterized in that, Each of the plurality of slice circuits further includes: The MUX circuit is used to combine the low-speed signals output by all LUT circuits in the target slice circuit into a single high-speed signal.

16. The electro-optic modulator according to claim 15, characterized in that, Each of the plurality of slice circuits corresponds to a weight used to indicate the driving capability of the slice circuit. The target slicing circuit is used to adjust the activation state of the weights of the target slicing circuit corresponding to the code pattern of the high-speed signal output by the MUX circuit, the preset output code pattern and the slicing weight mapping relationship, through the LUT circuit of the target slicing circuit, so as to adjust the output logic of the target slicing circuit.

17. The electro-optic modulator according to claim 16, characterized in that, The target slicing circuit is further configured to calculate a weighted value of the output level of the target slicing circuit based on the activation state of the weights of the target slicing circuit and the level of the high-speed signal of the target slicing circuit, through the LUT circuit of the target slicing circuit, so as to adjust the output level of the multi-amplitude signal input to the electro-optic modulator.

18. The electro-optic modulator according to claim 11, characterized in that, Each of the plurality of slice circuits further includes at least one retiming circuit, and each of the retiming circuits is connected to a LUT circuit. The retiming circuit is used to receive the low-speed signal input by the CDR module, sample the low-speed signal and align it according to the clock to obtain the processed low-speed signal, and input the processed low-speed signal into the corresponding LUT circuit.

19. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the method described in any one of claims 1 to 9.

20. A computer program product comprising a computer program that, when executed by a processor, implements the steps of the method described in any one of claims 1 to 9.

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