Frequency domain constant modulus algorithm equalization method and device and coherent receiving system

Abstract

The application relates to the field of optical communication technology and discloses a frequency domain constant modulus algorithm equalization method, a device and a coherent receiving system. The method performs frequency domain equalization on frequency domain data of a coherent receiving signal, performs inverse fast Fourier transform on equalization output to obtain a time domain output signal and calculates a constant modulus algorithm error signal; in a tap coefficient updating path, a symbol domain updating quantity is obtained by controlling the symbol of the time domain output signal by the error symbol to keep or reverse the polarity, and then quadrant quantization fast Fourier transform is performed on the symbol domain updating quantity to obtain frequency domain symbol information, based on which an updating direction and an updating coefficient are constructed and used for subsequent equalization; the transform maps a rotation factor into a value in a set {1, -1, j, -j}, multiplication is realized by symbol negation and / or real and imaginary part exchange, and multiplication is only arranged in the updating path, so that the requirement of a multiplier in the updating path is reduced under the condition that conventional processing is still adopted in a main signal path.

Description

Technical Field

[0001] This application relates to the field of optical communication technology, and in particular to a frequency domain constant mode algorithm equalization technique applied to coherent receiving systems. Background Technology

[0002] With the increasing demand for optical access network capacity, passive optical networks based on coherent detection have become a candidate solution for achieving access rates of 100G and above due to their high receiver sensitivity, large power budget, and flexible modulation methods. Compared with intensity modulation direct detection schemes, coherent receiving systems can carry information in multiple dimensions such as amplitude, phase, and polarization. Correspondingly, the digital signal processing link at the receiver is also more complex. Under high-speed, high-parallelism, and real-time processing conditions, the computational structure of digital signal processing algorithms directly affects the resource consumption, cabling pressure, and processing latency of the hardware platform.

[0003] In coherent digital signal processing, adaptive equalization is used to achieve polarization demultiplexing and channel distortion compensation. The constant modulus algorithm does not depend on the training sequence and can adapt to channel changes, and is widely used for blind equalization in coherent receiving systems. To meet the requirements of large tap numbers and high parallelism, frequency domain constant modulus equalization transforms time-domain convolution operations into frequency-domain dot product operations, which has advantages in parallel processing in high-speed real-time systems.

[0004] However, frequency-domain constant modulus equalization algorithms in related technologies still require numerous complex multiplications in the tap coefficient update path, including multiplication operations related to the error signal, fast Fourier transforms in the update path, and point-by-point multiplication updates in the frequency domain. These operations typically consume significant multiplier resources and increase wiring pressure, becoming one of the main sources of complexity in field-programmable gate array (FPGA) implementations. Although some related technologies employ symbolic multiplication to replace some complex multiplications, resulting in lower complexity, the fast Fourier transform in the update path still includes complex multiplication of rotation factors, leaving room for further reduction in multiplier resources. Therefore, further improvements to these technologies are necessary. Summary of the Invention

[0005] The purpose of this application is to provide a frequency domain constant modulus equalization method, apparatus and coherent receiving system to solve the problems in related technologies where the tap coefficient update path of frequency domain constant modulus equalization requires a large amount of complex multiplier resources and has high real-time hardware implementation complexity.

[0006] To achieve the above objectives, this application provides a frequency-domain constant modulus (CMM) equalization method applied to a coherent receiving system. The method includes: performing frequency-domain equalization on the frequency-domain data of the coherent received signal based on frequency-domain equalization coefficients to obtain a frequency-domain equalized output; performing an inverse fast Fourier transform (IFFT) on the frequency-domain equalized output to obtain a time-domain output signal; calculating a constant modulus algorithm error signal based on the time-domain output signal; extracting the symbol of the time-domain output signal and the symbol of the constant modulus algorithm error signal in the tap coefficient update path, and controlling the polarity preservation or polarity reversal of the symbol of the time-domain output signal by the symbol of the constant modulus algorithm error signal to obtain a symbol-domain update amount represented by the symbol direction; performing a quadrant quantization fast Fourier transform on the symbol-domain update amount to obtain the frequency-domain symbol information required for tap coefficient updates, wherein the quadrant quantization fast Fourier transform maps the rotation factor to the set {1, -1, j, -j}. The value is one of the values, and the multiplication between the quantized rotation factor and the complex number is achieved by sign inversion and / or real-imaginary part exchange; an update direction is constructed according to the frequency domain sign information, the frequency domain equalization coefficients are updated according to the update direction, and the updated frequency domain equalization coefficients are used for frequency domain equalization of subsequent frequency domain data; wherein, the quadrant quantization fast Fourier transform is only set in the tap coefficient update path, and the main signal path where the frequency domain equalization and the inverse fast Fourier transform are located does not use the quadrant quantization fast Fourier transform.

[0007] In some implementations, the quadrant quantization fast Fourier transform maps the rotation factor to a quantization rotation factor according to the following quadrant quantization operator: in, W Let arg(⋅) represent the rotation factor to be quantized, and let arg(⋅) represent the phase operator. Q (⋅) represents the quadrant quantization operator; the rotation operation corresponding to the quantization rotation factor is selected by a two-bit control code, wherein when the quantization rotation factor is +1, the input complex number is directly output; when the quantization rotation factor is -1, the real and imaginary parts of the input complex number are inverted respectively; when the quantization rotation factor is +j, the real and imaginary parts of the input complex number are swapped, and the real part of the output after the swap is inverted; when the quantization rotation factor is -j, the real and imaginary parts of the input complex number are swapped, and the imaginary part of the output after the swap is inverted.

[0008] Furthermore, in the embodiment where the rotation factor is mapped to a quantization rotation factor according to the aforementioned quadrant quantization operator, the quadrant quantization fast Fourier transform employs a radix-2 hierarchical butterfly structure, with a transformation point count of... N Powers of 2 N = 2 p The hierarchical butterfly structure includesp Level butterfly operation, the first s The length of the sub-block of level is m = 2 s The first in each sub-block t Each butterfly unit reads two input complex numbers. A and B According to the quantization rotation factor q s,t = Q ( W m t )right B Perform quadrant rotation to obtain quantized rotated data. B q and output Y 0 = A + B q and Y 1 = A - B q ,in, W m t Indicates the first s The first sub-block within the level t The rotation factor corresponds to each butterfly position; the quantization rotation factor for each level is pre-written into the control table, or generated by a combination of level number and position within the group.

[0009] In some implementations, the quadrant quantization fast Fourier transform includes multiple butterfly operation stages; each intermediate stage of the quadrant quantization fast Fourier transform maintains a fixed bit width output and does not sign the intermediate stage output; the last stage output is signified only after the last stage output, and the resulting sign direction is used as the frequency domain sign information for tap coefficient updates.

[0010] In some embodiments, the method further includes: symbolizing the conjugate of the frequency domain data in the tap coefficient update path to obtain the conjugate symbol Sign( x ) = S (Re( x )) - j S (Im( x The update direction is constructed jointly by the conjugate symbol and the frequency domain symbol information; wherein, x This represents the frequency domain data. x express x The conjugate of Re( x ) and Im( x ) represent respectivelyx The real and imaginary parts, S (⋅) is the sign function for real numbers. u , u > 0 o'clock S ( u ) = +1, u < 0 S ( u = -1.

[0011] In some implementations, when the constant modulus algorithm error signal is zero, the update enable signal for this update is turned off, and the update of the frequency domain equalization coefficient is not performed; when the real or imaginary part of the data to be acquired is zero, the symbol of the zero component retains the previous valid symbol.

[0012] In some implementations, according to W new = W old + μG The frequency domain equalization coefficients are updated; wherein, W old This represents the frequency domain equalization coefficients before the update. W new This represents the updated frequency domain equalization coefficients. μ Indicates the update step size. G This indicates the direction of the update.

[0013] In some embodiments, the frequency domain data includes frequency domain data in two polarization directions; the frequency domain equalization employs a dual-polarization 2 × 2 multiple-input multiple-output structure, and the frequency domain equalization coefficients include... W xx , W xy , W yx and W yy It is used to compensate for channel response and polarization crosstalk between two polarization directions.

[0014] This application also provides a frequency-domain constant-modulus algorithm equalization device, including a frequency-domain equalization module, an inverse fast Fourier transform module, an error calculation module, a symbol domain update module, a quadrant quantization fast Fourier transform module, and a coefficient update module. The frequency-domain equalization module performs frequency-domain equalization on the frequency-domain data of the coherent received signal based on frequency-domain equalization coefficients to obtain a frequency-domain equalized output, and provides the frequency-domain equalized output to the inverse fast Fourier transform module. The inverse fast Fourier transform module performs an inverse fast Fourier transform on the frequency-domain equalized output to obtain a time-domain output signal, and provides the time-domain output signal to the error calculation module and the symbol domain update module respectively. The error calculation module calculates the constant-modulus algorithm error signal based on the time-domain output signal and updates the constant-modulus algorithm. The algorithm error signal is provided to the symbol domain update module; the symbol domain update module is used to extract the symbol of the time-domain output signal and the symbol of the constant modulus algorithm error signal in the tap coefficient update path, and the symbol of the time-domain output signal is controlled by the symbol of the constant modulus algorithm error signal to perform polarity preservation or polarity reversal, so as to obtain the symbol domain update amount represented by the symbol direction, and the symbol domain update amount is provided to the quadrant quantization fast Fourier transform module; the quadrant quantization fast Fourier transform module is used to perform quadrant quantization fast Fourier transform on the symbol domain update amount to obtain the frequency domain symbol information required for tap coefficient update, and the frequency domain symbol information is provided to the coefficient update module, wherein the quadrant quantization fast Fourier transform maps the rotation factor to the set {1, The value is one of {-1, j, -j}, and the multiplication between the quantized rotation factor and the complex number is achieved by sign inversion and / or real-imaginary part exchange; the coefficient update module is used to construct an update direction based on the frequency domain sign information, update the frequency domain equalization coefficients according to the update direction, and feed the updated frequency domain equalization coefficients back to the frequency domain equalization module for frequency domain equalization of subsequent frequency domain data; wherein, the quadrant quantization fast Fourier transform module is only set in the tap coefficient update path, and the main signal path where the frequency domain equalization module and the inverse fast Fourier transform module are located does not use the quadrant quantization fast Fourier transform.

[0015] This application also provides a coherent receiving system, including an analog-to-digital conversion module and the aforementioned frequency domain constant modulus algorithm equalization device; the analog-to-digital conversion module is used to perform analog-to-digital conversion on the coherent received signal to obtain a coherent received digital signal; the frequency domain constant modulus algorithm equalization device is used to perform real-time frequency domain constant modulus algorithm equalization processing on the frequency domain data obtained from the coherent received digital signal; the frequency domain constant modulus algorithm equalization device is deployed on a field-programmable gate array (FPGA).

[0016] By adopting the above technical solution, this application can achieve at least the following technical effects.

[0017] The technical solution provided in this application addresses the problem of a large number of complex multiplications and high real-time hardware implementation complexity in frequency domain constant modulus equalization (VMO) during tap coefficient update. While maintaining the basic processing framework and main signal path processing method of VMO, the adaptive update of tap coefficients is driven by the sign direction, thereby reducing the requirement for complex multipliers in the update path and the corresponding real-time hardware implementation complexity.

[0018] Specifically, the sign of the time-domain output signal is controlled by the sign of the constant modulus algorithm error signal to maintain or reverse the polarity, so that the update quantity is represented by the sign direction. The complex multiplication of a real number operation that originally required a multiplier can be completed by sign judgment, sign inversion, and selection logic. Since the update quantity in this sign domain no longer carries amplitude information, the time-frequency transformation performed on it only needs to provide the sign direction. Therefore, quadrant quantization fast Fourier transform, which maps the rotation factor to a value in the set {1, -1, j, -j}, can be used. Its rotation operation is implemented by sign inversion and / or real-imaginary part exchange, so that the fast Fourier transform in this update path no longer requires a rotation factor complex multiplier. The corresponding operation can be completed by a data selector, inversion logic, exchange connection, and addition / subtraction logic. The obtained frequency domain sign information is used to construct the update direction and update the frequency domain equalization coefficients. The updated coefficients continue to be used for frequency domain equalization of subsequent frequency domain data, forming an adaptive closed loop that does not depend on the training sequence. This can meet the continuous tracking requirements of high-speed coherent receiving systems such as coherent passive optical networks for polarization demultiplexing and channel distortion compensation. The above methods are not isolated from each other: symbolic domain reconstruction provides the applicable conditions for quadrant quantization, while quadrant quantization ensures that the multiplications saved by symbolic domain reconstruction will not reappear in the transformation stage. The two pass the processing results in turn and work together on the same update path.

[0019] Since quadrant quantization Fast Fourier Transform is only applied to the tap coefficient update path, and not to the main signal path where frequency domain equalization and inverse Fast Fourier Transform are performed, the approximation introduced by quantization does not directly affect the signal recovery result. Therefore, it can reduce the hardware complexity of the update path while avoiding unnecessary accuracy loss in the main signal recovery path. Under exemplary verification conditions, this scheme reduces hardware resource consumption and processing latency while maintaining essentially no impact on convergence stability and receiver sensitivity, and only slightly extending the initial convergence speed.

[0020] Based on this, if quadrant quantization is performed according to phase intervals and the corresponding rotation operation is selected by two-bit control codes, then the operation corresponding to each quantization rotation factor, such as pass-through, double-component inversion, or real-imaginary part exchange combined with single-component inversion, can be uniquely determined by the selector and inversion logic. When the system adopts the opposite exponent sign convention, only the control codes need to be interchanged for adaptation. If a radix-2 hierarchical butterfly structure is adopted, the quantization rotation factors of each level can be pre-written into the control table or generated by combining the level number and the position within the group, which helps to reduce control overhead. If each intermediate level maintains a fixed bit width output and only takes the sign after the last level output, it helps to avoid premature loss of direction information. After multi-level butterfly processing, the main direction information required for tap coefficient updates can still be retained.

[0021] Furthermore, symbolizing the conjugate of the frequency domain data and constructing the update direction together with the frequency domain symbol information allows the role of the conjugate quantity of the frequency domain input data in the traditional update process to correspond in the symbol domain. Disabling the current update when the error signal is zero and maintaining the previous valid symbol when the component of the symbol to be retrieved is zero helps avoid meaningless updates and reduce symbol jitter and uncertain flips. W new = W old + μG When updating coefficients, since the update direction is restricted to a few predetermined directions, the cumulative update process can be achieved through addition / subtraction and sign control; when frequency domain equalization adopts a dual-polarization 2 × 2 multiple-input multiple-output structure, W xx , W xy , W yx and W yy The equalization processing, which continuously updates and feeds back to the subsequent frequency domain data in the above manner, can track and compensate for the channel response and polarization crosstalk between the two polarization directions. When deployed on a field-programmable gate array and implemented in a parallel pipeline structure, the update path operation consisting of selection, exchange, inversion, and addition / subtraction can be easily implemented step by step in the pipeline, providing technical support for real-time digital signal processing under high parallelism conditions.

[0022] In summary, the various technical means of this application work together around the processing principle that only direction information is needed in the adaptive update processing stage, while the signal recovery processing stage requires full amplitude and phase accuracy: symbol domain reconstruction changes the representation of the update quantity, quadrant quantization fast Fourier transform changes the implementation of the transformation stage in the update path accordingly, the construction of the update direction and coefficient feedback enable the products of both to be actually used for subsequent equalization, and the division between the main signal path and the update path limits the scope of approximate processing, thereby reducing hardware implementation overhead while meeting the equalization performance requirements within the same technical chain.

[0023] The specification of this application contains numerous technical features distributed across various technical solutions. Listing all possible combinations of these technical features (i.e., technical solutions) would make the specification excessively lengthy. To avoid this problem, the various technical features disclosed in the above-described invention, the various technical features disclosed in the following embodiments and examples, and the various technical features disclosed in the accompanying drawings can be freely combined to form various new technical solutions (all of which should be considered as described in this specification), unless such a combination of technical features is technically infeasible. For example, one example discloses feature A+B+C, and another example discloses feature A+B+D+E. Features C and D are equivalent technical means that serve the same function, and technically only one needs to be used; they cannot be used simultaneously. Feature E can technically be combined with feature C. Therefore, the solution A+B+C+D should not be considered as described because it is technically infeasible, while the solution A+B+C+E should be considered as described. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the modules and data flow of a frequency domain constant modulus algorithm equalization device according to an embodiment of this application.

[0025] Figure 2 This is a schematic diagram of the structure of a butterfly unit for quadrant quantization fast Fourier transform according to an embodiment of this application.

[0026] Figure 3 This is a schematic diagram illustrating a multiplier-free implementation of four quantization rotation factors in quadrant quantization fast Fourier transform according to an embodiment of this application.

[0027] Figure 4 This is a schematic diagram comparing the convergence process of three frequency domain constant modulus algorithm equalization schemes according to an embodiment of this application.

[0028] Figure 5This is a schematic diagram of the bit error rate performance of a system employing a frequency domain constant modulus algorithm equalization method according to an embodiment of this application under back-to-back and 40km standard single-mode fiber transmission conditions.

[0029] Figure 6 This is a schematic diagram comparing the bit error rate performance of three frequency domain constant mode equalization schemes according to an embodiment of this application under the condition of 40 km standard single-mode fiber transmission.

[0030] Figure 7 This is a schematic diagram of the receiver sensitivity and power budget of a system employing a frequency domain constant modulus algorithm equalization method according to an embodiment of this application. Detailed Implementation

[0031] In the following description, many technical details are presented to help the reader better understand this application. However, those skilled in the art will understand that the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0032] Explanation of some concepts: The Constant Modulus Algorithm (CMA) is an adaptive equalization algorithm that utilizes the characteristic that the modulated signal has a constant modulus value under ideal conditions. It constructs an error signal by the amplitude deviation of the output signal to drive the adaptive update of the equalization coefficients, and does not depend on the training sequence.

[0033] Frequency-Domain Constant Modulus Algorithm Equalization (FD-CMA Equalization) refers to constant modulus algorithm equalization implemented by converting time-domain convolution operations into frequency-domain dot product operations.

[0034] The tap coefficient update path refers to the processing path used to adaptively update the frequency domain equalization coefficients.

[0035] The main signal path refers to the processing path used to recover the signal, which includes frequency domain equalization and inverse fast Fourier transform.

[0036] The symbol field update amount refers to the tap coefficient update amount represented by the symbol direction, which is obtained by performing polarity preservation or polarity reversal on the symbol control time domain output signal of the constant modulus algorithm error signal.

[0037] Quadrant-Quantized Fast Fourier Transform (QQ-FFT) is a fast Fourier transform that maps the twitch factor in the fast Fourier transform to a value in the set {1, -1, j, -j} (where j is the imaginary unit), and the multiplication between the quantized twitch factor and the complex number is achieved by negating the sign and / or exchanging the real and imaginary parts.

[0038] The quantization twitch factor is the twitch factor obtained by mapping the twitch factor through the quadrant quantization operator, and whose value belongs to the set {1, -1, j, -j}.

[0039] Frequency domain symbol information refers to the symbol direction information obtained after performing quadrant quantization fast Fourier transform on the symbol domain update quantity, which is used to construct the update direction of the frequency domain equalization coefficients.

[0040] The update direction refers to the frequency domain update amount constructed based on the frequency domain symbol information, which is used to determine the direction of this adjustment of the frequency domain equalization coefficient.

[0041] Multiple-input multiple-output (MIMO) structure refers to a structure that performs equalization processing based on the coefficient relationship between multiple inputs and multiple outputs; the dual-polarization 2 × 2 MIMO structure in this application is used to equalize frequency domain data in two polarization directions.

[0042] A Field Programmable Gate Array (FPGA) is a programmable logic device that can achieve parallel data processing and pipelined operations by configuring its logic resources.

[0043] The following is a brief summary of some of the innovative aspects of this application: In summary, the technical contradiction addressed in this application lies in the fact that frequency-domain constant-modulus equalization in a coherent receiving system requires the signal recovery processing stage to perform polarization demultiplexing and channel distortion compensation with sufficient numerical accuracy, while simultaneously requiring the tap coefficient update stage, which performs adaptive functions, to consume as few multiplier resources as possible under high parallelism and real-time processing hardware conditions. However, in the processing framework of related technologies, these two requirements are simultaneously handled by the same set of high-precision complex number operations, thus increasing the multiplier overhead of the update stage in tandem with parallelism and the number of transform points. The underlying understanding of this application is that the iterative convergence of the tap coefficients depends on the direction of each update in the complex plane, rather than the complete amplitude and phase accuracy. Therefore, maintaining complete numerical accuracy in the update stage is not a necessary condition for achieving adaptive functions.

[0044] Based on this understanding, this application sends the time-domain output signal obtained from the inverse fast Fourier transform and the constant modulus algorithm error signal calculated from it into the tap coefficient update path. First, the sign of the error signal is used as the control quantity and the sign of the time-domain output signal is used as the controlled quantity. Through the operation of polarity preservation or polarity reversal, which is a value-restricted operation, the update quantity that originally had to participate in the calculation according to the amplitude is converged into the sign domain update quantity represented by the sign direction. Since this update quantity no longer carries amplitude information, the time-frequency transformation it subsequently undergoes does not need to aim at restoring the complete amplitude and phase. The quadrant quantization fast Fourier transform can replace the traditional fast Fourier transform here. The twitch factor is mapped to a value in the set {1, -1, j, -j}, and the multiplication between it and the complex number degenerates into sign inversion and / or real part and imaginary part exchange. The frequency domain sign information output by this transform can be used to construct the update direction of the tap coefficients. The update direction is constructed accordingly and used to update the frequency domain equalization coefficients. The updated coefficients are returned to the frequency domain equalization stage to participate in the subsequent processing of frequency domain data, and the adaptive loop is thus closed.

[0045] Furthermore, since quadrant quantization is introduced only in the update path, where amplitude and phase accuracy are insensitive, the main signal path containing frequency domain equalization and inverse fast Fourier transform does not employ this transformation. Therefore, the approximation introduced by quantization is constrained to a range that does not directly affect the signal recovery result. Thus, symbol domain reconstruction provides the prerequisite for quadrant quantization, while quadrant quantization ensures that the multiplications omitted by symbol domain reconstruction do not reappear in the transformation stage. Both, along with the aforementioned dual-path partitioning, work together on the same technical chain, reducing the complexity of the computational units in the update path without unnecessary loss of main signal recovery accuracy.

[0046] Furthermore, through in-depth research and analysis of the real-time hardware implementation process of frequency domain constant modulus equalization in a coherent receiving system, the inventors of this application discovered that the multiplier overhead of the tap coefficient update path is not concentrated in a single operation, but distributed across three interconnected stages: the time-domain output signal is multiplied by the real error signal to form the update quantity, which is then subjected to a Fast Fourier Transform (FFT) to enter the frequency domain, and then multiplied point-by-point by the conjugate of the frequency domain data to obtain the frequency domain update quantity. While the time-domain multiplication is not complex multiplication, two real multipliers are still required for each complex sample; the rotation factor in the transform stage is generally a unit complex number of arbitrary phase, and each butterfly stage requires complex multiplication accordingly; and the point-by-point frequency-domain multiplication requires complex multiplication for each frequency point. After these three factors are combined, the multiplier requirement of the update path increases with parallelism and the number of transform points, manifesting as increased multiplier resource consumption and wiring pressure in the implementation of a field-programmable gate array (FPGA).

[0047] If the computational precision of the signal recovery stage is reduced to save resources, it will directly affect the results of polarization demultiplexing and channel distortion compensation. If only the sign of the updated quantity is taken and the traditional transformation stage is retained, the complex multiplication of the rotation factor will still exist, and the extent of resource reduction will be limited. Therefore, the key issue is that the processing stage responsible for adaptive updating and the processing stage responsible for signal recovery are treated with the same precision requirements, but their actual needs for numerical precision are different: the former only needs to determine the adjustment direction of the coefficients, while the latter requires complete amplitude and phase information. Based on the above analysis, this application proposes a corresponding technical solution.

[0048] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0049] It should be understood that the following specific embodiments are only used to explain this application and are not intended to limit the scope of protection of this application; for those skilled in the art, various equivalent transformations, substitutions or combinations can be made to the following embodiments without departing from the technical concept of this application.

[0050] This application provides a frequency-domain constant modulus (CMA) equalization method, a frequency-domain CMA equalization device, and a coherent receiving system. These are primarily applied to adaptive equalization processing in coherent optical communication receivers, particularly suitable for coherent passive optical networks, dual-polarization coherent receiving systems, and other high-speed coherent receiving scenarios requiring real-time digital signal processing. The constant modulus algorithm (CMA) utilizes the characteristic that the modulated signal has a constant modulus value under ideal conditions. It constructs an error signal based on the amplitude deviation of the output signal and drives the adaptive update of the equalization coefficients, independent of the training sequence. The frequency-domain CMA equalization (hereinafter referred to as FD-CMA equalization) converts time-domain convolution operations into frequency-domain dot product operations, adapting to the implementation requirements of large tap numbers and high parallelism. In this application, the tap coefficient update path refers to the processing path used for adaptively updating the frequency-domain equalization coefficients; the main signal path refers to the processing path used for signal recovery, where frequency-domain equalization and inverse fast Fourier transform are performed. Quadrant quantized fast Fourier transform (hereinafter also referred to as QQ-FFT) refers to a fast Fourier transform that maps the twitch factor in the fast Fourier transform to a value in the set {1, -1, j, -j} (where j is the imaginary unit), and the multiplication between the quantized twitch factor and the complex number is achieved by negating the sign and / or exchanging the real and imaginary parts. Its specific implementation will be explained in detail below.

[0051] An important aspect of this application's embodiments is that, while maintaining the basic processing framework of the frequency domain constant modulus algorithm equalization, to address the issues of numerous complex multiplications and high hardware implementation complexity in the tap coefficient update path, the sign domain of the update quantity is first reconstructed in this update path, so that the update quantity is represented by the sign direction; then, quadrant quantization fast Fourier transform is used to replace the traditional fast Fourier transform in this update path to obtain the frequency domain sign information required for tap coefficient update; subsequently, the update direction is constructed based on the frequency domain sign information, and the frequency domain equalization coefficients are updated. The updated frequency domain equalization coefficients continue to be used for frequency domain equalization of subsequent frequency domain data, thereby forming a complete adaptive closed loop. Through the above processing, the rotation factor multiplication of the fast Fourier transform in the tap coefficient update path is implemented by sign inversion and / or real-imaginary part exchange, and the fast Fourier transform in this update path does not use a complex multiplier.

[0052] It should be noted that the reduction in multiplier requirements in this application mainly targets the tap coefficient update path. For the dot product operation between the frequency domain equalization coefficients and frequency domain data, and the inverse fast Fourier transform (IFFT) in the main signal path, conventional high-precision implementation can be used according to system performance requirements. That is, quadrant quantization IFFT is only used in the tap coefficient update path; the main signal path containing the frequency domain equalization and IFFT does not use quadrant quantization IFFT. The above statement does not mean that all operations in the coherent receiving system or the frequency domain constant modulus equalization algorithm do not use multipliers. This dual-path design is based on the understanding that after symbol domain reconstruction, the tap coefficient update mainly depends on the update direction, i.e., the symbol or quadrant direction information, and not on the complete amplitude and phase accuracy of the IFFT output. Therefore, the update path can use a low-complexity transformation that only estimates the symbol direction; maintaining conventional accuracy in the main signal path reduces the hardware complexity of the update path while avoiding unnecessary loss of accuracy in the main signal recovery.

[0053] Example 1 This embodiment provides a frequency domain constant modulus equalization algorithm method applied to a coherent receiving system. The method includes steps 100 to 700, where steps 500 to 700 are located in the tap coefficient update path. Figure 1 shows the flowchart of the method, and each step can be executed by the corresponding module in the frequency domain constant modulus equalization algorithm device shown in Figure 2.

[0054] Step 100: Obtain the frequency domain data of the coherent received signal.

[0055] This step provides input for frequency domain equalization. Frequency domain data can be obtained from the coherent received signal after analog-to-digital conversion, resampling, serial-to-parallel conversion, fast Fourier transform, and other pre-processing digital signal processing modules. Physically, it originates from the coherent detection results of the optical signal by the coherent receiver and has a clear signal technical meaning. For a dual-polarization coherent receiving system, the frequency domain data can include frequency domain data in two polarization directions, denoted as... X and Y In one exemplary implementation, the frequency domain data is multi-channel parallel frequency domain data, and the number of parallel channels can be a power of 2, such as 64, 128, or 256.

[0056] Step 200: Perform frequency domain equalization on the frequency domain data based on the frequency domain equalization coefficient to obtain the frequency domain equalized output.

[0057] For a dual-polarization coherent receiver system, frequency domain equalization can employ a dual-polarization 2 × 2 multiple-input multiple-output (MIMO) structure. The frequency domain equalization coefficients include... W xx , W xy , W yx and W yy This is used to compensate for channel response and polarization crosstalk between two polarization directions. In a typical implementation, the frequency domain equalization output can be obtained as shown in Equation (1) by multiplying and summing the frequency domain equalization coefficients with the frequency domain data point by point: E x = W xx ⋅ X + W xy ⋅ Y , E y = W yx ⋅ X + W yy ⋅ Y (1) in, X and Y These represent frequency domain data in two polarization directions, E x and E yThese represent the frequency domain equalization outputs in the two polarization directions, respectively. The multiplication in formula (1) is a point-by-point multiplication in the frequency domain, and all the above variables can be multi-channel parallel frequency domain data. Through this 2 × 2 multiple-input multiple-output frequency domain equalization structure, polarization demultiplexing and frequency domain channel compensation of dual-polarization coherent signals can be realized. This step belongs to the main signal path and can be implemented using conventional high-precision methods.

[0058] Step 300: Perform an inverse fast Fourier transform on the frequency domain equalization output to obtain the time domain output signal.

[0059] For a dual-polarization coherent receiver system, it is possible to separately... E x and E y Performing the inverse fast Fourier transform (IFFT) yields the time-domain output signals of each of the two polarization branches. The IFFT also belongs to the main signal path and can be implemented using conventional high-precision methods. The time-domain output signals serve two purposes: firstly, as the equalization result used in subsequent signal processing; and secondly, as the data source for error calculation and symbol domain reconstruction, serving as the update source for tap coefficients. For ease of explanation, the following uses the time-domain output signal of any polarization branch. y Let's take an example to describe it. y It is a complex signal.

[0060] Step 400: Calculate the constant modulus algorithm error signal based on the time-domain output signal.

[0061] The constant modulus algorithm leverages the characteristic that the modulated signal has a constant modulus value under ideal conditions. It constructs an error signal based on the amplitude deviation of the time-domain output signal, thereby driving the iterative update of the frequency-domain equalization coefficients. In one exemplary implementation, for a QPSK signal, the error signal can be calculated based on the deviation of the modulus value of the time-domain output signal from the constant modulus reference value. An exemplary expression for this can be found in the "Several Optional Exemplary Implementations" section below. The error signal is denoted as... e This can be a real number, used to control the direction and magnitude of the tap coefficient update. It should be noted that the specific error expression can be adjusted according to the modulation format, normalization method, and system implementation; this application is not limited to a single specific error calculation formula. Furthermore, this application is not limited to QPSK signals, and can also be applied to other modulation formats with constant or near-constant mode characteristics based on the constant mode algorithm or its variants.

[0062] Before explaining steps 500 to 700, let's first describe the processing of the traditional tap coefficient update path. In traditional FD-CMA equalization, tap coefficient updates typically involve time-domain error correlation calculations, fast Fourier transforms of the update path, and point-by-point complex multiplications in the frequency domain. Taking an update path as an example, the traditional update amount usually includes the product of the time-domain output signal and the error signal.y ⋅ e ,in y For complex signals, e The error signal is a real number; although this operation is not complex multiplication, it still typically requires two real multipliers for each complex sample. Furthermore, traditional FD-CMA requires converting the update-related time-domain signal to the frequency domain using a Fast Fourier Transform, and then performing point-by-point complex multiplication with the conjugate of the frequency-domain input data to obtain the frequency-domain tap coefficient update. For highly parallel systems, the overhead of these multipliers is significant, noticeably increasing the resource consumption of DSP multipliers in a Field-Programmable Gate Array (FPGA). To reduce this complexity, this embodiment executes steps 500 to 700 in the tap coefficient update path.

[0063] Step 500: In the tap coefficient update path, extract the sign of the time-domain output signal and the sign of the constant modulus algorithm error signal. The sign of the constant modulus algorithm error signal controls the polarity preservation or polarity reversal of the sign of the time-domain output signal to obtain the sign domain update amount represented by the sign direction.

[0064] First, the sign operation in this application embodiment is defined. For real numbers... u Sign function S (⋅) Satisfies: u >0 S ( u ) = +1, u < 0 S ( u ) = -1; for u In the case of = 0, its sign is determined according to the zero-value handling method described later. For complex numbers... z = a + j b ,in a and b They are respectively z The real and imaginary parts of the symbol are represented as shown in formula (2): Sign( z ) = S ( a ) + j S ( b (2) That is, to sign the real and imaginary parts of a complex number respectively, Sign(⋅) represents the complex number signification operator.

[0065] In this step, the time-domain output signal is... y Symbol extraction is performed according to formula (2) to obtain Sign( y ); for error signals eSymbol extraction is performed because e For a real number, its sign is... S ( e The value is +1 or -1. Because... e For real numbers, we have Sign( y ⋅ e ) = S ( e ) ⋅ Sign( y Therefore, the traditional y ⋅ e Operations can be transformed into... S ( e Control polarity selection operation: when S ( e When ) = +1, keep y The signs of the real and imaginary parts remain unchanged, i.e., the polarity is preserved; when S ( e When ) = -1, flip simultaneously. y The real and imaginary parts of the symbol are reversed, i.e., the polarity is flipped. The resulting symbol field update is represented by the sign direction, and its value is restricted to one of the four quadrants in the complex plane, namely {+1 + j, +1 - j, -1 + j, -1 - j}. Thus, the complex-to-real multiplication operation, which originally required a real multiplier, can be implemented by sign judgment, sign inversion, and selection logic, which can be completed in hardware by sign bit XOR, conditional inversion logic, or a data selector. This symbolization process is only used in the tap coefficient update path and does not change the regular processing of the main signal path.

[0066] Furthermore, for the zero-value case, in one optional implementation: when the error signal... e When the value is zero, the update enable signal for this update is turned off, and the update of the frequency domain equalization coefficients is not performed to avoid meaningless updates. When the real or imaginary part of the data to be acquired is zero, the symbol of the zero component retains the previous valid symbol to reduce symbol jitter and uncertain flipping. In the case where there is no previous valid symbol, such as at the beginning of processing, the symbol of the zero component can be a preset symbol. As another optional method, the update amount can be set to zero when the error signal is zero, or a preset symbol can be used for the zero component. The process of this embodiment is exemplified by the former method.

[0067] Step 600: Perform quadrant quantization fast Fourier transform on the symbol field update quantity to obtain the frequency domain symbol information required for tap coefficient update.

[0068] Even after performing the symbol domain reconstruction in step 500, the Fast Fourier Transform (FFT) in the tap coefficient update path may still contain a large number of complex multiplications involving rotation factors. To further eliminate these multipliers, this embodiment uses a quadrant-quantized FFT to replace the traditional FFT in the tap coefficient update path. This allows for rapid estimation of the symbol information of the FFT output without requiring precise calculation of its amplitude information.

[0069] In tradition N In the hierarchical butterfly structure of the point fast Fourier transform, the first... s The rotation factor corresponding to the butterfly operation can be shown in formula (3): W m t = exp(-j2π t / m (3) in, W m t This represents the rotation factor at the corresponding position. m = 2 s For the first s The length of the sub-blocks at each level, t Let exp(⋅) represent the butterfly position within this sub-block, where exp(⋅) represents an exponential function with the natural constant as the base, and π represents pi. This rotation factor is generally a unit complex number of arbitrary phase, requiring complex multiplication in hardware implementation. This embodiment uses the notation convention of the Fast Fourier Transform in the negative exponential form shown in formula (3) as an example for explanation.

[0070] Unlike traditional implementations, quadrant quantization Fast Fourier Transform maps the rotation factor to the nearest quadrant principal direction using a quadrant quantization operator, thus obtaining the quantized rotation factor. In one optional implementation, quadrant quantization is performed by dividing the rotation factor into phase intervals, and the quadrant quantization operator is shown in equation (4): in, W arg(⋅) represents the rotation factor to be quantized, and arg(⋅) represents the phase operator, with the phase value range being [-π, π]. Except for the interval [3π / 4, π], which is a closed interval, all other intervals are left-closed and right-open intervals. Q (⋅) denotes the quadrant quantization operator. Q ( W This refers to the quantization rotation factor, which takes a value from the set {1, -1, j, -j}.

[0071] For any complex number z = a + jb Quantization rotation factor and z The multiplication results are as follows: when the quantization rotation factor is +1, the output is... a + j b That is, inputting a complex number results in a direct output; when the quantization rotation factor is -1, the output is - a -j b This means inverting the real and imaginary parts of the input complex number; when the quantization twitch factor is +j, the output is -j. b + j a This involves swapping the real and imaginary parts of the input complex number and inverting the real part of the output after the swap; when the quantization twitch factor is -j, the output is... b - j a This means swapping the real and imaginary parts of the input complex number and inverting the imaginary part of the output after the swap. Figure 3 The four multiplier-free implementations of the quantized twiddle factor described above are illustrated. It can be seen that multiplication between the quantized twiddle factor and the complex number is achieved through sign inversion and / or real-imaginary part swapping, eliminating the need for a complex multiplier. For FPGAs, these operations can be implemented using lookup tables, data selectors, registers, and addition / subtraction logic, thus avoiding the consumption of DSP multiplier resources.

[0072] In one alternative implementation, the four types of rotation operations are selected by a two-bit control code, corresponding to the quantization rotation factor. For example, let the two-bit control code... q sel When 00, 01, 10, and 11 are taken, they correspond to +1, -1, +j, and -j, respectively. It should be noted that if the system adopts a Fast Fourier Transform with an exponent sign convention opposite to that in formula (3), it is only necessary to interchange the selection codes of +j and -j in the control table. The butterfly structure and other implementation methods are not affected.

[0073] like Figure 2 As shown, the butterfly unit of the quadrant-quantized fast Fourier transform includes a quadrant rotation branch, an addition branch, and a subtraction branch. Each butterfly unit reads two input complex numbers. A and B , B First, the data passes through a quadrant rotation unit and is rotated according to the quantization rotation factor to obtain the quantized and rotated data. B q ,Right now B q To quantize the rotation factor and B The product is achieved by inverting the sign and / or swapping the real and imaginary parts according to the four types of rotation operations mentioned above; then, the output as shown in formula (5) is obtained through butterfly addition and subtraction operations: Y0 = A + B q , Y 1 = A - B q (5) in, Y 0 and Y 1 represents the two outputs of this butterfly unit. Because... B q The computation only requires sign inversion and / or real-imaginary part exchange. The rotation factor multiplication in this butterfly unit does not require a complex multiplier. Compared with the traditional fast Fourier transform butterfly unit, this butterfly unit retains the addition and subtraction structure, but eliminates the rotation factor complex multiplier.

[0074] In one alternative implementation, the quadrant-quantized fast Fourier transform employs a radix-2 hierarchical butterfly structure, with the number of transform points... N Powers of 2 N = 2 p , p Given positive integers and representing series, hierarchical butterfly structures include... p The butterfly operation stage. The input data is first sorted by bit reversal, and then sequentially processed... p Level butterfly operation; s class( s = 1,2, …, p The length of the sub-block is m = 2 s Each sub-block contains m / 2 butterfly units, the first one in each sub-block t Each butterfly unit ( t = 0, 1, …, m The quantization rotation factor of / 2 - 1) is q s,t = Q ( W m t That is, the result of quadrant quantization of the rotation factor shown in formula (3) according to formula (4), the butterfly unit is based on q s,t For input B Quadrant rotation is performed to obtain B q And output according to formula (5). The quantization rotation factor for each level can be pre-written into the control table, or it can be generated by combining the level number and the position within the group. For example, for N= 128. The quadrant-quantized Fast Fourier Transform includes 7 levels of butterfly processing, with sub-block lengths of 2, 4, 8, 16, 32, 64, and 128 respectively. The rotation factor of the first level can be considered as +1, and subsequent levels select +1, -1, +j, or -j based on their position within the group. Those skilled in the art can adopt equivalent quadrant-quantization rules according to the specific Fast Fourier Transform structure and rotation factor distribution.

[0075] In one alternative implementation, the quadrant-quantized fast Fourier transform includes multiple butterfly operation stages, with each intermediate stage maintaining a fixed bit width output and not assigning a sign to the intermediate stage outputs; only after the last stage output (denoted as...) is the sign assigned to the last stage output. v Take the sign, that is, calculate Sign( according to formula (2)). v ) = S (Re( v )) + j S (Im( v )), where Re( v ) and Im( v ) represent respectively v The real and imaginary parts of the symbol are used to obtain the symbol direction, which is then used as frequency domain symbol information for tap coefficient updates. This process avoids premature symbol taking at intermediate stages, which could lead to excessive deviations between the output direction of subsequent stages and the expected direction. It also helps to retain the main direction information required for tap coefficient updates. For example, each data path can maintain a 16-bit fixed-point format, as detailed in Embodiment 3.

[0076] It should also be noted that quadrant-quantized Fast Fourier Transform (FFT) does not require the recovery of the complete amplitude and phase information of traditional FFT, but rather is used to quickly estimate the sign or quadrant direction of the FFT output data. Since the tap coefficient update process in this embodiment involves sign domain reconstruction, the update direction mainly depends on the sign information of the frequency domain result rather than the precise amplitude information. Therefore, quadrant-quantized FFT can meet the tap coefficient update requirements with lower hardware complexity. This design approach differs from the traditional FFT implementation that pursues numerical accuracy and is more suitable for low-complexity hardware implementation in adaptive update paths.

[0077] Step 700: Construct an update direction based on the frequency domain symbol information, update the frequency domain equalization coefficients according to the update direction, and use the updated frequency domain equalization coefficients for frequency domain equalization of subsequent frequency domain data.

[0078] In one alternative implementation, the conjugate of the frequency domain data is also symbolized in the tap coefficient update path to obtain the conjugate symbol as shown in formula (6): Sign( x ) = S (Re( x )) - j S (Im( x (6) in, x This represents frequency domain data (e.g., frequency domain input data of the corresponding polarization branch). x express x The conjugate of Re( x ) and Im( x ) represent respectively x The real and imaginary parts of the input data are then used. In this case, the update direction is constructed jointly by the conjugate sign and the frequency domain sign information, thus corresponding in the symbol domain to the role of the conjugate of the frequency domain input data in the calculation of the frequency domain update amount during the traditional update process. An exemplary construction method is described in the "Several Optional Exemplary Implementations" section below. Through the above processing, the tap coefficient update no longer depends on the high-precision complex multiplication result, but is driven by the sign direction, and can be completed through addition, subtraction, sign reversal, and selection logic.

[0079] In one alternative implementation, the frequency domain equalization coefficients are updated according to formula (7): W new = W old + μG (7) in, W old This represents the frequency domain equalization coefficients before the update. W new This represents the updated frequency domain equalization coefficients. μ Indicates the update step size. G This represents the frequency domain update direction constructed from the symbol information generated by the aforementioned symbol domain update processing and quadrant quantization fast Fourier transform. Because... G Primarily determined by sign information, its value can be restricted to several predetermined directions. The accumulation and update process of the coefficients can be achieved through addition, subtraction, and sign control. For a dual-polarization 2 × 2 multiple-input multiple-output structure, the frequency domain equalization coefficients... W xx , W xy , W yx and W yy All can be updated adaptively in the manner described above.

[0080] The updated frequency domain equalization coefficients are fed back to the frequency domain equalization process for frequency domain equalization of subsequent frequency domain data (i.e., return to step 200 to continue processing subsequent data blocks), thereby forming an adaptive blind equalization closed loop that does not depend on the training sequence, realizing continuous tracking compensation for polarization demultiplexing and channel distortion.

[0081] Example 2 This embodiment provides a frequency domain constant modulus algorithm equalization device, which can be used to execute the method described in Embodiment 1. As shown in Figure 2, the device includes a frequency domain equalization module 101, an inverse fast Fourier transform module 102, an error calculation module 103, a symbol domain update module 104, a quadrant quantization fast Fourier transform module 105, and a coefficient update module 106, wherein the symbol domain update module, the quadrant quantization fast Fourier transform module, and the coefficient update module are located in the tap coefficient update path.

[0082] The frequency domain equalization module performs frequency domain equalization on the frequency domain data of the coherent received signal based on the frequency domain equalization coefficients, obtaining a frequency domain equalized output. This output is then provided to the inverse fast Fourier transform (IFT) module, and its processing method is described in steps 100 and 200. The IFT module performs an IFT on the frequency domain equalized output to obtain a time domain output signal, which is then provided to both the error calculation module and the symbol domain update module. Its processing method is described in step 300. The error calculation module calculates the constant modulus algorithm error signal based on the time domain output signal and provides this error signal to the symbol domain update module. Its processing method is described in step 400. The symbol domain update module extracts the symbol of the time-domain output signal and the symbol of the constant modulus algorithm error signal in the tap coefficient update path. The symbol of the error signal controls the polarity preservation or polarity reversal of the symbol of the time-domain output signal, resulting in a symbol domain update amount represented by the symbol direction. This symbol domain update amount is then provided to the quadrant quantization fast Fourier transform module, and its processing method is described in step 500. The quadrant quantization fast Fourier transform module performs a quadrant quantization fast Fourier transform on the symbol domain update amount to obtain the frequency domain symbol information required for tap coefficient updates. This frequency domain symbol information is then provided to the coefficient update module. The quantization of the rotation factor and the multiplier-free rotation implementation method are described in step 600. The coefficient update module constructs an update direction based on the frequency domain symbol information, updates the frequency domain equalization coefficients according to the update direction, and feeds back the updated frequency domain equalization coefficients to the frequency domain equalization module for subsequent frequency domain equalization of the frequency domain data. Its processing method is described in step 700.

[0083] In this design, the quadrant quantization fast Fourier transform module is only located in the tap coefficient update path. The main signal path containing the frequency domain equalization module and the inverse fast Fourier transform module does not employ quadrant quantization fast Fourier transform; the main signal path can be implemented using conventional high-precision methods. Through the data provision and coefficient feedback relationships between the above modules, this device forms the same adaptive closed loop as in Embodiment 1.

[0084] It should be noted that the above module division is for illustrative purposes only and does not constitute a limitation on the implementation method. In actual implementation, multiple modules can be merged into one module, or a module can be split into multiple sub-modules; each process can be executed in parallel, interleaved, or sequentially according to the hardware pipeline structure.

[0085] Example 3 This embodiment provides a coherent receiving system, including an analog-to-digital conversion module and a frequency-domain constant-modulus (NCM) equalization device as described in Embodiment 2. The analog-to-digital conversion module performs analog-to-digital conversion on the coherent received signal to obtain a coherent received digital signal; the frequency-domain NCM equalization device performs real-time frequency-domain NCM equalization processing on the frequency-domain data obtained from the coherent received digital signal, and is deployed on a field-programmable gate array (FPGA) to implement real-time digital signal processing using a parallel pipeline structure.

[0086] For a dual-polarization coherent receiver system, the receiver obtains in-phase and quadrature components in two polarization directions through a coherent receiver. These components are then converted into coherent received digital signals by an analog-to-digital converter and enter the FPGA digital signal processing link. For example, the pre-processing module may include resampling, synchronization, frequency offset estimation, frame processing, fast Fourier transform, or other processing modules. The frequency domain data is obtained from the coherent received digital signal through the aforementioned pre-processing. The frequency domain constant modulus algorithm equalization device serves as the adaptive equalization module, used to complete polarization demultiplexing and frequency domain equalization.

[0087] In an exemplary FPGA implementation, the system as a whole adopts a 16-bit signed fixed-point fractional format, specifically including 1 sign bit, 7 integer bits, and 8 fractional bits, using binary two's complement form (which can be referred to as Q7.8 fixed-point format). This bit width is an engineering parameter chosen as a trade-off between system performance, hardware resources, and implementation complexity; the resource usage, processing delay analysis, and system verification described later are all performed under this fixed-point bit width. In actual implementation, other fixed-point bit widths, rounding methods, saturation methods, or processing clocks can be selected according to the system modulation format, link budget, FPGA model, and error tolerance. As long as the update path performs sign direction driving and quadrant quantization fast Fourier transform processing in the manner described in this application embodiment, they all belong to the same technical concept. The bit widths and control methods of the main signals and modules in this exemplary implementation are shown in Table 1.

[0088] Table 1. Bit width and control method in exemplary FPGA implementations In terms of pipeline, the quadrant-quantized fast Fourier transform employs a stage-by-stage pipelined structure. Each stage includes input registers, quadrant rotation, butterfly operations, bit width normalization, output registers, and delay alignment units. Quadrant rotation, located before butterfly operations, contains only selection, exchange, and inversion logic; butterfly operations can be implemented using lookup tables, carry chains, and registers. The valid signals and update enable signals at each stage are shifted synchronously with the data, aligning the final update direction with the corresponding frequency domain input.

[0089] As can be seen from the above implementation, the symbol domain reconstruction and quadrant quantization processes directly determine the composition of the computational units in the tap coefficient update path of the FPGA: the operations such as rotation factor complex multiplication originally handled by the DSP multiplier are replaced by data selectors, inversion logic, real-imaginary part exchange connections, and addition and subtraction logic; the updated frequency domain equalization coefficients are then fed back to the frequency domain equalization of the main signal path, thus making the above algorithm processing directly related to the reduction of hardware resource consumption.

[0090] Example 4 In one alternative application, the methods, apparatus, and systems described in Embodiments 1 to 3 can be applied to dual-polarization QPSK receivers in coherent passive optical networks. For real-time receiving systems in 100G and above coherent passive optical networks, the receiver typically requires a high sampling rate and high parallelism. Traditional FD-CMA equalization has high multiplier requirements in the tap coefficient update path, leading to increased FPGA resource consumption and wiring pressure. The update path processing method of the embodiments of this application can reduce the dependence of the tap coefficient update part on DSP multiplier resources, making it more suitable for real-time processing on resource-constrained FPGA platforms.

[0091] In an exemplary system verification, the transmitter generates a 25.06752 GBaud dual-polarization QPSK (DP-QPSK) signal, and the receiver's four analog-to-digital converters have a sampling rate of 28.20096 GSa / s, corresponding to approximately 1.125 sampling points per symbol. Real-time digital signal processing on the receiver side includes Fast Fourier Transform, frequency domain timing recovery, frequency domain constant modulus algorithm equalization, frequency offset estimation, and carrier phase estimation. The frequency domain constant modulus algorithm equalization module employs the tap coefficient update path scheme described in the embodiments of this application.

[0092] To illustrate the technical effects, the scheme of this application embodiment (hereinafter referred to as QQ-FFT FD-CMA) is compared with the traditional frequency domain constant modulus algorithm equalization (hereinafter referred to as traditional FD-CMA), and the scheme that only symbolizes the update amount but still uses the traditional fast Fourier transform for the update path (hereinafter referred to as symbolized FD-CMA, which is used as a control scheme in this exemplary verification, and its processing method is comparable to the low-complexity improvement method of replacing part of the complex multiplication with symbolic multiplication described in the background art). The three schemes have similar complexity in main signal path frequency domain equalization and inverse fast Fourier transform. The differences lie in the tap coefficient update path: traditional FD-CMA includes time-domain complex multiplication of real numbers, frequency-domain pointwise complex multiplication, and rotation factor multiplication in the update path fast Fourier transform; symbolic FD-CMA reduces some multiplications, but its update path fast Fourier transform still requires rotation factor multiplication; QQ-FFT FD-CMA further replaces the update path fast Fourier transform with quadrant quantized fast Fourier transform, replacing the rotation factor multiplication in the update path with inversion, real-imaginary part exchange, and selection logic.

[0093] From the statistical perspective of the theoretical number of real number multiplications, the complexity comparison of the three schemes is shown in Table 2, where... N To change the number of points. It should be noted that the statistics on the number of real number multiplications in Table 2 according to the algorithm structure are different from the statistics on DSP usage based on the FPGA synthesis results described later.

[0094] Table 2. Comparison of theoretical real multiplication complexity of the three schemes On the Xilinx XCVU13P FPGA platform, based on a 16-bit fixed-point data path (1 sign bit, 7 integer bits, 8 fractional bits) and a 261.12 MHz processing clock, FPGA resource and processing latency analysis was performed on three schemes. The processing latency was calculated as the product of the number of clock cycles and the clock cycle. In this example, the clock cycle is approximately 3.83 ns. The results are shown in Table 3.

[0095] Table 3 Comparison of FPGA resources and processing latency for the three schemes As shown in Table 3, under the same FPGA platform, fixed-point bit width, and processing clock conditions, QQ-FFTFD-CMA reduces the DSP usage from 58.33% to 23.96% and the processing latency from 497.90 ns to 375.34 ns compared to traditional FD-CMA. LUT and FF usage are also reduced by approximately 28.46% and 24.09%, respectively. Compared to symbolic FD-CMA only, it further reduces the DSP usage from 35.42% to 23.96% and the processing latency from 467.26 ns to 375.34 ns. The difference in resource consumption stems from the update path structure itself, rather than from the comparison deviation between different device platforms or different operating clocks. As mentioned earlier, the frequency domain equalization dot multiplication and inverse fast Fourier transform in the main signal path can be implemented using conventional high-precision methods; therefore, the overall system still occupies certain multiplier resources. The resource reduction reflected in the above comparison mainly comes from the tap coefficient update path.

[0096] Regarding convergence behavior, in this exemplary verification, the traditional FD-CMA, due to its use of full-precision gradients, exhibits the fastest initial convergence speed, with the error converging to a stable, relatively small range after approximately 300 data blocks. The symbolic FD-CMA and QQ-FFT FD-CMA, using polarity direction information, have slightly slower initial convergence speeds, but both achieve convergence and reach a stable convergence state after approximately 500 data blocks. The convergence trends of QQ-FFT FD-CMA and symbolic FD-CMA are similar, indicating that replacing the Fast Fourier Transform of the update path with a Quadrant Quantized Fast Fourier Transform still preserves the main directional information required for tap coefficient updates.

[0097] like Figure 5 As shown, the coherent passive optical network system employing the scheme of this application can be tested for performance under back-to-back transmission conditions and 40 km standard single-mode fiber transmission conditions. Figure 6 As shown, under 40 km standard single-mode fiber transmission conditions, the bit error rate (BER) curves of the three schemes—traditional FD-CMA, symbol-only FD-CMA, and QQ-FFT FD-CMA—show essentially the same variation with received optical power; at a BER threshold of 2 × 10⁻⁶, the BER curves are consistent. -2 At this point, the receiving sensitivity of all three schemes is approximately -37 dBm, indicating that the low-complexity update path in this embodiment does not cause significant degradation in receiving sensitivity.

[0098] The receiving sensitivity and power budget of the system employing the scheme of this application can be further tested. By adjusting the output power of the transmitter or optical amplifier and measuring the corresponding bit error rate performance at the receiver, the relationship between the system sensitivity and power budget can be obtained. Under 40 km standard single-mode fiber transmission without additional dispersion compensation, the scheme of this application can still achieve a bit error rate threshold of 2 × 10⁻⁶. -2 A receiver sensitivity of approximately -37 dBm was achieved; in this exemplary verification, the maximum system power budget was measured to be 43.8 dB when the semiconductor optical amplifier (SOA) output power reached 8 dBm. Figure 7 It can also be seen that the receiving sensitivity deteriorates with the increase of the semiconductor optical amplifier's output power. Therefore, the maximum power budget is not a simple difference between the receiving sensitivity and the semiconductor optical amplifier's output power, but should be determined based on the measured receiving sensitivity at each semiconductor optical amplifier's output power. It should be noted that... Figures 4 to 7 The results shown are merely illustrative verification results and do not constitute a limitation on transmission distance, modulation format, test conditions, or system architecture.

[0099] In summary, this application addresses the issue of high resource consumption of complex multipliers in the equalization tap coefficient update path of the frequency domain constant modulus algorithm. By combining symbol domain reconstruction with quadrant quantization fast Fourier transform, operations such as rotation factor multiplication in the update path are transformed into hardware-friendly operations such as sign inversion, real-to-imaginary part exchange, addition and subtraction, and selection logic. While maintaining the basic framework of the frequency domain constant modulus algorithm equalization and the processing accuracy of the main signal path, the complexity of FPGA implementation is reduced, making it suitable for real-time digital signal processing in coherent passive optical networks and other high-speed coherent receiving systems.

[0100] The above embodiments have the following technical effects: First, by mapping the twitch factor of the Fast Fourier Transform in the tap coefficient update path to a value in the set {1, -1, j, -j}, and making the multiplication between the quantized twitch factor and the complex number realized by sign inversion and / or real part and imaginary part exchange, the Fast Fourier Transform in this update path no longer needs a twitch factor complex multiplier. The corresponding operation can be completed by the data selector, inversion logic, exchange connection and addition and subtraction logic, thereby reducing the occupation of DSP multiplier resources in the FPGA. Secondly, by controlling the sign of the time-domain output signal with the sign of the constant modulus algorithm error signal to maintain or reverse the polarity, the update quantity is reconstructed into a sign-domain update quantity represented by the sign direction. This allows the complex multiplication of real numbers that originally required multipliers in the update path to be completed by sign judgment and selection logic, and makes the tap coefficient update driven by the sign direction. This, in conjunction with the frequency domain sign information output by the quadrant quantization fast Fourier transform, together replaces the complex multiplication operation in this update path with sign judgment, sign inversion, real-imaginary part swapping, and selection logic. Thirdly, the quadrant quantization fast Fourier transform is only set in the tap coefficient update path. The frequency domain equalization and inverse fast Fourier transform of the main signal path can still be implemented using conventional high-precision methods. Since the update process after sign domain reconstruction requires the update direction rather than the complete amplitude and phase accuracy, this dual-path design ensures that the approximation introduced by quantization does not directly affect the recovery result of the main signal. This reduces the hardware complexity of the update path while avoiding unnecessary accuracy loss in the main signal recovery path. Fourth, based on exemplary verification data, under the same FPGA platform, the same fixed-point bit width, and the same processing clock conditions, compared with the traditional FD-CMA, the DSP utilization rate of the scheme in this application embodiment is reduced from 58.33% to 23.96%, and the processing latency is reduced from 497.90 ns to 375.34 ns. According to the statistical caliber shown in Table 2, the theoretical number of real number multiplications is... N = 128, the error rate decreased from 8960 to 4224; at the same time, the convergence remained stable, and the curve of the bit error rate as a function of received optical power under 40 km standard single-mode fiber transmission was basically consistent with the traditional scheme, and the receiving sensitivity was about -37 dBm. This shows that the embodiment of this application reduced the hardware resource consumption and processing delay while keeping the convergence stability and receiving sensitivity basically unaffected and slightly extending the initial convergence speed. Fifth, the updated frequency domain equalization coefficients are fed back for frequency domain equalization of subsequent frequency domain data, forming an adaptive blind equalization closed loop that does not depend on the training sequence. This can meet the real-time processing requirements of high-speed coherent receiving systems such as coherent passive optical networks for polarization demultiplexing and channel distortion compensation.

[0101] Several optional exemplary implementations The above embodiments have described the processing flow, device configuration, system deployment, and exemplary verification results of this application. To facilitate understanding by those skilled in the art, several optional exemplary implementation methods are further described below. It should be noted that the content in this section is merely illustrative, used to illustrate a feasible specific form of the corresponding processing step, and is not intended to limit this application; those skilled in the art can adopt other equivalent implementation methods based on modulation format, normalization method, system implementation, and hardware conditions. Adopting any one of these methods, any combination thereof, or equivalent substitutions will not affect the implementation of the processing method in the aforementioned embodiments where the tap coefficient update is driven by the sign direction and the quadrant quantization fast Fourier transform is only set in the tap coefficient update path.

[0102] (a) An exemplary calculation method for the constant modulus algorithm error signal. In one exemplary implementation, for a QPSK signal, the constant modulus algorithm error signal in step 400 can be calculated according to formula (8): e = R 2 - | y | 2 (8) in, y Represents the time-domain output signal, | y | represents the magnitude of the time-domain output signal. R This represents the constant modulus reference value corresponding to the modulation format. The error signal is a real number, and its sign... S ( e This is used to control the polarity maintenance or polarity reversal of the time-domain output signal symbols. For other modulation formats with constant or near-constant mode characteristics, the constant mode reference value and error expression can be determined accordingly according to the constant mode algorithm or its variants, or a normalized error expression can be used.

[0103] (ii) An exemplary construction method for the update direction. In one exemplary implementation, the update direction in step 700... G It can be constructed by multiplying the signs point by point, that is, calculating each frequency point according to formula (9): G = Sign( x ) ⋅ Sign( v (9) Among them, Sign( x ) represents the conjugate symbol of the frequency domain data obtained according to formula (6). v Sign represents the output of the last stage of the quadrant quantization fast Fourier transform. v ) =S (Re( v )) + j S (Im( v )) For formula (2) v The frequency domain sign information is obtained by taking the sign. Since the real and imaginary parts of the two factors mentioned above both take values ​​in {+1, -1}, their product can be completed by combinational logic such as sign bit XOR and addition / subtraction, without calling a complex multiplier.

[0104] For example, for a dual-polarization 2 × 2 multiple-input multiple-output structure, W xx , W xy , W yx and W yy The respective update directions can be constructed according to the same pairing relationship as the traditional frequency domain constant modulus algorithm equalization, that is: W xx and W xy The update direction is determined by the frequency domain data. X and Y conjugate symbol and x Constructing frequency domain symbol pairings corresponding to polarization branches; W yx and W yy The update direction is determined by the frequency domain data. X and Y conjugate symbol and y The frequency domain symbol information corresponding to the polarization branch is paired and constructed. The above pairing relationship is only an example. In actual implementation, other equivalent correspondences can be used, or further scaling, accumulation, or block averaging can be performed after constructing the update direction.

[0105] (III) Exemplary Implementation of the Update Step Size and Coefficient Effectiveness Method. In one exemplary implementation, the update step size in formula (7) μ You can take 2 as a negative integer power. μG This can be implemented using shifting and addition / subtraction, without requiring a multiplier. The "Coefficient Update" column in Table 2 uses the absence of real multipliers in the update path as the statistical boundary, and is statistically analyzed according to this implementation method. When the update step size takes other values, corresponding constant multiplication or its approximate implementation method can be used, and its impact on the complexity of the update path can be statistically analyzed separately according to the specific implementation method.

[0106] In one exemplary implementation, the updated frequency domain equalization coefficients can take effect from the next data block onwards, that is, the frequency domain equalization coefficients used remain unchanged during the processing of the same data block to avoid mixing old and new coefficients within the same data block; alternatively, the corresponding effective delay can be set according to the pipeline depth, as long as the update direction is aligned with the corresponding frequency domain input in timing.

[0107] (iv) Exemplary Implementation of Bit Width Regularization and Zero Value Processing. In one exemplary implementation, the bit width regularization of each stage of the quadrant quantization fast Fourier transform can employ any one or a combination of rounding, truncation, or saturation, and overflow protection can be set accordingly; the tap coefficient accumulator can be implemented in conjunction with limiting, leakage factor, or saturation strategies. For the processing in step 500 of retaining the previous valid sign for zero components, if there is no previous valid sign at the start of processing or after reset, the sign of the zero component can be a preset sign, such as +1.

[0108] The above-described exemplary implementations can be used individually or in any combination, and all belong to the implementation methods of this application.

[0109] It should be noted that in this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. In this application, if a reference is made to performing an action based on an element, it means performing the action at least based on that element, including two cases: performing the action only based on that element, and performing the action based on that element and other elements. Expressions such as "multiple," "repeatedly," and "various" include two, two times, two kinds, and more than two, more than two times, and more than two kinds.

[0110] It should be understood that after reading the above disclosure of this application, those skilled in the art can make various alterations or modifications to this application, and these equivalent forms also fall within the scope of protection claimed in this application.

Claims

1. A frequency-domain constant modulus equalization algorithm method, applied to a coherent receiving system, characterized in that, The method includes: For the frequency domain data of the coherent received signal, frequency domain equalization is performed based on the frequency domain equalization coefficient to obtain the frequency domain equalized output; Perform an inverse fast Fourier transform on the frequency domain equalized output to obtain the time domain output signal; Calculate the constant modulus algorithm error signal based on the time-domain output signal; In the tap coefficient update path, the sign of the time-domain output signal and the sign of the constant modulus algorithm error signal are extracted. The sign of the constant modulus algorithm error signal controls the sign of the time-domain output signal to perform polarity preservation or polarity reversal, so as to obtain the sign domain update amount represented by the sign direction. Perform quadrant quantization fast Fourier transform on the symbol domain update to obtain the frequency domain symbol information required for tap coefficient update. The quadrant quantization fast Fourier transform maps the rotation factor to a value in the set {1, -1, j, -j}, and the multiplication between the quantized rotation factor and the complex number is achieved by sign inversion and / or real-imaginary part exchange. An update direction is constructed based on the frequency domain symbol information, the frequency domain equalization coefficients are updated based on the update direction, and the updated frequency domain equalization coefficients are used for frequency domain equalization of subsequent frequency domain data. Specifically, the quadrant quantization fast Fourier transform is only set in the tap coefficient update path, while the frequency domain equalization and the inverse fast Fourier transform are not implemented in the main signal path.

2. The method according to claim 1, characterized in that, The quadrant-quantized fast Fourier transform maps the rotation factor to a quantized rotation factor according to the following quadrant-quantization operator: in, W Let arg(⋅) represent the twitch factor to be quantized, and let arg(⋅) represent the phase operator. Q (⋅) denotes the quadrant quantization operator; A two-bit control code selects the rotation operation corresponding to the quantization rotation factor. When the quantization rotation factor is +1, the input complex number is directly output; when the quantization rotation factor is -1, the real and imaginary parts of the input complex number are inverted; when the quantization rotation factor is +j, the real and imaginary parts of the input complex number are swapped, and the real part of the output after the swap is inverted; when the quantization rotation factor is -j, the real and imaginary parts of the input complex number are swapped, and the imaginary part of the output after the swap is inverted.

3. The method according to claim 2, characterized in that, The quadrant-quantized fast Fourier transform employs a radix-2 hierarchical butterfly structure, with a transformation point count of... N Powers of 2 N = 2 p The hierarchical butterfly structure includes p Level butterfly operation, the first s The length of the sub-block of level is m = 2 s ; The first in each sub-block t Each butterfly unit reads two input complex numbers. A and B According to the quantization rotation factor q s,t = Q ( W m t ) right B Perform quadrant rotation to obtain quantized rotated data. B q and output Y 0 = A + B q and Y 1 = A - B q ,in, W m t Indicates the first s The first sub-block within the level t Rotation factor corresponding to each butterfly position; The quantization rotation factors at each level are pre-written into the control table, or generated by a combination of level number and position within the group.

4. The method according to claim 1, characterized in that, The quadrant-quantized fast Fourier transform includes multiple butterfly operation stages; Each intermediate stage of the quadrant-quantized fast Fourier transform maintains a fixed bit width output and does not sign the intermediate stage output. The sign of the last stage output is taken only after the last stage output, and the resulting sign direction is used as the frequency domain sign information for tap coefficient update.

5. The method according to claim 1, characterized in that, The method further includes: in the tap coefficient update path, symbolizing the conjugate of the frequency domain data to obtain the conjugate symbol Sign( x ) = S (Re( x )) -j S (Im( x )); The update direction is constructed by the conjugate symbol and the frequency domain symbol information; in, x This represents the frequency domain data. x express x The conjugate of Re( x ) and Im( x ) represent respectively x The real and imaginary parts, S (⋅) is the sign function for real numbers. u , u > 0 o'clock S ( u ) = +1, u < 0 S ( u = -1.

6. The method according to claim 1, characterized in that, When the constant modulus algorithm error signal is zero, the update enable signal for this update is turned off, and the update of the frequency domain equalization coefficients is not performed. When the real or imaginary part of the data to be symbolized is zero, the symbol of the zero component retains the previous valid symbol.

7. The method according to claim 1, characterized in that, according to W new = W old + μG Update the frequency domain equalization coefficients; in, W old This represents the frequency domain equalization coefficients before the update. W new This represents the updated frequency domain equalization coefficients. μ Indicates the update step size. G This indicates the direction of the update.

8. The method according to claim 1, characterized in that, The frequency domain data includes frequency domain data in two polarization directions; The frequency domain equalization employs a dual-polarization 2 × 2 multiple-input multiple-output structure, and the frequency domain equalization coefficients include... W xx , W xy , W yx and W yy It is used to compensate for channel response and polarization crosstalk between two polarization directions.

9. A frequency domain constant modulus algorithm equalization device, characterized in that, It includes a frequency domain equalization module, an inverse fast Fourier transform module, an error calculation module, a symbol domain update module, a quadrant quantization fast Fourier transform module, and a coefficient update module; The frequency domain equalization module is used to perform frequency domain equalization on the frequency domain data of the coherent received signal based on the frequency domain equalization coefficients, to obtain the frequency domain equalization output, and to provide the frequency domain equalization output to the inverse fast Fourier transform module. The inverse fast Fourier transform module is used to perform an inverse fast Fourier transform on the frequency domain equalization output to obtain a time domain output signal, and provides the time domain output signal to the error calculation module and the symbol domain update module respectively. The error calculation module is used to calculate the constant modulus algorithm error signal based on the time domain output signal, and provide the constant modulus algorithm error signal to the symbol domain update module; The symbol field update module is used to extract the symbol of the time-domain output signal and the symbol of the constant modulus algorithm error signal in the tap coefficient update path. The symbol of the constant modulus algorithm error signal controls the polarity preservation or polarity reversal of the symbol of the time-domain output signal to obtain the symbol field update amount represented by the symbol direction, and provides the symbol field update amount to the quadrant quantization fast Fourier transform module. The quadrant quantization fast Fourier transform module is used to perform quadrant quantization fast Fourier transform on the symbol domain update quantity to obtain the frequency domain symbol information required for tap coefficient update, and to provide the frequency domain symbol information to the coefficient update module. The quadrant quantization fast Fourier transform maps the rotation factor to a value in the set {1, -1, j, -j}, and the multiplication between the quantized rotation factor and the complex number is achieved by sign inversion and / or real part and imaginary part exchange. The coefficient update module is used to construct an update direction based on the frequency domain symbol information, update the frequency domain equalization coefficients according to the update direction, and feed back the updated frequency domain equalization coefficients to the frequency domain equalization module for frequency domain equalization of subsequent frequency domain data. The quadrant quantization fast Fourier transform module is only set in the tap coefficient update path, while the main signal path containing the frequency domain equalization module and the inverse fast Fourier transform module does not use the quadrant quantization fast Fourier transform.

10. A coherent receiving system, characterized in that, It includes an analog-to-digital conversion module and the frequency domain constant modulus algorithm equalization device as described in claim 9; The analog-to-digital conversion module is used to perform analog-to-digital conversion on the coherent received signal to obtain a coherent received digital signal; The frequency domain constant modulus algorithm equalization device is used to perform real-time frequency domain constant modulus algorithm equalization processing on the frequency domain data obtained from the coherent received digital signal. The frequency domain constant modulus algorithm equalization device is deployed on a field-programmable gate array (FPGA).

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