Accelerated method and system for radio frequency testing

Abstract

The application provides an acceleration method and system for radio frequency test, comprising: receiving original radio frequency signals generated by a radio frequency test device measuring an object to be tested, and pre-processing the original radio frequency signals through an FPGA to obtain pre-processed radio frequency data; using the FPGA to packetize and data block the pre-processed radio frequency data to obtain a plurality of data blocks, and transmitting the data blocks to an IPC through a high-speed transmission interface asynchronously; using a plurality of working threads of the IPC to obtain the data blocks from a task queue and perform radio frequency parameter calculation in parallel, and dynamically adjusting task distribution of each working thread according to a load state of each working thread to obtain radio frequency parameter calculation results corresponding to each data block; integrating the calculation results corresponding to each data block, and performing test determination to obtain a test result of the object to be tested. The problems of low test efficiency caused by hardware resource bottleneck, lack of dynamic adjustment capability and poor resource utilization, and time waste caused by serial processing mechanism are solved.

Description

Technical Field

[0001] This invention relates to the field of automated testing technology, and more specifically to an accelerated method and system for radio frequency testing. Background Technology

[0002] With the rapid development of wireless communication technology, modern wireless communication devices have become widespread. As communication standards evolve from 4G to 5G and even the future 6G, radio frequency (RF) components need to support multi-band, multi-mode, and high-bandwidth transmission, leading to an exponential increase in the items and conditions for RF performance testing. Therefore, RF testing has become an indispensable and crucial step before mass production.

[0003] In existing Automatic Test Equipment (ATE) architectures, radio frequency (RF) testing typically relies on embedded processors or field-programmable gate arrays (FPGAs) within the test equipment for data processing. Traditional test procedures require individual measurements and calibrations for different frequency bands, power levels, and modulation modes. During testing, the test instruments repeatedly switch test parameters and wait for signal settling time. Coupled with communication delays between instruments and control process overhead, the test time for a single device is significantly extended. Specifically, in existing technologies, RF test data processing is mainly concentrated on real-time computation on the on-board FPGA of the test equipment. With the increase in test sampling rates and the rapid growth in data volume, the logic operation resources and memory bandwidth within the FPGA are gradually becoming system bottlenecks.

[0004] Faced with large-scale mass production and complex testing standards, existing technologies still have certain limitations. Specifically, firstly, hardware resource bottlenecks lead to low testing efficiency. In traditional centralized processing architectures, on-board FPGAs must simultaneously handle data acquisition, format conversion, and complex RF parameter calculations (such as Fast Fourier Transform (FFT), demodulation, etc.). When the number of test items increases, the FPGA's computing resources and memory bandwidth are easily saturated, data processing delays accumulate, and the high-speed RF data cannot be processed in a timely manner, severely limiting production line throughput. Secondly, there is a lack of dynamic adjustment capabilities and poor resource utilization. Current RF testing processes mostly use fixed test sequences and cannot be adaptively adjusted according to the characteristics of the Device Under Test (DUT). Even high-yield products still need to perform complete test items, and cannot be dynamically reduced, resulting in wasted time. Furthermore, because the computing tasks are locked on the FPGA, external industrial personal computers (IPCs) cannot be used. The powerful multi-core parallel computing capabilities of IPC lead to uneven distribution of overall hardware resources in the test system and low utilization of test resources. Thirdly, the time wasted by the serial processing mechanism. Existing architectures mostly adopt serial or semi-serial processing modes, which require waiting for the previous step to be completely completed before the next step can be performed. This results in the data acquisition, transmission and computing processes not being effectively overlapped, generating a large amount of idle waiting time. In the mass production stage, these small delays will directly translate into huge manufacturing costs, becoming a major bottleneck restricting production efficiency.

[0005] Therefore, how to overcome the limitations of FPGA hardware resources while ensuring test accuracy and quality, and reduce RF test time, simplify test procedures, and improve the overall throughput of the test system by optimizing the data processing architecture, has become an important technical issue that urgently needs to be addressed in this field. Summary of the Invention

[0006] The present invention provides an acceleration method and system for radio frequency testing, which at least solves the problems of low testing efficiency caused by hardware resource bottlenecks, lack of dynamic adjustment capability and poor resource utilization, and time waste caused by serial processing mechanism.

[0007] According to one aspect of the present invention, an acceleration method for radio frequency testing is provided, comprising:

[0008] The system receives raw radio frequency data generated by the radio frequency test equipment measuring the device under test, and preprocesses it through a field-programmable gate array (FPGA) to obtain preprocessed radio frequency data.

[0009] The preprocessed radio frequency data is encapsulated and segmented using the FPGA to obtain multiple data blocks, which are then asynchronously transmitted to an industrial computer IPC via a high-speed transmission interface.

[0010] Multiple data blocks are written into a task queue. Multiple worker threads of the IPC retrieve data blocks from the task queue and perform RF parameter calculations in parallel. The task allocation of each worker thread is dynamically adjusted according to the load status of each worker thread to obtain the RF parameter calculation results corresponding to each data block. The asynchronous transmission and the parallel calculation are at least partially overlapped in a pipelined manner.

[0011] The calculation results corresponding to each data block are compiled and tested to obtain the test results of the object under test.

[0012] As an optional solution, the receiving RF test equipment measures the raw RF data generated by the device under test, and preprocesses it through an FPGA to obtain preprocessed RF data, including:

[0013] Configure test parameters and start the RF test program. Measure the device under test using the RF test equipment to generate raw RF data; wherein, the raw RF data is an I / Q data stream.

[0014] The raw radio frequency data is captured in real time using the FPGA.

[0015] The original radio frequency data after real-time data acquisition is subjected to digital down-conversion processing to reduce the high-frequency signal of the original radio frequency data to the base frequency, thereby obtaining the base frequency data.

[0016] The baseband data is resampled and time-aligned to unify the sampling rate of multi-channel data, and a timestamp is added to the baseband data.

[0017] The baseband data after being marked with a timestamp is filtered to eliminate out-of-band noise, resulting in preprocessed radio frequency data.

[0018] As an optional solution, the preprocessed radio frequency data is packetized and segmented using the FPGA to obtain multiple data blocks, and then asynchronously transmitted to the IPC via a high-speed transmission interface, including:

[0019] The preprocessed radio frequency data is encapsulated to obtain encapsulated data;

[0020] Based on the bandwidth of the high-speed transmission interface and the cache memory capacity of the IPC, the packet data is dynamically segmented to obtain multiple data blocks;

[0021] Multiple data blocks are asynchronously transmitted to the IPC via the high-speed transmission interface.

[0022] As an optional solution, in the process of asynchronously transmitting multiple data blocks to the IPC via a high-speed transmission interface, a ping-pong buffer architecture is adopted, including:

[0023] The system memory of the IPC is configured with an independent first buffer and a second buffer.

[0024] When the FPGA writes the first data block into the first buffer through the high-speed transmission interface, the IPC asynchronously reads and processes the second data block that has been stored in the second buffer; wherein, the high-speed transmission interface uses Direct Memory Access (DMA) technology for data transmission.

[0025] As an optional approach, multiple data blocks are written into a task queue, and multiple worker threads of the IPC retrieve data blocks from the task queue and perform RF parameter calculations in parallel. The task allocation of each worker thread is dynamically adjusted according to its load status to obtain the RF parameter calculation results corresponding to each data block, including:

[0026] The main control thread of the IPC monitors the high-speed transmission interface, encapsulates the received multiple data blocks into computing tasks, and writes them sequentially into the task queue.

[0027] The IPC uses multiple worker threads to obtain the computation tasks from the task queue in a mutually exclusive manner, and each worker thread performs radio frequency parameter calculations independently after unlocking.

[0028] The task allocation of each working thread is dynamically adjusted according to its load status to obtain the RF parameter calculation results corresponding to each data block.

[0029] As an optional approach, the step of dynamically adjusting the task allocation of each worker thread based on its load status, employing a work-stealing algorithm, includes:

[0030] Real-time monitoring of CPU core utilization and task queue length of each worker thread;

[0031] When the first worker thread completes its computation task and becomes idle, it actively steals unprocessed computation tasks from the task queue of the second worker thread and performs the computation, thereby achieving dynamic load balancing among the worker threads.

[0032] As an optional approach, the calculation results of the radio frequency parameters corresponding to each data block are aggregated and tested to obtain the test results of the device under test, including:

[0033] Receive and aggregate the RF parameter calculation results output by all working threads;

[0034] The results of the radio frequency parameter calculations are sorted and integrated based on the timestamp or sequence number of the data block.

[0035] The integrated RF parameter calculation results are used for RF parameter testing and system performance evaluation to determine whether the test object is qualified.

[0036] According to another aspect of the present invention, an acceleration system for radio frequency testing is also provided, comprising:

[0037] Radio frequency (RF) test equipment is used to measure the raw RF data generated by the device under test.

[0038] An FPGA, connected to the radio frequency test equipment, is used to receive the raw radio frequency data and preprocess it to obtain preprocessed radio frequency data; and to encapsulate and block the preprocessed radio frequency data to obtain multiple data blocks.

[0039] A high-speed transmission module, connected to the FPGA, is used to asynchronously transmit multiple data blocks;

[0040] An IPC, connected to the high-speed transmission module, is used to receive the data blocks; write multiple data blocks into a task queue; utilize multiple worker threads of the IPC to retrieve data blocks from the task queue and perform RF parameter calculations in parallel; dynamically adjust the task allocation of each worker thread according to its load status to obtain the RF parameter calculation results corresponding to each data block; wherein the asynchronous transmission and the parallel calculation are performed in a pipelined manner with at least partial overlap; and aggregate the RF parameter calculation results corresponding to each data block, perform test judgment, and obtain the test results of the device under test.

[0041] As an optional solution, the IPC includes:

[0042] The receiving module includes a main control thread for receiving multiple data blocks and establishing a task queue;

[0043] The worker thread pool includes multiple worker threads, which are used to retrieve the data blocks from the task queue and perform radio frequency parameter calculations in parallel to obtain the radio frequency parameter calculation results of each data block;

[0044] The dynamic load balancing module is used to dynamically adjust the task allocation of each worker thread according to the load status of each worker thread.

[0045] The result aggregation module is used to receive the RF parameter calculation results of each working thread, aggregate and test the results to obtain the test results of the device under test.

[0046] As an optional solution, the core memory of the IPC is configured with an independent first buffer and a second buffer, forming a ping-pong buffer architecture; when the FPGA writes the first data block into the first buffer through the high-speed transmission module, the IPC asynchronously reads and processes the second data block that has been stored in the second buffer.

[0047] As an optional approach, the task queue is used for mutual exclusion locking and condition variable notification; the multiple worker threads obtain computing tasks from the task queue in a mutual exclusion manner, and perform computing independently after unlocking.

[0048] As an optional solution, the dynamic load balancing module is configured with a job stealing algorithm to monitor the core utilization of each central processing unit (CPU) and the task queue length of each worker thread in real time; when the first worker thread completes its computing task and is idle, it actively steals unprocessed computing tasks from the task queue of the second worker thread for computing, thereby achieving dynamic load balancing among the worker threads.

[0049] As an optional solution, the high-speed transmission module includes a PCIe interface and an Ethernet interface, and uses direct memory access technology for data transmission.

[0050] As an optional solution, the IPC connects multiple computing nodes to form a distributed computing architecture; wherein, the computing nodes include servers and graphics processors.

[0051] According to another aspect of the present invention, an electronic device is also provided, characterized in that the electronic device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the method described above.

[0052] According to another aspect of the present invention, a computer-readable storage medium is also provided, the computer-readable storage medium storing a computer program, characterized in that the computer program, when executed by a processor, implements the method described above.

[0053] The beneficial effects of this invention are as follows:

[0054] 1. This invention effectively overcomes the resource bottleneck of single hardware by using a heterogeneous collaborative processing architecture of FPGA and IPC. The FPGA performs real-time preprocessing on the raw RF data, including digital down-conversion, resampling, time alignment, and basic filtering, completing signal conditioning at the data source. The preprocessed RF data is then packetized and segmented via a high-speed transmission interface and asynchronously transmitted to the IPC. Multiple threads on the IPC perform computationally intensive RF parameter calculations in parallel, such as fast Fourier transform spectrum analysis, error vector amplitude calculation, and adjacent channel leakage ratio calculation. This achieves a layered processing mode of "real-time preprocessing at the front end + parallel acceleration of general-purpose computing at the back end," effectively avoiding the accumulation of data processing delays caused by single-point overload of the FPGA.

[0055] 2. This invention solves the problem of poor resource utilization of multi-core processors by introducing a dynamic allocation mechanism based on task queues and load monitoring. Multiple data blocks are written to the task queue, and multiple worker threads of the IPC retrieve data blocks from the task queue and perform RF parameter calculations in parallel. Task allocation is dynamically adjusted based on the real-time load status of each worker thread, automatically balancing the load. This overcomes the uneven allocation problem caused by differences in task complexity in traditional static allocation, ensuring that the IPC's multi-core CPU resources maintain a high load during test runs, thereby maximizing hardware resource utilization.

[0056] 3. This invention eliminates the time waste caused by traditional serial processing through a full-link pipelined parallel processing and asynchronous transmission mechanism. Utilizing high-speed asynchronous transmission between the FPGA and IPC, coupled with a ping-pong buffer architecture, it achieves pipelined overlap between data transmission and data computation. That is, while the FPGA writes the current data block to the first buffer, the IPC simultaneously computes the RF parameters of the previous data block stored in the second buffer, ensuring that data writing and reading do not block each other. In this way, the traditional "fetch, wait, transmit, compute, output" serial mode is transformed into a "fetch, transmit, compute simultaneously" parallel mode, effectively eliminating hardware interrupt waiting time and system idle time. Attached Figure Description

[0057] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of the present invention, and those skilled in the art can obtain other embodiments based on these drawings without creative effort.

[0058] Figure 1 This is a flowchart of an embodiment of the invention.

[0059] Figure 2This is a schematic diagram of the system structure of an embodiment of the present invention.

[0060] Figure 3 This is a schematic diagram of the structure of the electronic device created by this invention. Detailed Implementation

[0061] Embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. While some embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present invention. It should be understood that the drawings and embodiments of the present invention are for illustrative purposes only and are not intended to limit the scope of protection of the present invention.

[0062] Example 1

[0063] Figure 1 The diagram illustrates an acceleration method for radio frequency (RF) testing, comprising:

[0064] Step S11: Receive the raw radio frequency data generated by the radio frequency test equipment measuring the device under test, and preprocess it through the field programmable gate array (FPGA) to obtain preprocessed radio frequency data.

[0065] The aforementioned programmable gate array (FPGA) is a reprogrammable semiconductor device that includes configurable logic blocks (CLBs) and programmable interconnect resources, enabling hardware-level parallel acceleration for specific data processing tasks. In this invention, the FPGA serves as a front-end data acquisition and preprocessing unit, responsible for real-time acquisition and signal conditioning of high-speed raw RF data output from the RF test equipment.

[0066] By leveraging the hardware parallel processing capabilities and deterministic low-latency characteristics of FPGAs, high-real-time preprocessing operations such as digital downconversion (DDC), resampling and time alignment, and FIR basic filtering are completed at the data source. Only the preprocessed data is transmitted to the back end, avoiding bus bandwidth congestion and processor interrupt overhead caused by the original high-speed data stream directly flooding into the back-end IPC. This effectively reduces the data processing pressure and I / O bottleneck of the back-end system.

[0067] Step S12: The preprocessed radio frequency data is packaged and divided into data blocks using the FPGA to obtain multiple data blocks, which are then asynchronously transmitted to the industrial computer IPC through a high-speed transmission interface.

[0068] The aforementioned data block refers to an independent data unit formed by cutting the pre-processed continuous radio frequency data stream according to preset rules. In this embodiment, the size of the data block is dynamically determined based on the available bandwidth of the high-speed transmission interface and the cache capacity of the IPC, so as to achieve an optimal balance between transmission efficiency and processing granularity.

[0069] The aforementioned high-speed transmission interface refers to the physical layer and data link layer path connecting the FPGA and IPC, used to achieve high-throughput, low-latency migration of pre-processed RF data from the FPGA to the IPC. In this embodiment, the high-speed transmission interface includes, but is not limited to, PCIe interface and Ethernet interface.

[0070] The aforementioned asynchronous transmission refers to a communication method in which data transmission operations and data processing operations are decoupled in time and do not block each other. In this embodiment, the process of the FPGA transmitting data blocks to the IPC through a high-speed transmission interface can continue without waiting for the IPC to complete the processing of the previous batch of data; the IPC also does not need to wait for all data transmissions to be completed before it can begin processing the arrived data blocks. The specific implementation of this asynchronous mechanism includes the use of direct memory access (DMA) technology and a ping-pong buffer architecture.

[0071] The aforementioned industrial computer (IPC) refers to a general-purpose computing platform with a multi-core processor and support for multi-threaded computing capabilities. In this embodiment, the IPC serves as the backend data processing and computing core, responsible for receiving multiple data blocks from the FPGA, performing RF parameter calculations in parallel through multiple working threads, and aggregating the calculation results for testing and judgment.

[0072] By employing a heterogeneous collaborative processing architecture of FPGA and IPC, the resource bottleneck of single hardware is effectively overcome. The FPGA performs real-time preprocessing on the raw RF data, including digital down-conversion, resampling, time alignment, and basic filtering, completing signal conditioning at the data source. The preprocessed RF data is then packetized and segmented via a high-speed transmission interface and asynchronously transmitted to the IPC. Multiple threads on the IPC perform parallel RF parameter calculations, achieving a layered processing mode of "real-time preprocessing at the front end + parallel acceleration of general-purpose computing at the back end." This effectively avoids the cumulative data processing delay caused by single-point overload of the FPGA.

[0073] Step S13: Write multiple data blocks into the task queue, use multiple worker threads of IPC to retrieve data blocks from the task queue and perform RF parameter calculations in parallel, and dynamically adjust the task allocation of each worker thread according to the load status of each worker thread to obtain the RF parameter calculation results corresponding to each data block; wherein, asynchronous transmission and parallel calculation are performed in a pipelined manner with at least partial overlap.

[0074] The aforementioned worker thread refers to a lightweight execution unit created at the IPC operating system level that can be independently scheduled to execute on different central processing unit cores. In this invention, the IPC starts multiple worker threads, each of which retrieves data blocks from the task queue and independently performs radio frequency parameter calculations, thereby achieving parallel processing of multiple data blocks.

[0075] The aforementioned pipelined approach refers to dividing the data processing flow into multiple stages, each executed by a different processing unit, with the execution of each stage overlapping in time. That is, while one stage is not yet fully completed, the next stage has already begun processing the completed data. In this embodiment, data acquisition and preprocessing on the FPGA side constitute the first stage of the pipeline, high-speed asynchronous transmission constitutes the second stage, and multi-threaded parallel computation on the IPC side constitutes the third stage. These three stages overlap at least partially.

[0076] By introducing a dynamic allocation mechanism based on task queues and load monitoring, the problem of poor resource utilization in multi-core processors is solved. Multiple data blocks are written to the task queue, and multiple worker threads of the IPC retrieve data blocks from the task queue and perform RF parameter calculations in parallel. Task allocation is dynamically adjusted based on the real-time load status of each worker thread, automatically balancing the load and overcoming the uneven allocation problem caused by differences in task complexity in traditional static allocation. This ensures that the IPC's multi-core CPU resources maintain a high load during test runs, thereby maximizing hardware resource utilization. Furthermore, the time wastage caused by traditional serial processing is eliminated through a full-link pipelined parallel processing and asynchronous transmission mechanism. Utilizing high-speed asynchronous transmission between the FPGA and IPC, combined with a ping-pong buffer architecture, pipelined overlap of data transmission and data computation is achieved—that is, while the FPGA writes the current data block to the first buffer, the IPC simultaneously calculates the RF parameters of the previous data block stored in the second buffer, ensuring that data writing and reading do not block each other. This transforms the traditional serial mode of "fetch, wait, transmit, calculate, output" into a parallel mode of "fetch, transmit, and calculate simultaneously," effectively eliminating hardware interrupt waiting time and system idle time.

[0077] Step S14: Compile the calculation results corresponding to each data block, perform test judgment, and obtain the test results of the object to be tested.

[0078] The execution entity of the above steps can be an integrated automated test equipment (ATE) that combines RF test equipment, FPGA, and industrial computer (IPC), suitable for standardized production line testing scenarios; it can also be a separate deployment of FPGA and IPC, where the FPGA is set on the RF test equipment side as a data acquisition front end, and the IPC is set on the local server or test management platform side, with the two connected remotely through a high-speed transmission interface to support a distributed test architecture; it can be a distributed computing cluster composed of multiple computing nodes to further improve data processing capabilities in large-scale parallel testing scenarios; or it can be a computing device deployed on edge computing nodes, or some computing tasks deployed on a cloud computing platform, achieving elastic scaling of computing resources through a virtualized resource pool. This invention does not limit a single physical entity or specific hardware form. Any computing device capable of implementing the business processing logic of this method—including but not limited to integrated automated test equipment, separately deployed FPGA and industrial computer combinations, multi-node distributed computing clusters, edge computing devices, or cloud servers—can be the execution entity of this invention and all fall within the scope of protection of this invention.

[0079] Specifically, in step S11, the raw radio frequency data generated by the radio frequency test equipment measuring the device under test is received, and preprocessed by the FPGA to obtain preprocessed radio frequency data, including:

[0080] Step S111: Configure test parameters and start the RF test program. Measure the device under test using the RF test equipment to generate raw RF data.

[0081] In this embodiment, the original radio frequency data is an I / Q data stream; where I represents in-phase and Q represents quadrature.

[0082] Step S112: Real-time data acquisition of raw radio frequency data is performed using FPGA.

[0083] Step S113: Perform digital downconversion processing on the raw radio frequency data after real-time data acquisition to reduce the high-frequency signal of the raw radio frequency data to the base frequency to obtain base frequency data.

[0084] Step S114: Resample and time-align the baseband data to unify the sampling rate of multi-channel data and mark the baseband data with timestamps.

[0085] In this embodiment, multi-channel data refers to raw radio frequency (RF) data acquired by multiple measurement modules from different test channels or test points. Specifically, multiple measurement modules include, but are not limited to, multiple RF signal receiving modules operating in parallel, multiple frequency band measurement modules, or multiple signal acquisition channels. By performing unified resampling and time alignment processing on the multi-channel data, time deviations between different measurement modules can be eliminated, ensuring the accuracy of subsequent data fusion and calculation.

[0086] Step S115: Filter the baseband data after marking the timestamp to eliminate out-of-band noise and obtain preprocessed radio frequency data.

[0087] In this embodiment, the format of the preprocessed radio frequency data is Float32 or Int16.

[0088] Specifically, in step S12, the preprocessed RF data is packetized and segmented using the FPGA to obtain multiple data blocks, which are then asynchronously transmitted to the IPC via a high-speed transmission interface, including:

[0089] Step S121: Encapsulate the preprocessed radio frequency data to obtain encapsulated data.

[0090] Step S122: Based on the bandwidth of the high-speed transmission interface and the cache memory capacity of the IPC, the packet data is dynamically segmented to obtain multiple data blocks.

[0091] In a preferred embodiment, taking a 5G 100MHz broadband scenario as an example, the original radio frequency data sampling rate is configured as 122.88MPs; the data segmentation rules are dynamically adapted and adjusted according to the bandwidth of the high-speed transmission interface and the cache memory capacity of the IPC. Based on a 1-millisecond subframe duration or a fixed byte length of 4MB~16MB, the packet data is segmented to generate multiple independent data chunks for asynchronous transmission of subsequent data chunks.

[0092] Step S123: Asynchronously transmit multiple data blocks to IPC through the high-speed transmission interface.

[0093] In this embodiment, during the asynchronous transmission of multiple data blocks to the IPC by the high-speed transmission interface, a ping-pong buffer architecture is adopted. This ping-pong buffer architecture, combined with DMA technology, decouples data transmission from CPU computation, enabling parallel processing of data writing and reading, achieving a pipelined effect. The ping-pong buffer architecture includes:

[0094] Step S1231: Configure independent first buffer and second buffer in the system memory of IPC.

[0095] In this embodiment, the sizes of the first buffer and the second buffer are configured according to the size of the data block. Specifically, the first buffer and the second buffer are each configured with a storage space no smaller than the size of the data block to ensure that a single data block can be completely written into a single buffer.

[0096] In step S1232, when the FPGA writes the first data block into the first buffer through the high-speed transmission interface, the IPC asynchronously reads and processes the second data block that has been stored in the second buffer.

[0097] In this embodiment, the high-speed transmission interface utilizes Direct Memory Access (DMA) technology for data transmission. Specifically, the FPGA directly writes data blocks into the buffer of the IPC system memory via the DMA engine, eliminating the need for CPU intervention in the data transmission process and thus decoupling data transmission from CPU computation.

[0098] In this embodiment, the asynchronous transmission between the FPGA and IPC is built based on a master thread-worker thread model, and uses an asynchronous pipelined RF data processing algorithm for system initialization, master thread processing flow, and worker thread processing flow. System initialization includes:

[0099] Step S12411: Configure a circular buffer pool and divide the circular buffer pool into multiple buffers; wherein the size of each buffer is determined by the size of the data block.

[0100] Step S12412: Initialize the task queue, mutex lock, first condition variable, and second condition variable.

[0101] Specifically, the mutex lock is used to ensure mutual exclusion access to the task queue in a multi-threaded environment; the first condition variable is used to put the worker thread into an idle state when the task queue is empty and to wake it up when the task queue is not empty; the second condition variable is used to put the main thread into an idle state when the task queue is full and to wake it up when the task queue is not full.

[0102] Step S12413: Start multiple worker threads, each worker thread enters a listening state, and waits for unprocessed computation tasks to appear in the task queue.

[0103] The main control thread processing flow includes:

[0104] Step S12421: Listen for the DMA interrupt signal from the high-speed transfer interface.

[0105] Specifically, when the FPGA writes the data block completely into the first buffer using the DMA engine, it generates an asynchronous interrupt signal.

[0106] Step S12422: Based on the DMA interrupt signal, encapsulate the memory index of the buffer where data writing has been completed and the corresponding timestamp into a computation task.

[0107] Step S12423: Acquire the mutex lock. If the task queue is full, wait for notification from the second condition variable; if the task queue is not full, push the computation task to the tail of the task queue.

[0108] Step S12424: Release the mutex lock and trigger the notification of the first condition variable to wake up the idle worker thread.

[0109] Step S12425: Switch the buffer index so that the FPGA writes the next data block into the second buffer, thus enabling continuous data transmission.

[0110] The worker thread processing flow includes:

[0111] Step S12431: Acquire the mutex lock. If the task queue is empty, wait for notification from the first condition variable; if the task queue is not empty, pop the computation task from the head of the task queue.

[0112] Step S12432: Release the mutex lock and trigger the notification of the second condition variable to wake up the main control thread that is in an idle state.

[0113] Step S12433: Based on the memory indicators in the computation task, directly access the corresponding buffer and perform radio frequency parameter calculations on the computation task in the buffer.

[0114] Step S12434: Write the RF parameter calculation results into an independent array and the storage area corresponding to the current working thread to avoid concurrency conflicts caused by multiple working threads writing to the same storage area at the same time.

[0115] Based on the master thread-worker thread model, the asynchronous transmission of the FPGA and the parallel operation of the IPC form a full-link pipelined parallel processing, so that data acquisition, data transmission and data operation are at least partially overlapped, thereby eliminating hardware interruption waiting time and system idle time as a whole.

[0116] Specifically, in step S13, multiple data blocks are written to a task queue. Multiple worker threads of the IPC retrieve data blocks from the task queue and perform RF parameter calculations in parallel. The task allocation of each worker thread is dynamically adjusted based on its load status to obtain the RF parameter calculation results corresponding to each data block, including:

[0117] Step S131: Use the main control thread of IPC to listen to the high-speed transmission interface, encapsulate the received multiple data blocks into computing tasks, and write them into the task queue in sequence.

[0118] Step S132: Using multiple worker threads of IPC, computation tasks are obtained from the task queue in a mutually exclusive manner, and after unlocking, each worker thread independently performs radio frequency parameter calculations.

[0119] In this embodiment, the algorithms for calculating radio frequency parameters include, but are not limited to, fast Fourier transform spectrum analysis, demodulation transformation, and root mean square power calculation.

[0120] In a preferred embodiment, the computational tasks executed by multiple worker threads can be divided according to test items. For example, a first worker thread can perform error vector magnitude (EVM) calculation, and a second worker thread can perform adjacent channel leakage ratio (ACLR) calculation. This allows each worker thread to perform the computation of the test item it is responsible for for the same data block, and the computation of different test items can be processed in parallel by different worker threads. Alternatively, the tasks can be divided according to time blocks. That is, multiple data blocks are ordered according to time sequence, and each worker thread performs RF parameter calculations on the computational tasks of different data blocks, thereby achieving parallel processing at the time-time dimension.

[0121] It should be noted that computational tasks executed by multiple worker threads can also adopt a hybrid partitioning method, that is, first dividing the task according to time blocks, and then further subdividing it according to test item dimensions. In practical applications, the appropriate method can be flexibly selected based on actual test requirements, the number of processor cores, and the size of data blocks.

[0122] By using different partitioning mechanisms, computational tasks can be flexibly assigned and processed in parallel among multiple worker threads, enabling each worker thread to independently and simultaneously perform computations on its assigned data blocks or test items. This effectively shortens the total computation time for all data and significantly improves test throughput.

[0123] Step S133: Dynamically adjust the task allocation of each working thread according to the load status of each working thread to obtain the RF parameter calculation results corresponding to each data block.

[0124] In this embodiment, the task allocation of each worker thread is dynamically adjusted according to its load status, employing a work-stealing algorithm, including:

[0125] Step S1331: Monitor the core utilization of each central processing unit CPU and the task queue length of each worker thread in real time.

[0126] Specifically, IPC is used to collect the utilization rate of each CPU core and the number of pending computing tasks in the task queue corresponding to each worker thread in real time.

[0127] It should be noted that the monitoring data acquired by IPC can be updated according to a preset period or triggered by changes in the task queue status.

[0128] Step S1332: When the first worker thread completes its computation task and becomes idle, it actively steals unprocessed computation tasks from the task queue of the second worker thread for computation, thereby achieving dynamic load balancing among the worker threads.

[0129] Specifically, if the task queue of the first worker thread is empty and the CPU core utilization rate bound to the first worker thread is lower than a preset threshold, the first worker thread is determined to be in an idle state.

[0130] When the first worker thread is idle, it steals at least one unprocessed computation task from the tail of the second worker thread's task queue and adds the stolen computation task to the tail of the first worker thread's task queue. This avoids concurrency conflicts with the second worker thread's normal acquisition of computation tasks from the head, and reduces the impact on the normal working process of the second worker thread.

[0131] It should be noted that when using the work-stealing algorithm to steal computational tasks, a strategy of stealing one task at a time can be adopted to maintain fine-grained task allocation and timely load balancing; alternatively, a strategy of stealing multiple tasks at once can be used to reduce the frequency and overhead of stealing operations between worker threads. The strategy of stealing multiple tasks at once is suitable for test projects with relatively small computational loads. In practical applications, the task-stealing strategy can be determined by comparing the task queue length with a first preset task queue length threshold; and the number of tasks to be stolen can be determined by comparing the task queue length with a second preset task queue length threshold.

[0132] Furthermore, when any worker thread performs a stealing operation, due to the mutex locking mechanism of the task queue, only one worker thread can read, pop, or steal from the task queue at any given time. Specifically, when any worker thread operates on the task queue, it acquires the mutex lock, releases the mutex lock after completing the operation, and only then can other worker threads perform operations. This ensures data consistency and security of the task queue in a multi-threaded environment.

[0133] In this embodiment, the work-stealing algorithm continues to run until all computational tasks in the task queue have been processed and each worker thread has completed its assigned computational task. Then, it sends a completion signal to the main control thread of the IPC so as to facilitate the aggregation of radio frequency parameter calculation results.

[0134] In this embodiment, asynchronous transmission and parallel computation are performed in a pipelined manner, at least partially overlapping.

[0135] Specifically, in step S14, the calculation results of the radio frequency parameters corresponding to each data block are aggregated and tested to obtain the test results of the device under test, including:

[0136] Step S141: Receive and aggregate the RF parameter calculation results output by all working threads.

[0137] In this embodiment, the RF parameter calculation results include Error Vector Magnitude (EVM), Adjacent Channel Leakage Ratio (ACLR), and Output Power. It should be noted that when the data block contains receive test data, the RF parameter calculation results also include receive sensitivity.

[0138] Step S142: Sort and integrate the RF parameter calculation results according to the timestamp of the data block mark or the data block sequence number.

[0139] By sorting and integrating the RF parameter calculation results through timestamps or data block sequence numbers, different computational tasks processed by different work threads can be processed to ensure that the RF parameter calculation results are recombined in the correct timing sequence, thereby ensuring the accuracy of test judgment.

[0140] Step S143: Perform RF parameter testing and system performance evaluation on the integrated RF parameter calculation results to determine whether the device under test is qualified.

[0141] In this embodiment, the RF parameter test determination is based on the upper and lower limits specified in international standards, judging whether the calculation results of each RF parameter meet the specification requirements. If all RF parameter calculation results fall within the corresponding upper and lower limits of the specification, the current device under test is determined to be qualified; if any RF parameter calculation result does not fall within the corresponding upper and lower limits of the specification, the current device under test is determined to be unqualified. These international standards include, but are not limited to, 3GPP, Bluetooth SIG, and IEEE 802.11.

[0142] In this embodiment, system performance evaluation includes total test time, production line throughput (UPH), hardware resource utilization, and system latency. Specifically, production line throughput is the number of chips that can be tested per hour, used to measure the production efficiency of the test system; hardware resource utilization includes the percentage decrease in FPGA logic gate utilization and the optimization of IPC CPU utilization, used to measure the optimization effect of hardware resources; system latency is the end-to-end latency from real-time acquisition of data blocks to the output RF parameter results, used to measure the real-time performance of the test system.

[0143] Example 2

[0144] In this embodiment, an acceleration method for radio frequency testing is provided to verify the effectiveness of the method of the present invention in multiple scenarios.

[0145] A traditional RF test architecture was used as a control group for comparative experiments. Specifically, the control group's test architecture was configured as a traditional on-board FPGA centralized processing architecture, and the test items were set to include Bluetooth Low Energy (BLE) and Basic Rate (BR) comprehensive Bluetooth tests. Under this configuration, RF test data was centrally processed and computed in real time on the on-board FPGA, with no data blocks and no IPC worker threads configured, i.e., the number of worker threads was 0, and only FPGA processing was performed.

[0146] Comparative experiments were conducted on embodiments of the method of the present invention under different configurations, specifically including:

[0147] Configuration 1 uses a heterogeneous collaborative processing architecture of FPGA and IPC, and the test items are set to include comprehensive Bluetooth testing of BLE and BR. In this configuration, the size of each data block is set to 4MB, and the number of IPC worker threads is set to 4.

[0148] Configuration two employs a heterogeneous collaborative processing architecture of FPGA and IPC, with test items including comprehensive Bluetooth testing of both BLE and BR. In this configuration, each data block size is set to 8MB, and the number of IPC worker threads is configured to 8.

[0149] Configuration three employs a heterogeneous collaborative processing architecture of FPGA and IPC, with a test item set to 5GNR 100MHz bandwidth testing to verify the acceleration effect of the method in this invention under large data volume testing scenarios. In this configuration, each data block size is set to 16MB, and the number of IPC worker threads is configured to 16.

[0150] Under each of the above test architectures, the total test time, production line throughput, FPGA load, and IPC CPU load were recorded respectively, and the results are shown in Table 1.

[0151] Table 1 System performance evaluation results under different test architecture configurations

[0152] As shown in Table 1, compared with the control group, the total test time of Configuration 1 was shortened by 25.1%, the production line throughput increased by 33.5%, the FPGA load decreased from 95% to 30%, and the IPC CPU load increased from 5% to 65%. This indicates that the method of the present invention effectively breaks through the FPGA hardware resource bottleneck by offloading the computing tasks from the FPGA to the IPC for multi-threaded parallel processing. The total test time of Configuration 2 was shortened by 44.5%, the production line throughput increased by 80.3%, the FPGA load remained at 30%, and the IPC CPU load increased to 85%. This indicates that increasing the data block size and the number of working threads can improve the system's parallel processing capability and overall production line throughput. The total test time of Configuration 3 was 14.50 seconds, the production line throughput was 248 units, the FPGA load was 40%, and the IPC CPU load was 92%. This indicates that the method of the present invention also has a significant acceleration effect in large-scale data testing scenarios and can effectively cope with the data processing challenges brought about by 5G high-bandwidth testing.

[0153] Based on the above experimental results, this invention, through a heterogeneous collaborative processing architecture of FPGA and IPC, combined with a dynamic load balancing mechanism and asynchronous pipelined transmission processing, significantly reduces testing time, increases production line throughput, and optimizes hardware resource utilization in both Bluetooth comprehensive testing and 5G NR high-bandwidth testing scenarios. Furthermore, the acceleration effect further improves with increasing data block size and the number of worker threads. Compared with existing technologies, this invention effectively solves the problems of low testing efficiency caused by hardware resource bottlenecks, lack of dynamic adjustment capabilities and poor resource utilization, and time waste caused by serial processing mechanisms, while ensuring testing accuracy and quality. It has significant industrial application value.

[0154] Example 3

[0155] Based on the same design concept, such as Figure 2 As shown, this embodiment provides an acceleration system for radio frequency testing, including:

[0156] Radio frequency (RF) test equipment is used to measure the raw RF data generated by the device under test (DUT).

[0157] An FPGA is connected to RF test equipment to receive raw RF data and preprocess it to obtain preprocessed RF data; and to encapsulate and block the preprocessed RF data to obtain multiple data blocks.

[0158] The high-speed transmission module, connected to the FPGA, is used to asynchronously transmit multiple data blocks.

[0159] In this embodiment, the high-speed transmission module includes a PCIe interface and an Ethernet interface, and uses direct memory access technology for data transmission.

[0160] The IPC connects to the high-speed transmission module and is used to receive data blocks. Multiple data blocks are written to a task queue. Multiple worker threads of the IPC retrieve data blocks from the task queue and perform RF parameter calculations in parallel. The task allocation of each worker thread is dynamically adjusted based on its load status to obtain the RF parameter calculation results for each data block. Asynchronous transmission and parallel calculations are performed in a pipelined manner, with at least partial overlap. The RF parameter calculation results for each data block are then aggregated and tested to obtain the test results for the device under test.

[0161] Specifically, IPC includes:

[0162] The receiving module includes a main control thread for receiving multiple data blocks and establishing a task queue.

[0163] In this embodiment, the task queue is used for mutual exclusion locking and condition variable notification; multiple worker threads obtain computing tasks from the task queue in a mutual exclusion manner, and perform computing independently after unlocking.

[0164] The worker thread pool consists of multiple worker threads, which are used to retrieve data blocks from the task queue and perform radio frequency parameter calculations in parallel to obtain the radio frequency parameter calculation results for each data block.

[0165] The dynamic load balancing module is used to dynamically adjust the task allocation of each worker thread based on the load status of each worker thread.

[0166] In this embodiment, the dynamic load balancing module is equipped with a job stealing algorithm to monitor the core utilization of each central processing unit (CPU) and the task queue length of each worker thread in real time. When the first worker thread completes its computing task and is idle, it actively steals unprocessed computing tasks from the task queue of the second worker thread for computing, thereby achieving dynamic load balancing among the worker threads.

[0167] The result aggregation module is used to receive the RF parameter calculation results from each working thread, aggregate and test the results to obtain the test results of the device under test.

[0168] In this embodiment, the core memory of the IPC is configured with an independent first buffer and a second buffer, forming a ping-pong buffer architecture. When the FPGA writes the first data block into the first buffer through the high-speed transmission module, the IPC asynchronously reads and processes the second data block that has been stored in the second buffer.

[0169] It should be noted that the sizes of the first and second buffers match the size of the data blocks.

[0170] In this embodiment, the IPC connects multiple computing nodes to form a distributed computing architecture; wherein, the computing nodes include servers and graphics processors.

[0171] Example 4

[0172] Embodiments of the present invention also provide a non-transitory machine-readable medium storing a computer program, wherein the computer program, when executed by a computer's processor, is used to cause the computer to perform a method according to an embodiment of the present invention.

[0173] Example 5

[0174] Embodiments of the present invention also provide a computer program product, including a computer program, wherein the computer program, when executed by a computer's processor, is used to cause the computer to perform the method of an embodiment of the present invention.

[0175] Example 6

[0176] An embodiment of the present invention also provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor. The memory stores a computer program executable by the at least one processor, which, when executed by the at least one processor, causes the electronic device to perform the method of the embodiment of the present invention.

[0177] refer to Figure 3 The present invention will now describe a structural block diagram of an electronic device that can serve as an embodiment of the present invention, serving as an example of a hardware device applicable to various aspects of the present invention. The electronic device is intended to represent various forms of digital electronic computer devices, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present invention described and / or claimed herein.

[0178] like Figure 3As shown, the electronic device includes a computing unit 301, which can perform various appropriate actions and processes based on a computer program stored in a read-only memory (ROM) 302 or a computer program loaded from a storage unit 308 into a random access memory (RAM) 303. The RAM 303 may also store various programs and data required for the operation of the electronic device. The computing unit 301, ROM 302, and RAM 303 are interconnected via a bus 304. An input / output (I / O) interface 305 is also connected to the bus 304.

[0179] Multiple components in the electronic device are connected to I / O interface 305, including: input unit 306, output unit 307, storage unit 308, and communication unit 309. Input unit 306 can be any type of device capable of inputting information into the electronic device. Input unit 306 can receive input digital or character information and generate key signal inputs related to user settings and / or function control of the electronic device. Output unit 307 can be any type of device capable of presenting information and may include, but is not limited to, a display, speaker, video / audio output terminal, vibrator, and / or printer. Storage unit 308 may include, but is not limited to, disks and optical discs. Communication unit 309 allows the electronic device to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks, and may include, but is not limited to, modems, network cards, infrared communication devices, and / or wireless communication transceivers, such as Bluetooth devices, WiFi devices, WiMax devices, cellular communication devices, and / or the like.

[0180] The computing unit 301 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 301 include, but are not limited to, CPUs, graphics processing units (GPUs), various special-purpose artificial intelligence (AI) computing units, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any suitable processors, controllers, microcontrollers, etc. The computing unit 301 performs the various methods and processes described above. For example, in some embodiments, the method embodiments of the present invention can be implemented as computer programs tangibly contained in a machine-readable medium, such as storage unit 308. In some embodiments, part or all of the computer program can be loaded and / or installed on an electronic device via ROM 302 and / or communication unit 309. In some embodiments, the computing unit 301 can be configured to perform the methods described above by any other suitable means (e.g., by means of firmware).

[0181] Computer programs for implementing the methods of embodiments of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0182] In the context of embodiments of this invention, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable signal medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, or infrared systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0183] It should be noted that the term "comprising" and its variations used in the embodiments of this invention are open-ended, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The modifications of "one" and "a plurality" mentioned in the embodiments of this invention are illustrative and not restrictive, and those skilled in the art should understand that unless explicitly indicated otherwise in the context, they should be understood as "one or more".

[0184] The user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in the embodiments of this invention are subject to strict compliance with relevant laws, regulations, and regulatory requirements in their collection, storage, use, processing, transmission, provision, and disclosure, and adhere to the principles of legality, legitimacy, necessity, and good faith. The acquisition of relevant information and data is premised on the user's explicit consent or other legitimate reasons, and a clear and convenient authorization management approach is provided to the user, allowing the user to independently choose to consent, withdraw consent, or refuse to provide relevant information. For functions that rely on user information, if the user does not authorize or withdraws authorization, the corresponding technical function cannot be implemented, and the technical solution of this invention is not applicable in this scenario. The steps described in the method implementation embodiments provided by the embodiments of this invention can be executed in different orders and / or in parallel. Furthermore, the method implementation embodiments may include additional steps and / or omit the steps shown. The scope of protection of this invention is not limited in this respect.

[0185] The term "embodiment" in this specification refers to a specific feature, structure, or characteristic described in connection with an embodiment that may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily imply the same embodiment, nor does it imply independence or alternativeity from other embodiments. The various embodiments in this specification are described in a related manner, with reference to each other for similar or identical parts. In particular, for apparatus, device, and system embodiments, since they are substantially similar to method embodiments, the description is relatively simple, and relevant details are referred to in the description of the method embodiments.

[0186] The above-described embodiments are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of protection. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. A method for accelerating radio frequency testing, characterized in that, include: The system receives raw radio frequency data generated by the radio frequency test equipment measuring the device under test, and preprocesses it through a field-programmable gate array (FPGA) to obtain preprocessed radio frequency data. The preprocessed radio frequency data is encapsulated and segmented using the FPGA to obtain multiple data blocks, which are then asynchronously transmitted to an industrial computer IPC via a high-speed transmission interface. Multiple data blocks are written into a task queue. Multiple worker threads of the IPC retrieve data blocks from the task queue and perform RF parameter calculations in parallel. The task allocation of each worker thread is dynamically adjusted according to the load status of each worker thread to obtain the RF parameter calculation results corresponding to each data block. The asynchronous transmission and the parallel calculation are at least partially overlapped in a pipelined manner. The calculation results corresponding to each data block are compiled and tested to obtain the test results of the object under test.

2. The acceleration method for radio frequency testing according to claim 1, characterized in that, The receiving radio frequency test equipment measures the raw radio frequency data generated by the device under test, and preprocesses it through an FPGA to obtain preprocessed radio frequency data, including: Configure test parameters and start the RF test program. Measure the device under test using the RF test equipment to generate raw RF data; wherein, the raw RF data is an I / Q data stream. The raw radio frequency data is captured in real time using the FPGA. The original radio frequency data after real-time data acquisition is subjected to digital down-conversion processing to reduce the high-frequency signal of the original radio frequency data to the base frequency, thereby obtaining the base frequency data. The baseband data is resampled and time-aligned to unify the sampling rate of multi-channel data, and a timestamp is added to the baseband data. The baseband data after being marked with a timestamp is filtered to eliminate out-of-band noise, resulting in preprocessed radio frequency data.

3. The acceleration method for radio frequency testing according to claim 1, characterized in that, The process of using the FPGA to encapsulate and segment the preprocessed radio frequency data to obtain multiple data blocks, and then asynchronously transmitting them to the IPC via a high-speed transmission interface, includes: The preprocessed radio frequency data is encapsulated to obtain encapsulated data; Based on the bandwidth of the high-speed transmission interface and the cache memory capacity of the IPC, the packet data is dynamically segmented to obtain multiple data blocks; Multiple data blocks are asynchronously transmitted to the IPC via the high-speed transmission interface.

4. The acceleration method for radio frequency testing according to claim 3, characterized in that, The process of asynchronously transmitting multiple data blocks to the IPC via a high-speed transmission interface employs a ping-pong buffer architecture, including: The system memory of the IPC is configured with an independent first buffer and a second buffer. When the FPGA writes the first data block into the first buffer through the high-speed transmission interface, the IPC asynchronously reads and processes the second data block that has been stored in the second buffer; wherein, the high-speed transmission interface uses Direct Memory Access (DMA) technology for data transmission.

5. The acceleration method for radio frequency testing according to claim 1, characterized in that, The process of writing multiple data blocks into a task queue, using multiple worker threads of the IPC to retrieve data blocks from the task queue and perform RF parameter calculations in parallel, and dynamically adjusting the task allocation of each worker thread according to its load status to obtain the RF parameter calculation results corresponding to each data block includes: The main control thread of the IPC monitors the high-speed transmission interface, encapsulates the received multiple data blocks into computing tasks, and writes them sequentially into the task queue. The IPC uses multiple worker threads to obtain the computation tasks from the task queue in a mutually exclusive manner, and each worker thread performs radio frequency parameter calculations independently after unlocking. The task allocation of each working thread is dynamically adjusted according to its load status to obtain the RF parameter calculation results corresponding to each data block.

6. The acceleration method for radio frequency testing according to claim 5, characterized in that, The method of dynamically adjusting the task allocation of each worker thread based on its load status, using a work-stealing algorithm, includes: Real-time monitoring of CPU core utilization and task queue length of each worker thread; When the first worker thread completes its computation task and becomes idle, it actively steals unprocessed computation tasks from the task queue of the second worker thread and performs the computation, thereby achieving dynamic load balancing among the worker threads.

7. The acceleration method for radio frequency testing according to claim 1, characterized in that, The results of the RF parameter calculations corresponding to each data block are aggregated and tested to obtain the test results of the device under test, including: Receive and aggregate the RF parameter calculation results output by all working threads; The results of the radio frequency parameter calculations are sorted and integrated based on the timestamp or sequence number of the data block. The integrated RF parameter calculation results are used for RF parameter testing and system performance evaluation to determine whether the test object is qualified.

8. An acceleration system for radio frequency testing, characterized in that, include: Radio frequency (RF) test equipment is used to measure the raw RF data generated by the device under test. An FPGA, connected to the radio frequency test equipment, is used to receive the raw radio frequency data and perform preprocessing to obtain preprocessed radio frequency data. The preprocessed radio frequency data is then encapsulated and divided into data blocks to obtain multiple data blocks. A high-speed transmission module, connected to the FPGA, is used to asynchronously transmit multiple data blocks; An IPC, connected to the high-speed transmission module, is used to receive the data blocks; write multiple data blocks into a task queue; utilize multiple worker threads of the IPC to retrieve data blocks from the task queue and perform RF parameter calculations in parallel; dynamically adjust the task allocation of each worker thread according to its load status to obtain the RF parameter calculation results corresponding to each data block; wherein the asynchronous transmission and the parallel calculation are performed in a pipelined manner with at least partial overlap; and aggregate the RF parameter calculation results corresponding to each data block, perform test judgment, and obtain the test results of the device under test.

9. The acceleration system for radio frequency testing according to claim 8, characterized in that, The IPC includes: The receiving module includes a main control thread for receiving multiple data blocks and establishing a task queue; The worker thread pool includes multiple worker threads, which are used to retrieve the data blocks from the task queue and perform radio frequency parameter calculations in parallel to obtain the radio frequency parameter calculation results of each data block; The dynamic load balancing module is used to dynamically adjust the task allocation of each worker thread according to the load status of each worker thread. The result aggregation module is used to receive the RF parameter calculation results of each working thread, aggregate and test the results to obtain the test results of the device under test.

10. The acceleration system for radio frequency testing according to claim 9, characterized in that, The core memory of the IPC is configured with an independent first buffer and a second buffer, forming a ping-pong buffer architecture; when the FPGA writes the first data block into the first buffer through the high-speed transmission module, the IPC asynchronously reads and processes the second data block that has been stored in the second buffer.

11. The acceleration system for radio frequency testing according to claim 9, characterized in that, The task queue is used for mutual exclusion locking and condition variable notification; the multiple worker threads obtain computing tasks from the task queue in a mutual exclusion manner, and perform computing independently after unlocking.

12. The acceleration system for radio frequency testing according to claim 9, characterized in that, The dynamic load balancing module is equipped with a job stealing algorithm, which is used to monitor the core utilization of each central processing unit CPU and the task queue length of each worker thread in real time. When the first worker thread completes its computing task and is idle, it actively steals unprocessed computing tasks from the task queue of the second worker thread for computing, thereby achieving dynamic load balancing among the worker threads.

13. The acceleration system for radio frequency testing according to claim 8, characterized in that, The high-speed transmission module includes a PCIe interface and an Ethernet interface, and uses direct memory access technology for data transmission.

14. The acceleration system for radio frequency testing according to claim 8, characterized in that, The IPC connects multiple computing nodes to form a distributed computing architecture; wherein, the computing nodes include servers and graphics processors.

15. An electronic device, characterized in that, The electronic device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the method according to any one of claims 1 to 7.

16. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the method of any one of claims 1 to 7.

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