Ad hoc network clock synchronization method and system based on FPGA and ARM architecture

Abstract

The application relates to a mesh network clock synchronization method and system based on FPGA and ARM architecture and belongs to the technical field of wireless mesh network communication. The method comprises the following steps: after system initialization, a local clock count value is cyclically maintained by the FPGA side according to a preset time slot length; when the count reaches a single time slot threshold, a time slot interrupt signal is sent to the ARM side; the ARM side updates a local time slot serial number in response to the interrupt; after a wireless broadcast frame is received and verified by the FPGA side, relevant data is latched, the data is synchronously updated to a mapping register in an idle gap of time slot alternation, and a data ready interrupt is triggered; the ARM side reads the data, identifies a synchronous parent node, calculates a clock calibration difference value, and issues the clock calibration difference value after aligning the time slot serial number; and the FPGA side adjusts the local clock count value in a preset time period of the next time slot. The application is adapted to the TDMA time slot cycle characteristics, guarantees the consistency of software and hardware interaction data and the certainty of time slot scheduling, and takes into account the synchronization accuracy and the stability of service transmission.

Description

Technical Field

[0001] This invention relates to the field of wireless ad hoc network communication technology, and in particular to an ad hoc network clock synchronization method and system based on FPGA and ARM architecture. Background Technology

[0002] TDMA-based wireless ad hoc networks are characterized by being decentralized, multi-hop forwarding, and highly resilient, making them widely used in emergency communications, industrial IoT, and mobile field networking scenarios. In TDMA networks, the clock synchronization accuracy of each node is a core prerequisite for determining the accuracy of time slot scheduling, channel multiplexing efficiency, and data transmission reliability. Excessive synchronization deviation will directly lead to time slot conflicts, increased packet loss rate, and even network timing disorder.

[0003] Currently, clock synchronization solutions for wireless ad hoc networks are mainly implemented based on a single hardware platform. One type is the pure FPGA implementation, which leverages the high real-time performance and low latency of FPGAs to perform clock counting, timestamp capture, and clock calibration at the hardware level, achieving high synchronization accuracy. However, FPGA logic development has a long cycle and is difficult to debug, making it difficult to support complex TDMA networking protocols and multi-scenario adaptive synchronization algorithms. Network topology expansion and functional iteration costs are extremely high. The other type is the pure ARM implementation, which relies on the high flexibility and rich software development environment of ARM processors to easily implement complex networking protocols and synchronization algorithms, with high debugging and iteration efficiency. However, ARM is affected by operating system scheduling jitter and interrupt response latency, resulting in insufficient real-time performance for timestamp capture and calibration, making it difficult to meet the synchronization accuracy requirements of high-throughput TDMA networks.

[0004] To balance synchronization accuracy and development flexibility, the field has begun to explore heterogeneous architectures using FPGA+ARM for clock synchronization. However, existing heterogeneous solutions directly adopt general industrial communication design principles without specifically adapting to the periodic characteristics of TDMA self-organizing networks, resulting in several technical defects. First, the interaction registers between the FPGA and ARM are updated in real-time. During the ARM's reading of the clock count and time slot number, hardware values ​​may jump, easily leading to inconsistent data sampling and introducing additional synchronization errors. Second, the timing of clock calibration operations is not bound to time slot boundaries. Calibration actions are randomly inserted into time slot operation, causing distortion of single time slot length, disrupting the periodicity and determinism of TDMA time slot scheduling, and consequently causing service transmission jitter. Third, the reporting of key data such as hardware timestamps and time slot numbers lacks unified timing coordination with the execution of synchronization algorithms, making it impossible to maintain stable TDMA service operation while ensuring calibration accuracy, and failing to simultaneously meet the triple requirements of high precision, high flexibility, and high service stability. Summary of the Invention

[0005] Therefore, it is necessary to provide a clock synchronization method and system for self-organizing networks based on FPGA and ARM architecture to address the aforementioned technical problems. In TDMA wireless self-organizing networks based on FPGA+ARM heterogeneous architecture, existing clock synchronization schemes do not specifically adapt to the periodic characteristics of time slots, resulting in inconsistencies in hardware and software register data exchange, calibration execution disrupting the integrity of time slot lengths, and insufficient timing coordination. This paper aims to ensure the determinism of TDMA time slot scheduling and the stability of service transmission while balancing synchronization accuracy and development flexibility.

[0006] A self-organizing network clock synchronization method based on FPGA and ARM architecture, the method comprising: After system initialization, the FPGA side maintains the local clock count value cyclically according to the preset time slot length. Whenever the local clock count value reaches the counting threshold corresponding to a single time slot, a time slot interrupt signal is sent to the ARM side. The ARM side responds to the time slot interrupt signal and updates the local time slot sequence number; When the FPGA receives a wireless broadcast frame and the CRC check passes, it latches the local clock count value at the current moment, and at the same time parses and latches the peer timestamp information and time slot number information carried in the wireless broadcast frame; during the idle gap between the end of the current time slot and the beginning of the next time slot, it synchronously updates all latched data to the ARM-readable mapping register, and triggers a data ready interrupt signal to the ARM side. The ARM side responds to the data ready interrupt signal, reads the latched data in each mapping register, and identifies the identity of the transmitting node of the wireless broadcast frame. If the transmitting node is determined to be the current synchronization parent node, the clock calibration difference is calculated based on the local clock count value and the peer timestamp information. At the same time, the local timestamp sequence number is aligned according to the timestamp number information carried by the wireless broadcast frame. The ARM side writes the clock calibration difference into the downlink calibration register and transmits it to the FPGA side; On the FPGA side, within a preset time period in the next time slot, the local clock count value is adjusted according to the clock calibration difference.

[0007] On the other hand, a self-organizing network clock synchronization system based on FPGA and ARM architecture is also provided, including: The local clock counting and time slot interrupt generation module is used to maintain the local clock count value on the FPGA side according to the preset time slot length after system initialization. Whenever the local clock count value reaches the counting threshold corresponding to a single time slot, a time slot interrupt signal is sent to the ARM side. The local time slot number update module is used by the ARM side to update the local time slot number in response to the time slot interrupt signal. The broadcast frame receiving and data latching reporting module is used to latch the local clock count value at the current moment when the FPGA side receives a wireless broadcast frame and the CRC check passes, and at the same time parse and latch the peer timestamp information and time slot number information carried in the wireless broadcast frame; during the idle gap between the end of the current time slot and the beginning of the next time slot, all latched data are synchronously updated to the ARM-readable mapping register, and a data ready interrupt signal is triggered to the ARM side. The clock calibration difference calculation and time slot alignment module is used by the ARM side to respond to the data ready interrupt signal, read the latched data in each mapping register, and identify the identity of the transmitting node of the wireless broadcast frame. If the transmitting node is determined to be the current synchronization parent node, the clock calibration difference is calculated based on the local clock count value and the peer timestamp information, and the local time slot sequence number is aligned according to the time slot number information carried by the wireless broadcast frame. The calibration difference register sending module is used by the ARM side to write the clock calibration difference into the sending calibration register and transmit it to the FPGA side. The local clock calibration execution module is used by the FPGA side to adjust the local clock count value according to the clock calibration difference within a preset time period in the next time slot.

[0008] Compared with existing technologies, the self-organizing network clock synchronization method and system based on FPGA and ARM architecture provided by this invention have the following advantages: 1. When the FPGA receives a wireless broadcast frame that has passed CRC verification, it first performs hardware latching on the local clock count, the peer timestamp information, and the timeslot number information. Then, it uses the idle gaps of the alternating timeslots to synchronously update all latched data to the ARM-readable mapping register. Finally, it notifies the ARM side to read the data through a data ready interrupt. This process avoids the sampling misalignment and data inconsistency caused by hardware value jumps during ARM reading in the real-time register update mode. It eliminates the synchronization error introduced by software and hardware data interaction, eliminates the source of additional synchronization error from the software and hardware interaction level, ensures data sampling consistency, and effectively improves the basic accuracy of clock synchronization.

[0009] 2. Clock calibration is constrained to be performed within a preset time period of the next time slot. The calibration operation does not intrude into the service transmission window of the time slot, thus avoiding distortion of single-time slot service segment length and disrupting the periodicity of time slot scheduling. While continuously performing clock calibration, the integrity of the TDMA time slot structure is fully preserved, effectively avoiding service transmission jitter and time slot conflicts caused by calibration, ensuring the determinism of TDMA time slot scheduling, and balancing the stable operation of synchronous calibration and service transmission.

[0010] 3. A standardized collaborative timing sequence for FPGA and ARM was constructed using time slot interrupts and data-ready interrupts. On the FPGA side, high-real-time operations such as clock counting cycle maintenance, hardware-level data latching, and calibration execution are handled, leveraging the low latency and high determinism of hardware to ensure synchronization accuracy. On the ARM side, complex calculations such as synchronization deviation calculation, time slot number alignment, and network logic processing are performed, relying on the flexibility of the software architecture to support iterative upgrades of network protocols and synchronization strategies. With clear division of labor and matching timing, both achieve high-precision synchronization, flexible functional expansion, and stable service carrying under the same architecture, solving the shortcomings of insufficient timing coordination in existing heterogeneous solutions and simultaneously meeting the requirements of high precision and high flexibility. Attached Figure Description

[0011] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention, and those skilled in the art can obtain other related drawings based on these drawings without creative effort.

[0012] Figure 1 This is a flowchart illustrating a self-organizing network clock synchronization method based on FPGA and ARM architecture in one embodiment. Figure 2 This is a block diagram of a self-organizing network clock synchronization system based on FPGA and ARM architecture in one embodiment; Figure 3 This is an internal structural diagram of a computer device in one embodiment.

[0013] The objectives, features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0014] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0015] It is understood that the technical solutions of the various embodiments of the present invention can be combined with each other, but only if they are based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by the present invention.

[0016] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0017] Example 1 like Figure 1 As shown, a self-organizing network clock synchronization method based on FPGA and ARM architecture is provided, including the following steps: Step 201: After system initialization, the FPGA side maintains the local clock count value cyclically according to the preset time slot length. Whenever the local clock count value reaches the counting threshold corresponding to a single time slot, a time slot interrupt signal is sent to the ARM side.

[0018] This step provides the basic clock and timing reference for the entire TDMA self-organizing network. The FPGA-side hardware implements accurate counting of time slot cycles and interrupt triggering, ensuring the determinism of time slot scheduling. The counting threshold for a single time slot refers to the total number of local crystal oscillator clock cycles corresponding to the duration of a single time slot. It is a hardware reference parameter for determining the time slot boundary and is calculated from the system's preset time slot length and the local crystal oscillator operating frequency.

[0019] In the specific implementation of this step, during the system power-on initialization phase, the FPGA side completes the parameter configuration of the clock counting module and writes the preset counting threshold corresponding to a single time slot. After initialization, the clock counting module on the FPGA side uses the crystal oscillator clock as a reference to cyclically accumulate and maintain the local clock count value. When the count value accumulates to the counting threshold corresponding to a single time slot, it automatically clears the count value and restarts the counting cycle for the next time slot, while simultaneously generating a pulse-shaped time slot interrupt signal to the ARM side.

[0020] This step uses FPGA hardware to implement clock counting and time slot interrupt generation, ensuring high counting accuracy and stable interrupt triggering delay, thus guaranteeing the determinism of the TDMA time slot period from the source.

[0021] Step 202: The ARM side responds to the time slot interrupt signal and updates the local time slot sequence number.

[0022] This step achieves synchronization and alignment between the ARM-side time slot sequence number and the physical boundary of the time slot, which is the timing basis for the TDMA protocol scheduling and synchronization algorithm operation.

[0023] In the specific implementation of this step, the ARM side runs the TDMA protocol stack and clock synchronization algorithm program. Upon receiving a time slot interrupt signal from the FPGA side, it immediately triggers the interrupt service routine, accumulating and updating the local time slot sequence number according to the preset time slot cycle, completing the time slot-by-time advancement of the node's time slot sequence number. For slave nodes not yet connected to the network, the local time slot sequence number is only used for internal timing scheduling; for nodes already connected to the network, the local time slot sequence number is aligned with the global network time slot sequence number and used as the timing basis for channel access, data transmission and reception, and synchronization calculation. After updating the local time slot sequence number, the ARM side synchronously executes the corresponding TDMA channel scheduling logic based on the current time slot sequence number, including operations such as wireless broadcast frame transmission, service data transmission and reception, and neighbor node status maintenance.

[0024] This step uses the hardware time slot interrupt on the FPGA side as the trigger source to ensure that the time slot number update on the ARM side is strictly aligned with the physical boundary of the time slot, avoiding scheduling jitter caused by software timing and ensuring the consistency and accuracy of TDMA time slot scheduling.

[0025] Step 203: When the FPGA receives the wireless broadcast frame and the CRC check passes, it latches the local clock count value at the current moment, and at the same time parses and latches the peer timestamp information and time slot number information carried in the wireless broadcast frame; during the idle gap between the end of the current time slot and the beginning of the next time slot, it synchronously updates all latched data to the ARM-readable mapping register, and triggers a data ready interrupt signal to the ARM side.

[0026] This step completes the hardware capture and cross-domain reporting of key synchronization information for wireless broadcast frames, which is the data acquisition foundation for achieving high-precision clock synchronization. The idle gap refers to the blank time period reserved between two adjacent time slots. It does not carry business data transmission and is dedicated to auxiliary operations such as data synchronization updates and clock calibration, avoiding interference with normal business transmission.

[0027] In the specific implementation of this step, the RF receiving module on the FPGA side continuously receives the over-the-air wireless signal. When a complete wireless broadcast frame is parsed and the CRC check is completed and the check result is correct, a hardware latching action is immediately triggered, latching two types of data within the same clock cycle: one is the local clock count value at the current moment, and the other is the peer's timestamp information and timeslot number information parsed from the corresponding fields of the wireless broadcast frame. The peer's timestamp information is the peer's local clock count value latched at the moment when the node that sent the wireless broadcast frame received the previous wireless broadcast frame and the CRC check passed, which is used to calculate the clock deviation using the bidirectional delay method.

[0028] The FPGA side is configured with a primary hardware latch register and a secondary mapping register. The primary hardware latch register is a dedicated register inside the FPGA used for instantaneous capture of synchronization data. It is updated only when the trigger condition of CRC check passing is met, and its value remains stable during the time slot operation. The secondary mapping register is a readable register exposed to the ARM bus by the FPGA side, used for batch synchronous latching of data, and is exclusively for ARM side reading and access. Both types of latched data are written to the primary hardware latch register. During the idle interval between the end of the current time slot and the beginning of the next time slot, the FPGA side synchronously updates all data in the primary hardware latch register to the secondary mapping register in batches. After the update is completed, the FPGA side immediately triggers a data ready interrupt signal to the ARM side, notifying the ARM side to read the captured synchronization data.

[0029] If multiple CRC-verified wireless broadcast frames are received within a single time slot, the primary hardware latch register is updated once for each successfully received frame, and the latch result of the previously received frame is overwritten by the data of the later received frame. During idle intervals, the latch data corresponding to the last frame is updated to the secondary mapping register, triggering a data ready interrupt. The ARM side can update the neighbor node status table based on the results read in each time slot, completing the information maintenance of multiple neighbor nodes.

[0030] For slave nodes not yet connected to the network, this step also triggers coarse synchronization network connection processing. Specifically, for nodes not yet connected to the network, when the FPGA receives a radio broadcast frame, passes the CRC check, and latches the data, it immediately clears the local clock count and restarts counting. Simultaneously, it reports the latched time slot number information to the ARM side. The ARM side updates the local time slot sequence number at the next time slot interrupt signal trigger moment, completing coarse synchronization. After coarse synchronization is completed, the ARM side performs an initial synchronization parent node election based on the neighbor node status table. The election rules are consistent with the re-election rules after the parent node loses connection. After the election is completed, the first synchronization parent node is determined, and the node enters the fine synchronization state. The fine synchronization state refers to the normalized closed-loop synchronization state after the node completes the initial coarse alignment of the time slot and clock phase, using the current synchronization parent node as the reference, performing radio broadcast frame reception, clock calibration difference calculation, calibration parameter distribution, and local clock count value adjustment in each time slot. This corresponds to the cyclic execution process of steps 203 to 206 of this method, and is used to continuously converge the clock deviation between nodes and maintain it within a high-precision range.

[0031] This step employs a hardware instantaneous latching + time-slot interval batch update mechanism, combined with a two-level register architecture design, to ensure that all fields are sampled at the same moment when the ARM side reads data. This completely avoids the data sampling inconsistency problem caused by value jumps during the reading process in the real-time register update mode, eliminates the additional synchronization error introduced by software and hardware interaction, and significantly improves the basic accuracy of synchronous calculation.

[0032] Step 204: The ARM side responds to the data ready interrupt signal, reads the latched data in each mapping register, and identifies the identity of the transmitting node of the wireless broadcast frame. If the transmitting node is determined to be the current synchronization parent node, the clock calibration difference is calculated based on the local clock count value and the peer timestamp information. At the same time, the local timestamp sequence number is aligned according to the timestamp number information carried by the wireless broadcast frame.

[0033] This step is the core computational component of the clock synchronization algorithm, where the ARM side performs node identification, clock offset calculation, and time slot alignment. The current synchronization parent node refers to the upstream node of the clock synchronization reference selected by this node in the multi-hop network topology. It is the sole reference source for this node to perform clock calibration. The node performs calibration operations solely based on the parent node's broadcast data; data from other neighboring nodes is only used for topology maintenance. Simultaneously, the root node in the network serves as the global clock reference source. The root node has no synchronization parent node and does not perform clock calibration operations. The root node is automatically elected during network initialization. After initialization, it autonomously starts local clock counting and time slot number cycling, operating solely based on its local crystal oscillator clock. Its wireless broadcast frames carry its local time slot number and clock count value, providing a unified timing reference for the entire network.

[0034] In the specific implementation of this step, after receiving the data-ready interrupt signal, the ARM side enters the corresponding interrupt service routine and reads all latched data in the secondary mapping register at once, including the local clock count value, peer timestamp information, and timeslot number information. The ARM side identifies the sending node's identity based on the node identifier field in the wireless broadcast frame and compares the sending node with the locally maintained list of synchronization parent nodes. The list of synchronization parent nodes is a table stored locally on the ARM side, used to record the node identifier, link status, and other baseline information of the currently selected synchronization parent node, which serves as the basis for node identity determination.

[0035] If the sending node is determined not to be the current synchronization parent node, the data is stored in the neighbor node status table for network topology maintenance. The neighbor node status table is a global table maintained by the ARM side, recording information such as the identifier, link quality, timeslot number, and timestamp of all detectable neighbor nodes. It is the core data basis for topology maintenance and new parent node election. The data in this table also serves as input for neighbor node scanning and new parent node election in the subsequent synchronization maintenance phase. Clock calibration calculation is not performed in this case. If the sending node is determined to be the current synchronization parent node, clock calibration difference calculation and timeslot number alignment are performed.

[0036] The clock calibration difference is calculated using the bidirectional delay symmetry method. This method is based on the assumption of bidirectional link delay symmetry and calculates the clock phase deviation between nodes using the round-trip timestamps. It is a classic synchronization deviation calculation method in wireless ad hoc networks. The calculation expression is: .

[0037] In the formula, To calibrate the clock difference; This is the peer's timestamp information, that is, the parent node's local clock count value latched when the parent node receives the previous wireless broadcast frame from this node. This is the local clock count value latched when the FPGA receives a wireless broadcast frame and the CRC check passes.

[0038] After obtaining the clock calibration difference, the ARM side first performs anomaly filtering. Anomaly filtering is a preprocessing step that verifies the validity of the calculated calibration difference. It is used to eliminate invalid calibration values ​​caused by channel interference and data anomalies. After the anomaly filtering passes, the filtered clock calibration difference is output.

[0039] The anomaly filtering process includes: determining whether the absolute value of the clock calibration difference exceeds a preset anomaly threshold; if it exceeds the preset anomaly threshold, discarding the current clock calibration difference, not generating a valid output, and not performing a distribution operation; if it does not exceed the preset anomaly threshold, determining that the anomaly filtering has passed, and outputting the filtered clock calibration difference.

[0040] Simultaneously, the ARM side determines the sampling phase by combining the remaining clock count value in the latch and aligns and corrects the local time slot number according to the time slot number information carried in the wireless broadcast frame. The alignment operation takes effect synchronously at the next time slot interrupt trigger time: if the difference between the local time slot number and the parent node's time slot number is within the preset alignment range, it is directly corrected to the parent node's time slot number when the sequence number is updated in the next time slot interrupt; if the difference exceeds the preset range, it is corrected step by step in a single time slot manner to avoid the impact of a single time slot jump being too large on service scheduling, ensuring that the time slot number of this node is consistent with that of the parent node, and completing the synchronous alignment of the time slot domain.

[0041] This step involves the ARM side performing complex synchronization algorithm calculations, adapting to different network topologies and channel environments. Simultaneously, it uses high-precision timestamps latched by hardware for calculation, balancing algorithm flexibility and computational accuracy, and improving synchronization stability in complex networking scenarios.

[0042] Step 205: The ARM side writes the clock calibration difference into the downlink calibration register and transmits it to the FPGA side.

[0043] In this step, the ARM side writes the filtered clock calibration difference into the downlink calibration register and transmits it to the FPGA side. This mainly completes the downlink transmission of calibration parameters from the ARM side to the FPGA side, serving as a crucial bridge connecting synchronous computation and calibration execution. The downlink calibration register is a cross-domain data transmission register between the ARM and FPGA sides; calibration parameters are written to the ARM side, and the FPGA side directly reads and executes them, achieving efficient data interaction between hardware and software.

[0044] Step 206: On the FPGA side, within a preset time period of the next time slot, the local clock count value is adjusted according to the clock calibration difference.

[0045] This step is the hardware execution phase of clock calibration, in which the FPGA side performs phase adjustment of the local clock count value to achieve precise synchronization with the parent node's clock.

[0046] In the specific implementation of this step, after the FPGA side reads the filtered clock calibration difference value from the calibration register, it does not immediately perform the adjustment. Instead, it waits until the preset time period of the next time slot before performing the calibration operation. This preset time period is the idle gap at the beginning of the time slot and does not carry service data transmission. The calibration is performed using a phase superposition method: at the beginning of the protection interval, the filtered clock calibration difference value is directly superimposed on the local clock count value to complete the clock phase correction. If the absolute value of the filtered clock calibration difference value exceeds the maximum allowable adjustment amount corresponding to the single time slot protection interval, the correction is performed according to the maximum allowable adjustment amount. The remaining deviation is synchronously updated to the corresponding status field of the secondary mapping register and reported to the ARM side along with the next data ready interrupt, to be adjusted sequentially in subsequent time slots.

[0047] This step constrains the calibration execution timing within the time slot protection interval, completely avoiding intrusion into the service transmission window and preventing distortion of single time slot length, thus ensuring the periodicity and determinism of TDMA time slot scheduling. Furthermore, this method also includes a synchronization maintenance switching process. This process is an exception handling mechanism where, when the parent node link is interrupted, the node maintains its local clock independently and reselects a synchronization parent node, used for timing maintenance and network recovery in scenarios where the parent node link is lost. If the ARM side does not receive a wireless broadcast frame sent by the parent node for a consecutive preset number of time slot periods, it is determined that the parent node link is lost; the node enters synchronization maintenance mode, the FPGA side continues to maintain the local clock count value according to the current counting benchmark, and the ARM side initiates a neighbor node scan and new parent node election process. The election process is based on the locally stored neighbor node status table data, and the specific execution process is as follows: The ARM side traverses all neighbor nodes in the neighbor node status table and selects nodes that simultaneously meet the admission criteria as candidate parent nodes: the node can successfully receive wireless broadcast frames within a consecutive preset number of time slot periods, and the CRC check pass rate is not lower than the preset qualified threshold, the link quality is stable and reliable, and the continuity of subsequent synchronous interaction is guaranteed.

[0048] All candidate parent nodes selected through screening are prioritized. The first priority is link quality and reception stability; the higher the frame reception success rate and the smaller the reception status fluctuation, the stronger the reliability of synchronization interaction, and the higher the priority. The second priority is clock stability, which is calculated based on the clock fluctuation degree of the timestamp sequence carried by the node's historical broadcast frames. The smaller the fluctuation, the more stable the node's local clock, and the more guaranteed the accuracy of the synchronization benchmark, and the higher the priority.

[0049] The candidate node with the highest priority is selected as the new synchronization parent node, and the local synchronization parent node list is updated synchronously. If no candidate parent node that meets the admission criteria is found after traversal, the synchronization hold mode is maintained, and neighbor nodes are continuously scanned and the neighbor node status table is updated in real time until a candidate node that meets the criteria is found, and it is selected as the new synchronization parent node.

[0050] After the election is completed, the ARM side first performs coarse alignment of the local time slot number based on the time slot number information carried in the latest broadcast frame of the new synchronization parent node, and then uses the new synchronization parent node as the synchronization reference to resume the calculation, distribution and adjustment of the clock calibration difference for each time slot and the local clock count value.

[0051] In the aforementioned self-organizing network clock synchronization method based on FPGA and ARM architecture, the local clock count value, peer timestamp information, and time slot number information are immediately latched in hardware when the CRC check of the wireless broadcast frame passes. After completing the synchronization update of all latched data during the idle interval at the end of the current time slot, a data ready interrupt is triggered to notify the ARM side to read the data uniformly. This fundamentally eliminates the data sampling inconsistency problem caused by value jumps during the reading process in the real-time register update mode, reducing synchronization errors introduced by software and hardware interaction. By constraining the clock calibration action to be performed within a preset time period of the next time slot, the calibration operation... It operates without intruding on the time-slot service transmission window, avoiding single-slot length distortion caused by calibration, ensuring the periodicity and determinism of TDMA time-slot scheduling, and maintaining stable service transmission. At the same time, it builds a standardized collaborative timing based on time-slot interrupts and data-ready interrupts. The FPGA side is responsible for real-time operations such as clock counting maintenance, hardware-level data latching, and calibration execution, while the ARM side is responsible for synchronization deviation calculation, time-slot number alignment, and network logic processing. This achieves a balance between synchronization accuracy and development flexibility under heterogeneous architecture, and solves the technical defects of existing heterogeneous solutions that are insufficient in timing coordination and cannot simultaneously meet high precision and high service stability.

[0052] It should be understood that, although this embodiment Figure 1 The steps are shown sequentially as indicated by the arrows, but they are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order in which these steps are performed; they can be executed in other orders. Figure 1 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0053] Example 2 Based on the self-organizing network clock synchronization method based on FPGA and ARM architecture in Embodiment 1, this embodiment discloses a self-organizing network clock synchronization system based on FPGA and ARM architecture, such as... Figure 2 As shown, the self-organizing network clock synchronization system based on FPGA and ARM architecture includes: a local clock counting and time slot interrupt generation module 401, a local time slot sequence number update module 402, a broadcast frame reception and data latch reporting module 403, a clock calibration difference calculation and time slot alignment module 404, a calibration difference register distribution module 405, and a local clock calibration execution module 406, wherein: The local clock counting and time slot interrupt generation module 401 is used to maintain the local clock count value on the FPGA side according to the preset time slot length after system initialization. Whenever the local clock count value reaches the counting threshold corresponding to a single time slot, a time slot interrupt signal is sent to the ARM side.

[0054] The local timeslot number update module 402 is used by the ARM side to respond to the timeslot interrupt signal and update the local timeslot number.

[0055] The broadcast frame receiving and data latching reporting module 403 is used to latch the local clock count value at the current moment when the FPGA side receives a wireless broadcast frame and the CRC check passes, and at the same time parse and latch the peer timestamp information and time slot number information carried in the wireless broadcast frame; during the idle gap between the end of the current time slot and the beginning of the next time slot, all latched data are synchronously updated to the ARM-readable mapping register, and a data ready interrupt signal is triggered to the ARM side.

[0056] The clock calibration difference calculation and time slot alignment module 404 is used by the ARM side to respond to the data ready interrupt signal, read the latched data in each mapping register, and identify the identity of the transmitting node of the wireless broadcast frame. If the transmitting node is determined to be the current synchronization parent node, the clock calibration difference is calculated based on the local clock count value and the peer timestamp information. At the same time, the local time slot sequence number is aligned according to the time slot number information carried by the wireless broadcast frame.

[0057] The calibration difference register sending module 405 is used by the ARM side to write the clock calibration difference into the sending calibration register and transmit it to the FPGA side.

[0058] The local clock calibration execution module 406 is used by the FPGA side to adjust the local clock count value according to the clock calibration difference within a preset time period in the next time slot.

[0059] In this embodiment, the specific working process and working principle of the local clock counting and time slot interrupt generation module 401, the local time slot sequence number update module 402, the broadcast frame reception and data latch reporting module 403, the clock calibration difference calculation and time slot alignment module 404, the calibration difference register distribution module 405, and the local clock calibration execution module 406 are the same as those in Embodiment 1, and therefore will not be described again in this embodiment. Each unit module can be implemented entirely or partially through software, hardware, or a combination thereof. Each unit module can be embedded in the processor of the computer device in hardware form or independent of it, or it can be stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to the above unit modules.

[0060] Example 3 like Figure 3 The diagram illustrates a computer device disclosed in this embodiment, including a transmitter, a receiver, a memory, and a processor. The transmitter is used to send instructions and data, the receiver is used to receive instructions and data, the memory is used to store computer execution instructions, and the processor is used to execute the computer execution instructions stored in the memory to implement the method in Embodiment 1 above.

[0061] It is important to note that the aforementioned memory can be either standalone or integrated with the processor. When the memory is set up independently, the terminal device also includes a bus for connecting the memory and the processor.

[0062] Example 4 This embodiment discloses a computer-readable storage medium storing computer-executable instructions. When a processor executes the computer-executable instructions, it implements the method in Embodiment 1 above.

[0063] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0064] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0065] The embodiments described above are merely examples of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention.

Claims

1. A self-organizing network clock synchronization method based on FPGA and ARM architecture, characterized in that, The method includes: After system initialization, the FPGA side maintains the local clock count value cyclically according to the preset time slot length. Whenever the local clock count value reaches the counting threshold corresponding to a single time slot, a time slot interrupt signal is sent to the ARM side. The ARM side responds to the time slot interrupt signal and updates the local time slot sequence number; When the FPGA receives a wireless broadcast frame and the CRC check passes, it latches the local clock count value at the current moment, and at the same time parses and latches the peer timestamp information and time slot number information carried in the wireless broadcast frame; during the idle gap between the end of the current time slot and the beginning of the next time slot, it synchronously updates all latched data to the ARM-readable mapping register, and triggers a data ready interrupt signal to the ARM side. The ARM side responds to the data ready interrupt signal, reads the latched data in each mapping register, and identifies the identity of the transmitting node of the wireless broadcast frame. If the transmitting node is determined to be the current synchronization parent node, the clock calibration difference is calculated based on the local clock count value and the peer timestamp information. At the same time, the local timestamp sequence number is aligned according to the timestamp number information carried by the wireless broadcast frame. The ARM side writes the clock calibration difference into the downlink calibration register and transmits it to the FPGA side; On the FPGA side, within a preset time period in the next time slot, the local clock count value is adjusted according to the clock calibration difference.

2. The self-organizing network clock synchronization method based on FPGA and ARM architecture according to claim 1, characterized in that, The FPGA side is configured with a first-level hardware latch register and a second-level mapping register; When the CRC check of the received wireless broadcast frame passes, the local clock count value, the peer timestamp information and the timeslot number information are latched into the first-level hardware latch register. During the idle interval between the end of the current time slot and the beginning of the next time slot, all data in the first-level hardware latch register is synchronously updated to the second-level mapping register, and a data ready interrupt signal is triggered to the ARM side.

3. The self-organizing network clock synchronization method based on FPGA and ARM architecture according to claim 1, characterized in that, The clock calibration difference is calculated based on the local clock count and the peer timestamp information, and the calculation expression is as follows: ； In the formula, To calibrate the clock difference; This is the peer's timestamp information, which is the parent node's local clock count value latched when the parent node receives the previous wireless broadcast frame from this node. This is the local clock count value latched when the FPGA receives a wireless broadcast frame and the CRC check passes.

4. The self-organizing network clock synchronization method based on FPGA and ARM architecture according to claim 1, characterized in that, After the ARM side obtains the clock calibration difference, it first performs anomaly filtering. After the anomaly filtering passes, it outputs the filtered clock calibration difference and then writes the filtered clock calibration difference into the downlink calibration register.

5. The self-organizing network clock synchronization method based on FPGA and ARM architecture according to claim 4, characterized in that, The anomaly filtering process includes: Determine whether the absolute value of the clock calibration difference exceeds a preset abnormal threshold. If it exceeds the preset abnormal threshold, discard the current clock calibration difference and do not perform the distribution operation. If it does not exceed the preset abnormal threshold, determine that the abnormal filtering has passed and output the filtered clock calibration difference.

6. The self-organizing network clock synchronization method based on FPGA and ARM architecture according to any one of claims 1 to 5, characterized in that, The preset time period is the idle gap at the beginning of the next time slot, and the idle gap does not carry service data transmission.

7. The self-organizing network clock synchronization method based on FPGA and ARM architecture according to any one of claims 1 to 5, characterized in that, Also includes: For slave nodes that are not connected to the network, when the FPGA side receives a wireless broadcast frame and the CRC check passes and the data is latched, it immediately clears the local clock count value and restarts counting, while reporting the latched time slot number information to the ARM side. The ARM side updates the local time slot number at the moment the next time slot interrupt signal is triggered, and after completing the coarse synchronization, it enters the fine synchronization state of time slot closed-loop calibration.

8. The self-organizing network clock synchronization method based on FPGA and ARM architecture according to any one of claims 1 to 5, characterized in that, It also includes synchronous switching processing: If the ARM side does not receive the wireless broadcast frame from the parent node for a preset number of consecutive time slots, it is determined that the parent node link is lost. The node enters the synchronization maintenance mode. The FPGA side continues to maintain the local clock count value according to the current counting benchmark, while the ARM side starts the neighbor node scanning and new parent node election process to obtain a new synchronization parent node. Using the new synchronization parent node as the synchronization reference, resume the calculation, distribution, and adjustment of clock calibration difference values ​​for each time slot, as well as the adjustment of local clock count values.

9. A self-organizing network clock synchronization system based on FPGA and ARM architecture, characterized in that, The system includes: The local clock counting and time slot interrupt generation module is used to maintain the local clock count value on the FPGA side according to the preset time slot length after system initialization. Whenever the local clock count value reaches the counting threshold corresponding to a single time slot, a time slot interrupt signal is sent to the ARM side. The local time slot number update module is used by the ARM side to update the local time slot number in response to the time slot interrupt signal. The broadcast frame receiving and data latching reporting module is used to latch the local clock count value at the current moment when the FPGA side receives a wireless broadcast frame and the CRC check passes, and at the same time parse and latch the peer timestamp information and time slot number information carried in the wireless broadcast frame; during the idle gap between the end of the current time slot and the beginning of the next time slot, all latched data are synchronously updated to the ARM-readable mapping register, and a data ready interrupt signal is triggered to the ARM side. The clock calibration difference calculation and time slot alignment module is used by the ARM side to respond to the data ready interrupt signal, read the latched data in each mapping register, and identify the identity of the transmitting node of the wireless broadcast frame. If the transmitting node is determined to be the current synchronization parent node, the clock calibration difference is calculated based on the local clock count value and the peer timestamp information, and the local time slot sequence number is aligned according to the time slot number information carried by the wireless broadcast frame. The calibration difference register sending module is used by the ARM side to write the clock calibration difference into the sending calibration register and transmit it to the FPGA side. The local clock calibration execution module is used by the FPGA side to adjust the local clock count value according to the clock calibration difference within a preset time period in the next time slot.

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