FPGA-based synchronous audio stream sending method, system, device and medium

Abstract

The application relates to the technical field of audio transmission, and discloses a synchronization audio stream sending method based on FPGA, which comprises the following steps: candidate comparison keys are constructed based on PTP announcement message extraction candidate master clock attributes, and current master clock reference state snapshots are latched; the candidate comparison keys are compared with reference comparison keys to obtain slice comparison results; the candidate is taken as a current remote master clock, and a flag bit of a master-slave role is reset; a preset event triggers rebinding and updates a generation mark to obtain a ready state; when the ready state is obtained, a timestamp is extracted according to the generation mark and current remote master clock information to calculate a deviation; a period adjustment amount is obtained through filtering and integration, and a local clock period is adjusted; and a digital control oscillator is driven to generate an audio sampling clock to control playing stability. The application further discloses a synchronization audio stream sending system based on FPGA, equipment and a storage medium. The application can improve the frequency locking precision of an audio sampling clock and playing continuity.

Description

Technical Field

[0001] This invention relates to the field of audio transmission technology, and in particular to a method, system, device and medium for synchronous audio stream transmission based on FPGA. Background Technology

[0002] Currently, clock synchronization and audio stream transmission for AES67 audio nodes primarily rely on a combination of embedded processors running PTP and RTP protocol stacks. Traditional solutions use the standard PTPv2 protocol stack for master clock election and synchronization, the operating system's network protocol stack for RTP packet encapsulation and transmission, and the CPU for audio buffer management and clock servo control.

[0003] However, the PTP protocol stack stamps timestamps at the operating system's network layer, which is affected by interrupt response and task scheduling, resulting in some jitter and limited synchronization accuracy. Furthermore, state cleanup during master clock switching is time-consuming, posing a potential risk of old data residue. These factors, to some extent, limit the applicability of AES67 audio nodes in professional audio scenarios such as broadcasting and live sound reinforcement, where high synchronization accuracy and latency stability are required. Summary of the Invention

[0004] This invention provides a synchronous audio stream transmission method, system, device, and medium based on FPGA, the main purpose of which is to improve the frequency locking accuracy and playback continuity of the audio sampling clock.

[0005] To achieve the above objectives, the present invention provides a synchronous audio stream transmission method based on FPGA, comprising: Based on the preset PTP notification message, the attributes of the candidate master clock are extracted, a candidate comparison key is constructed, the information of the candidate master clock is latched, and a snapshot of the current master clock reference state is obtained. Obtain the reference comparison key of the candidate comparison key; based on the current master clock reference state snapshot, divide the candidate comparison key and the reference comparison key into multiple comparison segments for comparison to obtain the segmented comparison result. Based on the fragmentation comparison results, the candidate master clock is selected as the current remote master clock to obtain the current remote master clock information. Based on the current remote master clock information, the master-slave roles are determined, and the master-slave role flag is obtained. When a preset event is detected, a master clock rebinding event is generated based on the master-slave role flag, and the generation flag of the current remote master clock is updated to obtain a rebinding ready state. When the rebinding ready state is valid, multiple timestamps are obtained based on the generation flag of the current remote master clock and the current remote master clock information, and the time deviation is calculated based on the multiple timestamps. The time deviation is filtered and integrated to obtain the clock cycle adjustment amount. The preset local clock cycle is adjusted according to the clock cycle adjustment amount to obtain the local clock adjustment cycle. The local PTP time is obtained according to the local clock cycle. According to the adjustment of the local clock cycle, a preset numerically controlled oscillator is driven to generate an audio sampling clock, an RTP timestamp is generated according to the local PTP time, and audio playback is controlled according to the audio sampling clock and the RTP timestamp.

[0006] Optionally, the step of extracting the attributes of candidate master clocks and constructing candidate comparison keys based on preset PTP notification messages includes: The PTP notification message is parsed, and multiple clock attribute fields of the candidate master clock are extracted from the specified offset position of the message; The multiple clock attribute fields are concatenated in a preset priority order to construct a candidate comparison key.

[0007] Optionally, the step of dividing the candidate comparison key and the preset reference comparison key into multiple comparison segments for comparison based on the current master clock reference state snapshot to obtain a segmented comparison result includes: Based on the current master clock reference state snapshot, the candidate comparison key and the reference comparison key are synchronized and aligned, and divided into multiple comparison segments; Multiple comparison segments are compared in parallel to generate slices that are less than or equal to the results of the comparison segments. The results of the fragment being less than and the fragment being equal to are latched to obtain the fragment comparison result.

[0008] Optionally, determining the master / slave role and obtaining the master / slave role flag based on the current remote master clock information includes: The steps involve monitoring the current remote master clock using a preset liveness counter, triggering a failure reselection when the liveness counter reaches zero, obtaining a failure reselection trigger signal, returning a PTP notification message based on a preset value, extracting the attributes of candidate master clocks, constructing candidate comparison keys, latching the information of the candidate master clocks, and obtaining a snapshot of the current master clock reference state.

[0009] Optionally, generating a master clock rebinding event based on the master-slave role flag when a preset event is detected includes: Obtain the current state and the previous latch state of the master-slave role flag, and compare the current state and the previous latch state of the master-slave role flag. If the current state of the master-slave role flag is inconsistent with the previous latch state, then the local role is determined to have changed based on the master-slave role flag, triggering rebinding and generating a master clock rebinding event.

[0010] Optionally, when the rebinding ready state is valid, multiple timestamps are obtained based on the generation flag of the current remote master clock and the current remote master clock information, including: Check whether the rebinding ready state is valid; If the rebinding ready state is valid, then obtain the synchronization message and the generation tag of the synchronization message, as well as the delay measurement message and the generation tag of the delay measurement message; Based on the generation flag of the current remote master clock, determine whether the generation flags of the synchronization message and the delay measurement message are consistent; If the generation markers are consistent, the source identifier and source port number are extracted from the synchronization message and the delay measurement message, and the source identifier and source port number are compared with the master clock identifier and port number in the current remote master clock information; If the source identity and the source port number match, the sequence numbers of the synchronization message and the delay measurement message are extracted and their continuity is verified with the sequence numbers of the previous synchronization message and the previous delay measurement message. If the continuity check passes, the timestamps of the synchronization message and the delay measurement message are extracted to obtain the multiple timestamps.

[0011] Optionally, calculating the time deviation based on the plurality of timestamps includes: Obtain the first and second timestamps from the plurality of timestamps, and calculate the first difference between the first timestamp and the second timestamp; Obtain the third and fourth timestamps from the plurality of timestamps, and calculate the second difference between the third and fourth timestamps; The difference between the first difference and the second difference is calculated to obtain a third difference, and half of the third difference is taken as the time deviation.

[0012] To address the aforementioned problems, the present invention also provides a synchronous audio stream transmission system based on FPGA, the system comprising: The shard comparison module is used to extract the attributes of candidate master clocks based on preset PTP announcement messages, construct candidate comparison keys, latch the information of the candidate master clocks, and obtain a snapshot of the current master clock reference state. Based on the current master clock reference state snapshot, the candidate comparison key and the preset reference comparison key are divided into multiple comparison segments for comparison to obtain the segmented comparison result; The master-slave determination module is used to select the candidate master clock as the current remote master clock based on the fragmentation comparison result, obtain the current remote master clock information, determine the master-slave role based on the current remote master clock information, and obtain the master-slave role flag bit; The deviation calculation module is used to generate a master clock rebinding event based on the master-slave role flag when a preset event is detected, and update the generation flag of the current remote master clock to obtain a rebinding ready state. When the rebinding ready state is valid, multiple timestamps are obtained based on the generation flag of the current remote master clock and the current remote master clock information, and the time deviation is calculated based on the multiple timestamps. The playback control module is used to filter and integrate the time deviation to obtain the clock cycle adjustment amount, adjust the preset local clock cycle according to the clock cycle adjustment amount to obtain the local clock adjustment cycle, and obtain the local PTP time according to the local clock cycle. According to the adjustment of the local clock cycle, a preset numerically controlled oscillator is driven to generate an audio sampling clock, an RTP timestamp is generated according to the local PTP time, and audio playback is controlled according to the audio sampling clock and the RTP timestamp.

[0013] To address the above problems, the present invention also provides an electronic device, the electronic device comprising: At least one processor; and, A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, which enables the at least one processor to perform the FPGA-based synchronous audio stream transmission method as described above.

[0014] To address the aforementioned problems, the present invention also provides a computer-readable storage medium, including a data storage area and a program storage area, wherein the data storage area stores created data and the program storage area stores a computer program; wherein, when the computer program is executed by a processor, it implements the FPGA-based synchronous audio stream transmission method described above.

[0015] This invention extracts candidate master clock attributes from PTP notification messages to construct candidate comparison keys, and latches a snapshot of the current master clock reference state. The candidate comparison keys are then compared with the reference comparison key in segments to obtain segment comparison results. Based on these results, the candidate is designated as the current remote master clock, and a flag is used to re-determine the master-slave roles. A preset event triggers rebinding and updates the generation flag to obtain a ready state. Upon ready state, the timestamp is extracted based on the generation flag and the current remote master clock information to calculate the deviation. The period adjustment is obtained through filtering and integration, and the local clock period is adjusted. A digitally controlled oscillator is driven to generate an audio sampling clock for stable playback. Therefore, the FPGA-based synchronous audio stream transmission method, system, electronic device, and computer-readable storage medium proposed in this invention construct a synchronous audio transmission architecture centered on PTP master clock election and dynamic role determination, generation mark isolation and rebinding mechanism, timestamp extraction and proportional-integral adjustment, and numerically controlled oscillator audio clock mapping. This enables the clock synchronization and audio stream transmission of the AES67 audio node to be adjusted to an FPGA hardware closed-loop synchronization mode, solving the problems of limited synchronization accuracy, delayed state switching, clock drift accumulation, and playback rhythm inaccuracy in the previous scheme, and improving the frequency locking accuracy and playback continuity of the audio sampling clock. Attached Figure Description

[0016] Figure 1 This is a flowchart illustrating a synchronous audio stream transmission method based on FPGA, as provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of a synchronous audio stream transmission system based on FPGA provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the internal structure of an electronic device that implements a synchronous audio stream transmission method based on FPGA, according to an embodiment of the present invention.

[0017] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0018] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0019] This application provides a synchronous audio stream transmission method based on FPGA. The execution entity of the FPGA-based synchronous audio stream transmission method includes, but is not limited to, at least one of the following electronic devices that can be configured to execute the method provided in this application embodiment: a server, a terminal, etc. The server can be a standalone server or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (CDNs), and big data and artificial intelligence platforms. In other words, the FPGA-based synchronous audio stream transmission method can be executed by software or hardware installed on a remote device or server-side device, and the software can be a blockchain platform. The server includes, but is not limited to, a single server, a server cluster, a cloud server, or a cloud server cluster.

[0020] Reference Figure 1 The diagram shown is a flowchart illustrating a synchronous audio stream transmission method based on an FPGA according to an embodiment of the present invention. In this embodiment, the synchronous audio stream transmission method based on an FPGA includes the following steps S1-S7: S1. Based on the preset PTP notification message, extract the attributes of the candidate master clock, construct the candidate comparison key, latch the information of the candidate master clock, and obtain a snapshot of the current master clock reference state.

[0021] Understandably, by extracting candidate master clock attributes based on preset PTP announcement messages and constructing candidate comparison keys, the clock quality information of multiple devices in the network can be transformed into a unified data format that can be directly compared by hardware. This allows the subsequent election algorithm to only process standardized key values, reducing the consumption of logical resources. At the same time, by latching candidate master clock information, data changes caused by the arrival of new messages during the comparison process are avoided, thus improving the stability and accuracy of the election results.

[0022] Among them, PTP announcement messages are messages that are periodically sent by PTP master clock devices or devices with master clock capabilities in the network in a multicast manner according to the message format defined by the IEEE 1588 standard. They are the basis for other devices to identify and evaluate whether the device is suitable as a master clock.

[0023] Among them, the attributes of the candidate master clock refer to the set of multi-dimensional features extracted by the FPGA from the received PTP announcement message according to the field offset positions specified by the IEEE 1588 standard to describe the clock quality of the device. These features include at least the first priority, clock level, clock accuracy, offset scaling logarithm, second priority, master clock identifier, path level, source clock identifier, and source port identifier. These attributes together constitute the complete basis for evaluating whether the device is suitable to be the master clock followed by this device.

[0024] The candidate comparison key is a fixed-width binary value formed by concatenating multiple attribute fields of the candidate master clock from the high bit to the low bit. This allows the superiority or inferiority of any two candidate master clocks to be directly determined by comparing the value of the key. The smaller key value indicates that the clock quality is better. The width of the candidate comparison key is usually 208 bits.

[0025] The candidate master clock information refers to the complete descriptive data set of a device when the FPGA receives and processes a PTP announcement message for a certain device. It includes at least the device's clock identity, port number, IP address, and corresponding candidate comparison key, which are used to uniquely identify and track the device in the subsequent master clock election process.

[0026] The current master clock reference state snapshot refers to a comprehensive data snapshot obtained by merging the information of the candidate master clock currently being evaluated with the latched current master clock reference state of the device when the step of constructing the candidate comparison key is completed. It contains complete description information of the current candidate master clock and the instantaneous value of the internal state of the device when the notification message is received. It serves as a standardized input data source for subsequent fragment comparison and identity change detection, ensuring the stability and consistency of the input data during the comparison process.

[0027] Furthermore, the step of extracting the attributes of candidate master clocks and constructing candidate comparison keys based on preset PTP notification messages includes: The PTP notification message is parsed, and multiple clock attribute fields of the candidate master clock are extracted from the specified offset position of the message; The multiple clock attribute fields are concatenated in a preset priority order to construct a candidate comparison key.

[0028] Among them, multiple clock attribute fields refer to a set of multi-dimensional features extracted by the FPGA from the specified offset position of the PTP notification message to describe the clock quality of the candidate master clock, including at least the following 9 fields: first priority, clock level, clock accuracy, offset scaling logarithmic variance, second priority, master clock identifier, path level, source clock identifier, and source port identifier.

[0029] The preset priority order refers to the pre-defined order of multiple attributes used to determine the quality of different master clock devices. The order, from high to low, is as follows: first priority, clock level, clock precision, logarithmic square of offset scaling, second priority, master clock identifier, path level, source clock identifier, and source port identifier. Priority 1 is the highest priority attribute, and the source port identifier is the lowest priority attribute. The lower-order attributes are compared only when the high-order attribute values ​​are the same. The attribute with the smaller value indicates better clock quality or higher priority. This order determines the concatenation position of each attribute field in the candidate comparison key.

[0030] S2. Obtain the reference comparison key of the candidate comparison key. Based on the current master clock reference state snapshot, divide the candidate comparison key and the reference comparison key into multiple comparison segments for comparison to obtain the segmented comparison result.

[0031] Understandably, by dividing the candidate comparison key and the reference comparison key into multiple comparison segments for parallel comparison, the wide-bit key value comparison task can be split into multiple narrow-bit subtasks, shortening the combinational logic path and increasing the FPGA operating clock frequency; at the same time, when the high-bit segment determines the winner, the low-bit segment is automatically masked to avoid invalid calculations and reduce logic resource consumption; the pipelined architecture makes the comparison process stably distributed over multiple clock cycles, improving the response speed and determination efficiency of the master clock election.

[0032] The reference comparison key refers to the attribute concatenation key value of the remote master clock currently being tracked by this device, which is latched inside the FPGA. Its bit width and concatenation order are completely consistent with the candidate comparison key, serving as the comparison benchmark for determining whether the candidate master clock is superior to the current master clock.

[0033] The segmented comparison result refers to the set of comparison status flags output in parallel by each segment comparator after the FPGA divides the complete candidate comparison key and the reference comparison key into multiple segments with the same bit width. The comparison status of each segment includes at least the segment less than flag and the segment equal flag for whether the candidate value of the segment is less than the reference value, which are used for subsequent pipeline stage synthesis of global comparison results.

[0034] Further, the step of dividing the candidate comparison key and the reference comparison key into multiple comparison segments for comparison based on the current master clock reference state snapshot to obtain a segmented comparison result includes: Based on the current master clock reference state snapshot, the candidate comparison key and the reference comparison key are synchronized and aligned, and divided into multiple comparison segments; Multiple comparison segments are compared in parallel to generate slices that are less than or equal to the results of the comparison segments. The results of the fragment being less than and the fragment being equal to are latched to obtain the fragment comparison result.

[0035] In this context, multiple comparison segments refer to dividing the complete candidate comparison key and reference comparison key into multiple equal-length sub-segments with the same start bit and bit width. For example, dividing the 208-bit candidate comparison key and reference comparison key into eight 26-bit comparison segments (the 7th segment is the most significant segment, and the 0th segment is the least significant segment) aims to decompose a wide-bit comparison task into multiple narrow-bit comparison tasks, thereby shortening the single-stage combinational logic path and increasing the FPGA operating clock frequency.

[0036] Furthermore, during the segmented comparison process, eight parallel comparators operate simultaneously, each comparing the candidate key and the reference key within the same segment. Since the priority order of the comparison keys is from high-order bits to low-order bits (segment 7 > segment 6 > ... > segment 0), the comparison result of the current segment is only valid if all high-order bits of the segment are equal. To this end, the FPGA passes a "prefix equality state" step by step in subsequent pipeline stages and reduces it step by step to generate the final result.

[0037] Furthermore, the prefix equality calculation can be decomposed into a two-level or multi-level tree structure, and pipeline registers can be set between levels to access each comparison segment; in the pipeline stage, the equality status of the candidate master clock identifier and the reference master clock identifier, the missing reference master clock status, and the comparison valid status are also calculated synchronously.

[0038] The "segment less than result" refers to the fact that when the candidate comparison key and the reference comparison key are compared on the same comparison segment, if the value of the candidate key in the segment is less than the value of the reference key, then the valid flag signal output by the parallel comparator corresponding to the segment is given. When the signal is 1, it indicates that the candidate is inferior to the reference in the current segment.

[0039] The segment comparison result refers to the set of segments corresponding to each segment that are less than the result and segments that are equal to the result after the candidate comparison key and the reference comparison key are compared in parallel.

[0040] Furthermore, when neither "less than" nor "equal to" is true, "greater than" must be true. Therefore, the "greater than" result can be logically derived from the former two. Generating additional "slice greater than result" would increase the register width and combinational logic overhead, and would not provide any new information, making it somewhat redundant.

[0041] Therefore, each comparison segment only needs to output the fragment less than result and the fragment equal to result. Subsequent pipeline stages pass the high-order prefix equal state and the fragment less than result step by step, so that a complete global comparison result containing greater than, equal to, and less than can be synthesized at the final stage.

[0042] S3. Based on the fragmentation comparison result, the candidate master clock is used as the current remote master clock to obtain the current remote master clock information. Based on the current remote master clock information, the master-slave role is determined and the master-slave role flag is obtained.

[0043] Understandably, by establishing the best candidate master clock from the fragmentation comparison results as the current remote master clock, the system always locks onto the optimal clock source in the network; based on the updated current remote master clock information, the master-slave roles are redefined to ensure that the role of this device is dynamically adjusted according to changes in network clock quality, avoiding synchronization disorder caused by role fixation; at the same time, the master-slave role flag is used as a hardware control switch for subsequent synchronization processes. Only by reading this flag can the execution of the slave clock synchronization path or the master clock announcement path be determined without software intervention, thereby improving the system's response speed and adaptability.

[0044] The current remote master clock refers to the complete set of information of the remote PTP master clock device that is currently selected by this device as the time reference source and is latched in the FPGA's internal register. It includes at least the device's clock identity, port number, IP address, and corresponding reference comparison key. It is the target clock source that this device follows when performing subsequent clock synchronization and audio stream transmission. It is empty or has a default value when the system is reset, and is replaced by a new candidate master clock after the update operation is performed in step S3.

[0045] Furthermore, the candidate master clock is the remote device currently being processed and evaluated in step S1, but not yet confirmed as the synchronization target; the current remote master clock is the remote device that has been confirmed and latched in step S3, serving as the current synchronization target. The candidate master clock is "pending," and the current remote master clock is "in place." When the candidate master clock outperforms the current remote master clock in the S2 sharding comparison, it is promoted to the new current remote master clock in step S3.

[0046] In this context, the master-slave role refers to the synchronization position of this device relative to the current remote master clock in the PTP clock synchronization network. It includes two states: master clock state and slave clock state. When the local clock quality of this device is better than that of the current remote master clock, the role is master clock. When the local clock quality of this device is worse than that of the current remote master clock, the role is slave clock. In the master clock state, this device does not need to follow any remote clock source and needs to send PTP announcement messages. In the slave clock state, this device needs to continuously receive and process the synchronization messages of the current remote master clock to calibrate the local clock.

[0047] Furthermore, the master clock state and slave clock state belong to the automatic election mode. In addition, there are forced master clock mode and slave-only clock mode. In forced master clock mode, the comparison result of the remote master clock is ignored, and the local device is directly set as the master clock. In slave-only clock mode, the comparison result of the local clock is ignored, and the local device is forced to be set as the slave clock and follow the remote master clock.

[0048] The master-slave role flag is a binary status value stored in the FPGA's internal register, used to identify the current synchronization position of the device. This flag is written in step S3 based on the comparison result between the current remote master clock and the local clock. A value of 0 indicates that the device is in slave clock state, and a value of 1 indicates that the device is in master clock state. This flag serves as a global control switch for multiple hardware modules such as identity change detection, synchronization message reception enable, clock cycle adjustment, and audio transmission control. Each module only needs to read this flag to determine its own execution path without software intervention.

[0049] Further, determining the master-slave role based on the current remote master clock information and obtaining the master-slave role flag includes: The steps involve monitoring the current remote master clock using a preset liveness counter, triggering a failure reselection when the liveness counter reaches zero, obtaining a failure reselection trigger signal, returning a PTP notification message based on a preset value, extracting the attributes of candidate master clocks, constructing candidate comparison keys, latching the information of the candidate master clocks, and obtaining a snapshot of the current master clock reference state.

[0050] The preset liveness counter is a hardware decrement counter set inside the FPGA. This counter is reset to a preset maximum value (e.g., 3 seconds) each time a PTP notification message from the current remote master clock is successfully received. It then automatically decrements in each clock cycle or fixed time interval. Its function is to continuously monitor whether the current remote master clock is still running normally. When the counter reaches zero, it means that the current remote master clock has not sent a notification message for a long time, and is therefore determined to be inactive.

[0051] Among them, failure reselection refers to the mechanism in which the system actively abandons the current failed master clock relationship and restarts the entire master clock election process (i.e., returns to S1 to start again) when the current remote master clock is detected to be inactive, identity changes, or local role changes. Its purpose is to quickly restore the system's clock synchronization capability when the network topology changes or the master clock fails.

[0052] The failure reselection trigger signal is a pulse flag signal automatically generated by the hardware when the survival counter returns to zero. This signal is used to notify the master state machine that the current remote master clock has failed, triggering the state machine to jump back to step S1 to restart the election. At the same time, this signal also resets the current reference comparison key register to the maximum value (all 1s) to ensure that the next received candidate master clock can be unconditionally accepted as the new master clock.

[0053] S4. When a preset event is detected, a master clock rebinding event is generated based on the master-slave role flag, and the generation flag of the current remote master clock is updated to obtain a rebinding ready state.

[0054] Understandably, by detecting preset events and triggering the rebinding process, a rebinding event can be quickly generated and the generation flag updated when the master clock relationship is abnormal or changes. This ensures that all subsequent synchronization messages carry the new generation flag, and all timestamps, delay requests, and servo states of the old generation are automatically masked and isolated in the pipeline. After the generation flag is updated, newly received synchronization messages are completely isolated from old data at the hardware level. State switching can be achieved without clearing each register individually, and a usable synchronization-ready state can be restored in a very short time. This effectively avoids data residue and state conflicts during clock switching, ensuring the rapid recovery and continuous stability of the synchronization link.

[0055] Among them, the preset events refer to the set of pre-set triggering conditions that will cause the current master clock synchronization relationship to fail and require re-establishment of synchronization. These include at least three types: remote master clock inactivation event, identity change event, and local role change event. The remote master clock inactivation event is triggered when the survival counter reaches zero. The identity change event is triggered when the newly received candidate master clock identity identifier is inconsistent with the currently latched master clock identity identifier. The local role change event is triggered when the master-slave role flag bit changes. The three events are detected independently, and the rebinding process is triggered when any event occurs.

[0056] Among them, the master clock rebinding event refers to an internal trigger pulse signal automatically generated by the FPGA hardware logic when a preset event occurs. This signal serves as the start flag of the S4 process and is used to notify subsequent logic that the current master clock synchronization relationship has failed and a rebinding operation needs to be performed immediately. After the event is generated, the hardware will latch the current PTP time as the rebinding timestamp and start a series of subsequent actions such as generation mark update and old state clearing.

[0057] Furthermore, in response to this event, the master clock generation marker is updated, forming a commit barrier for at least one clock cycle to prevent old timestamps and old delay responses from entering the new servo calculation. To reduce the impact of audio clock switching, during rebinding, it is possible to either maintain the stable local clock cycle before the switch or restore it to the nominal cycle; once the effective servo adjustment amount of the new master clock is obtained, it is then gradually adjusted to the target cycle in a manner that each adjustment cycle does not exceed a preset step size.

[0058] The generation flag of the current remote master clock is a monotonically increasing value stored in the FPGA's internal register. It is used to identify the generation to which the current master clock synchronization relationship belongs. The flag is automatically incremented by one each time a master clock rebinding event occurs. All received PTP synchronization messages and delay measurement messages carry this flag. During the message verification phase, the hardware only processes messages whose generation flag matches the current value. Messages with different generation flags are automatically discarded in the pipeline, thereby achieving hardware-level isolation between old and new synchronization data without having to clear registers one by one.

[0059] The rebinding ready state refers to a valid flag stored in the FPGA's internal register. This flag is automatically set by the hardware when all cleanup actions are completed after the master clock rebinding event. A valid flag indicates that the current system is in a state where it can safely restart synchronization. Before receiving and processing synchronization messages, the subsequent S5 steps need to check whether this flag is valid. If it is invalid, all newly received synchronization messages are discarded and the rebinding is waited for to complete. If it is valid, the normal synchronization process is allowed to start, thus ensuring that S5 will not mistakenly use old data for deviation calculation when the data is inconsistent.

[0060] Furthermore, the step of generating a master clock rebinding event based on the master-slave role flag when a preset event is detected includes: Obtain the current state and the previous latch state of the master-slave role flag, and compare the current state and the previous latch state of the master-slave role flag. If the current state of the master-slave role flag is inconsistent with the previous latch state, then the local role is determined to have changed based on the master-slave role flag, triggering rebinding and generating a master clock rebinding event.

[0061] The current state refers to the master-slave role flag value that is stored in the FPGA's internal register at the current moment and last written by step S3. This value is updated when S3 completes the master-slave role re-determination, indicating the synchronization position of this device at that moment (Slave=0 or Master=1).

[0062] The previous latch state refers to the historical value of the master-slave role flag stored in the FPGA's internal register during the previous S3 master-slave role determination cycle. This value is updated and overwritten by the current state value after each S3 role determination is completed. It is used to compare with the current state to detect whether the master-slave role has changed.

[0063] Rebinding refers to a complete state reset process executed by the FPGA when the current master clock synchronization relationship is detected to be invalid or changed. It includes at least generating a rebinding event, latching the current PTP time as a rebinding timestamp, incrementing the generation flag register value of the current remote master clock by one, clearing the old timestamp register, clearing the incomplete delay request status and resetting the clock servo integration status, and finally outputting the rebinding ready state, so that the system can restart synchronization tracking in a clean and isolated hardware environment.

[0064] Among them, the change of local role refers to the change of the synchronization position state of the device itself. Specifically, the current state of the master-slave role flag stored in the FPGA internal register is inconsistent with the latch state at the previous moment, including two cases: switching from slave clock state to master clock state (0→1) or switching from master clock state to slave clock state (1→0).

[0065] Furthermore, the local role change occurs after the master-slave role re-determination is completed in step S3. It is triggered when the newly determined role differs from the original role. This change is one of three preset events in step S4, alongside remote master clock deactivation and identity change. The occurrence of any of these events initiates the master clock rebinding process, ensuring that the system can immediately clear old synchronization data and use the new role to configure subsequent hardware behavior paths after a role switch. A change in the master-slave role flag value indicates a local role change.

[0066] In another embodiment of the present invention, when the preset event is remote master clock inactivation, identity change, or local role change, the step of generating a master clock rebinding event based on the master-slave role flag when the preset event is detected includes: The liveness counter in the current remote master clock information is periodically decremented, and the liveness counter is monitored to see if it returns to zero. If the survival counter reaches zero, the remote master clock is determined to be inactive, triggering a rebinding event; Obtain the new identity identifier of the candidate master clock in the newly received PTP notification message, and compare the new identity identifier of the candidate master clock with the master clock identity identifier in the current remote master clock information; If the new identity identifier of the candidate master clock is inconsistent with the master clock identity identifier in the current remote master clock information, then an identity change is determined and a rebinding event is triggered. Obtain the current state of the master-slave role flag and compare it with the master-slave role flag state latched at the previous moment; If the current state of the master-slave role flag is inconsistent with the state locked at the previous moment, it is determined that the local role has changed and a rebinding event is triggered. When any one of the inactivation determination, the identity change determination, or the role change determination is met, a master clock rebinding event is generated.

[0067] In this embodiment, by independently monitoring three types of preset events and triggering rebinding when any one of them occurs, the system can proactively detect synchronization relationship failures and promptly initiate state reset, avoiding the use of failed master clock data for continued synchronization and improving the self-healing and recovery capability of the synchronization link under abnormal conditions.

[0068] S5. When the rebinding ready state is valid, multiple timestamps are obtained based on the generation mark of the current remote master clock and the current remote master clock information, and the time deviation is calculated based on the multiple timestamps.

[0069] Understandably, by using the rebinding ready state as the starting condition and the generation mark and current remote master clock information as the filtering criteria, it ensures that timestamps are extracted and deviations are calculated only on messages with correct verification sources and belonging to the current synchronization generation, avoiding old data residues or interfering messages from polluting the calculation results, thus improving the accuracy and reliability of time deviation calculation.

[0070] Among them, multiple timestamps refer to four time values ​​extracted from synchronization messages and delay measurement messages within the same master clock generation, including the time t1 when the master clock sends the Sync message, the time t2 when the slave clock receives the Sync message, the time t3 when the slave clock sends the Delay_Req message, and the time t4 when the master clock receives the Delay_Req message. t1 and t4 are parsed from the messages, while t2 and t3 are automatically latched by the FPGA hardware when the messages enter and leave the physical layer.

[0071] The time deviation refers to the time difference between the local PTP clock of this device and the current remote master clock, calculated based on four timestamps. It is a signed value in nanoseconds. A positive value indicates that the local clock is lagging behind the master clock, and a negative value indicates that the local clock is ahead of the master clock. This value is directly used as the input basis for subsequent clock cycle adjustments.

[0072] Furthermore, when the rebinding ready state is valid, multiple timestamps are obtained based on the generation flag of the current remote master clock and the current remote master clock information, including: Check whether the rebinding ready state is valid; If the rebinding ready state is valid, then obtain the synchronization message and the generation tag of the synchronization message, as well as the delay measurement message and the generation tag of the delay measurement message; Based on the generation flag of the current remote master clock, determine whether the generation flags of the synchronization message and the delay measurement message are consistent; If the generation markers are consistent, the source identifier and source port number are extracted from the synchronization message and the delay measurement message, and the source identifier and source port number are compared with the master clock identifier and port number in the current remote master clock information; If the source identity and the source port number match, the sequence numbers of the synchronization message and the delay measurement message are extracted and their continuity is verified with the sequence numbers of the previous synchronization message and the previous delay measurement message. If the continuity check passes, the timestamps of the synchronization message and the delay measurement message are extracted to obtain the multiple timestamps.

[0073] Among them, the synchronization message refers to the Sync message that the current remote master clock periodically sends according to the time interval specified by the PTP protocol, and the Follow_Up message that follows it with the master clock’s precise sending timestamp. It is used to transmit the current time information of the master clock to the slave clock, so that the slave clock can obtain the master clock’s sending time t1 and local receiving time t2.

[0074] The generation flag of the synchronization message refers to the flag field embedded in the synchronization message and the Follow_Up message. Its value is equal to the generation flag of the current remote master clock. It is filled in by the master clock when sending the message and is used by the slave clock to verify whether the message belongs to the current valid synchronization generation in step S5.

[0075] Among them, the delay measurement message refers to the message pair initiated by the clock to measure the uplink transmission delay of the network, including the Delay_Req message sent by the clock and the Delay_Resp message replied by the master clock, which is used to obtain the sending time t3 of the clock and the receiving time t4 of the master clock.

[0076] The generation flag of the delay measurement message refers to the flag field embedded in the Delay_Req message and the Delay_Resp message. Its value is equal to the generation flag of the current remote master clock. It is filled in by the message sender and is used by the slave clock to verify in step S5 whether the delay measurement message pair belongs to the current valid synchronization generation.

[0077] The source identity identifier refers to the clock identity identifier of the sending device embedded in the synchronization message and the delay measurement message. It is filled in by the message sending end and is used to compare with the master clock identity identifier in the current remote master clock information in step S5 to confirm whether the message comes from the currently locked master clock and prevent interference messages from other devices from participating in the synchronization calculation.

[0078] The source port number refers to the PTP protocol port number of the sending device embedded in the synchronization message and the delay measurement message. It is used to compare with the port number in the current remote master clock information in step S5 to further confirm the correctness of the message source.

[0079] The sequence number of the synchronization message refers to the sequence ID embedded in the Sync message and the Follow_Up message. It is incremented sequentially by the master clock during transmission and is used for continuity verification in step S5 to ensure that the sequence number of the Sync message matches the corresponding Follow_Up message, thus preventing mismatch between t1 and t2 caused by network out-of-order delivery.

[0080] The sequence number of the delay measurement message refers to the sequence ID embedded in the Delay_Req message and the Delay_Resp message. It is filled in by the slave clock when sending Delay_Req and returned unchanged by the master clock when replying to Delay_Resp. It is used in step S5 to confirm that the Delay_Resp message corresponds one-to-one with the previously sent Delay_Req message, and to prevent mismatch between delay request and delay response from causing errors in the calculation of t3 and t4.

[0081] Further, the calculation of time deviation based on the plurality of timestamps includes: Obtain the first and second timestamps from the plurality of timestamps, and calculate the first difference between the first timestamp and the second timestamp; Obtain the third and fourth timestamps from the plurality of timestamps, and calculate the second difference between the third and fourth timestamps; The difference between the first difference and the second difference is calculated to obtain a third difference, and half of the third difference is taken as the time deviation.

[0082] In another embodiment of the present invention, the first difference is referred to as the synchronization message transmission delay, and the second difference is referred to as the delay measurement message transmission delay.

[0083] S6. Filter and integrate the time deviation to obtain the clock cycle adjustment amount, adjust the preset local clock cycle according to the clock cycle adjustment amount to obtain the local clock adjustment cycle, and obtain the local PTP time according to the local clock cycle.

[0084] Understandably, by filtering and integrating, instantaneous deviation noise is filtered out and long-term static frequency deviation is eliminated. The time deviation is converted into a local clock cycle adjustment and the local clock is corrected, so that the local clock continuously tracks the master clock, achieving stable and reliable high-precision synchronization.

[0085] The clock cycle adjustment refers to the value calculated by the proportional-integral controller in step S6 based on the input time deviation, used to correct the increment step size of the local PTP clock counter. It is a signed value in nanoseconds or sub-nanoseconds. A positive value indicates that the increment step size of the local clock needs to be increased to catch up with the master clock, while a negative value indicates that the increment step size of the local clock needs to be decreased to slow down and wait for the master clock. This value directly affects the local clock cycle control register and serves as a bridge connecting deviation calculation and physical clock adjustment.

[0086] The local clock cycle refers to the time interval between two consecutive increments of the PTP hardware counter inside the FPGA. It is generated by dividing the local crystal oscillator. The nominal value of this cycle is usually a fixed value (e.g., 8ns corresponds to a 125MHz clock), but its actual length can be finely adjusted by writing the clock cycle adjustment amount, thereby achieving fine control of the local clock frequency. It is a basic parameter at the physical execution level of clock discipline.

[0087] Adjusting the local clock cycle refers to superimposing the clock cycle adjustment amount calculated by S6 with the current local clock cycle value to generate a new clock cycle control word and writing it into the frequency control register of the DCO (digitally controlled oscillator) or clock divider. This causes the local PTP counter to subsequently increase with the corrected step size, thereby making the local clock frequency continuously approach the master clock and ultimately achieving long-term synchronization with the master clock.

[0088] The local PTP time refers to the current reading of the PTP hardware counter inside the FPGA, which continuously increases in steps with the corrected local clock period. This time value has been kept synchronized with the master clock through closed-loop adjustment of the time deviation and serves as the physical time reference for the generation of the RTP timestamp, with an accuracy of sub-microseconds.

[0089] Furthermore, the time deviation is low-pass filtered to form a proportional adjustment amount, and the filtered time deviation is accumulated to form an integral adjustment amount. The sum of the proportional adjustment amount and the integral adjustment amount is saturated and limited to serve as the clock cycle adjustment amount. When the clock cycle adjustment amount is within the locking threshold for multiple consecutive adjustment cycles, the clock lock state is output. When the clock cycle adjustment amount exceeds the exit threshold, the clock lock state is cleared.

[0090] S7. Adjust the local clock cycle as described above, drive the preset numerically controlled oscillator to generate an audio sampling clock, generate an RTP timestamp based on the local PTP time, and control audio playback based on the audio sampling clock and the RTP timestamp.

[0091] Understandably, by driving a numerically controlled oscillator to generate an audio sampling clock based on the adjusted local clock cycle, the clock information calibrated by PI control can be directly mapped to the audio sampling rate, ensuring that the frequency and phase of the audio sampling clock are strictly synchronized with the network master clock, avoiding audio sampling point drift or buffer underload / overflow caused by clock frequency deviation; at the same time, using the audio sampling clock as the control reference for audio playback ensures that the audio data is output at a rhythm completely consistent with the master clock, eliminating abnormal phenomena such as stuttering, popping, or speed changes during playback, and ensuring the continuity and stability of audio output.

[0092] The numerically controlled oscillator refers to a programmable clock generator hardware module built inside the FPGA based on direct digital frequency synthesis technology. It receives an externally input reference clock and frequency control word, and outputs a periodic clock signal whose frequency can be precisely adjusted by the control word through digital logic circuits such as a phase accumulator and a lookup table. In this scheme, the control word is derived from the adjustment of the local clock period value. By adjusting the control word, the output clock frequency is kept in sync with the master clock.

[0093] The audio sampling clock refers to the periodic square wave signal output by the numerically controlled oscillator, which is used to drive the audio codec or digital audio interface to perform digital-to-analog conversion. Each beat of this clock determines the time interval for audio data to be sent into the DAC. When the frequency and phase of this clock are locked with the network master clock, the rhythm of the audio output is consistent with that of other nodes in the network.

[0094] For example, with an audio sampling rate of 48kHz, a numerically controlled oscillator generates a 24.576MHz audio master clock. An initial RTP timestamp value is generated based on the second and nanosecond fields of the synchronized PTP time and the audio sampling rate, and this initial value is incremented by a corresponding step size for each audio sample point or each audio data packet. The receiving side writes the RTP audio payload corresponding to the initial RTP timestamp value into the audio buffer. When the buffer level reaches a threshold, valid audio output is allowed. The audio playback is controlled collaboratively based on the audio sampling clock, RTP timestamp, and audio buffer level, which improves audio output stability under network jitter, packet loss, and master clock switching conditions.

[0095] The RTP timestamp is a 32-bit unsigned integer field filled in the header of an RTP (Real-Time Transport Protocol) data packet. It is used to indicate the sampling time of the first audio sample point in the RTP packet, so that the receiving end can recover the audio data stream in the correct timing.

[0096] Furthermore, this timestamp is not a random value, but is calculated by the sender based on the current local PTP time. The receiver determines the playback interval of audio sampling points by comparing the timestamp differences of adjacent RTP packets, thereby ensuring continuous playback of audio data and cross-device synchronization.

[0097] This invention extracts candidate master clock attributes from PTP notification messages to construct candidate comparison keys, and latches a snapshot of the current master clock reference state. The candidate comparison keys are then compared with the reference comparison key in segments to obtain segment comparison results. Based on these results, the candidate is designated as the current remote master clock, and a flag is used to re-determine the master-slave roles. A preset event triggers rebinding and updates the generation flag to obtain a ready state. Upon ready state, the timestamp is extracted based on the generation flag and the current remote master clock information to calculate the deviation. The period adjustment is obtained through filtering and integration, and the local clock period is adjusted. A digitally controlled oscillator is driven to generate an audio sampling clock for stable playback. Therefore, the FPGA-based synchronous audio stream transmission method, system, electronic device, and computer-readable storage medium proposed in this invention construct a synchronous audio transmission architecture centered on PTP master clock election and dynamic role determination, generation mark isolation and rebinding mechanism, timestamp extraction and proportional-integral adjustment, and numerically controlled oscillator audio clock mapping. This enables the clock synchronization and audio stream transmission of the AES67 audio node to be adjusted to an FPGA hardware closed-loop synchronization mode, solving the problems of limited synchronization accuracy, delayed state switching, clock drift accumulation, and playback rhythm inaccuracy in the previous scheme, and improving the frequency locking accuracy and playback continuity of the audio sampling clock.

[0098] like Figure 2 The diagram shown is a schematic of the module of the synchronous audio stream transmission system based on FPGA of the present invention.

[0099] The FPGA-based synchronous audio stream transmission system 100 described in this invention can be installed in an electronic device. Depending on the functions implemented, the FPGA-based synchronous audio stream transmission system may include a segment comparison module 101, a master-slave determination module 102, an offset calculation module 103, and a playback control module 104. The module described in this invention can also be called a unit, which refers to a series of computer program segments that can be executed by the processor of an electronic device and can perform a fixed function, and are stored in the memory of the electronic device.

[0100] In this embodiment, the functions of each module / unit are as follows: The segment comparison module 101 is used to extract the attributes of the candidate master clock based on the preset PTP announcement message, construct the candidate comparison key, latch the information of the candidate master clock, and obtain a snapshot of the current master clock reference state. Based on the current master clock reference state snapshot, the candidate comparison key and the preset reference comparison key are divided into multiple comparison segments for comparison to obtain the segmented comparison result; The master-slave determination module 102 is used to determine the candidate master clock as the current remote master clock based on the fragmentation comparison result, obtain the current remote master clock information, determine the master-slave role based on the current remote master clock information, and obtain the master-slave role flag bit. The deviation calculation module 103 is used to generate a master clock rebinding event based on the master-slave role flag bit when a preset event is detected, and update the generation flag of the current remote master clock to obtain a rebinding ready state. When the rebinding ready state is valid, multiple timestamps are obtained based on the generation flag of the current remote master clock and the current remote master clock information, and the time deviation is calculated based on the multiple timestamps. The playback control module 104 is used to filter and integrate the time deviation to obtain a clock cycle adjustment amount, adjust the preset local clock cycle according to the clock cycle adjustment amount to obtain a local clock adjustment cycle, and obtain the local PTP time according to the local clock cycle. According to the adjustment of the local clock cycle, a preset numerically controlled oscillator is driven to generate an audio sampling clock, an RTP timestamp is generated according to the local PTP time, and audio playback is controlled according to the audio sampling clock and the RTP timestamp.

[0101] In detail, the modules in the FPGA-based synchronous audio stream transmission system 100 described in this embodiment of the invention employ the same methods as described above. Figure 1 The method used is the same as the FPGA-based synchronous audio stream transmission method and can produce the same technical effect, so it will not be described in detail here.

[0102] like Figure 3 The diagram shown is a structural schematic of an electronic device that implements the FPGA-based synchronous audio stream transmission method of the present invention.

[0103] The electronic device may include a processor 10, a memory 11, a communication bus 12, and a communication interface 13. It may also include a computer program stored in the memory 11 and capable of running on the processor 10, such as an FPGA-based synchronous audio stream transmission program.

[0104] In some embodiments, the processor 10 may be composed of integrated circuits, such as a single packaged integrated circuit or multiple integrated circuits with the same or different functions, including combinations of one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and various control chips. The processor 10 is the control unit of the electronic device, connecting various components of the entire electronic device through various interfaces and lines. It executes programs or modules stored in the memory 11 (e.g., executing a synchronous audio stream transmission program based on an FPGA) and calls data stored in the memory 11 to perform various functions of the electronic device and process data.

[0105] The memory 11 includes at least one type of readable storage medium, including flash memory, portable hard drive, multimedia card, card-type memory (e.g., SD or DX memory), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, the memory 11 can be an internal storage unit of an electronic device, such as a portable hard drive. In other embodiments, the memory 11 can be an external storage device of the electronic device, such as a plug-in portable hard drive, Smart Media Card (SMC), Secure Digital (SD) card, Flash Card, etc. Furthermore, the memory 11 can include both internal and external storage units of the electronic device. The memory 11 can be used not only to store application software and various types of data installed on the electronic device, such as the code of a synchronous audio stream transmission program based on an FPGA, but also to temporarily store data that has been output or will be output.

[0106] The communication bus 12 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This bus can be divided into an address bus, a data bus, a control bus, etc. The bus is configured to enable communication between the memory 11 and at least one processor 10, etc.

[0107] The communication interface 13 is used for communication between the aforementioned electronic device and other devices, including a network interface and a user interface. Optionally, the network interface may include a wired interface and / or a wireless interface (such as a Wi-Fi interface, Bluetooth interface, etc.), typically used to establish communication connections between the electronic device and other electronic devices. The user interface may be a display, an input unit (such as a keyboard), or optionally, a standard wired or wireless interface. Optionally, in some embodiments, the display may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, or an OLED (Organic Light-Emitting Diode) touchscreen, etc. The display may also be appropriately referred to as a screen or display unit, used to display information processed in the electronic device and to display a visual user interface.

[0108] Figure 3 Only electronic devices with components are shown; it will be understood by those skilled in the art that... Figure 3 The structure shown does not constitute a limitation on the electronic device and may include fewer or more components than shown, or combine certain components, or have different component arrangements.

[0109] For example, although not shown, the electronic device may also include a power supply (such as a battery) to power the various components. Preferably, the power supply can be logically connected to the at least one processor 10 through a power management device, thereby enabling functions such as charging management, discharging management, and power consumption management. The power supply may also include one or more DC or AC power supplies, recharging devices, power fault detection circuits, power converters or inverters, power status indicators, and other arbitrary components. The electronic device may also include various sensors, Bluetooth modules, Wi-Fi modules, etc., which will not be described in detail here.

[0110] It should be understood that the embodiments described are for illustrative purposes only and are not limited to this structure in the scope of the patent application.

[0111] The FPGA-based synchronous audio stream transmission program stored in the memory 11 of the electronic device is a combination of multiple computer programs. When run in the processor 10, it can achieve the following: Based on the preset PTP notification message, the attributes of the candidate master clock are extracted, a candidate comparison key is constructed, the information of the candidate master clock is latched, and a snapshot of the current master clock reference state is obtained. Obtain the reference comparison key of the candidate comparison key; based on the current master clock reference state snapshot, divide the candidate comparison key and the reference comparison key into multiple comparison segments for comparison to obtain the segmented comparison result. Based on the fragmentation comparison results, the candidate master clock is selected as the current remote master clock to obtain the current remote master clock information. Based on the current remote master clock information, the master-slave roles are determined, and the master-slave role flag is obtained. When a preset event is detected, a master clock rebinding event is generated based on the master-slave role flag, and the generation flag of the current remote master clock is updated to obtain a rebinding ready state. When the rebinding ready state is valid, multiple timestamps are obtained based on the generation flag of the current remote master clock and the current remote master clock information, and the time deviation is calculated based on the multiple timestamps. The time deviation is filtered and integrated to obtain the clock cycle adjustment amount. The preset local clock cycle is adjusted according to the clock cycle adjustment amount to obtain the local clock adjustment cycle. The local PTP time is obtained according to the local clock cycle. According to the adjustment of the local clock cycle, a preset numerically controlled oscillator is driven to generate an audio sampling clock, an RTP timestamp is generated according to the local PTP time, and audio playback is controlled according to the audio sampling clock and the RTP timestamp.

[0112] Specifically, the processor 10's implementation method of the above-mentioned computer program can be found in [reference needed]. Figure 1 The descriptions of the relevant steps in the corresponding embodiments are not repeated here.

[0113] Furthermore, if the modules / units integrated into the electronic device are implemented as software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium. The computer-readable storage medium can be volatile or non-volatile. For example, the computer-readable medium may include: any entity or device capable of carrying the computer program code, a recording medium, a USB flash drive, a portable hard drive, a magnetic disk, an optical disk, a computer memory, or a read-only memory (ROM).

[0114] The present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor of an electronic device, can perform the following: Based on the preset PTP notification message, the attributes of the candidate master clock are extracted, a candidate comparison key is constructed, the information of the candidate master clock is latched, and a snapshot of the current master clock reference state is obtained. Obtain the reference comparison key of the candidate comparison key; based on the current master clock reference state snapshot, divide the candidate comparison key and the reference comparison key into multiple comparison segments for comparison to obtain the segmented comparison result. Based on the fragmentation comparison results, the candidate master clock is selected as the current remote master clock to obtain the current remote master clock information. Based on the current remote master clock information, the master-slave roles are determined, and the master-slave role flag is obtained. When a preset event is detected, a master clock rebinding event is generated based on the master-slave role flag, and the generation flag of the current remote master clock is updated to obtain a rebinding ready state. When the rebinding ready state is valid, multiple timestamps are obtained based on the generation flag of the current remote master clock and the current remote master clock information, and the time deviation is calculated based on the multiple timestamps. The time deviation is filtered and integrated to obtain the clock cycle adjustment amount. The preset local clock cycle is adjusted according to the clock cycle adjustment amount to obtain the local clock adjustment cycle. The local PTP time is obtained according to the local clock cycle. According to the adjustment of the local clock cycle, a preset numerically controlled oscillator is driven to generate an audio sampling clock, an RTP timestamp is generated according to the local PTP time, and audio playback is controlled according to the audio sampling clock and the RTP timestamp.

[0115] In the several embodiments provided by this invention, it should be understood that the disclosed devices, systems, and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and other division methods may be used in actual implementation.

[0116] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0117] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in the form of hardware plus software functional modules.

[0118] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0119] Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be embraced within the invention. No appended diagram markings in the claims should be construed as limiting the scope of the claims.

[0120] The blockchain referred to in this invention is a novel application model of computer technologies such as distributed data storage, peer-to-peer transmission, consensus mechanisms, and encryption algorithms. Essentially, a blockchain is a decentralized database, a chain of data blocks linked together using cryptographic methods. Each data block contains information about a batch of network transactions, used to verify the validity of the information (anti-counterfeiting) and generate the next block. A blockchain can include an underlying blockchain platform, a platform product service layer, and an application service layer.

[0121] The embodiments of this application can acquire and process relevant data based on artificial intelligence technology. Artificial intelligence (AI) refers to the theories, methods, technologies, and application systems that use digital computers or machines controlled by digital computers to simulate, extend, and expand human intelligence, perceive the environment, acquire knowledge, and use that knowledge to obtain optimal results.

[0122] Furthermore, it is clear that the word "comprising" does not exclude other units or steps, and the singular does not exclude the plural. Multiple units or systems stated in a system claim may also be implemented by a single unit or system through software or hardware. The term "second class" is used to indicate names and does not indicate any specific order.

[0123] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A synchronous audio stream transmission method based on FPGA, characterized in that, The method includes: Based on the preset PTP notification message, the attributes of the candidate master clock are extracted, a candidate comparison key is constructed, the information of the candidate master clock is latched, and a snapshot of the current master clock reference state is obtained. Obtain the reference comparison key of the candidate comparison key; based on the current master clock reference state snapshot, divide the candidate comparison key and the reference comparison key into multiple comparison segments for comparison to obtain the segmented comparison result. Based on the fragmentation comparison results, the candidate master clock is selected as the current remote master clock to obtain the current remote master clock information. Based on the current remote master clock information, the master-slave roles are determined, and the master-slave role flag is obtained. When a preset event is detected, a master clock rebinding event is generated based on the master-slave role flag, and the generation flag of the current remote master clock is updated to obtain a rebinding ready state. When the rebinding ready state is valid, multiple timestamps are obtained based on the generation flag of the current remote master clock and the current remote master clock information, and the time deviation is calculated based on the multiple timestamps. The time deviation is filtered and integrated to obtain the clock cycle adjustment amount. The preset local clock cycle is adjusted according to the clock cycle adjustment amount to obtain the local clock adjustment cycle. The local PTP time is obtained according to the local clock cycle. The audio sampling clock is generated by driving a preset numerically controlled oscillator according to the local clock adjustment period, and an RTP timestamp is generated according to the local PTP time. Audio playback is controlled according to the audio sampling clock and the RTP timestamp.

2. The FPGA-based synchronous audio stream transmission method as described in claim 1, characterized in that, The process of extracting attributes of candidate master clocks and constructing candidate comparison keys based on preset PTP announcement messages includes: The PTP notification message is parsed, and multiple clock attribute fields of the candidate master clock are extracted from the specified offset position of the message; The multiple clock attribute fields are concatenated in a preset priority order to construct a candidate comparison key.

3. The FPGA-based synchronous audio stream transmission method as described in claim 1, characterized in that, The step of dividing the candidate comparison key and the preset reference comparison key into multiple comparison segments for comparison based on the current master clock reference state snapshot, and obtaining the segmented comparison result, includes: Based on the current master clock reference state snapshot, the candidate comparison key and the reference comparison key are synchronized and aligned, and divided into multiple comparison segments; Multiple comparison segments are compared in parallel to generate slices that are less than or equal to the results of the comparison segments. The results of the fragment being less than and the fragment being equal to are latched to obtain the fragment comparison result.

4. The FPGA-based synchronous audio stream transmission method as described in claim 1, characterized in that, The step of determining the master / slave role based on the current remote master clock information and obtaining the master / slave role flag includes: The steps involve monitoring the current remote master clock using a preset liveness counter, triggering a failure reselection when the liveness counter reaches zero, obtaining a failure reselection trigger signal, returning a PTP notification message based on a preset value, extracting the attributes of candidate master clocks, constructing candidate comparison keys, latching the information of the candidate master clocks, and obtaining a snapshot of the current master clock reference state.

5. The FPGA-based synchronous audio stream transmission method as described in claim 1, characterized in that, The step of generating a master clock rebinding event based on the master-slave role flag when a preset event is detected includes: Obtain the current state and the previous latch state of the master-slave role flag, and compare the current state and the previous latch state of the master-slave role flag. If the current state of the master-slave role flag is inconsistent with the previous latch state, then the local role is determined to have changed based on the master-slave role flag, triggering rebinding and generating a master clock rebinding event.

6. The FPGA-based synchronous audio stream transmission method as described in claim 1, characterized in that, When the rebinding ready state is valid, multiple timestamps are obtained based on the generation flag and current remote master clock information, including: Check whether the rebinding ready state is valid; If the rebinding ready state is valid, then obtain the synchronization message and the generation tag of the synchronization message, as well as the delay measurement message and the generation tag of the delay measurement message; Based on the generation flag of the current remote master clock, determine whether the generation flags of the synchronization message and the delay measurement message are consistent; If the generation markers are consistent, the source identifier and source port number are extracted from the synchronization message and the delay measurement message, and the source identifier and source port number are compared with the master clock identifier and port number in the current remote master clock information; If the source identity and the source port number match, the sequence numbers of the synchronization message and the delay measurement message are extracted and their continuity is verified with the sequence numbers of the previous synchronization message and the previous delay measurement message. If the continuity check passes, the timestamps of the synchronization message and the delay measurement message are extracted to obtain the multiple timestamps.

7. The FPGA-based synchronous audio stream transmission method as described in claim 1, characterized in that, The calculation of time deviation based on the multiple timestamps includes: Obtain the first and second timestamps from the plurality of timestamps, and calculate the first difference between the first timestamp and the second timestamp; Obtain the third and fourth timestamps from the plurality of timestamps, and calculate the second difference between the third and fourth timestamps; The difference between the first difference and the second difference is calculated to obtain a third difference, and half of the third difference is taken as the time deviation.

8. A synchronous audio stream transmission system based on FPGA, characterized in that, The system includes: The shard comparison module is used to extract the attributes of candidate master clocks based on preset PTP announcement messages, construct candidate comparison keys, latch the information of the candidate master clocks, and obtain a snapshot of the current master clock reference state. Based on the current master clock reference state snapshot, the candidate comparison key and the preset reference comparison key are divided into multiple comparison segments for comparison to obtain the segmented comparison result; The master-slave determination module is used to determine the master-slave role based on the fragmentation comparison result, select the candidate master clock as the current remote master clock, obtain the current remote master clock information, determine the master-slave role based on the current remote master clock information, and obtain the master-slave role flag bit. The deviation calculation module is used to generate a master clock rebinding event based on the master-slave role flag when a preset event is detected, and update the generation flag of the current remote master clock to obtain a rebinding ready state. When the rebinding ready state is valid, multiple timestamps are obtained based on the generation flag of the current remote master clock and the current remote master clock information, and the time deviation is calculated based on the multiple timestamps. The playback control module is used to filter and integrate the time deviation to obtain the clock cycle adjustment amount, adjust the preset local clock cycle according to the clock cycle adjustment amount to obtain the local clock adjustment cycle, and obtain the local PTP time according to the local clock cycle. The audio sampling clock is generated by driving a preset numerically controlled oscillator according to the local clock adjustment period, and an RTP timestamp is generated according to the local PTP time. Audio playback is controlled according to the audio sampling clock and the RTP timestamp.

9. An electronic device, characterized in that, The electronic device includes: At least one processor; and, A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor to enable the at least one processor to perform the FPGA-based synchronous audio stream transmission method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, It includes a data storage area and a program storage area. The data storage area stores the created data, and the program storage area stores the computer program. When the computer program is executed by the processor, it implements the FPGA-based synchronous audio stream transmission method as described in any one of claims 1 to 7.

Images