An encoding, decoding method and communication device

Abstract

The application provides an encoding and decoding method and a communication device, and relates to the technical field of communication encoding. The method comprises the following steps: a first device acquires a log-likelihood ratio sequence; a first bit sequence is determined according to P decoders and the log-likelihood ratio sequence; a codeword sequence is determined according to P encoders, the first bit sequence and an information bit sequence; and the codeword sequence is output, wherein the P decoders comprise a first decoder, the first decoder is an RM decoder, P is an integer greater than or equal to 1, the first bit sequence is used for probability shaping, the P encoders comprise a first encoder, and the first encoder is an RM encoder. The method only needs to decode the first bit sequence by using the first decoder, and does not need to decode the information bit sequence, so that the decoding process is simplified, the decoding complexity is reduced, and low-complexity probability shaping can be realized.

Description

Technical Field

[0001] This application relates to the field of communication coding technology, and in particular to an encoding and decoding method and a communication device. Background Technology

[0002] Channel coding is one of the core technologies in wireless communication. In third-generation (3G) and fourth-generation (4G) mobile communication technologies, turbo codes, as an encoding and decoding technology defined by the 3rd Generation Partnership Project (3GPP) standard, exhibit excellent performance, approaching the limits of Shannon's theory. In fifth-generation (5G) mobile communication technologies, data transmission rates are orders of magnitude higher than in 4G, and 5G mobile communication systems include a wider range of service applications, placing new demands on channel coding technologies. For example, massive machine-type communications (mMTC) scenarios require smaller data packets, while ultra-reliable low-latency communication (uRLLC) scenarios have high requirements for encoding and decoding latency and low bit error rate. Therefore, based on the key channel coding requirements of 5G application scenarios, the 5G standard adopts low-density parity-check (LDPC) codes and polar codes. Compared to traditional encoding methods, LDPC codes and polar codes offer superior performance, approaching the limits of Shannon's theory.

[0003] To achieve greater performance gains, the encoding end can perform probabilistic shaping (or probabilistic encoding) on ​​the information bit sequence before encoding. Currently, the industry has proposed a probabilistic shaping scheme, namely a polar decoder + polar encoder. However, in this scheme, the parameters of the polar decoder are the same as those of the polar encoder. For example, the information bit sequence length K and codeword sequence length N of the polar decoder are the same as those of the polar encoder. Thus, the polar decoder needs to input the information bit sequence and the shaped bit sequence (or the shaped bit sequence) into the polar encoder after decoding them. Therefore, the complexity of the polar decoder is relatively high, which in turn leads to the high complexity of probabilistic shaping.

[0004] How to achieve low-complexity probabilistic shaping requires further research. Summary of the Invention

[0005] This application provides an encoding and decoding method and a communication device for implementing low-complexity probabilistic shaping.

[0006] In a first aspect, this application provides an encoding method, which can be executed by a first device or a module in the first device (e.g., a processor, a chip, or a chip system). Optionally, the method can also be implemented by a logic node, logic module, or software capable of implementing all or part of the functions of the first device. The following example illustrates the encoding method executed by the first device. The method may include the following steps: the first device acquires a log-likelihood ratio sequence; then, the first device determines a first bit sequence based on P decoders and the log-likelihood ratio sequence, wherein the P decoders include a first decoder, which is a Reed-Muller RM decoder, P is an integer greater than or equal to 1, and the first bit sequence is used for probability shaping; then, the first device determines a codeword sequence based on P encoders, the first bit sequence, and an information bit sequence, wherein the P encoders include a first encoder, which is an RM encoder; finally, the first device outputs the codeword sequence.

[0007] In this method, the first device only needs to decode the first bit sequence (which can be understood as an integer bit sequence) using the first decoder, without needing to decode the information bit sequence. This simplifies the decoding process (the decoding process of the first decoder is more simplified, and the complexity of the decoding process is low), helping to reduce decoding complexity and thus achieving low-complexity probability shaping. Furthermore, compared to the relatively high complexity of probability shaping in existing technologies, this method, using a cascaded first decoder and first encoder, can achieve probability shaping more accurately and efficiently, not only with low complexity but also with virtually no loss in decoding performance even at longer code lengths.

[0008] In one possible implementation, the order of the first decoder is less than or equal to the order of the first encoder.

[0009] In the above implementation, with the same code length parameter, if the order of the first decoder is less than the order of the first encoder, then the number of information bits that the first decoder can carry is less than the number of information bits that the first encoder can carry. Therefore, the complexity of the first decoder will be lower, which makes the decoding implementation of the first decoder simpler and helps to achieve low-complexity probability shaping.

[0010] In one possible implementation, when P equals 1, the method further includes: the first device determining a first sequence based on the information bit sequence; the first device determining the first bit sequence based on P decoders and the log-likelihood ratio sequence includes: the first device inputting the log-likelihood ratio sequence and the first sequence into the first decoder to obtain the first bit sequence.

[0011] In the above implementation, the information bit sequence is known to the first decoder. By preprocessing the information bit sequence, the first decoder does not need to decode the information bit sequence, thus simplifying the decoding process and reducing decoding complexity. In other words, the first sequence can be used to assist the first decoder in decoding, helping to reduce decoding complexity.

[0012] In one possible implementation, when P equals 1, the first device determines the codeword sequence based on P encoders, the first bit sequence, and the information bit sequence, including: the first device interleaving the first bit sequence and the information bit sequence to obtain a second bit sequence, and then the first device can input the second bit sequence into the first encoder to obtain the codeword sequence.

[0013] In the above implementation, the encoding performance of the information bit sequence can be improved by interleaving the first bit sequence and the information bit sequence (such as placing the information bit sequence in a more important bit position).

[0014] In one possible implementation, the first device interleaves the first bit sequence and the information bit sequence to obtain the second bit sequence, including: the first device arranging the first bit sequence before the information bit sequence to obtain the second bit sequence; or the first device interleaving the first bit sequence and the information bit sequence to obtain the second bit sequence; or the first device arranging the first bit sequence at a low code weight position and arranging the information bit sequence at a high code weight position to obtain the second bit sequence.

[0015] The above implementation provides a variety of interleaving methods, making the interleaving of information bit sequences more flexible and diverse, which helps to meet different needs.

[0016] In one possible implementation, the method further includes: if the number of information bits included in the information bit sequence (which can be understood as the number, length, or size of information bits included in the information bit sequence) is less than a first threshold, then the first device can add X padding bits to the information bit sequence, wherein the first threshold is determined based on the number of inputs required by the first encoder and the number of outputs required by the first decoder, and X is the difference between the first threshold and the number of information bits.

[0017] The above implementation method can ensure that the number of information bits input to the first encoder meets the input parameter requirements of the first encoder, thereby ensuring encoding performance.

[0018] In one possible implementation, the first device adds X padding bits to the information bit sequence, including: the first device adding X padding bits before the information bit sequence; or the first device adding X padding bits after the information bit sequence; or the first device adding X padding bits to the information bit sequence in a preset interleaving manner; or the first device adding X padding bits to the information bit sequence at preset intervals.

[0019] The above implementation provides a variety of different bit addition methods, making bit addition to the information bit sequence more flexible and diverse, which helps to meet different needs and can guarantee encoding performance.

[0020] In one possible implementation, when P is greater than 1, the P decoders may include a first decoder and a second decoder; the log-likelihood ratio sequence includes a first sub-log-likelihood ratio sequence and a second sub-log-likelihood ratio sequence; the first bit sequence includes a third bit sequence and a fourth bit sequence; the information bit sequence includes a first sub-information bit sequence and a second sub-information bit sequence; the first sub-information bit sequence corresponds to the first sub-log-likelihood ratio sequence, and the second sub-information bit sequence corresponds to the second sub-log-likelihood ratio sequence; the first device determines the first bit sequence based on the P decoders and the log-likelihood ratio sequence, including: the first device determines the third bit sequence based on the first sub-log-likelihood ratio sequence and the first decoder; and the first device determines the fourth bit sequence based on the second sub-log-likelihood ratio sequence and the second decoder.

[0021] The above implementation method can split a long code length into two or more sub-units for decoding and encoding, thus reducing the complexity of probabilistic encoding. Generally speaking, the complexity of encoding and decoding is not linear at the N-order (N is the code length), but rather grows at the N^2 or NlogN order.

[0022] In one possible implementation, the method further includes: a first device determining a second sequence based on a first sub-information bit sequence; the first device determining a third bit sequence based on a first sub-log-likelihood ratio sequence and a first decoder, including: the first device inputting the first sub-log-likelihood ratio sequence and the second sequence into the first decoder to obtain the third bit sequence.

[0023] In the above implementation, the first sub-information bit sequence is a known quantity for the first decoder. By preprocessing the first sub-information bit sequence, the first decoder does not need to decode the first sub-information bit sequence, thus simplifying the decoding process and reducing decoding complexity. That is to say, the second sequence can be used to assist the first decoder in decoding, which helps to reduce decoding complexity.

[0024] In one possible implementation, when the second decoder is an RM decoder, the method further includes: the first device determining a third sequence based on the second sub-information bit sequence; the first device determining a fourth bit sequence based on the second sub-log-likelihood ratio sequence and the second decoder, including: the first device inputting the second sub-log-likelihood ratio sequence and the third sequence into the second decoder to obtain the fourth bit sequence.

[0025] In the above implementation, the second sub-information bit sequence is a known quantity for the second decoder. By preprocessing the second sub-information bit sequence, the second decoder does not need to decode it, thus simplifying the decoding process and reducing decoding complexity. In other words, the third sequence can be used to assist the second decoder in decoding, helping to reduce decoding complexity.

[0026] In one possible implementation, if the second decoder is not an RM decoder, the first device determines the fourth bit sequence based on the second sub-log-likelihood ratio sequence and the second decoder, including: the first device inputs the second sub-log-likelihood ratio sequence to the second decoder to obtain the fifth bit sequence, wherein the fifth bit sequence may include the fourth bit sequence and the second sub-information bit sequence.

[0027] In one possible implementation, when P is greater than 1, the P encoders may include a first encoder and a second encoder, and the codeword sequence includes a first sub-codeword sequence and a second sub-codeword sequence. The first device determines the codeword sequence based on the P encoders, the first bit sequence, and the information bit sequence, including: the first device inputs a third bit sequence and a first sub-information bit sequence to the first encoder to obtain a first sub-codeword sequence; then, the first device may input a fourth bit sequence to the second encoder to obtain a third sub-codeword sequence; and then, the first device may perform an XOR operation on the first sub-codeword sequence and the third sub-codeword sequence to obtain a second sub-codeword sequence.

[0028] The above implementation method can split a long code length into two or more sub-units for decoding and encoding, thus reducing the complexity of probabilistic encoding. Generally speaking, the complexity of encoding and decoding is not linear at the N-order (N is the code length), but rather grows at the N^2 or NlogN order.

[0029] In one possible implementation, the first device inputs the third bit sequence and the first sub-information bit sequence into the first encoder to obtain the first sub-codeword sequence, including: the first device interleaving the third bit sequence and the first sub-information bit sequence to obtain the sixth bit sequence, and then the first device can input the sixth bit sequence into the first encoder to obtain the first sub-codeword sequence.

[0030] In the above implementation, the coding performance of the first sub-information bit sequence can be improved by interleaving the third bit sequence and the first sub-information bit sequence.

[0031] In one possible implementation, the first device interleaves the third bit sequence and the first sub-information bit sequence to obtain the sixth bit sequence, including: the first device arranging the third bit sequence before the first sub-information bit sequence to obtain the sixth bit sequence; or the first device interleaving the third bit sequence and the first sub-information bit sequence to obtain the sixth bit sequence; or the first device arranging the third bit sequence in a sequence position with low code weight and arranging the first sub-information bit sequence in a sequence position with high code weight to obtain the sixth bit sequence.

[0032] The above implementation provides a variety of interleaving methods, making the interleaving of the first sub-information bit sequence more flexible and diverse, which helps to meet different needs.

[0033] In one possible implementation, when the second encoder is an RM encoder, the first device inputs a fourth bit sequence to the second encoder to obtain a third sub-codeword sequence, including: the first device inputs the fourth bit sequence and the second sub-information bit sequence to the second encoder to obtain a third sub-codeword sequence.

[0034] In the above implementation, the third subcodeword sequence can be obtained in a timely and accurate manner by performing RM encoding on the fourth bit sequence and the second sub-information bit sequence.

[0035] In one possible implementation, the first device inputs the fourth bit sequence and the second sub-information bit sequence into the second encoder to obtain the third sub-codeword sequence, including: the first device interleaving the fourth bit sequence and the second sub-information bit sequence to obtain the seventh bit sequence, and then the first device inputs the seventh bit sequence into the second encoder to obtain the third sub-codeword sequence.

[0036] In the above implementation, the coding performance of the second sub-information bit sequence can be improved by interleaving the fourth bit sequence and the second sub-information bit sequence.

[0037] In one possible implementation, the first device interleaves the fourth bit sequence and the second sub-information bit sequence to obtain the seventh bit sequence, including: the first device arranging the fourth bit sequence before the second sub-information bit sequence to obtain the seventh bit sequence; or the first device interleaving the fourth bit sequence and the second sub-information bit sequence to obtain the seventh bit sequence; or the first device arranging the fourth bit sequence in a sequence position with low code weight and arranging the second sub-information bit sequence in a sequence position with high code weight to obtain the seventh bit sequence.

[0038] The above implementation provides a variety of interleaving methods, making the interleaving of the second sub-information bit sequence more flexible and diverse, which helps to meet different needs.

[0039] In one possible implementation, if the second encoder is not an RM encoder, the first device inputs a fourth bit sequence to the second encoder to obtain a third sub-codeword sequence, including: the first device inputs a fifth bit sequence to the second encoder to obtain a third sub-codeword sequence, wherein the fifth bit sequence may include the fourth bit sequence and the second sub-information bit sequence.

[0040] Secondly, this application provides a decoding method, which can be executed by a second device or a module in the second device (e.g., a processor, chip, or chip system). Optionally, the method can also be implemented by a logic node, logic module, or software capable of implementing all or part of the functions of the second device. The following example illustrates the decoding method executed by a second device. The method may include the following steps: the second device acquires a sequence to be decoded, wherein the sequence to be decoded corresponds to a codeword sequence; then, the second device determines an information bit sequence based on P decoders and the sequence to be decoded, wherein the P decoders include a first decoder, which is an RM decoder, and P is an integer greater than or equal to 1.

[0041] The technical effects achievable in the second aspect are similar to those achievable in the first aspect, and will not be elaborated upon here.

[0042] In one possible implementation, when P equals 1, the second device determines the information bit sequence based on P decoders and the sequence to be decoded, including: the second device inputs the sequence to be decoded into the first decoder to obtain the information bit sequence.

[0043] In the above implementation, by performing RM decoding on the sequence to be decoded, the information bit sequence can be obtained in a timely and accurate manner.

[0044] In one possible implementation, the second device inputs the sequence to be decoded into the first decoder to obtain an information bit sequence, including: the second device inputs the sequence to be decoded into the first decoder to obtain a second bit sequence, and then the second device can perform deinterleaving processing on the second bit sequence to obtain an information bit sequence.

[0045] In the above implementation, the interleaving of the information bit sequence not only improves encoding performance but also decoding performance. By performing RM decoding on the sequence to be decoded, the second bit sequence can be obtained promptly and accurately.

[0046] In one possible implementation, when P is greater than 1, the P decoders may include a first decoder and a second decoder. The sequence to be decoded includes a first sub-sequence to be decoded and a second sub-sequence to be decoded. The first sub-sequence to be decoded corresponds to the first sub-codeword sequence in the codeword sequence, and the second sub-sequence to be decoded corresponds to the second sub-codeword sequence in the codeword sequence. The information bit sequence includes a first sub-information bit sequence and a second sub-information bit sequence. The second device determines the information bit sequence based on the P decoders and the sequence to be decoded, including: the second device performing an XOR operation on the first sub-sequence to be decoded and the second sub-sequence to be decoded to obtain a third sub-sequence to be decoded, wherein the third sub-sequence to be decoded corresponds to the third sub-codeword sequence, and the second sub-codeword sequence is determined based on the first sub-codeword sequence and the third sub-codeword sequence; the second device inputs the first sub-sequence to be decoded to the first decoder to obtain the first sub-information bit sequence; and the second device inputs the third sub-sequence to be decoded to the second decoder to obtain the second sub-information bit sequence.

[0047] The above implementation method can split a long code length into two or more sub-units for decoding, thus reducing decoding complexity.

[0048] In one possible implementation, the second device inputs the first sub-sequence to be decoded into the first decoder to obtain the first sub-information bit sequence, including: the second device inputs the first sub-sequence to be decoded into the first decoder to obtain the sixth bit sequence, and then the second device can perform deinterleaving processing on the sixth bit sequence to obtain the first sub-information bit sequence.

[0049] In the above implementation, the interleaving of the first sub-information bit sequence not only improves coding performance but also decoding performance. By performing RM decoding on the first sub-decoding sequence, the sixth bit sequence can be obtained promptly and accurately.

[0050] In one possible implementation, when the second decoder is an RM decoder, the second device inputs the third sub-sequence to be decoded into the second decoder to obtain the second sub-information bit sequence, including: the second device inputs the third sub-sequence to be decoded into the second decoder to obtain the seventh bit sequence, and then the second device can perform deinterleaving processing on the seventh bit sequence to obtain the second sub-information bit sequence.

[0051] In the above implementation, the interleaving of the second sub-information bit sequence not only improves coding performance but also decoding performance. By performing RM decoding on the third sub-decoding sequence, the seventh bit sequence can be obtained promptly and accurately.

[0052] In one possible implementation, if the second decoder is not an RM decoder, the second device inputs the third sub-decoding sequence to the second decoder to obtain the second sub-information bit sequence, including: the second device inputs the third sub-decoding sequence to the second decoder to obtain the fifth bit sequence, wherein the fifth bit sequence may include the second sub-information bit sequence.

[0053] In the above implementation, when the second decoder is not an RM decoder, a bit sequence including the second sub-information bit sequence and the shaped bit sequence (i.e., the fourth bit sequence) can be obtained by performing non-RM decoding on the third sub-decoder sequence.

[0054] Thirdly, this application provides a communication device that implements the functions described in the first and second aspects above. For example, the communication device includes modules, units, or means corresponding to the operations described in the first and second aspects above. These functions, units, or means can be implemented by software, hardware, or hardware executing corresponding software. For instance, in some examples, the communication device can be a first device or a module within a first device, and the communication device implements the functions described in the first aspect. In other examples, the communication device can be a second device or a module within a second device, and the communication device implements the functions described in the second aspect.

[0055] In one possible implementation, the communication device may include a transceiver module and a processing module. Optionally, the communication device may further include a storage module. The transceiver module can be used to transmit and receive signals to enable communication between the communication device and other devices, for example, to send data to other communication devices; the processing module can be used to perform some internal operations of the communication device. The functions performed by the transceiver module and the processing module may correspond to the operations involved in the first to second aspects described above; the storage module is used to store the program code and / or data of the communication device.

[0056] In one possible implementation, the communication device includes at least one processor, which can be coupled to a memory. The memory can store necessary computer programs or instructions for implementing the functions described in the first to second aspects above. The processor can execute the computer programs or instructions stored in the memory, causing the communication device to implement the methods in any possible implementation of any of the first to second aspects above when the computer programs or instructions are executed.

[0057] In one possible implementation, the communication device includes at least one processor and a memory, the memory of which can store necessary computer programs or instructions for implementing the functions involved in the first to second aspects described above. The at least one processor can execute the computer programs or instructions stored in the memory, and when the computer programs or instructions are executed, cause the communication device to implement the methods in any possible implementation of any of the first to second aspects described above.

[0058] In one possible implementation, the communication device includes at least one processor and a communication interface, wherein the at least one processor is configured to communicate with other devices via the communication interface and execute the methods in any of the possible implementations of the first to second aspects described above. The communication interface is used to enable communication between the communication device and other devices, for example, to receive signals from other communication devices and transmit them to the at least one processor, or to send signals from the at least one processor of the communication device to other communication devices, such as the transmission or reception of data and / or signals. Exemplarily, the communication interface may be a transceiver, circuit, bus, module, or other type of communication interface.

[0059] It is understood that, in the third aspect mentioned above, the processor can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, integrated circuit, etc.; when implemented in software, the processor can be a general-purpose processor that reads software code stored in memory. Furthermore, there can be one or more processors, and one or more memories. The memory can be integrated with the processor or separated from it. In specific implementations, the memory can be integrated with the processor on the same chip or disposed on different chips. This application does not limit the type of memory or the arrangement of the memory and processor.

[0060] Fourthly, this application provides a communication system that may include a first device and a second device. The first device may be used to perform the methods described in the first aspect or any possible implementation of the first aspect. The second device may be used to perform the methods described in the second aspect or any possible implementation of the second aspect.

[0061] Fifthly, this application provides a computer program product comprising a computer program or instructions that, when executed on a communication device (or computer), cause the communication device (or computer) to perform the method in any possible implementation of any of the first to second aspects described above.

[0062] In a sixth aspect, this application provides a computer-readable storage medium storing a computer program or instructions that, when executed by a communication device (or computer), cause the communication device (or computer) to perform the method in any possible implementation of any of the first to second aspects described above.

[0063] In a seventh aspect, this application provides a chip that may include at least one processor and may also include a memory (or the chip may be coupled to the memory), wherein the at least one processor executes program instructions in the memory to cause the chip to perform any possible implementation of any of the first to second aspects described above. Here, "coupling" refers to two components being directly or indirectly connected to each other, such as coupling referring to an electrical connection between two components.

[0064] Eighthly, this application also provides a chip system including at least one processor for supporting a computer device in implementing any possible implementation of the methods in any of the first to second aspects described above. In one possible implementation, the chip system further includes a memory for storing programs and data necessary for the computer device. The chip system may be composed of chips or may include chips and other discrete devices.

[0065] Based on the implementation methods provided in the above aspects, this application can be further combined to provide more implementation methods. Attached Figure Description

[0066] Figure 1 An exemplary schematic diagram of the architecture of a communication system provided in an embodiment of this application is shown;

[0067] Figure 2 This illustration shows a schematic diagram of an air interface transmission process provided in an embodiment of this application;

[0068] Figures 3a to 3d An exemplary diagram illustrating a mobile communication scenario provided in an embodiment of this application is shown.

[0069] Figure 4 An exemplary flowchart of a coding / decoding method provided in an embodiment of this application is shown.

[0070] Figure 5a An exemplary illustration shows a probability shaping diagram for the case where P equals 1, provided in an embodiment of this application.

[0071] Figure 5b This illustration provides an exemplary schematic diagram of another probability shaping case where P equals 1, provided in an embodiment of this application.

[0072] Figure 5c This illustration shows a schematic diagram of adding padding bits when P equals 1, provided in an embodiment of this application.

[0073] Figure 6 This illustration shows a schematic diagram of the correspondence between two parameters m and r of an RM code provided in an embodiment of this application and (N,K);

[0074] Figure 7a An exemplary illustration shows a probability shaping diagram for the case where P is greater than 1, provided in an embodiment of this application.

[0075] Figure 7b This illustration provides an example of another probability shaping diagram for the case where P is greater than 1, provided in an embodiment of this application.

[0076] Figure 8 An exemplary schematic diagram of a communication device provided in an embodiment of this application is shown;

[0077] Figure 9 An exemplary schematic diagram of another communication device provided in an embodiment of this application is shown. Detailed Implementation

[0078] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0079] The following describes the communication system architecture to which the encoding and decoding methods provided in this application are applicable. It should be noted that this description is for the convenience of those skilled in the art and is not intended to limit the scope of protection claimed in this application.

[0080] The technical solutions of this application can be applied to various wireless communication systems, such as Universal Mobile Telecommunications System (UMTS), Wireless Local Area Network (WLAN), short-range wireless communication systems (such as sidelink, wireless fidelity, Wi-Fi, Bluetooth, etc.), wired networks, vehicle-to-everything (V2X) communication systems, device-to-device (D2D) communication systems, vehicle-to-everything (V2X) communication systems, 4G mobile communication systems (such as Long Term Evolution (LTE) systems), LTE Frequency Division Duplex (FDD) systems, LTE Time Division Duplex (TDD) systems, 5G mobile communication systems (such as New Radio (NR) systems), Future Communications systems, or other similar communication systems, and are not limited thereto. The embodiments of this application use... Figure 1 The communication system shown is used as an example for description. When the technical solutions of the embodiments of this application are applied to other communication systems, the devices, components, modules, etc. in the embodiments can be replaced with corresponding devices, components, modules in other communication systems without limitation.

[0081] Figure 1 This is a schematic diagram of the architecture of the communication system used in the embodiments of this application. Figure 1 As shown, the communication system includes an access network 100. Optionally, the communication system may also include a core network 200 and an Internet 300. The access network 100 may include at least one network device, such as... Figure 1 110a and 110b may also include at least one terminal device, such as Figure 1 The series consists of 120a-120j. Specifically, 110a is a base station, 110b is a micro-station, 120a, 120e, 120f, and 120j are mobile phones, 120b is a car, 120c is a fuel dispenser, 120d is a home access point (HAP) deployed indoors or outdoors, 120g is a laptop, 120h is a printer, and 120i is a drone. The same terminal device or network device can provide different functions in different application scenarios. For example... Figure 1The mobile phones included are 120a, 120e, 120f, and 120j. Mobile phone 120a can access base station 110a, connect to car 120b, communicate directly with mobile phone 120e, and access HAP. Car 120b can access HAP and communicate directly with mobile phone 120a. Mobile phone 120f can connect to micro-station 110b, connect to laptop 120g, and connect to printer 120h. Mobile phone 120j can control drone 120i.

[0082] The communication system provided in this application may also include artificial intelligence (AI) network elements to implement some or all AI-related operations. AI network elements can also be referred to as AI nodes, AI devices, AI entities, AI modules, AI models, or AI units, etc. The AI ​​network elements may be built into the network elements of the communication system. For example, an AI network element may be an AI module built into access network equipment, core network equipment, cloud servers, or operation, administration, and maintenance (OAM) equipment to implement AI-related functions. The OAM equipment may act as the network management system for core network equipment and / or access network equipment. Alternatively, the AI ​​network element may be an independently configured network element in the communication system. Optionally, the terminal or its built-in chip may also include an AI entity to implement AI-related functions.

[0083] (1) Network equipment

[0084] A network device is a network-side device with wireless transceiver capabilities. A network device can be a device within a radio access network (RAN) that provides wireless communication functionality to terminal devices; this is called a RAN device. The RAN can be an access network in 3GPP, such as 4G, 5G, or future networks. The RAN can also be an open RAN (O-RAN or ORAN), a cloud radio access network (CRAN), or a communication network combining two or more of these.

[0085] RAN equipment can also be a base station, an evolved NodeB (eNodeB), a transmission reception point (TRP), a next-generation NodeB (gNB) in a 5G mobile communication system, a base station in a future mobile communication system, or an access node in a WiFi system, etc.

[0086] RAN equipment can also be modules or units that perform some of the functions of a base station. For example, it can be a central unit (CU), a distributed unit (DU), or a radio unit (RU). The CU performs the functions of the radio resource control (RRC) protocol and the packet data convergence protocol (PDCP) protocol of the base station, and can also perform the functions of the service data adaptation protocol (SDAP). The CU can be further divided into a CU control plane (CP) (i.e., CU-CP) and a CU user plane (UP) (i.e., CU-UP). The DU performs the functions of the radio link control (RLC) layer and the medium access control (MAC) layer of the base station, and can also perform some or all of the physical layer functions. For specific descriptions of the above protocol layers, please refer to the relevant 3GPP technical specifications. The CU and DU can be set up separately, or they can be included in the same network element, such as in the baseband unit (BBU). The RU can be included in radio frequency equipment or radio frequency units, such as in a remote radio unit (RRU), an active antenna unit (AAU), or a remote radio head (RRH). In different systems, CU, DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an ORAN system, CU can also be called O-CU (open CU), DU can also be called O-DU, and RU can also be called O-RU. Any of the units among CU (or CU-CP, CU-UP), DU, and RU in this application can be implemented through software modules, hardware modules, or a combination of software and hardware modules. RAN equipment can be a macro base station (such as...) Figure 1 110a in the text), can also be a micro base station or an indoor station (such as... Figure 1 In 110b), it can also be a relay node or a donor node, etc. The embodiments of this application do not limit the specific technology or device form used in the network equipment.

[0087] In the embodiments of this application, the functions of the network device can be executed by modules (such as chips) within the network device, or by a control subsystem that includes the functions of the network device. This control subsystem, which includes the functions of the network device, can be a control center in the aforementioned application scenarios such as smart grids, industrial control, intelligent transportation, and smart cities.

[0088] (2) Terminal equipment

[0089] A terminal device is a user-side device with wireless transceiver capabilities. Terminal devices can also be called terminals, user equipment (UE), mobile stations, mobile terminals, etc. Terminal devices can be widely used in various scenarios, such as D2D communication, V2X communication, machine-type communication (MTC), the Internet of Things (IoT), virtual reality, augmented reality, industrial control, autonomous driving, telemedicine, smart grids, smart furniture, smart offices, smart wearables, intelligent transportation, and smart cities. Terminal devices can be mobile phones, tablets, computers with wireless transceiver capabilities, wearable devices, vehicle devices (such as vehicle units, in-vehicle modules, in-vehicle chips, onboard units (OBUs) or telematics boxes (T-BOXs)), drones, helicopters, airplanes, ships, robots, robotic arms, smart home devices, satellite terminals, Internet of Things (IoT) terminals, virtual reality (VR) devices, augmented reality (AR) devices, smart point-of-sale (POS) machines, customer-premises equipment (CPE), light user equipment (UE), reduced capability UE (REDCAP UE), etc. In the embodiments of this application, the device used to implement the functions of the terminal device can be the terminal device itself, or a device capable of supporting the terminal device in implementing that function, such as a chip system or a combination of devices or components capable of implementing the functions of the terminal device. This device can be installed in the terminal device. The embodiments of this application do not limit the specific technology or specific device form used in the terminal device.

[0090] In this embodiment of the application, the functions of the terminal device can also be performed by modules (such as chips or modems) in the terminal device, or by a device that includes the functions of the terminal device.

[0091] Network devices and terminal devices can be fixed in location or mobile. They can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; they can also be deployed on water; and they can also be deployed in the air on airplanes, balloons, and artificial satellites. The embodiments of this application do not limit the application scenarios of the network devices and terminal devices.

[0092] The roles of network devices and terminal devices can be relative, for example, Figure 1 The helicopter or drone 120i can be configured as a mobile network device. For terminal devices 120j that access the wireless access network 100 via 120i, terminal device 120i is a network device; however, for network device 110a, 120i is a terminal device, meaning that 110a and 120i communicate via a wireless air interface protocol. Of course, 110a and 120i can also communicate via a network device-to-network device interface protocol; in this case, 120i is also a network device relative to 110a. Therefore, both network devices and terminal devices can be collectively referred to as communication devices. Figure 1 110a and 110b can be referred to as communication devices with network equipment functions. Figure 1 The 120a-120j in the text can be referred to as communication devices with terminal equipment functions.

[0093] Network devices and terminal devices, network devices and network devices, and terminal devices can communicate through licensed spectrum, unlicensed spectrum, or both simultaneously, without limitation.

[0094] The network architecture and business scenarios described in this application are intended to more clearly illustrate the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0095] The following is an explanation of the relevant terms used in the embodiments of this application. Unless otherwise specified, these explanations are provided to support the meaning of the relevant terms and to make the embodiments of this application easier to understand, and should not be regarded as a strict limitation of the relevant terms within the scope of protection claimed by this application.

[0096] (1) Reed Müller (RM) code

[0097] Relative perfect codes (RM codes) possess unique and rich structural characteristics, and can be modeled and represented in various ways, such as through finite geometry, polynomial rings, or Boolean functions. For example, we will introduce the definition of RM codes based on polynomial rings. Binary RM codes encompass multivariate polynomials in a binary domain. The evaluation results are as follows. Consider a polynomial ring with m variables. For a polynomial and a binary vector Define Eval z (f)=f(z1,z2,…,z m Let f be the value of the polynomial f in the binary vector z. Based on this, the evaluation vector of the polynomial f can be defined. That is, a coordinate of Eval(f) is the evaluation result of the polynomial f at a certain binary vector. Since The CCP has 2 m There are m-dimensional binary vectors, therefore the evaluation vector Eval(f) has a total of 2 m Each dimension. For an RM code with parameters m and r, its codeword set can be defined as the set of evaluation vectors for all polynomials of order no higher than r. The RM code can be represented as follows:

[0098]

[0099] Where deg(f) represents the order of polynomial f; m is the first parameter of the RM code (also known as the code length parameter), which is related to the code length of the RM code. For example, the code length of the RM code is 2. m ; r is the second parameter of the RM code (also known as the order), which represents the order of the RM code.

[0100] (2) Projection of RM code

[0101] definition Let be an s-dimensional subspace of an m-dimensional binary vector space, denoted as . It is a subspace The set of all cosets, i.e. {T:T is The accompanying collection, special There are 2 in the middle m-s A coset. Define an RM codeword y in a subspace. The projection of the subspace is but

[0102] (3) Automorphic permutation of RM code

[0103] For a valid codeword x of RM(m,r), its 2 mThe bits of a codeword can be represented by an m-dimensional binary vector z = (z1, ..., z2). m Use ) as the index. For any binary full-rank matrix and vectors Define coordinate transformation That is, placing the bit at position z of codeword x into Position, thus obtaining a new length of 2 m The code This yields the RM code after automorphic permutation.

[0104] (3) Information bit sequence

[0105] An information bit sequence refers to a sequence of bits to be transmitted. For example, if the bits to be transmitted are 1, 0, 1, 0, 1, 1, 0, 0, 1, 0, 1, then the resulting information bit sequence is 10101100101. In this application, K represents the length of the information bit sequence. The information bits may include payload bits. Optionally, the information bits may also include check bits, such as cyclic redundancy check (CRC) bits.

[0106] against Figure 1 The communication system architecture shown allows for air interface transmission between terminal devices and network devices. Taking network devices as an example, air interface transmission includes uplink and downlink transmission, such as... Figure 2 The air interface transmission process is shown below. For downlink transmission: the network device sequentially encodes, modulates, maps, precodes, frames, and performs inverse fast fourier transform (IFFT) on the layer 2 (L2) data, and then processes it into an air interface signal to be transmitted through the intermediate radio frequency (IRF) module. For uplink transmission: the network device processes the received signal through the IRF module to obtain baseband data, and then performs inverse fast fourier transform (FFT), deframes, equalizes, demaps, demodulates, and decodes it to complete the physical layer signal processing.

[0107] (4) Polar code

[0108] Polar codes are a coding scheme that can be rigorously proven to "achieve" Shannon channel capacity. They have the advantages of good decoding performance and low complexity, and have been selected by 3GPP as the control channel coding scheme for enhanced mobile broadband (eMBB) scenarios.

[0109] The encoding and decoding methods provided in this application can be applied to various mobile communication scenarios, where the first device and the second device can be a terminal device and a network device in the mobile communication scenario, respectively. For example, Figure 3a The mobile communication scenario shown is between network devices and terminal devices, or as... Figure 3b The scenario shown illustrates a dual connectivity (DC) scenario involving multiple network devices and terminal devices, or as... Figure 3c The scenario shown illustrates a multi-hop single-connection between network devices and terminal devices, or as... Figure 3d The diagram illustrates a multi-hop, multi-connection scenario involving network devices and terminal devices. This is understandable. Figures 3a to 3d This application merely illustrates several possible mobile communication scenarios and does not limit the mobile communication scenarios to which this application applies. The mobile communication scenarios applicable to the embodiments of this application may include, but are not limited to, scenarios where one or more network-side devices transmit signals to one or more terminal devices, such as network devices transmitting signals to terminal devices, network devices transmitting signals to relay devices, relay network devices transmitting signals to terminal devices, multiple network devices transmitting signals to one terminal device, or multiple network devices transmitting signals to multiple terminal devices.

[0110] The specific implementation of the encoding and decoding methods in the embodiments of this application will be described in detail below with reference to the accompanying drawings. It is understood that this application uses the first device and the second device as examples of the execution subjects in the interactive illustration, but this application does not limit the execution subjects in the interactive illustration. For example, the method executed by the first device in this application can also be executed by a module applied to the first device (e.g., a processor, a chip (such as a modem chip, or a system-on-a-chip (SoC) chip containing a modem core, or a system-in-package (SIP) chip, or a chip system, etc.), or it can also be implemented by a logical node, logical module, or software that can implement all or part of the functions of the first device, or it can be implemented through a combination of hardware and software. Similarly, the method executed by the second device in this application can also be executed by a module applied to the second device (e.g., a processor, chip, or chip system, etc.), or it can also be implemented by a logical node, logical module, or software that can implement all or part of the functions of the second device, or it can be implemented through a combination of hardware and software. For example, the first device can be... Figure 1 The network device shown (e.g., network device 110a), the second device can be... Figure 1 The terminal device shown (e.g., terminal device 120a). Alternatively, the first device could be... Figure 1 The terminal device shown (e.g., terminal device 120a), the second device can be Figure 1The network device shown (e.g., network device 110a).

[0111] Figure 4 This illustration shows a flowchart of a coding / decoding method (i.e., encoding / decoding method) provided in an embodiment of this application. This method is applicable to... Figure 1 The illustrated communication system architecture. For example... Figure 4 As shown, the method includes:

[0112] S401: The first device acquires the log-likelihood ratio sequence.

[0113] Alternatively, the log-likelihood ratio sequence can also be described as a "bit soft value sequence".

[0114] In one possible implementation, the first device can determine N log likelihood ratios (LLRs) based on a target probability distribution (which can be understood as a desired probability distribution or a certain probability distribution). These N LLRs (or bit soft values) are used to determine (or form or constitute) a sequence of LLRs. It can be understood that these N LLRs follow the target probability distribution, where N is an integer greater than 1.

[0115] For example, the log-likelihood ratio sequence can be used as the sequence to be decoded (or the sequence of symbols to be decoded) and input to the corresponding decoder to obtain one or more integer bits (or shaped bits, auxiliary bits, or the first bit sequence). Among them, one or more integer bits are used for probabilistic shaping.

[0116] For example, the corresponding decoder described above may be an RM decoder, a polarization decoder, or other types of decoders.

[0117] S402: The first device determines the first bit sequence based on the P decoders and the log-likelihood ratio sequence.

[0118] The P decoders include a first decoder. In this application, the first decoder is an RM decoder. Here, P is an integer greater than or equal to 1. It can be understood that the order of the first decoder is less than or equal to the order of the first encoder. For example, the order of the first decoder can be 1st or 2nd order. For instance, the first decoder can be a low-complexity decoder such as a 1st order Fast Hadamard Transform (FHT) decoder.

[0119] The following examples illustrate the specific implementation of the first device determining the first bit sequence based on P decoders and a log-likelihood ratio sequence.

[0120] Method a1: When P equals 1, this single decoder is the first decoder. The first device can determine the first sequence based on the information bit sequence. Then, the first device can input the log-likelihood ratio sequence and the first sequence into the first decoder to obtain the first bit sequence.

[0121] In one possible implementation, the first device can determine the first sequence based on the information bit sequence and the corresponding generator matrix (or first matrix). Optionally, the first sequence can be described as a first mask sequence or a first mask.

[0122] The following example illustrates method a1.

[0123] Please see Figure 5a , Figure 5a This is a schematic diagram illustrating probability shaping when P equals 1, provided as an embodiment of this application. Figure 5a Taking a log-likelihood ratio sequence consisting of N log-likelihood ratios (which can be understood as N log-likelihood ratios or bit soft values ​​following a certain probability distribution), an information bit sequence consisting of K2-K1 information bits, an RM decoder as the first decoder (e.g., an RM(m,r1) decoder), and an RM encoder as the first encoder (e.g., an RM(m,r2) encoder) as an example. Figure 5a As shown, the first device can determine the first sequence, such as mask 1, based on K2-K1 information bits and the corresponding generator matrix. Then, the first device can input N log-likelihood ratios and mask 1 into the RM decoder to obtain K1 integer bits. These K1 integer bits can be used to determine the first bit sequence. Here, K1 represents the required output information bit length of the RM decoder, and K2 represents the required input information bit length of the RM encoder.

[0124] The parameters of RM codes are briefly introduced below.

[0125] RM(m,r) has two typical parameters, m and r. m is the first parameter of the RM code (also called the code length parameter), and r is the second parameter (also called the order). Generally, the two typical parameters for encoding and decoding are (N,K), where N represents the length of the output codeword bit sequence after encoding, and K represents the length of the input information bit sequence before encoding. K / N corresponds to the code rate. A lower code rate means fewer small information bits are transmitted for the same codeword length, resulting in more redundant bits and stronger resistance to channel fading and interference, thus better performance and suitability for low signal-to-noise ratio (SNR) ranges. Conversely, a higher code rate transmits more information bits but has weaker resistance to channel interference, making it suitable for high SNR ranges. The correspondence between the two parameters m and r of the RM code and (N,K) satisfies the following formula. As an example, the correspondence between the two parameters m and r of the RM code and (N,K) can be found in [reference needed]. Figure 6 .

[0126]

[0127] N=2 m

[0128] Corresponding to Figure 5a The parameters of the RM decoder are (m, r1), and the parameters of the RM encoder are (m, r2). Here, m represents the first parameter of the RM decoder and RM encoder, which is related to the code length of the RM code. For example, if the code length of the RM code is 2... m r1 represents the second parameter (also known as the order) of the RM decoder, and r2 represents the second parameter (also known as the order) of the RM encoder. r1 is less than or equal to r2.

[0129] For example, RM encoding can be viewed as obtaining K information bits by multiplying them with a generator matrix G, that is:

[0130] x(1,2,…,N)=u(1,2,…,K)·G(val1,val2,…,val K )

[0131] Where x(1,2,…,N) is the encoded output codeword, a row vector of length N. u(1,2,…,K) is the input information bit sequence before encoding, a row vector of length K. G(val1,val2,…,val K ) is the generator matrix encoded in RM, val i Let N be the i-th column vector, and let N be the length of each column vector. There are a total of K column vectors.

[0132] Since the matrix operations described above are linear operations, the K information bits can be split into two parts of length K1 and K-K1. In this case, the formula for the RM encoding can be transformed into:

[0133]

[0134] Therefore, it can be seen that Figure 5a The K2-K1 information bits shown correspond to the K-K1 part (the second half) on the right side of the equation above, while the K1 integer bits correspond to the K1 part (the first half). Based on this, the mask generation operation corresponds to the following formula:

[0135]

[0136] The above RM encoding formula can be transformed into:

[0137]

[0138] Using the above transformation formula as an RM(m,r1) decoder, that is, given N log-likelihood ratios following a certain probability distribution as input to the decoder, and having already calculated mask1 based on K2-K1 information bits, it can finally decode to obtain K1 integer bits. Wherein,

[0139]

[0140] Method a2: When P is greater than 1, taking P decoders (including a first decoder and a second decoder), a log-likelihood ratio sequence (including a first sub-log-likelihood ratio sequence and a second sub-log-likelihood ratio sequence), a first bit sequence (including a third bit sequence and a fourth bit sequence), and an information bit sequence (including a first sub-information bit sequence and a second sub-information bit sequence) as an example. The first sub-information bit sequence corresponds to the first sub-log-likelihood ratio sequence, and the second sub-information bit sequence corresponds to the second sub-log-likelihood ratio sequence. The first device can determine the third bit sequence based on the first sub-log-likelihood ratio sequence and the first decoder. Furthermore, the first device can determine the fourth bit sequence based on the second sub-log-likelihood ratio sequence and the second decoder. It can be understood that the first decoder in method a2 is an RM decoder.

[0141] In one possible implementation, the first device can determine the second sequence based on the first sub-information bit sequence. Then, the first device can input the first sub-log-likelihood ratio sequence and the second sequence into a first decoder to obtain a third bit sequence. Optionally, the second sequence can be described as a second mask sequence or a second mask.

[0142] The following describes the specific implementation of the first device determining the fourth bit sequence based on the second sublog-likelihood ratio sequence and the second decoder. For details, please refer to method b1 and method b2 below.

[0143] Method b1: When the second decoder is an RM decoder, the first device can determine the third sequence based on the second sub-information bit sequence. Then, the first device can input the third sequence and the second sub-log-likelihood ratio sequence into the second decoder to obtain the fourth bit sequence. Optionally, the third sequence can be described as a third mask sequence or a third mask. It is understood that the order of the second decoder as an RM decoder is less than or equal to the order of the second encoder as an RM encoder. For example, the order of the second decoder can be 1st or 2nd order. For instance, the second decoder can be a low-complexity decoder such as a 1st order FHT decoder.

[0144] Please see Figure 7a , Figure 7a This is a schematic diagram illustrating probability shaping when P is greater than 1, provided as an embodiment of this application. Figure 7a Taking an RM decoder (e.g., an RM(m-1,r1) decoder), an RM encoder (e.g., an RM(m-1,r2) encoder), an RM decoder (e.g., an RM(m-1,r3) decoder), and an RM encoder (e.g., an RM(m-1,r2-1) encoder) as an example, where the first and second sub-log-likelihood ratio sequences each include N / 2 log-likelihood ratios, the first sub-information bit sequence includes K2'-K1' information bits, and the second sub-information bit sequence includes K2"-K1" information bits, where K2 = K2' + K2", and K1 = K1' + K1. K1' represents the required output bit length of the RM(m-1,r1) decoder, K2' represents the required input bit length of the RM(m-1,r2) encoder, K1” represents the required output bit length of the RM(m-1,r3) decoder, K2” represents the required input bit length of the RM(m-1,r2-1) encoder, and r3 is less than or equal to r2-1. For example... Figure 7aAs shown, the first device can determine the second sequence, such as mask 2, based on K2'-K1' information bits and the corresponding generator matrix. Then, the first device can input N / 2 log-likelihood ratios and mask 2 into an RM(m-1,r1) decoder to obtain K1' integer bits. These K1' integer bits can be used to determine the third bit sequence. Furthermore, the first device can determine the third sequence, such as mask 3, based on K2"-K1" information bits and the corresponding generator matrix. Then, the first device can input N / 2 log-likelihood ratios and mask 3 into an RM(m-1,r3) decoder to obtain K1" integer bits. These K1" integer bits can be used to determine the third bit sequence.

[0145] It is understandable that, based on the decomposition principle of RM codes, a large RM integer unit can be constructed from multiple sub-probability integer units, as detailed in the following formula:

[0146]

[0147] Based on the above decomposition formula for RM codes, the codeword length N = 2 for RM(m,r) m It can be split into two codewords with a length of N=2. m-1 The vector, the first half of which corresponds to RM(m-1,r), and the second half of which corresponds to the XOR result of the first half and RM(m-1,r-1).

[0148] Therefore, based on the decomposition principle of RM codes, Figure 7a The overall RM probabilistic shaping is divided into an upper part and a lower part. The right-hand module of the upper part uses an RM(m-1,r2) encoder, while the right-hand module of the lower part uses an RM(m-1,r2-1) encoder. The encoded codeword sequence of length N / 2 obtained from the upper part is then XORed with the encoded codeword sequence of length N / 2 obtained from the lower part, forming the latter half of the final output codeword sequence, which is also N / 2 in length. Thus, the encoded codeword sequence of length N / 2 obtained from the upper part and the codeword sequence of length N / 2 obtained through the XOR operation together constitute the final codeword sequence.

[0149] Method b2: If the second decoder is not an RM decoder, the first device can input the second sub-log-likelihood ratio sequence into the second decoder to obtain the fifth bit sequence. The fifth bit sequence includes the fourth bit sequence and the second sub-information bit sequence.

[0150] For example, when the second decoder is not an RM decoder, the second decoder can be a polar decoder or other decoders, etc.

[0151] Please see Figure 7b , Figure 7b This is a schematic diagram illustrating another probability shaping case where P is greater than 1, provided as an embodiment of this application. Figure 7b Taking an RM decoder (e.g., an RM(m-1,r1) decoder), an RM encoder (e.g., an RM(m-1,r2) encoder), a polar decoder, and a polar encoder as an example, where the first and second sub-log-likelihood ratio sequences each include N / 2 log-likelihood ratios, the first sub-information bit sequence includes K2'-K1' information bits, and the second sub-information bit sequence includes K2"-K1" information bits, as an example. Here, K1' represents the required output information bit length of the RM(m-1,r1) decoder, and K2' represents the required input information bit length of the RM(m-1,r2) encoder. Figure 7b As shown, the first device can determine the second sequence, such as mask 2, based on K2'-K1' information bits and the corresponding generator matrix. Then, the first device can input N / 2 log-likelihood ratios and mask 2 into an RM(m-1,r1) decoder to obtain K1' integer bits. These K1' integer bits can be used to determine the third bit sequence. Furthermore, the first device can input N / 2 log-likelihood ratios into a polar decoder to obtain N / 2 bits. These N / 2 bits can be used to determine the fifth bit sequence. For example, the N / 2 bits include K1” integer bits, K2”-K1” information bits, and N / 2-K1”-(K2”-K1”) freeze bits.

[0152] S403: The first device determines the codeword sequence based on P encoders, the first bit sequence, and the information bit sequence.

[0153] Among them, P encoders include a first encoder. In this application, the first encoder is an RM encoder.

[0154] The following describes the specific implementation of the first device determining the codeword sequence based on P encoders, the first bit sequence, and the information bit sequence through several possible implementation methods.

[0155] Method c1: When P equals 1, this encoder is the first encoder. The first device can input the information bit sequence and the first bit sequence into the first encoder to obtain the codeword sequence.

[0156] The following example illustrates method c1.

[0157] Please continue reading Figure 5aAfter obtaining K1 shaped bits through the RM decoder, the first device can input K2-K1 information bits and K1 shaped bits into the RM encoder to obtain N probabilistically shaped bits. These N probabilistically shaped bits can be used to determine the codeword sequence.

[0158] In one possible implementation, the first device may also interleave (or map) the first bit sequence and the information bit sequence to obtain the second bit sequence. For example, the first device can input the first bit sequence and the information bit sequence into an interleaver (or mapper) to obtain the second bit sequence. Then, the first device can input the second bit sequence into a first encoder to obtain a codeword sequence.

[0159] Please see Figure 5b , Figure 5b This is a schematic diagram illustrating another probability shaping scenario where P equals 1, provided as an embodiment of this application. Figure 5b Continuing with the example of a log-likelihood ratio sequence comprising N log-likelihood ratios (which can be understood as N log-likelihood ratios or bit soft values ​​following a certain probability distribution), an information bit sequence comprising K2-K1 information bits, a first decoder being an RM decoder (e.g., an RM(m,r1) decoder), and a first encoder being an RM encoder (e.g., an RM(m,r2) encoder). Figure 5b As shown, after obtaining K1 shaped bits through the RM decoder, the first device can interleave (or map) the K1 shaped bits and K2-K1 information bits to obtain K2 bits. For example, the first device can input the K1 shaped bits and K2-K1 information bits into an interleaver (or mapper) to obtain K2 bits. Then, the first device can input the K2 bits into the RM encoder to obtain N probabilistically shaped bits.

[0160] The following examples illustrate the specific implementation of the first device interleaving the first bit sequence and the information bit sequence to obtain the second bit sequence.

[0161] Example d1: The first device arranges the first bit sequence before the information bit sequence to obtain the second bit sequence.

[0162] Please continue reading Figure 5bTaking the interleaving of K1 integer bits and K2-K1 information bits as an example, the first device can arrange the K1 integer bits before the K2-K1 information bits to obtain K2 bits. Alternatively, the first device can input the K1 integer bits and K2-K1 information bits into an arrangement interleaver to obtain K2 bits. The arrangement interleaver is used to arrange the K1 integer bits before the K2-K1 information bits. The K2 bits can be used to determine the second bit sequence.

[0163] Example d2: The first device interleaves the first bit sequence and the information bit sequence to obtain the second bit sequence.

[0164] Please continue reading Figure 5b Continuing with the example of interleaving K1 integer bits and K2-K1 information bits, in one example, the first device can perform regular interleaving (e.g., equal-interval interleaving) of the K1 integer bits and K2-K1 information bits to obtain K2 bits. For example, the first device can input the K1 integer bits and K2-K1 information bits into an equal-interval interleaver to obtain K2 bits. The equal-interval interleaver is used to perform equal-interval interleaving (or equal-interval arrangement) of the K1 integer bits and K2-K1 information bits.

[0165] In another example, the first device can irregularly interleave K1 integer bits and K2-K1 information bits to obtain K2 bits. For example, the first device can input K1 integer bits and K2-K1 information bits into an irregular interleaver to obtain K2 bits. The irregular interleaver is used to irregularly interleave (or irregularly arrange) the K1 integer bits and K2-K1 information bits according to a given interleaving rule (or a given interleaving pattern or a given interleaving method).

[0166] In another example, the first device can input K1 integer bits and K2-K1 information bits into a row-column interleaver to obtain K2 bits.

[0167] Example d3: The first device arranges the first bit sequence in the sequence position with low code weight and arranges the information bit sequence in the sequence position with high code weight to obtain the second bit sequence.

[0168] Here, code weight represents the number of basis vectors with a value of 1 in the RM code matrix corresponding to the sequence position.

[0169] For example, when the number of information bits included in the information sequence is greater than or equal to 3 and less than or equal to 11, the RM code encoding matrix can be found in Table 1. It is understood that Table 1 is merely a simple example, intended to facilitate the illustration of the technical solutions in the embodiments of this application, and does not constitute a limitation on the technical solutions in the embodiments of this application.

[0170] Table 1

[0171]

[0172]

[0173] In Table 1, each column represents a basis vector.

[0174] For example, when the number of information bits in the information sequence is greater than or equal to 3 and less than or equal to 11, the length of the encoded codeword sequence is 32 bits. When the first parameter m of the RM code is 5, the first 6 columns in Table 1 can be the 6 basis vectors corresponding to the RM code.

[0175] Please continue reading Figure 5b Continuing with the example of interleaving K1 integer bits and K2-K1 information bits, the first device can arrange the K1 integer bits in the sequence position with lower code weight and arrange the K2-K1 information bits in the sequence position with higher code weight, thus obtaining K2 bits.

[0176] Optionally, when the number of information bits in the information bit sequence (which can be understood as the length or size of the information bit sequence) is less than a first threshold, the first device can first add X padding bits to the information bit sequence. This ensures that the length of the information bit sequence after adding padding bits meets the first threshold, thereby satisfying the input parameter requirements of the first encoder (such as the length requirement of the first encoder's input parameters). Then, the first device can input the information bit sequence with added padding bits (such as zero bits or a known (or predefined) bit sequence) and the first bit sequence to the first encoder to obtain a codeword sequence. The first threshold is determined based on the number of inputs required by the first encoder (which can be understood as the required length of the information bits input by the first encoder) and the number of outputs required by the first decoder (which can be understood as the required length of the information bits output by the first decoder). X is the difference between the first threshold and the number of information bits.

[0177] Please see Figure 5c , Figure 5c This is a schematic diagram illustrating the addition of padding bits when P equals 1, as provided in an embodiment of this application. Figure 5c Taking an example where the number of inputs required by the first encoder is K2, the number of outputs required by the first decoder is K1, and the number of information bits in the information bit sequence is K3-K1. Figure 5c As shown, when the number of information bits K3-K1 in the information bit sequence is less than the first threshold K2-K1, the first device can add (or pad) a certain number (e.g., X) of padding bits to the information bit sequence, such as adding a certain number of 0s or known bit sequences. This ensures that the length of the information bit sequence after adding padding bits meets the input parameter requirements of the first encoder; this process is also known as rate matching. Here, X = (K2-K1) - (K3-K1) = K2-K3, which means adding K2-K3 padding bits to the information bit sequence. Afterward, the first device can determine mask 1' based on the information bit sequence after adding padding bits and the corresponding generator matrix. Then, the first device can input mask 1' and N soft bits following a certain probability distribution into the RM(m,r1) decoder to obtain K1 integer bits.

[0178] The following examples illustrate the specific implementation of adding X padding bits to an information bit sequence using a first device.

[0179] Example e1: The first device adds X padding bits before the information bit sequence.

[0180] Example e2: The first device adds X padding bits after the information bit sequence.

[0181] Example e3: The first device adds X padding bits to the information bit sequence in a preset interleaving method (such as a given interleaving rule).

[0182] Example e4: The first device adds X padding bits to the information bit sequence at preset intervals (such as equal-interval interleaving).

[0183] Optionally, the first and second devices may also involve parameter configuration for the RM encoder and RM decoder. The parameter configuration is described below with examples.

[0184] For example, the first device is the base station, the second device is the UE, the base station acts as the encoding side device, and the UE acts as the decoding side device. Figure 5aThe following are examples of RM encoder and RM decoder parameters. The base station can carry at least one of the following RM parameters to the UE through layer 1 (L1) signaling (such as downlink control information (DCI)) or L2 signaling (such as RRC signaling): one or more of the RM decoder parameters m and r1, one or more of the RM decoder and RM encoder parameters m, r1 and r2, the number of integer bits K1, the number of integer bits K1 and the number of information bits K2-K1, and the number of integer bits K1 and the total number of bits K2.

[0185] For example, taking the first device as the base station and the second device as the UE, with the base station acting as the decoding side device and the UE acting as the encoding side device, a set or more sets of RM parameter tables (including one or more RM parameters carried by the base station in L1 signaling or L2 signaling) are predefined by the protocol. The base station can configure the RM parameter index to the UE through L1 signaling or L2 signaling, or the base station can configure the specified RM parameters to the UE through L1 signaling or L2 signaling.

[0186] Method c2: When P is greater than 1, taking P encoders (including a first encoder and a second encoder), a first bit sequence (including a third bit sequence and a fourth bit sequence), an information bit sequence (including a first sub-information bit sequence and a second sub-information bit sequence), and a codeword sequence (including a first sub-codeword sequence and a second sub-codeword sequence) as an example: The first device can input the third bit sequence and the first sub-information bit sequence into the first encoder to obtain the first sub-codeword sequence. Additionally, the first device can also input the fourth bit sequence into the second encoder to obtain the third sub-codeword sequence. Then, the first device can perform an XOR operation on the first and third sub-codeword sequences to obtain the second sub-codeword sequence. It can be understood that the first encoder in method c2 is an RM encoder.

[0187] In one possible implementation, the first device can also interleave the third bit sequence and the first sub-information bit sequence to obtain the sixth bit sequence. Then, the first device can input the sixth bit sequence into the first encoder to obtain the first sub-codeword sequence. For example, the first device can input the third bit sequence and the first sub-information bit sequence into an interleaver to obtain the sixth bit sequence.

[0188] The following examples illustrate the specific implementation of the first device interleaving the third bit sequence and the first sub-information bit sequence to obtain the sixth bit sequence.

[0189] Example f1: The first device arranges the third bit sequence before the first sub-information bit sequence to obtain the sixth bit sequence.

[0190] Please continue reading Figure 7a Taking the interleaving of K1' integer bits and K2'-K1' information bits as an example, the first device can arrange the K1' integer bits before the K2'-K1' information bits to obtain K2' bits. Alternatively, the first device can input the K1' integer bits and K2'-K1' information bits into an arrangement interleaver to obtain K2' bits. The arrangement interleaver is used to arrange the K1' integer bits before the K2'-K1' information bits. The K2' bits can be used to determine the sixth bit sequence.

[0191] Example f2: The first device interleaves the third bit sequence and the first sub-information bit sequence to obtain the sixth bit sequence.

[0192] Please continue reading Figure 7a Continuing with the example of interleaving K1' integer bits and K2'-K1' information bits, in one example, the first device can perform regular interleaving (e.g., equal-interval interleaving) of the K1' integer bits and K2'-K1' information bits to obtain K2' bits. For example, the first device can input the K1' integer bits and K2'-K1' information bits into an equal-interval interleaver to obtain K2' bits. The equal-interval interleaver is used to perform equal-interval interleaving (or equal-interval arrangement) of the K1' integer bits and K2'-K1' information bits.

[0193] In another example, the first device can irregularly interleave K1' integer bits and K2'-K1' information bits to obtain K2' bits. For example, the first device can input K1' integer bits and K2'-K1' information bits into an irregular interleaver to obtain K2' bits. The irregular interleaver is used to irregularly interleave (or irregularly arrange) the K1' integer bits and K2'-K1' information bits according to a given interleaving rule (or a given interleaving pattern or a given interleaving method).

[0194] In another example, the first device can input K1' integer bits and K2'-K1' information bits into the row-column interleaver to obtain K2' bits.

[0195] Example f3: The first device arranges the third bit sequence in the low-weight sequence position and the first sub-information bit sequence in the high-weight sequence position to obtain the sixth bit sequence.

[0196] Please continue reading Figure 7aContinuing with the example of interleaving K1' integer bits and K2'-K1' information bits, the first device can arrange (or place or carry) the K1' integer bits in the sequence position with lower code weight, and arrange the K2'-K1' information bits in the sequence position with higher code weight, thus obtaining K2' bits.

[0197] Optionally, when the number of information bits in the first sub-information bit sequence (which can be understood as the length or size of the first sub-information bit sequence) is less than the second threshold, the first device can first add X' padding bits to the first sub-information bit sequence. This ensures that the length of the first sub-information bit sequence after adding padding bits meets the second threshold, thereby satisfying the input parameter requirements of the first encoder (here, the first encoder is an RM encoder) (e.g., the length requirement of the input parameters of the RM encoder). Then, the first device can input the first sub-information bit sequence with added padding bits (e.g., zero bits or a known bit sequence) and the third bit sequence to the RM encoder (e.g., an RM(m-1,r2) encoder) to obtain the first sub-codeword sequence. The second threshold is determined based on the number of inputs required by the RM encoder and the number of outputs required by the first decoder (here, the first decoder is an RM decoder). X' is the difference between the second threshold and the number of first sub-information bits. It can be understood that the specific implementation of the first device adding X' padding bits to the first sub-information bit sequence can be referred to the relevant descriptions in Examples e1 to e4 above, and will not be repeated here.

[0198] For example, see [link to previous article] Figure 7a When the number of information bits K3'-K1' in the first sub-information bit sequence is less than the second threshold K2'-K1', the first device can add a certain number (e.g., X') of padding bits to the first sub-information bit sequence, such as adding a certain number of 0s or known bit sequences. This ensures that the length of the first sub-information bit sequence after adding padding bits meets the input parameter requirements of the first encoder. This process is also known as the rate matching process. Here, X' = (K2'-K1') - (K3'-K1') = K2'-K3', which means adding K2'-K3' padding bits to the first sub-information bit sequence.

[0199] The following describes the specific implementation of the first device inputting the fourth bit sequence into the second encoder to obtain the third subcodeword sequence. For details, please refer to method g1 and method g2 below.

[0200] Method g1: When the second encoder is an RM encoder, the first device can input the fourth bit sequence and the second sub-information bit sequence into the second encoder to obtain the third sub-codeword sequence.

[0201] In one possible implementation, the first device can also interleave the fourth bit sequence and the second sub-information bit sequence to obtain the seventh bit sequence. Then, the first device can input the seventh bit sequence into the second encoder to obtain the third sub-codeword sequence. For example, the first device can input the fourth bit sequence and the second sub-information bit sequence into an interleaver to obtain the seventh bit sequence.

[0202] The following examples illustrate the specific implementation of the first device interleaving the fourth bit sequence and the second sub-information bit sequence to obtain the seventh bit sequence.

[0203] Example h1: The first device arranges the fourth bit sequence before the second sub-information bit sequence to obtain the seventh bit sequence.

[0204] Please continue reading Figure 7a Continuing with the example of interleaving K1” integer bits and K2”-K1” information bits, the first device can arrange the K1” integer bits before the K2”-K1” information bits to obtain K2” bits. Alternatively, the first device can input the K1” integer bits and K2”-K1” information bits into an arrangement interleaver to obtain K2” bits. The arrangement interleaver is used to arrange the K1” integer bits before the K2”-K1” information bits. The K2” bits can be used to determine the seventh bit sequence.

[0205] Example h2: The first device interleaves the fourth bit sequence and the second sub-information bit sequence to obtain the seventh bit sequence.

[0206] Please continue reading Figure 7a Continuing with the example of interleaving K1” integer bits and K2”-K1” information bits, in one example, the first device can perform regular interleaving (e.g., equal-interval interleaving) of the K1” integer bits and K2”-K1” information bits to obtain K2” bits. For example, the first device can input the K1” integer bits and K2”-K1” information bits into an equal-interval interleaver to obtain K2” bits. The equal-interval interleaver is used to perform equal-interval interleaving (or equal-interval arrangement) of the K1” integer bits and K2”-K1” information bits.

[0207] In another example, the first device can irregularly interleave K1” integer bits and K2”-K1” information bits to obtain K2” bits. For example, the first device can input K1” integer bits and K2”-K1” information bits into an irregular interleaver to obtain K2” bits. The irregular interleaver is used to irregularly interleave (or irregularly arrange) the K1” integer bits and K2”-K1” information bits according to a given interleaving rule (or a given interleaving pattern or a given interleaving method).

[0208] In another example, the first device can input K1” integer bits and K2”-K1” information bits into the row-column interleaver to obtain K2” bits.

[0209] Example h3: The first device arranges the fourth bit sequence in the low-weight sequence position and the second sub-information bit sequence in the high-weight sequence position to obtain the seventh bit sequence.

[0210] Please continue reading Figure 7a Continuing with the example of interleaving K1” integer bits and K2”-K1” information bits, the first device can arrange the K1” integer bits in the sequence position with lower code weight and arrange the K2”-K1” information bits in the sequence position with higher code weight, thus obtaining K2” bits.

[0211] The following example illustrates method g1.

[0212] In one example, please see [link to example]. Figure 7a When the K1' shaped bits and K2'-K1' information bits are not interleaved, and when the K1" shaped bits and K2"-K1" information bits are not interleaved, the first device, after obtaining K1' shaped bits through the RM(m-1,r1) decoder, can input the K1' shaped bits and K2'-K1' information bits into the RM(m-1,r2) encoder to obtain the first bit after N / 2 probability shaping. Furthermore, after obtaining K1" shaped bits through the RM(m-1,r3) decoder, the first device can... The first bit and K2”-K1” information bits are input to the RM(m-1,r2-1) encoder to obtain N / 2 probability-shaped second bits. Then, the first device can XOR the N / 2 probability-shaped first bits and the N / 2 probability-shaped second bits to obtain N / 2 probability-shaped third bits. The N / 2 probability-shaped first bits (equivalent to the first half of the final output codeword sequence) and the N / 2 probability-shaped third bits (equivalent to the second half of the final output codeword sequence) are used as the final output codeword sequence.

[0213] In another example, please see [link to example]. Figure 7a In cases where K1' integer bits and K2'-K1' information bits are interleaved, and K1" integer bits and K2"-K1" information bits are also interleaved, the first device, after interleaving the K1' integer bits and K2'-K1' information bits to obtain K2' bits, can input the K2' bits into the RM(m-1,r2) encoder to obtain N / 2 probability-shaped first bits. Furthermore, after interleaving the K1" integer bits and K2"-K1" information bits to obtain K2" bits, the first device can input the K2" bits into the RM(m-1,r2-1) encoder to obtain N / 2 probability-shaped second bits. Then, the first device can perform an XOR operation on the N / 2 probability-shaped first bits and N / 2 probability-shaped second bits to obtain N / 2 probability-shaped third bits. The first bit and the third bit, after being shaped by N / 2 probabilities, are used as the codeword sequence for the final output.

[0214] In yet another example, please see [link to example]. Figure 7a In cases where K1' integer bits and K2'-K1' information bits are interleaved, and K1" integer bits and K2"-K1" information bits are not interleaved, the first device, after interleaving K1' integer bits and K2'-K1' information bits to obtain K2' bits, can input K2' bits into the RM(m-1,r2) encoder to obtain N / 2 probability-shaped first bits. Furthermore, the first device obtains K1" through the RM(m-1,r3) decoder. After shaping the first N / 2 integer bits, K1” integer bits and K2”-K1” information bits can be input to the RM(m-1,r2-1) encoder to obtain N / 2 probabilistically shaped second bits. Then, the first device can XOR the N / 2 probabilistically shaped first bits and the N / 2 probabilistically shaped second bits to obtain N / 2 probabilistically shaped third bits. These N / 2 probabilistically shaped first and third bits are used as the final output codeword sequence.

[0215] Optionally, based on the above method g2, when the number of information bits included in the second sub-information bit sequence (which can be understood as the length or size of the second sub-information bit sequence) is less than the third threshold, the first device can first add X” padding bits to the second sub-information bit sequence. This ensures that the length of the second sub-information bit sequence after adding padding bits meets the third threshold, thereby satisfying the input parameter requirements of the second encoder (here, the second encoder is an RM encoder) (e.g., the length requirement of the input parameters of the RM encoder). Then, the first device can input the second sub-information bit sequence with added padding bits (e.g., zero bits or a known bit sequence) and the fourth bit sequence to the RM encoder (e.g., an RM(m-1,r2-1) encoder) to obtain the third sub-codeword sequence. The third threshold is determined based on the number of inputs required by the RM encoder and the number of outputs required by the second decoder (here, the second decoder is an RM decoder). X” is the difference between the third threshold and the number of second sub-information bits. It can be understood that the specific implementation of the first device adding X” padding bits to the second sub-information bit sequence can be referred to the relevant descriptions in Examples e1 to e4 above, and will not be repeated here.

[0216] For example, see [link to previous article] Figure 7a When the number of information bits K3”-K1” in the second sub-information bit sequence is less than the second threshold K2”-K1”, the first device can add a certain number (e.g., X”) of padding bits to the second sub-information bit sequence, such as adding a certain number of 0s or known bit sequences. This ensures that the length of the second sub-information bit sequence after adding padding bits meets the input parameter requirements of the second encoder. This process is also known as the rate matching process. X' = (K2”-K1”) - (K3”-K1”) = K2”-K3”, which means adding K2”-K3” padding bits to the second sub-information bit sequence.

[0217] Method g2: If the second encoder is not an RM encoder, the first device can input the fifth bit sequence into the second encoder to obtain the third sub-codeword sequence. The fifth bit sequence may include the fourth bit sequence and the second sub-information bit sequence.

[0218] For example, when the second encoder is not an RM encoder, the second decoder can be a polar encoder or other encoders, etc.

[0219] The following example illustrates method g1.

[0220] In one example, please see [link to example]. Figure 7bWithout interleaving the K1' integer bits and K2'-K1' information bits, the first device, after obtaining K1' integer bits through the RM(m-1,r1) decoder, can input the K1' integer bits and K2'-K1' information bits into the RM(m-1,r2) encoder to obtain the first bit after N / 2 probability shaping. Furthermore, after obtaining N / 2 bits through the polar decoder, the first device can input N / 2 bits into the polar encoder to obtain the second bit after N / 2 probability shaping. Then, the first device can XOR the first and second bits after N / 2 probability shaping to obtain the third bit after N / 2 probability shaping. The first and third bits after N / 2 probability shaping are used as the final output codeword sequence. It is understood that the N / 2 bits mentioned here include K1” integer bits, K2”-K1” information bits, and N / 2-K1”-(K2”-K1”) frozen bits.

[0221] In another example, please see [link to example]. Figure 7b When the K1' integer bits and K2'-K1' information bits are interleaved, the first device, after interleaving the K1' integer bits and K2'-K1' information bits to obtain K2' bits, can input the K2' bits into the RM(m-1,r2) encoder to obtain the first bit after N / 2 probability shaping. Furthermore, after obtaining N / 2 bits through the polar decoder, the first device can input the N / 2 bits into the polar encoder to obtain the second bit after N / 2 probability shaping. Then, the first device can perform an XOR operation on the first bit and the second bit to obtain the third bit after N / 2 probability shaping. The first bit and the third bit after N / 2 probability shaping are used as the final output codeword sequence.

[0222] S404: The first device outputs a codeword sequence. Correspondingly, the second device acquires the sequence to be decoded.

[0223] In this application, "output" can refer to output via air interface or output to other devices or modules via internal interface of the device, and then the other devices or modules interleave and modulate the codeword sequence and map it onto resources for air interface transmission.

[0224] For example, the sequence to be decoded can be the information to be decoded obtained by the second device. Here, the sequence to be decoded corresponds to the encoded codeword sequence (or can be called the encoded bit sequence or the encoded information bit sequence).

[0225] In one implementation, the second device acquires the sequence to be decoded by receiving a physical signal over an air interface and then parsing the physical signal to obtain the sequence. Parsing the physical signal may involve operations such as demodulation and deinterleaving. Alternatively, the second device can acquire the sequence to be decoded locally via its internal interface. This acquisition can be obtained by parsing the physical signal from other local devices, apparatuses, or modules. The physical signal can carry the encoded bit sequence sent by the first device. The generation process of the encoded bit sequence can be referred to... Figure 4 The action of the first device in the process can be the codeword sequence obtained by the first device encoding the information bit sequence.

[0226] In other words, as an example, the first device can send a physical signal to the second device, which carries a codeword sequence. The second device receives the physical signal generated based on the codeword sequence, parses the physical signal, and obtains the sequence to be decoded. That is, the sequence to be decoded corresponds to the codeword sequence sent by the first device.

[0227] Optionally, the sequence to be decoded can be a codeword sequence that has undergone rate matching, modulation, and other operations and then transmitted to a second device via a wireless transmission environment.

[0228] S405: The second device determines the information bit sequence based on P decoders and the sequence to be decoded.

[0229] Among the P decoders, there is a first decoder. In this application, the first decoder is an RM decoder. Here, P is an integer greater than or equal to 1. It can be understood that the first decoder here corresponds to the first encoder on the first device side. For example, the order of the first decoder can be 1st or 2nd order. For instance, the first decoder can be a low-complexity decoder such as a 1st order FHT decoder.

[0230] The following describes several possible implementation methods for the second device to determine the information bit sequence based on P decoders and the sequence to be decoded.

[0231] Mode v1: When P equals 1, this single decoder is the first decoder. If the information bit sequence has not been interleaved, the second device inputs the sequence to be decoded into the first decoder to obtain the information bit sequence. Optionally, the second device can also input the sequence to be decoded into the first decoder to obtain the first bit sequence.

[0232] In one possible implementation, if the information bit sequence has been interleaved, the second device inputs the sequence to be decoded into the first decoder to obtain the second bit sequence. Then, the second device can deinterleave the second bit sequence to obtain the information bit sequence.

[0233] Method v2: When P is greater than 1, taking P decoders (including a first decoder and a second decoder), the sequence to be decoded (including a first sub-sequence to be decoded and a second sub-sequence to be decoded), and the information bit sequence (including a first sub-information bit sequence and a second sub-information bit sequence) as an example. The first sub-sequence to be decoded corresponds to the first sub-codeword sequence in the codeword sequence, and the second sub-sequence to be decoded corresponds to the second sub-codeword sequence in the codeword sequence. The second device can perform an XOR operation on the first and second sub-sequences to be decoded to obtain a third sub-sequence to be decoded. The third sub-sequence to be decoded corresponds to the third sub-codeword sequence, and the second sub-codeword sequence is determined based on the first and third sub-codeword sequences. Then, the second device can input the first sub-sequence to be decoded into the first decoder to obtain the first sub-information bit sequence. Similarly, the second device can input the third sub-sequence to be decoded into the second decoder to obtain the second sub-information bit sequence. For example, the second decoder can be an RM decoder, or it can be a non-RM decoder. Optionally, the second device can input the first sub-sequence to be decoded into the first decoder to obtain the third bit sequence. It can be understood that the second decoder here corresponds to the second encoder on the first device side.

[0234] In one possible implementation, if the first sub-information bit sequence has been interleaved, the second device inputs the first sub-decoder sequence to the first decoder to obtain the sixth bit sequence. Then, the second device can deinterleave the sixth bit sequence to obtain the first sub-information bit sequence.

[0235] The following examples illustrate the specific implementation of how a second device inputs a third sub-sequence to be decoded into a second decoder to obtain a second sub-information bit sequence.

[0236] Example y1: When the second decoder is an RM decoder, if the second sub-information bit sequence has not undergone interleaving, the second device inputs the third sub-sequence to be decoded into the second decoder to obtain the second sub-information bit sequence. Optionally, the second device can also input the sequence to be decoded into the first decoder to obtain the fourth bit sequence.

[0237] In one possible implementation, if the second sub-information bit sequence has been interleaved, the second device inputs the third sub-decoder sequence to the second decoder to obtain the seventh bit sequence. Then, the second device can deinterleave the seventh bit sequence to obtain the second sub-information bit sequence.

[0238] Example y2: When the second decoder is not an RM decoder, the second device inputs the third sub-sequence to be decoded into the second decoder (e.g., a polar decoder) to obtain the fifth bit sequence. The fifth bit sequence includes the second sub-information bit sequence. Optionally, the fifth bit sequence also includes the fourth bit sequence.

[0239] As can be seen from S401 to S405 above, the first device only needs to decode the first bit sequence (which can be understood as the integer bit sequence) using the first decoder, without needing to decode the information bit sequence. This simplifies the decoding process (the decoding process of the first decoder is more simplified, and the complexity of the decoding process is low), helping to reduce decoding complexity and thus achieving low-complexity probability shaping. Furthermore, compared to the relatively high complexity of probability shaping in existing technologies, this method, utilizing a cascaded first decoder and first encoder, can achieve probability shaping more accurately and efficiently, not only with low complexity but also with virtually no loss in decoding performance even at longer code lengths.

[0240] The above mainly describes the solution provided by the embodiments of this application from the perspective of the interaction between the first device and the second device. It is understood that, in order to achieve the above functions, the first device and the second device may include hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should readily recognize that, in conjunction with the units and algorithm steps of the various examples described in the embodiments disclosed herein, the embodiments of this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed by hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0241] In this application embodiment, the first device and the second device can be divided into functional units according to the above method example. For example, each function can be divided into a separate functional unit, or two or more functions can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0242] When using integrated units, Figure 8 This diagram illustrates a possible exemplary block diagram of a communication device involved in an embodiment of this application. This communication device can be used to implement the functions of the first or second device in the above method embodiments, and thus can also achieve the beneficial effects of the above method embodiments. For example, the communication device can be the first or second device, or it can be a module (e.g., a processor, chip, or chip system, etc.) within the first or second device.

[0243] like Figure 8 As shown, the communication device 800 may include a transceiver module 801 (or a communication module, transceiver unit, or communication unit, used for sending and receiving data) and a processing module 802 (or a processing unit). The transceiver module 801 supports communication between the communication device 800 and other communication devices. Optionally, Figure 8 The communication device 800 shown may further include a storage module 803 (or storage unit). For example, the transceiver module 801 may include a sending module and / or a receiving module, respectively used to perform the sending and receiving steps of the first device or the second device in the above method embodiments. The processing module 802 may be used to read instructions and / or data from the storage module to enable the communication device 800 to implement the aforementioned method embodiments. The storage module 803 is used to store the program code and / or data of the communication device 800.

[0244] When the communication device 800 is used to achieve the above Figure 4 In the illustrated method embodiment, the first device functions as follows: a transceiver module 801 is used to acquire a log-likelihood ratio sequence. A processing module 802 is used to determine a first bit sequence based on P decoders and the log-likelihood ratio sequence. The P decoders include a first decoder, which is an RM decoder. P is an integer greater than or equal to 1. The first bit sequence is used for probability shaping. The processing module 802 is also used to determine a codeword sequence based on P encoders, the first bit sequence, and an information bit sequence. The P encoders include a first encoder, which is an RM encoder.

[0245] When the communication device 800 is used to achieve the above Figure 4 In the illustrated method embodiment, the second device functions as follows: a transceiver module 801, used to acquire the sequence to be decoded. The sequence to be decoded corresponds to a codeword sequence. A processing module 802, used to determine the information bit sequence based on P decoders and the sequence to be decoded. The P decoders include a first decoder, which is an RM decoder. Here, P is an integer greater than or equal to 1.

[0246] For a more detailed description of the processing module 802 and the transceiver module 801, please refer to the above. Figure 4 The relevant descriptions in the method embodiments shown will not be repeated here.

[0247] It should be understood that the transceiver module 801 in the embodiments of this application can be implemented by a communication interface or communication interface-related circuit components, and the processing module 802 can be implemented by a processor or processor-related circuit components.

[0248] It should be noted that the module division in the embodiments of this application is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods. Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, exist as separate physical entities, or have two or more units integrated into one unit. The integrated units described above can be implemented in hardware or as software functional units.

[0249] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, or a server, etc.) or processor to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0250] Based on the same technical concept, embodiments of this application also provide a communication device for implementing the functions of the first or second device described above. For example... Figure 9 As shown, the communication device 900 can be a communication device or a component within a communication device (e.g., a processor, chip, or chip system). The communication device 900 includes a processor 901 and a communication interface 902. Optionally, the communication device 900 also includes a memory 903. The memory 903 can be independent of the processor 901 or integrated into the processor 901; no specific limitation is made. It is understood that... Figure 9 Only the main components of the communication device 900 are shown. In one possible implementation, the communication device 900 may further include input / output devices (not shown in the figure).

[0251] The processor 901 is used to execute the program code stored in the memory 903, specifically to perform the actions of the processing module 802 described above, which will not be described in detail here. The communication interface 902 is specifically used to perform the actions of the transceiver module 801 described above, which will not be described in detail here.

[0252] Processor 901 can be a central processing unit (CPU) or a digital processing unit, etc. Processor 901 can be used to process communication protocols and communication data, control the entire communication device, execute software programs, and process software program data, such as, but not limited to, baseband-related processing. Communication interface 902 can be used for transmitting and receiving signals, such as, but not limited to, radio frequency (RF) transceiver. The above-mentioned devices can be disposed on separate chips, or at least partially or entirely on the same chip. For example, processor 901 can be further divided into an analog baseband processor and a digital baseband processor. The analog baseband processor can be integrated with the transceiver on the same chip, while the digital baseband processor can be disposed on a separate chip. With the continuous development of integrated circuit technology, more and more devices can be integrated on the same chip. For example, a digital baseband processor can be integrated with multiple application processors (such as, but not limited to, graphics processors, multimedia processors, etc.) on the same chip. Such a chip can be called a system-on-a-chip (SoC). Whether to dispose of individual devices independently on different chips or integrate them on one or more chips often depends on the specific needs of the product design. The embodiments of this application do not limit the specific implementation of the above-mentioned devices.

[0253] The communication interface 902 can be a transceiver, an interface circuit such as a transceiver circuit, or a transceiver chip, etc. Optionally, the communication interface 902 may include radio frequency (RF) circuitry and an antenna. The RF circuitry is mainly used for converting baseband signals to RF signals and processing RF signals. The antenna is mainly used for transmitting and receiving RF signals in the form of electromagnetic waves. Optionally, the communication interface 902 can be an input / output interface or a chip pin.

[0254] Input / output devices, such as touchscreens, displays, and keyboards, are primarily used to receive user input data and output data to the user.

[0255] Memory 903 is used to store programs executed by processor 901. Memory 903 can be non-volatile memory, such as a hard disk drive (HDD) or solid-state drive (SSD), or it can be volatile memory, such as cache or random-access memory (RAM). Memory 903 can be any other medium capable of carrying or storing desired program code in the form of instructions or data structures that can be accessed by a computer, but is not limited to this.

[0256] When the communication device is powered on, the processor 901 can read the software program in the memory 903, interpret and execute the instructions of the software program, and process the data of the software program. When data needs to be transmitted wirelessly, the processor 901 performs baseband processing on the data to be transmitted and outputs the baseband signal to the radio frequency (RF) circuit. The RF circuit processes the baseband signal and transmits the RF signal outward in the form of electromagnetic waves through the antenna. When data is sent to the communication device, the RF circuit receives the RF signal through the antenna, converts the RF signal into a baseband signal, and outputs the baseband signal to the processor 901. The processor 901 converts the baseband signal into data and processes the data.

[0257] In another implementation, the radio frequency circuitry and antenna can be set up independently of the processor performing baseband processing. For example, in a distributed scenario, the radio frequency circuitry and antenna can be arranged remotely, independent of the communication device.

[0258] This application embodiment does not limit the specific connection medium between the communication interface 902, processor 901, and memory 903. This application embodiment... Figure 9 The memory 903, processor 901, and communication interface 902 are connected via a bus 904. Figure 9 The connections between other components are shown in bold lines only and are not intended to be limiting. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, Figure 9 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0259] Optionally, the communication device described above can be a standalone device or part of a larger device. For example, the communication device can be:

[0260] (1) An independent integrated circuit (IC), or chip, or chip system or subsystem;

[0261] (2) A collection of one or more ICs, optionally including a storage component for storing data and instructions;

[0262] (3) Application-specific integrated circuit (ASIC), such as modem;

[0263] (4) Modules that can be embedded in other devices;

[0264] (5) Receivers, smart terminals, wireless devices, handheld devices, mobile units, vehicle-mounted devices, cloud devices, artificial intelligence devices, etc.;

[0265] (6) Others, etc.

[0266] Based on the same concept, this application also provides a communication system, including the first device and the second device involved in the above method embodiments.

[0267] Based on the same concept, this application also provides a computer program product, which includes a computer program or instructions that, when run on a communication device (or computer), cause the communication device (or computer) to perform the methods provided in the above embodiments.

[0268] Based on the same concept, embodiments of this application also provide a computer-readable storage medium storing a computer program or instructions that, when executed by a communication device (or computer), cause the communication device (or computer) to perform the methods provided in the above embodiments.

[0269] The storage medium can be any available medium that a computer can access. For example, but not limited to, a computer-readable medium can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, magnetic disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer.

[0270] Based on the same concept, embodiments of this application also provide a chip, which may include a processor and a memory (or the chip may be coupled to the memory). The processor executes program instructions in the memory to cause the chip to perform the methods provided in the above embodiments. Here, "coupling" means that two components are directly or indirectly connected to each other, such as coupling can refer to an electrical connection between two components.

[0271] Based on the same concept, embodiments of this application also provide a chip system, which includes a processor for supporting a computer device in implementing the functions involved in the first or second device in the above embodiments. In one possible implementation, the chip system further includes a memory for storing necessary programs and data of the computer device. This chip system may be composed of chips or may include chips and other discrete components.

[0272] In this application embodiment, "multiple" can refer to two or more. Therefore, in this application embodiment, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, "including at least one" means including one, two, or more. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A, B, and C. "And / or" describes the association relationship between related objects. Specifically, there can be three relationships. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / ", unless otherwise specified, generally indicates that the preceding and following related objects have an "or" relationship.

[0273] Furthermore, the terms "system" and "network" in the embodiments of this application can be used interchangeably, as can "according to" and "based on". The ordinal numbers such as "first" and "second" mentioned in the embodiments of this application are generally used to distinguish different objects and are not used to limit the order, sequence, priority, or importance of multiple objects. For example, the first device and the second device in the embodiments of this application are used to distinguish two communication devices, but do not limit the priority or importance of these two communication devices.

[0274] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0275] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0276] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0277] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

Claims

1. An encoding method, characterized in that, The method, which applies to a first device or a chip in the first device, includes: Obtain the log-likelihood ratio sequence; A first bit sequence is determined based on P decoders and the log-likelihood ratio sequence, wherein the P decoders include a first decoder, which is a Reid-Muller RM decoder, and P is an integer greater than or equal to 1. The first bit sequence is used for probability shaping. A codeword sequence is determined based on P encoders, the first bit sequence, and the information bit sequence. The P encoders include the first encoder, which is an RM encoder. Output the codeword sequence.

2. The method as described in claim 1, characterized in that, The order of the first decoder is less than or equal to the order of the first encoder.

3. The method as described in claim 1 or 2, characterized in that, The value of P is 1; The method further includes: Based on the information bit sequence, determine the first sequence; Determining the first bit sequence based on the P decoders and the log-likelihood ratio sequence includes: The log-likelihood ratio sequence and the first sequence are input into the first decoder to obtain the first bit sequence.

4. The method according to any one of claims 1-3, characterized in that, The value of P is 1; The step of determining the codeword sequence based on the P encoders, the first bit sequence, and the information bit sequence includes: The first bit sequence and the information bit sequence are interleaved to obtain the second bit sequence; The second bit sequence is input into the first encoder to obtain the codeword sequence.

5. The method as described in claim 4, characterized in that, The first bit sequence and the information bit sequence are interleaved to obtain a second bit sequence, including: The first bit sequence is arranged before the information bit sequence to obtain the second bit sequence; or... The first bit sequence and the information bit sequence are interleaved to obtain the second bit sequence; or... The first bit sequence is arranged in a low-weight sequence position, and the information bit sequence is arranged in a high-weight sequence position to obtain the second bit sequence.

6. The method according to any one of claims 1-5, characterized in that, The method further includes: If the number of information bits in the information bit sequence is less than a first threshold, then X padding bits are added to the information bit sequence. The first threshold is determined based on the number of inputs required by the first encoder and the number of outputs required by the first decoder, and X is the difference between the first threshold and the number of information bits.

7. The method as described in claim 6, characterized in that, Adding X padding bits to the information bit sequence includes: Add X padding bits before the information bit sequence; or, Add X padding bits after the information bit sequence; or, X padding bits are added to the information bit sequence using a preset interleaving method; or, X padding bits are added to the information bit sequence at preset intervals.

8. The method as described in claim 1 or 2, characterized in that, Where P is greater than 1, the P decoders include the first decoder and the second decoder, the log-likelihood ratio sequence includes the first sub-log-likelihood ratio sequence and the second sub-log-likelihood ratio sequence, the first bit sequence includes the third bit sequence and the fourth bit sequence, and the information bit sequence includes the first sub-information bit sequence and the second sub-information bit sequence, the first sub-information bit sequence corresponds to the first sub-log-likelihood ratio sequence, and the second sub-information bit sequence corresponds to the second sub-log-likelihood ratio sequence; Determining the first bit sequence based on the P decoders and the log-likelihood ratio sequence includes: The third bit sequence is determined based on the first sublog-likelihood ratio sequence and the first decoder; The fourth bit sequence is determined based on the second sublog-likelihood ratio sequence and the second decoder.

9. The method as described in claim 8, characterized in that, The method further includes: Determine the second sequence based on the first sub-information bit sequence; Determining the third bit sequence based on the first sub-log-likelihood ratio sequence and the first decoder includes: The first sublog-likelihood ratio sequence and the second sequence are input into the first decoder to obtain the third bit sequence.

10. The method as described in claim 8 or 9, characterized in that, The second decoder is an RM decoder; The method further includes: The third sequence is determined based on the second sub-information bit sequence; Determining the fourth bit sequence based on the second sub-log-likelihood ratio sequence and the second decoder includes: The second sublog-likelihood ratio sequence and the third sequence are input into the second decoder to obtain the fourth bit sequence.

11. The method as described in claim 8 or 9, characterized in that, The second decoder is not an RM decoder; Determining the fourth bit sequence based on the second sub-log-likelihood ratio sequence and the second decoder includes: The second sub-log-likelihood ratio sequence is input to the second decoder to obtain the fifth bit sequence, which includes the fourth bit sequence and the second sub-information bit sequence.

12. The method as described in claim 8, characterized in that, Where P is greater than 1, the P encoders include the first encoder and the second encoder, and the codeword sequence includes the first sub-codeword sequence and the second sub-codeword sequence; The step of determining the codeword sequence based on the P encoders, the first bit sequence, and the information bit sequence includes: The third bit sequence and the first sub-information bit sequence are input into the first encoder to obtain the first sub-codeword sequence; The fourth bit sequence is input into the second encoder to obtain the third sub-codeword sequence; The second sub-codeword sequence is obtained by performing an XOR operation on the first sub-codeword sequence and the third sub-codeword sequence.

13. The method as described in claim 12, characterized in that, The step of inputting the third bit sequence and the first sub-information bit sequence into the first encoder to obtain the first sub-codeword sequence includes: The third bit sequence and the first sub-information bit sequence are interleaved to obtain the sixth bit sequence; The sixth bit sequence is input into the first encoder to obtain the first subcodeword sequence.

14. The method as described in claim 13, characterized in that, The process of interleaving the third bit sequence and the first sub-information bit sequence to obtain the sixth bit sequence includes: Arrange the third bit sequence before the first sub-information bit sequence to obtain the sixth bit sequence; or... The third bit sequence and the first sub-information bit sequence are interleaved to obtain the sixth bit sequence; or... The third bit sequence is arranged in a low-weight sequence position, and the first sub-information bit sequence is arranged in a high-weight sequence position to obtain the sixth bit sequence.

15. The method according to any one of claims 12-14, characterized in that, The second encoder is an RM encoder; The step of inputting the fourth bit sequence into the second encoder to obtain the third sub-codeword sequence includes: The fourth bit sequence and the second sub-information bit sequence are input into the second encoder to obtain the third sub-codeword sequence.

16. The method as described in claim 15, characterized in that, The step of inputting the fourth bit sequence and the second sub-information bit sequence into the second encoder to obtain the third sub-codeword sequence includes: The fourth bit sequence and the second sub-information bit sequence are interleaved to obtain the seventh bit sequence; The seventh bit sequence is input into the second encoder to obtain the third subcodeword sequence.

17. The method as described in claim 16, characterized in that, The process of interleaving the fourth bit sequence and the second sub-information bit sequence to obtain the seventh bit sequence includes: Arrange the fourth bit sequence before the second sub-information bit sequence to obtain the seventh bit sequence; or... The fourth bit sequence and the second sub-information bit sequence are interleaved to obtain the seventh bit sequence; or... The fourth bit sequence is arranged in a low-weight sequence position, and the second sub-information bit sequence is arranged in a high-weight sequence position to obtain the seventh bit sequence.

18. The method according to any one of claims 12-14, characterized in that, The second encoder is not an RM encoder; The step of inputting the fourth bit sequence into the second encoder to obtain the third sub-codeword sequence includes: The fifth bit sequence is input to the second encoder to obtain the third sub-codeword sequence, wherein the fifth bit sequence includes the fourth bit sequence and the second sub-information bit sequence.

19. A decoding method, characterized in that, The method, which applies to a second device or a chip in the second device, includes: Obtain the sequence to be decoded, which corresponds to the codeword sequence; The information bit sequence is determined based on P decoders and the sequence to be decoded. The P decoders include a first decoder, which is an RM decoder, and P is an integer greater than or equal to 1.

20. The method as described in claim 19, characterized in that, The value of P is 1; The step of determining the information bit sequence based on P decoders and the sequence to be decoded includes: The sequence to be decoded is input into the first decoder to obtain the information bit sequence.

21. The method as described in claim 20, characterized in that, The step of inputting the sequence to be decoded into the first decoder to obtain the information bit sequence includes: The sequence to be decoded is input into the first decoder to obtain the second bit sequence; The second bit sequence is deinterleaved to obtain the information bit sequence.

22. The method as described in claim 19, characterized in that, Where P is greater than 1, the P decoders include the first decoder and the second decoder, the sequence to be decoded includes the first sub-sequence to be decoded and the second sub-sequence to be decoded, the first sub-sequence to be decoded corresponds to the first sub-codeword sequence in the codeword sequence, the second sub-sequence to be decoded corresponds to the second sub-codeword sequence in the codeword sequence, and the information bit sequence includes the first sub-information bit sequence and the second sub-information bit sequence. The step of determining the information bit sequence based on P decoders and the sequence to be decoded includes: An XOR operation is performed on the first sub-decoding sequence and the second sub-decoding sequence to obtain a third sub-decoding sequence, which corresponds to a third sub-codeword sequence. The second sub-codeword sequence is determined based on the first sub-codeword sequence and the third sub-codeword sequence. The first sub-sequence to be decoded is input into the first decoder to obtain the first sub-information bit sequence; The third sub-sequence to be decoded is input into the second decoder to obtain the second sub-information bit sequence.

23. The method as described in claim 22, characterized in that, The step of inputting the first sub-sequence to be decoded into the first decoder to obtain the first sub-information bit sequence includes: The first sub-sequence to be decoded is input into the first decoder to obtain the sixth bit sequence; The sixth bit sequence is deinterleaved to obtain the first sub-information bit sequence.

24. The method as described in claim 22 or 23, characterized in that, The second decoder is an RM decoder; The step of inputting the third sub-decoding sequence into the second decoder to obtain the second sub-information bit sequence includes: The third sub-sequence to be decoded is input into the second decoder to obtain the seventh bit sequence; The seventh bit sequence is deinterleaved to obtain the second sub-information bit sequence.

25. The method as described in claim 22 or 23, characterized in that, The second decoder is not an RM decoder; The step of inputting the third sub-decoding sequence into the second decoder to obtain the second sub-information bit sequence includes: The third sub-sequence to be decoded is input into the second decoder to obtain the fifth bit sequence, which includes the second sub-information bit sequence.

26. A communication device, characterized in that, It includes modules or units for performing the method as described in any one of claims 1-18, or modules or units for performing the method as described in any one of claims 19-25.

27. A communication device, characterized in that, Includes at least one processor and a communication interface; The communication interface is used to receive signals from other communication devices and transmit them to the at least one processor, or to send signals from the at least one processor to other communication devices. The at least one processor is configured to implement the method as described in any one of claims 1-18 or the method as described in any one of claims 19-25 through logic circuits or execution code instructions.

28. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program or instructions that, when executed by a communication device, cause the method as described in any one of claims 1-18 or the method as described in any one of claims 19-25 to be implemented.

29. A computer program product, characterized in that, The computer program product includes a computer program or instructions that, when executed on a communication device, cause the method as described in any one of claims 1-18 or the method as described in any one of claims 19-25 to be implemented.

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