Data encoding, data decoding method, device, equipment and storage medium

Abstract

The application discloses a data coding method, a data decoding method, a device, an apparatus and a storage medium, and belongs to the technical field of communication. The method comprises the following steps: acquiring a bit sequence, the bit sequence comprising two bit groups, a first bit group in the two bit groups comprising two binary data, and a second bit group comprising three binary data; encoding the bit sequence according to a coding conversion relationship to obtain a symbol sequence, the symbol sequence comprising two hexadecimal symbols, the coding conversion relationship being a conversion relationship from the two binary data in the first bit group and two ternary symbols to the two hexadecimal symbols, and the two ternary symbols being obtained by encoding the three binary data in the second bit group. The two ternary symbols are obtained by encoding the binary data in the second bit group through a PAM3 coding circuit, and the PAM3 coding circuit has the advantages of simple structure and low time delay.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to data encoding, data decoding methods, apparatus, devices and storage media. Background Technology

[0002] In the field of communication technology, pulse amplitude modulation (PAM) is used for data encoding, which encodes binary data into a symbol sequence for transmission in the physical medium. Among them, six-level pulse amplitude modulation (PAM6) encoding can provide higher data rates and better spectral efficiency compared to three-level pulse amplitude modulation (PAM3) encoding.

[0003] In related technologies, 5-bit 2-senary (5B2S) encoding based on 32-constellation quadrature amplitude modulation (QAM) can be implemented in two ways. One method involves looking up a table for each 5-bit binary data to determine its corresponding 2-senary symbol, then encoding the 5 bits into the found 2-senary symbol. This method has high lookup complexity and significant latency. The other method converts the 5-bit data directly into 2-senary symbols, which consumes more resources. Summary of the Invention

[0004] This application provides a data encoding and decoding method, apparatus, device, and storage medium to solve the problems existing in related technologies. The technical solution is as follows.

[0005] Firstly, a data encoding method is provided, comprising: acquiring a bit sequence, the bit sequence including two bit groups, the first bit group including two binary data, and the second bit group including three binary data; encoding the bit sequence according to an encoding conversion relationship to obtain a symbol sequence, the symbol sequence including two hexadecimal symbols, the encoding conversion relationship being a conversion relationship from the two binary data and two ternary symbols in the first bit group to two hexadecimal symbols, the two ternary symbols being obtained by encoding the three binary data in the second bit group.

[0006] The two ternary symbols obtained by encoding the binary data in the second bit group are achieved through PAM3 encoding. First, PAM3 encoding is performed to obtain ternary symbols, and then the two ternary symbols obtained by encoding are converted into two hexadecimal symbols based on the binary data in the first bit group. The above encoding process can reuse the PAM3 encoding circuit, taking advantage of the simple structure and low latency of the PAM3 encoding circuit.

[0007] Furthermore, the process of converting two ternary symbols into two hexadecimal symbols based on the first bit group can be directly converted using logic circuits. Compared to related technologies that involve looking up the entire 5-bit binary data in a table to obtain two hexadecimal symbols, this method has lower latency and higher encoding efficiency. This application splits the bit sequence into shorter bit groups. The computational complexity involved in performing the conversion based on these shorter bit groups is lower than directly calculating the bit sequence. Converting the entire bit sequence into two binary data based on the calculation result has lower computational complexity and reduces resource consumption.

[0008] In one possible implementation, the two ternary symbols are obtained based on a mapping relationship, which indicates the mapping relationship between the three binary data in the second bit group and the two ternary symbols. Since there is a mapping relationship between the two ternary symbols and the three binary data in the second bit group, this mapping relationship can be used not only to encode the three binary data into two ternary symbols during encoding, but also to decode the two ternary symbols into three binary data during decoding, resulting in high utilization.

[0009] In one possible implementation, the encoding conversion relationship includes a first conversion relationship and a second conversion relationship. The first conversion relationship is the conversion relationship from two binary data in the first bit group to any symbol partition, where any symbol partition includes eight hexadecimal symbol pairs. The second conversion relationship is the conversion relationship from two ternary symbols to one of the eight hexadecimal symbol pairs. Since encoding three binary data may result in 8 ternary symbol pairs, and encoding five binary data may result in 32 hexadecimal symbol pairs, these 32 hexadecimal symbol pairs are divided into different symbol partitions. The number of hexadecimal symbol pairs included in a symbol partition is the same as the number of ternary symbol pairs obtained from encoding three binary data, for example, both are 8. Hexadecimal symbol pairs and ternary symbol pairs with the same number can be converted based on the second conversion relationship.

[0010] In one possible implementation, in any pair of hexadecimal symbols included in a symbol partition, the signal level of the hexadecimal symbol in the first bit field is a first level, and the signal level of the hexadecimal symbol in the second bit field is a second level, and both the first and second levels include three signal levels; or, in any pair of hexadecimal symbols included in a symbol partition, the signal level of the hexadecimal symbol in the first bit field is a third level, and the signal level of the hexadecimal symbol in the second bit field is a fourth level, and the three signal levels included in the third level are different from the three signal levels included in the first level, and the three signal levels included in the fourth level are different from the three signal levels included in the second level; or, in any pair of hexadecimal symbols included in a symbol partition, the signal level of the hexadecimal symbol in the first bit field is a first level, and the signal level of the hexadecimal symbol in the second bit field is a fourth level; or, in any pair of hexadecimal symbols included in a symbol partition, the signal level of the hexadecimal symbol in the first bit field is a third level, and the signal level of the hexadecimal symbol in the second bit field is a second level. First, the signal level of the hexadecimal symbol in each bit field is classified. Then, based on the classification of the signal level, multiple hexadecimal symbol pairs are divided into different symbol partitions. The process of dividing the symbol partitions is simple and has low operational complexity.

[0011] In one possible implementation, at least one of the first, second, third, or fourth levels comprises three signal levels that are equally spaced. This equal-spaced classification ensures that the three signal levels within each level maintain a similar leveling distance to the PAM3 signal levels. In this case, the probability of any signal level malfunctioning into an adjacent level is the same, allowing for the use of the same error probability calculation, resulting in low circuit complexity.

[0012] In one possible implementation, the three signal levels included in the first level are the same as the three signal levels included in the second level, and the three signal levels included in the third level and the three signal levels included in the fourth level are the same. Classifying the signal levels of the hexadecimal symbols in the first bit field and the second bit field in the same way reduces classification complexity and thus improves the efficiency of symbol partitioning.

[0013] In one possible implementation, at least one of the first, second, third, or fourth levels includes three consecutive signal levels. Since the three signal levels corresponding to the same bit field in a symbol partition are consecutive, and the hexadecimal symbol pairs in the same symbol partition are hexadecimal symbol pairs with adjacent signal levels, and since the binary data in the first bit group of the five binary data corresponding to the hexadecimal symbol pairs in a symbol partition are identical, the number of different bits between the five binary data corresponding to the same symbol partition may be lower than the number of different bits between the five binary data corresponding to different symbol partitions. By controlling the number of different bits between the five binary data corresponding to the hexadecimal symbol pairs with adjacent signal levels, the number of different bits between the decoded bit sequence and the encoded bit sequence can be reduced when the symbol sequence changes during transmission, thereby reducing the number of erroneous bits.

[0014] In one possible implementation, at least one of the first, second, third, or fourth levels comprises three discontinuous signal levels. In a symbol partition based on the first, second, third, and fourth levels, the level interval between hexadecimal symbol pairs is large, and the probability of the signal level of a hexadecimal symbol within a hexadecimal symbol pair changing to an adjacent signal level is low.

[0015] In one possible implementation, obtaining the bit sequence includes: obtaining the data segment to be encoded; performing forward error correction (FEC) encoding on the data segment; and obtaining the bit sequence based on the encoding result. The data encoding method provided in this application can also be used in conjunction with FEC encoding. FEC encoding allows for error correction during the decoding process, resulting in higher accuracy.

[0016] Secondly, a data decoding method is provided, comprising: acquiring a symbol sequence, the symbol sequence including two hexadecimal symbols; decoding the two hexadecimal symbols into a bit sequence according to a decoding conversion relationship, the bit sequence including two bit groups, the first bit group including two binary data, and the second bit group including three binary data; wherein, the decoding conversion relationship is a conversion relationship from two hexadecimal symbols to two ternary symbols and the two binary data in the first bit group, and the two ternary symbols are obtained by encoding the three binary data in the second bit group.

[0017] Since two ternary symbols are obtained by encoding three binary data points in the second bit group, PAM3 decoding of the two ternary symbols yields the three binary data points in the second bit group. During the process of decoding the symbol sequence to obtain the bit sequence, the PAM3 decoding circuit can be reused, leveraging its advantages of simple structure and low latency. Furthermore, through the decoding conversion relationship, two hexadecimal symbols can be converted into two ternary symbols obtained from the first bit group and the encoded second bit group. Two hexadecimal symbols can be converted into multiple types of information, resulting in high conversion efficiency.

[0018] In one possible implementation, the two hexadecimal symbols are located in any symbol partition. The decoding conversion relationship includes a third conversion relationship and a fourth conversion relationship. The third conversion relationship is the conversion relationship from any symbol partition to two binary data in the first bit group, and the fourth conversion relationship is the conversion relationship from two hexadecimal symbols to two ternary symbols. Both the third and fourth conversion relationships can be implemented by logic circuits, and the above conversion process can be directly converted based on logic circuits, resulting in low latency. Furthermore, this application does not limit the order in which the conversion based on the third conversion relationship and the conversion based on the fourth conversion relationship are performed; they can be executed serially or in parallel, offering high flexibility.

[0019] In one possible implementation, the signal level of the hexadecimal symbol located in the first bit field of the two hexadecimal symbols belongs to the first level, and the signal level of the hexadecimal symbol located in the second bit field belongs to the second level. Any symbol partition where the two hexadecimal symbols are located is the symbol partition corresponding to the first level and the second level, and both the first and second levels comprise three signal levels. Alternatively, the signal level of the hexadecimal symbol located in the first bit field of the two hexadecimal symbols belongs to the third level, and the signal level of the hexadecimal symbol located in the second bit field belongs to the fourth level. Any symbol partition where the two hexadecimal symbols are located is the symbol partition corresponding to the third and fourth levels, and the third level comprises the three signal levels and the first level. The three signal levels included in the first level are all different; the three signal levels included in the fourth level are all different from the three signal levels included in the second level. Alternatively, in two hexadecimal symbols, the signal level of the hexadecimal symbol in the first bit field belongs to the first level, and the signal level of the hexadecimal symbol in the second bit field belongs to the fourth level. Any symbol partition in which the two hexadecimal symbols are located corresponds to the first and fourth levels. Or, in two hexadecimal symbols, the signal level of the hexadecimal symbol in the first bit field belongs to the third level, and the signal level of the hexadecimal symbol in the second bit field belongs to the second level. Any symbol partition in which the two hexadecimal symbols are located corresponds to the third and second levels. When symbol partitioning is based on signal level, the signal levels of each pair of hexadecimal symbols in a symbol partition follow a pattern. For example, the signal levels of the hexadecimal symbols in the first bit field of a certain symbol partition all belong to the first level. In this case, the symbol partition to which the two hexadecimal symbols belong can be determined based on the signal levels of each hexadecimal symbol, resulting in a short time requirement and high efficiency.

[0020] Thirdly, a symbol sequence structure is also provided. The symbol sequence structure is a sequence structure obtained by encoding a bit sequence according to an encoding conversion relationship. The bit sequence includes two bit groups. The first bit group includes two binary data, and the second bit group includes three binary data. The symbol sequence structure includes two hexadecimal symbols. The encoding conversion relationship is the conversion relationship from the two binary data and two ternary symbols in the first bit group to two hexadecimal symbols. The two ternary symbols are obtained by encoding the three binary data in the second bit group.

[0021] In one possible implementation, when the three binary data in the second bit group are 101, the two ternary symbols are 1-1; when the three binary data in the second bit group are 100, the two ternary symbols are 10; when the three binary data in the second bit group are 110, the two ternary symbols are 11; when the three binary data in the second bit group are 001, the two ternary symbols are 0-1; when the three binary data in the second bit group are 111, the two ternary symbols are 01; when the three binary data in the second bit group are 000, the two ternary symbols are -1-1; when the three binary data in the second bit group are 010, the two ternary symbols are -10; and when the three binary data in the second bit group are 011, the two ternary symbols are -11.

[0022] In one possible implementation, the encoding conversion relationship includes a first conversion relationship and a second conversion relationship. The first conversion relationship is the conversion relationship from two binary data in the first bit group to any symbol partition, where any symbol partition includes eight hexadecimal symbol pairs. The second conversion relationship is the conversion relationship from two ternary symbols to one of the eight hexadecimal symbol pairs.

[0023] In one possible implementation, in any pair of hexadecimal symbols included in a symbol partition, the signal level of the hexadecimal symbol in the first bit field belongs to {+5, +3, +1}, and the signal level of the hexadecimal symbol in the second bit field belongs to {+5, +3, +1}; or, in any pair of hexadecimal symbols included in a symbol partition, the signal level of the hexadecimal symbol in the first bit field belongs to {-5, -3, -1}, and the signal level of the hexadecimal symbol in the second bit field belongs to {-5, -3, -1}; or, in any pair of hexadecimal symbols included in a symbol partition, the signal level of the hexadecimal symbol in the first bit field belongs to {+5, +3, +1}, and the signal level of the hexadecimal symbol in the second bit field belongs to {-5, -3, -1}; or, in any pair of hexadecimal symbols included in a symbol partition, the signal level of the hexadecimal symbol in the first bit field belongs to {-5, -3, -1}, and the signal level of the hexadecimal symbol in the second bit field belongs to {+5, +3, +1}.

[0024] In one possible implementation, when both binary data in the first bit group are 11, in any symbol partition obtained by converting 11 based on the first conversion relationship, the signal level of the hexadecimal symbol in the first bit field belongs to {+5, +3, +1}, and the signal level of the hexadecimal symbol in the second bit field belongs to {+5, +3, +1}; or, when both binary data in the first bit group are 00, in any symbol partition obtained by converting 00 based on the first conversion relationship, the signal level of the hexadecimal symbol in the first bit field belongs to {-5, -3, -1}, and the signal level of the hexadecimal symbol in the second bit field belongs to {-5, -3, -1}. , -1}; or, when the two binary data in the first bit group are 10, in any symbol partition including the hexadecimal symbol pair obtained by converting 10 based on the first conversion relationship, the signal level of the hexadecimal symbol located in the first bit field belongs to {+5, +3, +1}, and the signal level of the hexadecimal symbol located in the second bit field belongs to {-5, -3, -1}; or, when the two binary data in the first bit group are 01, in any symbol partition including the hexadecimal symbol pair obtained by converting 01 based on the first conversion relationship, the signal level of the hexadecimal symbol located in the first bit field belongs to {-5, -3, -1}, and the signal level of the hexadecimal symbol located in the second bit field belongs to {+5, +3, +1}.

[0025] In one possible implementation, in any pair of hexadecimal symbols included in a symbol partition, the signal level of the hexadecimal symbol in the first bit field belongs to {5, 4, 3}, and the signal level of the hexadecimal symbol in the second bit field belongs to {5, 4, 3}; or, in any pair of hexadecimal symbols included in a symbol partition, the signal level of the hexadecimal symbol in the first bit field belongs to {2, 1, 0}, and the signal level of the hexadecimal symbol in the second bit field belongs to {2, 1, 0}; or, in any pair of hexadecimal symbols included in a symbol partition, the signal level of the hexadecimal symbol in the first bit field belongs to {5, 4, 3}, and the signal level of the hexadecimal symbol in the second bit field belongs to {2, 1, 0}; or, in any pair of hexadecimal symbols included in a symbol partition, the signal level of the hexadecimal symbol in the first bit field belongs to {2, 1, 0}, and the signal level of the hexadecimal symbol in the second bit field belongs to {5, 4, 3}.

[0026] In one possible implementation, when both binary data in the first bit group are 11, in any symbol partition obtained by converting 11 based on the first conversion relation, the signal level of the hexadecimal symbol in the first bit field belongs to {5, 4, 3}, and the signal level of the hexadecimal symbol in the second bit field belongs to {5, 4, 3}; or, when both binary data in the first bit group are 00, in any symbol partition obtained by converting 00 based on the first conversion relation, the signal level of the hexadecimal symbol in the first bit field belongs to {2, 1, 0}, and the signal level of the hexadecimal symbol in the second bit field belongs to {2, 1, 0}. 1, 0}; or, if the two binary data in the first bit group are 10, in any symbol partition obtained by converting 10 based on the first conversion relationship, the signal level of the hexadecimal symbol in the first bit field belongs to {5, 4, 3}, and the signal level of the hexadecimal symbol in the second bit field belongs to {2, 1, 0}; or, if the two binary data in the first bit group are 01, in any symbol partition obtained by converting 01 based on the first conversion relationship, the signal level of the hexadecimal symbol in the first bit field belongs to {2, 1, 0}, and the signal level of the hexadecimal symbol in the second bit field belongs to {5, 4, 3}.

[0027] Fourthly, an encoding apparatus is provided for performing the data encoding method in the first aspect or any possible implementation thereof.

[0028] In one possible implementation, the encoding device includes an encoding circuit for acquiring a bit sequence comprising two bit groups, wherein the first bit group comprises two binary data and the second bit group comprises three binary data; the encoding circuit is further configured to encode the bit sequence according to an encoding conversion relationship to obtain a symbol sequence comprising two hexadecimal symbols, wherein the encoding conversion relationship is a conversion relationship from the two binary data and two ternary symbols in the first bit group to two hexadecimal symbols, and the two ternary symbols are obtained by encoding the three binary data in the second bit group.

[0029] In one possible implementation, the encoding device further includes an interface circuit for acquiring the data segment to be encoded and an encoding circuit for performing FEC encoding on the data segment and obtaining a bit sequence based on the encoding result.

[0030] In another possible implementation, the encoding device includes an acquisition module and an encoding module. The acquisition module is used to acquire a bit sequence, which includes two bit groups. The first bit group includes two binary data, and the second bit group includes three binary data. The encoding module is used to encode the bit sequence according to an encoding conversion relationship to obtain a symbol sequence. The symbol sequence includes two hexadecimal symbols. The encoding conversion relationship is a conversion relationship from the two binary data and two ternary symbols in the first bit group to two hexadecimal symbols. The two ternary symbols are obtained by encoding the three binary data in the second bit group.

[0031] In one possible implementation, an acquisition module is used to acquire the data segment to be encoded; the data segment is FEC encoded, and a bit sequence is obtained based on the encoding result.

[0032] Regardless of whether the encoding device includes an encoding circuit or an acquisition module and an encoding module, in one possible implementation, the two ternary symbols are obtained based on a mapping relationship indicating the mapping relationship between the three binary data in the second bit group and the two ternary symbols.

[0033] In one possible implementation, the encoding conversion relationship includes a first conversion relationship and a second conversion relationship. The first conversion relationship is the conversion relationship from two binary data in the first bit group to any symbol partition, where any symbol partition includes eight hexadecimal symbol pairs. The second conversion relationship is the conversion relationship from two ternary symbols to one of the eight hexadecimal symbol pairs.

[0034] In one possible implementation, in any pair of hexadecimal symbols included in a symbol partition, the signal level of the hexadecimal symbol in the first bit field is a first level, and the signal level of the hexadecimal symbol in the second bit field is a second level, and both the first and second levels include three signal levels; or, in any pair of hexadecimal symbols included in a symbol partition, the signal level of the hexadecimal symbol in the first bit field is a third level, and the signal level of the hexadecimal symbol in the second bit field is a fourth level, and the three signal levels included in the third level are different from the three signal levels included in the first level, and the three signal levels included in the fourth level are different from the three signal levels included in the second level; or, in any pair of hexadecimal symbols included in a symbol partition, the signal level of the hexadecimal symbol in the first bit field is a first level, and the signal level of the hexadecimal symbol in the second bit field is a fourth level; or, in any pair of hexadecimal symbols included in a symbol partition, the signal level of the hexadecimal symbol in the first bit field is a third level, and the signal level of the hexadecimal symbol in the second bit field is a second level.

[0035] In one possible implementation, at least one of the first level, second level, third level, or fourth level comprises three signal levels that are equally spaced.

[0036] In one possible implementation, the three signal levels included in the first level are the same as the three signal levels included in the second level, and the three signal levels included in the third level and the three signal levels included in the fourth level are the same.

[0037] In one possible implementation, at least one of the first level, second level, third level, or fourth level comprises three consecutive signal levels.

[0038] In one possible implementation, at least one of the first level, second level, third level, or fourth level comprises three discontinuous signal levels.

[0039] Fifthly, a decoding apparatus is provided for performing the data decoding method in the second aspect or any possible implementation thereof.

[0040] In one possible implementation, the decoding device includes a decoding circuit for acquiring a symbol sequence, the symbol sequence including two hexadecimal symbols; the decoding circuit is also used to decode the two hexadecimal symbols into a bit sequence according to a decoding conversion relationship, the bit sequence including two bit groups, the first bit group including two binary data, and the second bit group including three binary data; wherein the decoding conversion relationship is a conversion relationship from two hexadecimal symbols to two ternary symbols and the two binary data in the first bit group, and the two ternary symbols are obtained by encoding the three binary data in the second bit group.

[0041] In one possible implementation, the decoding device further includes an interface circuit, through which the decoding circuit acquires the symbol sequence.

[0042] In another possible implementation, the decoding device includes an acquisition module and a decoding module. The acquisition module is used to acquire a symbol sequence, which includes two hexadecimal symbols. The decoding module is used to decode the two hexadecimal symbols into a bit sequence according to a decoding conversion relationship. The bit sequence includes two bit groups, the first bit group of which includes two binary data, and the second bit group of which includes three binary data. The decoding conversion relationship is a conversion relationship from two hexadecimal symbols to two ternary symbols and the two binary data in the first bit group. The two ternary symbols are obtained by encoding the three binary data in the second bit group.

[0043] Regardless of whether the decoding device includes a decoding circuit or an acquisition module and a decoding module, in one possible implementation, two hexadecimal symbols are located in any symbol partition, and the decoding conversion relationship includes a third conversion relationship and a fourth conversion relationship. The third conversion relationship is the conversion relationship from any symbol partition to two binary data in the first bit group, and the fourth conversion relationship is the conversion relationship from two hexadecimal symbols to two ternary symbols.

[0044] In one possible implementation, the signal level of the hexadecimal symbol located in the first bit field of the two hexadecimal symbols belongs to the first level, and the signal level of the hexadecimal symbol located in the second bit field belongs to the second level. Any symbol partition where the two hexadecimal symbols are located is the symbol partition corresponding to the first level and the second level, and both the first and second levels comprise three signal levels. Alternatively, the signal level of the hexadecimal symbol located in the first bit field of the two hexadecimal symbols belongs to the third level, and the signal level of the hexadecimal symbol located in the second bit field belongs to the fourth level. Any symbol partition where the two hexadecimal symbols are located is the symbol partition corresponding to the third and fourth levels, and the third level comprises the three signal levels and the first level. The three signal levels included in the first level are all different, and the three signal levels included in the second level are all different; or, the signal level of the hexadecimal symbol located in the first bit field of the two hexadecimal symbols belongs to the first level, and the signal level of the hexadecimal symbol located in the second bit field belongs to the fourth level, and any symbol partition in which the two hexadecimal symbols are located is the symbol partition corresponding to the first level and the fourth level; or, the signal level of the hexadecimal symbol located in the first bit field of the two hexadecimal symbols belongs to the third level, and the signal level of the hexadecimal symbol located in the second bit field belongs to the second level, and any symbol partition in which the two hexadecimal symbols are located is the symbol partition corresponding to the third level and the second level.

[0045] In a sixth aspect, a data processing apparatus is provided, the apparatus including a processor for loading and executing at least one instruction to cause the data processing apparatus to perform the method of the first aspect or any possible implementation thereof, or to perform the method of the second aspect or any possible implementation thereof.

[0046] In one possible implementation, the device includes a memory coupled to a processor, the memory storing at least one instruction.

[0047] In a seventh aspect, a computer-readable storage medium is provided, wherein at least one instruction is stored in the computer-readable storage medium, the instruction being loaded and executed by a processor to implement the data encoding method in the first aspect or any possible implementation of the first aspect, or to implement the data decoding method in the second aspect or any possible implementation of the second aspect.

[0048] Eighthly, a computer program (product) is provided, comprising computer program / instructions, which are executed by a processor to enable a computer to implement the data encoding method of the first aspect or any possible implementation thereof, or to implement the data decoding method of the second aspect or any possible implementation thereof.

[0049] A ninth aspect provides a communication device comprising: a transceiver, a memory, and a processor. The transceiver, the memory, and the processor communicate with each other via an internal connection path. The memory stores instructions, and the processor executes the instructions stored in the memory to control the transceiver to receive and transmit signals. When the processor executes the instructions stored in the memory, it causes the processor to perform a method of the first aspect or any possible implementation thereof, or to perform a method of the second aspect or any possible implementation thereof. Optionally, the communication device may be a chip.

[0050] Optionally, there may be one or more processors and one or more memories.

[0051] Alternatively, the memory can be integrated with the processor, or the memory can be set up separately from the processor.

[0052] In the specific implementation process, the memory can be a non-transitory memory, such as read-only memory (ROM), which can be integrated with the processor on the same chip or set on different chips. This application does not limit the type of memory or the way the memory and processor are set.

[0053] In a tenth aspect, a chip is provided, including a processor for retrieving and executing program instructions or code stored in a memory, causing a communication device equipped with the chip to perform the methods described in the foregoing aspects.

[0054] Eleventhly, another chip is provided, comprising: an input interface, an output interface, a processor, and a memory, wherein the input interface, the output interface, the processor, and the memory are connected by an internal connection path, the processor being used to execute code in the memory, and when the code is executed, the processor being used to perform the methods in the above aspects.

[0055] In a twelfth aspect, a data processing system is provided, the system including an encoding device and a decoding device, the encoding device being used to perform the method of the first aspect or any possible implementation thereof, and the decoding device being used to perform the method of the second aspect or any possible implementation thereof.

[0056] It should be understood that the apparatus mentioned in the fourth, fifth, or ninth aspects above can be the chip mentioned in the tenth or eleventh aspects, or the data processing device of the sixth aspect. The beneficial effects achieved by the technical solutions and corresponding possible implementations of the third to twelfth aspects of this application can be found in the above descriptions of the technical effects of the first aspect and its corresponding possible implementations or the second aspect and its corresponding possible implementations, and will not be repeated here. Attached Figure Description

[0057] Figure 1 This application provides a schematic diagram of the structure of an OSI model layer.

[0058] Figure 2 A schematic diagram of an implementation environment provided for an embodiment of this application;

[0059] Figure 3 A schematic diagram of a data center structure provided in an embodiment of this application;

[0060] Figure 4 This is a schematic diagram of the structure of a computing storage network provided in an embodiment of this application;

[0061] Figure 5 A flowchart illustrating a data encoding and decoding method provided in this application embodiment;

[0062] Figure 6 This application provides a schematic diagram of a data transmission process.

[0063] Figure 7 A schematic diagram of a 3B2T mapping relationship provided for an embodiment of this application;

[0064] Figure 8 A schematic diagram of a symbol partition provided for an embodiment of this application;

[0065] Figure 9 A schematic diagram illustrating the distribution of hexadecimal symbol pairs provided in an embodiment of this application;

[0066] Figure 10 A schematic diagram of the 3B2T mapping relationship provided for embodiments of this application;

[0067] Figure 11 A schematic diagram illustrating the distribution of another hexadecimal symbol pair provided in an embodiment of this application;

[0068] Figure 12 A schematic diagram illustrating the distribution of another hexadecimal symbol pair provided in an embodiment of this application;

[0069] Figure 13 A schematic diagram of another symbol partitioning provided for an embodiment of this application;

[0070] Figure 14 A schematic diagram illustrating the distribution of another hexadecimal symbol pair provided in an embodiment of this application;

[0071] Figure 15 A schematic diagram illustrating the distribution of another hexadecimal symbol pair provided in an embodiment of this application;

[0072] Figure 16 A schematic diagram illustrating another 3B2T mapping relationship provided for an embodiment of this application;

[0073] Figure 17 This is a schematic diagram of the structure of an encoding device provided in an embodiment of this application;

[0074] Figure 18 This is a schematic diagram of the structure of a decoding device provided in an embodiment of this application;

[0075] Figure 19 This application provides a schematic diagram of the structure of a network device according to an embodiment of the present application.

[0076] Figure 20 This is a schematic diagram of another network device provided in an embodiment of this application. Detailed Implementation

[0077] The terminology used in the embodiments section of this application is only for explaining specific embodiments of this application and is not intended to limit this application. To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be further described in detail below with reference to the accompanying drawings.

[0078] In the field of communication technology, Ethernet is a computer local area network (LAN) technology. The IEEE 802.3 standard, organized by the Institute of Electrical and Electronics Engineers (IEEE), defines the technical standard for Ethernet, specifying aspects including physical layer cabling, electronic signals, and media access control. Currently, high-speed Ethernet interfaces, represented by 100 Gigabit Ethernet (GE / GbE) and higher speeds, are widely used in carrier networks, data centers, and high-performance computing interconnects.

[0079] In some cases, Ethernet references the layered architecture of the Open Systems Interconnection (OSI) model. OSI is an Open Systems Interconnection reference model, also known as the OSI reference model. OSI defines a seven-layer model for interconnection; see [link to relevant documentation]. Figure 1In related technologies, the OSI seven-layer model consists of the Application layer, Presentation layer, Session layer, Transport layer, Network layer, Data Link layer, and Physical layer. The Physical layer provides physical links and transmission media for data transmission, supporting data transmission over these media, such as cables.

[0080] In the design of Ethernet, based on the Ethernet interface type or application scenario, the functionality of some model layers of the OSI model can be simplified, enhanced, or selectively implemented. This can be understood as some sub-layer functions in the OSI model being optional. Taking the data center application scenario as an example, some model layer functions are selectively implemented. For example, the forward error correction (FEC) function in the physical layer is enabled to cope with the high bit error rate in data centers.

[0081] With the development of Ethernet technology, the transmission rate in Ethernet has been continuously improving. Taking interface speed as an example, under the IEEE 802.3 200GbE / 400GbE standard, the single-channel electrical interface speed reaches 50 gigabits per second (Gbps or G or Gb / s). Under the next-generation Ethernet 800GbE / 1.6 terabit Ethernet (TE) standard, the single-channel electrical interface speed reaches 100G or 224Gbps. A single-channel electrical interface can be called an Ethernet interface. In some cases, the Ethernet interface speed is expected to increase from 224Gbps to 484Gbps. For example, the interface speed of Ethernet interfaces under standards such as the Optical Internetworking Forum (OIF) and IEEE 802.3 can reach 484Gbps.

[0082] As Ethernet interface speeds increase, the encoding methods also change. Ethernet interfaces of 25Gbps and below typically use non-return-to-zero (NRZ) modulation, which uses high and low signal levels to represent the 1s and 0s of the transmitted digital logic signal, with each symbol period representing 1 bit of digital logic information. PAM modulation, on the other hand, can use more signal levels, allowing more bits of digital logic information to be transmitted per symbol period. This enables PAM modulation on high-speed Ethernet interfaces, such as 224Gbps or 484Gbps.

[0083] At 224Gbps speeds, there has been industry discussion on choosing between four-level pulse amplitude modulation (PAM4) or six-level pulse amplitude modulation (PAM6) modulation methods. PAM4 modulation encodes binary data into quaternary symbols, while PAM6 modulation encodes binary data into hexadecimal symbols. The binary data indicates the digital logic information to be transmitted. In some cases, "hexadecimal" can be expressed as Senary, Base-6, Heximal, or Seximal; in the following description of this application, Senary will be used consistently. Furthermore, a hexadecimal symbol has six possible values, corresponding to six signal levels, to characterize a specific level state of a PAM6 symbol. These six values ​​are, for example, 0 / 1 / 2 / 3 / 4 / 5 or -5 / -3 / -1 / +1 / +3 / +5.

[0084] As the technology evolves towards 448Gbps single-channel speeds, the increased signal attenuation and crosstalk will pose greater technical challenges. PAM6, by introducing higher-order modulation techniques, can achieve the required transmission bandwidth with a lower bandwidth compared to PAM4 modulation (see Table 1).

[0085] Table 1

[0086]

[0087] In Table 1, at a rate of 112Gbps, the selectable modulation scheme is PAM4, and at a rate of 224Gbps, the selectable modulation schemes include PAM4, PAM5, PAM6, PAM7, PAM8, and PAM16. The signaling rate in Table 1 indicates the transmission bandwidth. Referring to Table 1, PAM6 modulation requires less transmission bandwidth than PAM4 modulation. Therefore, PAM6 modulation can be selected to encode binary data into hexadecimal symbols.

[0088] According to communication principles, in PAM6 modulation, one hexadecimal symbol can represent approximately 2.58 bits of binary data (log(6) / log(2) ≈ 2.58 bits). If only one hexadecimal symbol is used to encode one or two binary data, it would waste the symbol state and the transmission bandwidth of the hexadecimal symbol, failing to fully utilize the advantages of multi-level transmission under PAM6 modulation. Therefore, multiple consecutive hexadecimal symbols can be combined to represent multiple binary data to be transmitted. When the number of Senary state combinations in the PAM6 sequence is greater than or equal to the number of Bit state combinations in the binary sequence to be transmitted, the advantages of PAM6 encoding can be maximized. The mapping between the two sequences can be understood as PAM6 encoding and decoding. Multiple binary data can be referred to as binary patterns, multi-bit binary data, binary designs, or data sequences in some cases. This representation method can be represented as #B#S encoding. B indicates binary data, S indicates hexadecimal symbol, and # indicates quantity. #B#S encoding can be understood as encoding # binary data to obtain # hexadecimal symbols. Table 2 below shows various #B#S encodings.

[0089] Table 2

[0090]

[0091]

[0092] In Table 2, Binary Bit indicates the number of binary data before encoding, Binary Pattern indicates the number of data combinations formed by multiple binary data, Senary Symbol indicates the number of hexadecimal symbols after encoding, Senary Pattern indicates the number of symbol combinations formed by multiple hexadecimal symbols, Capacity indicates the maximum amount of information carried by the hexadecimal symbols after encoding, and Efficiency indicates encoding efficiency, which can be understood as equivalent bandwidth.

[0093] Taking 5B2S encoding as an example, the Binary Bit is 5, indicating that there are 5 binary data before encoding; the Senary Symbol is 2, indicating that there are 2 hexadecimal symbols obtained by encoding the 5 binary data; and the Binary Pattern is 32, indicating that the number of data combinations formed by the 5 binary data is 2^32, given that each binary data has two possible values. 5=32, Senary Pattern is 36, indicating that when each hexadecimal symbol has six possible values, the number of symbol combinations formed by two hexadecimal symbols is 6 × 6 = 36. For other #B#S encodings, please refer to Table 2, which will not be repeated here. Based on the Binary Pattern and Senary Pattern columns in Table 2, it is clear that when using #B#S encoding, the number of symbol combinations formed by hexadecimal symbols must be greater than or equal to the number of data combinations formed by binary data.

[0094] Furthermore, the different encoding and decoding schemes in Table 2 above only provide the possibility of "different combinations of binary bit counts and hexadecimal senary counts". The specific mapping relationship still needs to be designed differently to meet the requirements of simple implementation of encoding and decoding circuits, low latency, allow the largest possible run length, the lowest possible power spectral density (PSD), the largest possible Hamming distance, and the lowest possible bit error rate performance of the cooperating Reed-Solomon-forward error correction (RS-FEC) and transceiver.

[0095] As shown in Table 2 above, different combinations of binary bit counts (sequences) and hexadecimal sensory counts (sequences) can achieve encoding and decoding schemes with varying efficiencies. Since different #B#S encodings have different efficiencies, and there is a balance between efficiency (effective bandwidth) and Hamming distance (code pattern fault tolerance), different #B#S encodings have different code pattern fault tolerance capabilities. In Table 2, the 5B2S encoding scheme can achieve an efficiency of 96.71%, which is higher than other encoding schemes such as 7B3S. Furthermore, 5B2S encoding can generally be used with encodings based on Galois distances of 2... 10 When used in conjunction with RS-FEC error correction codes, it offers a comprehensive advantage in terms of latency, area power consumption, bit error rate performance, and other aspects.

[0096] In related technologies, 32-constellation QAM is used to implement 5B2S encoding. 32-constellation QAM is a modulation method that performs amplitude modulation on two PAM6 symbols separately. By modulating the two PAM6 symbols separately, 6B2S encoding can be constructed. 2 = 36 constellation combinations, 32 of which are constellation combinations and 5 bits of binary code = 2 5The system maps 32 data sequences together, while the remaining four constellation combinations are not involved in encoding / decoding and can be used for other information transmission. QAM-based 5B2S encoding specifically includes two methods. One method stores the mapping relationship between 5 binary data and 2 hexadecimal symbols in a table. Then, based on the 5 binary data to be encoded, a lookup is performed sequentially in each bit field. Once a match is found in the table, the corresponding 2 hexadecimal symbols are used as the encoding result. This method requires 5 table lookups, resulting in high complexity and latency. The other method converts the 5 binary data into 2 hexadecimal symbols. However, this conversion requires a long data length, involves complex circuitry, and consumes significant resources.

[0097] This application provides a data encoding method and a data decoding method for encoding and decoding using 5B2S. Figure 2 A schematic diagram of an implementation environment provided for an embodiment of this application, see below. Figure 2 The implementation environment includes an encoding device 01 and a decoding device 02, which establish a communication connection via a wired or wireless network. The encoding device 01 executes the data encoding method provided in this embodiment, encoding a bit sequence comprising 5 binary data units according to an encoding conversion relationship to obtain a symbol sequence comprising 2 hexadecimal symbols. The decoding device 02 executes the data decoding method provided in this embodiment, decoding the symbol sequence according to a decoding conversion relationship to obtain a bit sequence.

[0098] Optionally, the data encoding and decoding methods provided in this application can be used as physical layer technologies. Encoding device 01 encodes the bit sequence into a symbol sequence at the physical layer, and sends the symbol sequence to decoding device 02 using a physical medium. Decoding device 02 also decodes the symbol sequence into a bit sequence at the physical layer. In this case, the above-mentioned encoding conversion relationship can be implemented through logic circuits configured in encoding device 01, and the decoding conversion relationship can be implemented through logic circuits configured in decoding device 02. For example, the encoding conversion relationship can be implemented through forward logic circuits, and the decoding conversion relationship can be implemented through reverse logic circuits.

[0099] In one possible implementation, encoding device 01 and decoding device 02 can be configured within a data center. Figure 3 This diagram illustrates a data center comprising multiple points of delivery (PoDs), designated PoD1-PoDn. Each PoD is structured in a three-tier architecture. Figure 3In this diagram, T1 is the access layer, T2 is the aggregation layer, and T3 is the core layer. The access layer is configured with servers and access switches, the aggregation layer is configured with aggregation switches, and the core layer is configured with core switches. Figure 2 The encoding device 01 and decoding device 02 shown can be Figure 3 The diagram shows any switch within the data center, whose interconnecting interfaces are used to interactively execute data encoding and decoding methods.

[0100] For example, encoding device 01 and decoding device 02 can also be configured in a computing storage network, where components are interconnected via a high-speed serial computer expansion bus (peripheral component interconnect express, PCI Express / PCIe). Figure 4 This is a schematic diagram of a computing and storage network structure provided in an embodiment of this application. Figure 4 In this context, the computing and storage network includes a central processing unit (CPU), a root complex, memory, a switch, a legacy endpoint, a PCI Express endpoint, and a PCI Express Endpoint-PCI / PCI-X Bridge. Figure 2 The encoding device 01 and decoding device 02 shown can be Figure 4 In a system where any two components are connected via PCI Express, encoding device 01 is, for example, the Root Complex, and decoding device 02 is, for example, the Switch, the bit sequence encoded by the Root Complex can be a data transfer request initiated by the CPU through the Root Complex.

[0101] Optionally, the encoding device 01 and decoding device 02 can also be other devices with interactive requirements. The encoding device 01 and decoding device 02 can be servers, such as central servers, edge servers, or local servers in a local data center. The server can be a physical server or a cloud server providing cloud computing services. In some embodiments, the encoding device 01 and decoding device 02 can be terminal devices such as desktop computers, laptops, personal computers (PCs), or smartphones; alternatively, the encoding device 01 and decoding device 02 can be other communication devices, set-top boxes, televisions (TVs), etc. Optionally, the encoding device 01 and decoding device 02 can be independent devices or components within a device, such as transceivers, processors, memory and their controllers, chips, or interfaces. Optionally, the interface can be an Ethernet interface, a dynamic random access memory (DRAM) interface, a chiplet interface, an audio / video multimedia interface, PCIe / universal serial bus (USB), etc. The audio / video multimedia interface is, for example, a general-purpose media interface (GPMI).

[0102] This application provides a data encoding method and a data decoding method, which can be applied to the above-mentioned... Figures 2-4 In any of the implementation environments shown, taking the method executed interactively by encoding device 01 and decoding device 02 as an example, the flowchart of the method is as follows: Figure 5 As shown, it includes S501-S504, where S501 and S502 are data encoding processes, and S503 and S504 are data decoding processes.

[0103] S501, the encoding device acquires a bit sequence, which includes two bit groups. The first bit group includes two binary data, and the second bit group includes three binary data.

[0104] For example, a bit sequence includes multiple discrete bits. Since any discrete bit can be represented by binary data, and one binary data is 1 bit, a discrete bit can also be called a discrete number in some cases. The multiple discrete bits included in a bit sequence can also be called multiple binary data. Optionally, the encoding device can acquire a data segment to be encoded and determine a symbol sequence based on the data segment. The data segment is also obtained by encoding characters. For example, after acquiring the characters to be transmitted, the encoding device encodes the characters to obtain the data segment. The characters can be of any type, including but not limited to video characters, audio characters, image characters, and application software characters. The data segment can be encoded in normal transmission mode or low-latency transmission mode. The number of discrete bits included in a data segment encoded in low-latency transmission mode is less than the number of discrete bits included in a data segment encoded in normal transmission mode.

[0105] After acquiring a data segment, the encoding device can determine the bit sequence based on the data segment. For example, it can divide the data segment into multiple bit sequences, each containing 5 binary data bytes. Alternatively, the encoding device can perform FEC encoding on the data segment and obtain the bit sequence based on the encoding result. See also... Figure 6 The encoding device performs RS FEC encoding on the data segment, adds redundant bits to the data segment, and obtains the FEC encoding result. Figure 6 The dashed line markings in RS FEC encoding are used because the encoding device can selectively perform RS FEC encoding. If the encoding device performs RS FEC encoding on a data segment, the encoding process involves, for example, segmenting the data segment, determining redundant bits based on the segmentation results, and merging the data segments and redundant bits to obtain the FEC encoded result. Redundant bits may be referred to as RS FEC symbols, check information, or RS FEC check information in some cases.

[0106] Taking a 5140-bit data segment as an example, with FEC encoding as RS(544, 514), 514 indicates the number of characters before encoding, and 544 indicates the number of characters after encoding. Each character is 10 bits in size. The encoding device divides the data segment into 514 characters, constructs a polynomial based on a finite field, uses the 514 characters as coefficients of the polynomial, and calculates 30 redundant characters, totaling 300 redundant bits. These 30 redundant characters are then combined with the 514 characters to obtain the FEC encoded result containing 544 characters.

[0107] After determining the FEC encoding result, the encoding device can divide the FEC encoding result into bit sequences. Optionally, the encoding device can directly divide the FEC encoding result. For example, in the above embodiment, the FEC encoding includes 544 characters. Since one character is 10 bits, the FEC encoding result includes a total of 5440 discrete bits. The encoding device can divide it into a bit sequence of 5 bits each. Taking the FEC encoding result 0110100100111010011…11001 as an example, then 01101 is one bit sequence, and 00100 is another bit sequence. In some cases, the encoding device can also first scramble the FEC encoding result and divide the scrambled result into multiple bit sequences.

[0108] After acquiring the bit sequence, the encoding device can divide the five binary data included in the bit sequence into two bit groups. For example, starting from the low bit or high bit of the five binary data, the five binary data can be divided into two bit groups according to the bit field of each binary data in the bit sequence. The binary data included in different bit groups have different bit fields in the bit sequence.

[0109] The encoding device can divide the bit sequence according to the encoding rules. The encoding rules include the grouping rules of the encoding device and the encoding rules for each bit group. The grouping rules indicate the bit fields of the binary data included in each bit group in the bit sequence. The bit fields of the binary data included in each bit group in the bit sequence can be continuous or non-contiguous. Taking the binary data included in the bit group as a continuous bit field as an example, the encoding device divides the first two binary data into the first bit group and the last three binary data into the second bit group, starting from the high bit. The first two binary data are binary data located in B[4:3] and the last three binary data are binary data located in B[2:0]. B[] represents the bit field of the binary data, the number represents the number of bits of the binary data in the bit sequence, and ":" represents the range. For example, the bit field represented by B[2:0] is the 2nd bit, the 1st bit, and the 0th bit. Continuing with the bit sequence 01101 as an example, the binary data located in B[4:3] is 01, and the binary data located in B[2:0] is 101.

[0110] Taking a bit group where the binary data is not located in a continuous bit field as another example, the encoding device can group the 5 binary data based on equally spaced bit fields. The encoding device divides the binary data located in B[4, 2, 0] into the second bit group and the binary data located in B[3, 1] into the first bit group.

[0111] The first bit group and the second bit group in this application are intended to distinguish different bit groups, rather than to limit the order in which different groups are divided. The first bit group and the second bit group can be divided simultaneously, or they can be divided sequentially according to the division order. The division order can be as shown in the above embodiment, dividing the first bit group first and then dividing the second bit group. The division order can also be other orders, such as dividing the second bit group first and then dividing the first bit group.

[0112] S502, the encoding device encodes the bit sequence according to the encoding conversion relationship to obtain the symbol sequence, which includes two hexadecimal symbols.

[0113] In one possible implementation, since the PAM3 codec circuit is simpler and more mature than the PAM6 codec circuit, the PAM3 codec circuit can be directly implemented through combinational logic encoding and decoding circuits, resulting in low encoding latency. Figure 7 A PAM3 encoding method based on circuit conversion is shown. This PAM3 encoding is used to encode three binary data into two ternary symbols, which can be called 3-bit 2-trit (3B2T) encoding. The two ternary symbols can be called 2D-PAM3.

[0114] The process of performing 3B2T encoding based on the conversion relationship is, for example, defining the conversion relationship between two binary data and one ternary symbol, for example... Where, Bit refers to the two binary data located in B[1:0] of the three binary data, and Trit refers to the ternary symbol located in T[1] of the two ternary symbols. The conversion relationship is indicated. Based on the conversion relationship between the two binary data and one ternary symbol, the conversion relationship between the three binary data B[2:0] and the two ternary symbols T[1:0] is as follows: Where Trit refers to the ternary symbol obtained by converting B[1:0], and Tr refers to the ternary symbol obtained by converting B[2]=0 or B[2]=1. The ternary symbol obtained by converting B[2]=0 is different from the ternary symbol obtained by converting B[2]=1, and can be any two of +1, -1 and 0. Figure 7 middle,

[0115] Taking three binary data as 000 as an example, B[2] = 0, B[1:0] = 00, based on and The conversion relationship yields two ternary symbols -1-1. Taking the three binary data 111 as an example, B[2] = 1, B[1:0] = 11, based on... The conversion relationship yields two ternary symbols, both of which are +10.

[0116] Since a hexadecimal symbol can be understood as the superposition of two ternary symbols, and two hexadecimal symbols can be constructed from four ternary symbols, 5B2S encoding and decoding can be implemented using PAM3 encoding and decoding. That is, the encoding device uses PAM3 encoding during the process of obtaining the symbol sequence from the encoded bit sequence to obtain ternary symbols. Based on the relationship between ternary and hexadecimal symbols, the symbol sequence is determined. In some cases, two hexadecimal symbols are called 2D-PAM6, and four ternary symbols can be called 4D-PAM3.

[0117] For example, the encoding device can perform 3B2T encoding on the second bit group to obtain two ternary symbols, and then convert the three binary data and two ternary symbols in the second bit group into two hexadecimal symbols based on the encoding conversion relationship, resulting in a symbol sequence including two hexadecimal symbols. The encoding conversion relationship includes a first conversion relationship and a second conversion relationship. The first conversion relationship is the conversion relationship from the two binary data in the first bit group to any symbol partition, and the second conversion relationship is the conversion relationship from the two ternary symbols to one of eight hexadecimal symbol pairs.

[0118] Since 3B2T encoding of three different binary data results in different ternary symbol pairs, and the three binary data can form eight possible combinations, 3B2T encoding may yield eight ternary symbol pairs. Similarly, 5B2S encoding of different bit sequences also yields different hexadecimal symbol pairs. Five binary data can combine to form a 32-bit sequence, and 5B2S encoding may yield 32 hexadecimal symbol pairs. Therefore, the encoding device can partition these 32 hexadecimal symbol pairs into four symbol partitions, each containing eight hexadecimal symbol pairs. This allows for the conversion between hexadecimal and ternary symbol pairs within a symbol partition; different ternary symbol pairs will be converted into different hexadecimal symbols within the same symbol partition.

[0119] This application does not limit the 32 hexadecimal symbol pairs to be partitioned. Since one hexadecimal symbol has six signal levels, two hexadecimal symbols can form 36 hexadecimal symbol pairs. The encoding device can randomly select 32 hexadecimal symbol pairs from the 36 hexadecimal symbol pairs as the symbol pairs for 5B2S encoding. Alternatively, the encoding device can select the four hexadecimal symbol pairs with the largest disparity change (DC) from the 36 hexadecimal symbol pairs and exclude them from 5B2S encoding, using the remaining 32 hexadecimal symbol pairs as the hexadecimal symbol pairs to be partitioned. DC is used to indicate the level distribution of the hexadecimal symbol pairs, reflecting the uniformity of the level distribution. In some cases, the 32 hexadecimal symbol pairs can be referred to as a 32-constellation.

[0120] Optionally, the encoding device can also divide the symbol partitions where each hexadecimal symbol is located based on the signal level of each hexadecimal symbol. This application does not limit the six signal levels present in the hexadecimal symbols; they can be any equally spaced signal levels. For example, the six signal levels could be 0, 1, 2, 3, 4, and 5, or +5, +3, +1, -1, -3, and -5. Since the encoding process for different signal levels is similar, the following example uses six signal levels of 0, 1, 2, 3, 4, and 5 to illustrate the process of obtaining a symbol sequence from an encoded bit sequence.

[0121] For cases where two hexadecimal symbols are divided into a hexadecimal symbol located in the first bit field and a hexadecimal symbol located in the second bit field, the encoding device will divide the multiple signal levels of the hexadecimal symbol in each bit field into two levels, each level including three signal levels, and then determine four symbol partitions based on the two levels. Among them, the first bit field and the second bit field are intended to distinguish different hexadecimal symbols, rather than to limit them. The first bit field can be the high bit S[1] in the hexadecimal symbol pair, and the second bit field can be the low bit S[0] in the hexadecimal symbol pair. Alternatively, the first bit field can be the low bit S[0] in the hexadecimal symbol pair, and the second bit field can be the high bit S[1] in the hexadecimal symbol pair. Among them, S[] represents the bit field of the hexadecimal symbol, and the number represents the number of bits of the hexadecimal symbol. For example, the bit field represented by S[1] is the first bit.

[0122] For a hexadecimal symbol in the first field, the encoding device can divide the six signal levels of the hexadecimal symbol into a first level and a third level. The three signal levels included in the first level are different from the three signal levels included in the third level. The encoding device can randomly select three signal levels from the six signal levels as one level and use the remaining three signal levels as another level. Taking the six signal levels as 5, 4, 3, 2, 1, and 0 as an example, the encoding device randomly selects 5, 3, and 2 as the first level and uses the remaining three signal levels 4, 1, and 0 as the third level.

[0123] Optionally, the encoding device can also select three equally spaced signal levels from the six signal levels as one level, and the remaining three signal levels as another level. The encoding device selects 5, 3, and 1 as the third level, and the remaining 4, 2, and 0 as the first level. This can be understood as at least one of the first or third levels comprising three equally spaced signal levels. This equally spaced classification ensures that the three signal levels included in the first and third levels maintain a similar equal spacing as the PAM3 signal levels. In this case, the error probability of any signal level being misinterpreted as an adjacent level is the same, allowing for the same error probability calculation on the decoding side, resulting in low circuit complexity.

[0124] Furthermore, the encoding device can select consecutive signal levels as one level to reduce the amount of erroneous binary data when an error occurs on the decoding side of a hexadecimal symbol within the same symbol partition. For example, the encoding device selects three consecutive signal levels from six signal levels as one level and the remaining three signal levels as another level. This can be understood as at least one of the first or third levels comprising three consecutive signal levels. The process of selecting consecutive levels is, for example, selecting 4, 3, and 2 as the first level and the remaining 5, 1, and 0 as the second level, or selecting 5, 4, and 3 as the first level and 2, 1, and 0 as the third level.

[0125] For hexadecimal symbols in the second bit field, the encoding device can use a similar classification method to divide the six signal levels of the hexadecimal symbol into a second level and a fourth level. The encoding device can randomly select three signal levels from the second and fourth levels, or it can select three equally spaced signal levels, or it can select three consecutive signal levels.

[0126] Furthermore, the encoding device can use different classification methods to divide the six signal levels corresponding to the first bit field and the six signal levels corresponding to the second bit field, or it can use the same classification method to divide the six signal levels corresponding to the first bit field and the six signal levels corresponding to the second bit field. In this case, the three signal levels included in the first level are the same as the three signal levels included in the second level, and the three signal levels included in the third level and the three signal levels included in the fourth level are the same. Alternatively, the three signal levels included in the first level and the three signal levels included in the fourth level are the same, and the three signal levels included in the third level and the three signal levels included in the second level are the same.

[0127] Regardless of how the encoding device divides the first, second, third, and fourth levels, the first and third levels can be combined with the second and fourth levels in pairs to obtain four symbol partitions. In order to distinguish the four symbol partitions, the four symbol partitions will be referred to as symbol partition 1, symbol partition 2, symbol partition 3, and symbol partition 4 respectively.

[0128] In the hexadecimal symbol pairs included in symbol partition 1, the signal level of the hexadecimal symbol located in the first bit field is at the first level, and the signal level of the hexadecimal symbol located in the second bit field is at the second level; in the hexadecimal symbol pairs included in symbol partition 2, the signal level of the hexadecimal symbol located in the first bit field is at the third level, and the signal level of the hexadecimal symbol located in the second bit field is at the fourth level; in the hexadecimal symbol pairs included in symbol partition 3, the signal level of the hexadecimal symbol located in the first bit field is at the first level, and the signal level of the hexadecimal symbol located in the second bit field is at the fourth level; in the hexadecimal symbol pairs included in symbol partition 4, the signal level of the hexadecimal symbol located in the first bit field is at the third level, and the signal level of the hexadecimal symbol located in the second bit field is at the second level.

[0129] Figure 8 Multiple symbol partitions are shown. Figure 8 In the diagram, S[1] corresponds to the first bit field, S[0] corresponds to the second bit field, the first and second levels are both {5, 4, 3}, and the third and fourth levels are both {2, 1, 0}. The symbol partition 1 composed of the S[1] bit field {5, 4, 3} and the S[0] bit field {5, 4, 3} is shown in the square marking, the symbol partition 2 composed of the S[1] bit field {2, 1, 0} and the S[0] bit field {2, 1, 0} is shown in the black diagonal marking, the symbol partition 3 composed of the S[1] bit field {5, 4, 3} and the S[0] bit field {2, 1, 0} is shown in the black marking, and the symbol partition 4 composed of the S[1] bit field {2, 1, 0} and the S[0] bit field {5, 4, 3} is shown in the white diagonal marking.

[0130] The encoding device can divide 32 hexadecimal symbol pairs into 4 symbol partitions based on the signal levels of the hexadecimal symbols in the first bit field and the second bit field. For example, if a hexadecimal symbol pair is 55, the hexadecimal symbol in the first bit field is 5, belonging to the first level, and the hexadecimal symbol in the second bit field is also 5, belonging to the second level. The encoding device thus determines that the hexadecimal symbol pair belongs to symbol partition 1, which corresponds to the first and second levels.

[0131] Figure 9 This is a schematic diagram showing the distribution of hexadecimal symbol pairs provided in an embodiment of this application. Figure 9One of the coordinate points indicates a pair of hexadecimal symbols. The vertical coordinate of the coordinate point indicates the signal level of the hexadecimal symbol of the first field S[1], and the horizontal coordinate indicates the signal level of the hexadecimal symbol of the second field S[0]. Figure 9 The code uses eight hexadecimal symbol pairs in partition 1, represented by white circular symbols: {55, 54, 53, 45, 43, 35, 34, 33}. Figure 9 It can be seen that the signal level of the hexadecimal symbol located in the first field S[1] of symbol partition 1 is any one of {5, 4, 3}, and the signal level of the hexadecimal symbol located in the second field S[0] is any one of {5, 4, 3}. Figure 9 The system uses 8 pairs of hexadecimal symbols from white square symbol partition 2, 8 pairs of hexadecimal symbols from black circular symbol partition 3, and 8 pairs of hexadecimal symbols from black square symbol partition 4.

[0132] For example, in the case where a symbol partition includes 8 hexadecimal symbol pairs and 8 ternary symbol pairs are obtained by 3B2T encoding, any one of the 8 hexadecimal symbol pairs has a second conversion relationship with a ternary symbol pair. That is, a ternary symbol pair can be converted into any one of the 8 hexadecimal symbol pairs based on the second conversion relationship. The 8 ternary symbol pairs used to convert to obtain the 8 hexadecimal symbol pairs in a symbol partition are referred to as the 8 ternary symbol pairs corresponding to the symbol partition.

[0133] The eight ternary symbol pairs corresponding to the four symbol partitions can be different, and the difference can be partial. For example, the eight ternary symbol pairs corresponding to symbol partition 1 and symbol partition 3 are: Figure 10 The values ​​shown in (3) are +1-1, +10, +1+1, 0-1, 0+1, -1-1, -10, and -1+1. The eight ternary symbol pairs corresponding to symbol partitions 2 and 4 are... Figure 10 (1) shows +1-1, +10, +1+1, 0-1, 00, 0+1, -10, and -1+1. The eight ternary symbol pairs corresponding to the four symbol partitions can also be completely different. For example, the eight ternary symbol pairs corresponding to symbol partition 1 are as follows: Figure 10 As shown in (1), the 8 ternary symbol pairs corresponding to symbol partition 2 are as follows: Figure 10 As shown in (2), the 8 ternary symbol pairs corresponding to symbol partition 3 are as follows: Figure 10 As shown in (3), the eight ternary symbol pairs corresponding to symbol partition 4 are as follows: Figure 10As shown in (4). Optionally, the eight ternary symbol pairs corresponding to the four symbol partitions can also be the same, for example, the eight ternary symbol pairs corresponding to each symbol partition are all +1-1, +10, +1+1, -10, +10, -1-1, -10 and -1+1.

[0134] Regardless of the specific configuration of the eight ternary symbol pairs corresponding to each symbol partition, a second transformation relationship exists between the eight hexadecimal symbol pairs included in any symbol partition and the ternary symbol pairs. This second transformation relationship can be randomly established, or it can be established based on the positions of the ternary and hexadecimal symbol pairs in the constellation diagram. Continuing with... Figure 9 and Figure 10 For example, (3), Figure 9 The hexadecimal symbol for 50 is located at the top left corner of symbol section 3 in the constellation diagram, while... Figure 10 The ternary symbol pair +1-1 in (3) is also located at the top left corner of the constellation diagram. Therefore, there is a second conversion relationship between 50 and +1-1. Table 3 shows the conversion relationship based on... Figure 9 and Figure 10 (3) The second conversion relationship between each hexadecimal symbol pair and ternary symbol pair constructed.

[0135] Table 3

[0136]

[0137]

[0138] In some cases, during the process of constructing the second transformation relationship based on location, the second transformation relationship can also be constructed by mirroring different symbol partitions. Figure 11 This is a schematic diagram illustrating the distribution of another hexadecimal symbol pair provided in an embodiment of this application. Figure 11 The four symbol partitions in the code correspond to the same eight ternary symbol pairs, all of which are... Figure 10 The ternary symbol pair shown in (3) is a ternary symbol pair. For the same ternary symbol pair, the ternary symbol pair can be converted into four hexadecimal symbol pairs, and the four hexadecimal symbol pairs are mirrored in the positions of the four symbol partitions.

[0139] Taking the ternary symbol pair +1 and -1 as an example, this ternary symbol pair is respectively with... Figure 11 The second conversion relationship exists between 50 located in the upper left corner of symbol partition 4, 55 located in the upper right corner of symbol partition 1, 00 located in the lower left corner of symbol partition 2, and 05 located in the lower right corner of symbol partition 3.

[0140] based on Figure 11From the last three of the five binary data, we can see that if the Hamming distance between the three binary data corresponding to every two adjacent ternary symbol pairs is 1, the maximum Hamming distance between the five binary data corresponding to every two adjacent hexadecimal symbol pairs can be 1 through mirror distribution, so as to control the number of error bits in the encoding and decoding process.

[0141] Based on the above examples, if the eight ternary symbol pairs corresponding to the four symbol partitions are the same, then one ternary symbol pair can be converted into four hexadecimal symbol pairs based on the second conversion relation, and the four hexadecimal symbol pairs are located in different symbol partitions. Continuing with... Figure 9 For example, Figure 9 The eight ternary symbol pairs corresponding to the four symbol partitions are the same, all of which are Figure 10 Given the eight ternary symbol pairs shown in (3), for the ternary symbol pair +1-1, the four hexadecimal symbol pairs obtained based on the second conversion relation are respectively Figure 9 The binary data on B[2:0] is 010, corresponding to the hexadecimal symbol pairs 31, 34, 01, and 04.

[0142] Furthermore, the above examples are intended to illustrate the second conversion relationship between ternary symbols and hexadecimal symbols, rather than to limit the construction process of the second conversion relationship. Besides constructing it at the overall granularity as shown in the above embodiments, using two ternary symbols as a whole and two hexadecimal symbols as a whole, it can also be constructed at the single-symbol granularity. For example, the hexadecimal symbol to which each ternary symbol is converted is determined, and then the hexadecimal symbol pair to which the ternary symbol is converted is determined based on the hexadecimal symbol to which each ternary symbol is converted, thus obtaining the second conversion relationship. The process of determining the hexadecimal symbol corresponding to each ternary symbol is similar to determining the second conversion relationship between ternary symbol pairs and hexadecimal symbol pairs in the above embodiments, and can be found in the relevant descriptions, which will not be repeated here. Table 4 shows a conversion relationship between ternary symbols and hexadecimal symbols provided by an embodiment of this application.

[0143] Table 4

[0144] Ternary symbols hexadecimal symbols +1 5，0 -1 2，3 0 4，1

[0145] In determining the hexadecimal symbol pair from a ternary symbol pair based on the hexadecimal symbol conversion from ternary to hexadecimal, there is a correspondence between the bit fields of the ternary symbol pair and the bit fields of the hexadecimal symbol pair. Taking the third and fourth bit fields of a ternary symbol pair as an example, the third bit field corresponds to the first bit field, and the fourth bit field corresponds to the second bit field. The descriptions of the third and fourth bit fields are similar to those of the first and second bit fields, and can be found in relevant descriptions, so they will not be repeated here. Furthermore, the correspondence between bit fields in different symbol partitions may or may not be consistent.

[0146] Next, taking the first field as S[1], the third field as T[1], the second field as S[0], the fourth field as T[0], and the ternary symbol pair as +10 as an example, since the ternary symbol {+1} is converted to the hexadecimal symbol {5, 0}, and the ternary symbol {0} is converted to the hexadecimal symbol {4, 1}, the hexadecimal symbols converted to the ternary symbol pair +10 are 54, 51, 04, and 01, respectively.

[0147] In one possible implementation, each ternary symbol pair also has a mapping relationship with three binary data, which in some cases can be called a 3B2T mapping relationship. This mapping relationship can be a random mapping or it can be constructed based on the Hamming spacing between different three binary data. Table 5 shows a mapping relationship between three binary data and ternary symbol pairs provided by an embodiment of this application.

[0148] Table 5

[0149] Three binary data Ternary symbol pairs 101 +1-1 100 +10 110 +1+1 001 0-1 111 0+1 000 -1-1 010 -10 011 -1+1

[0150] The mapping relationships shown in Table 5 and Figure 10 The constellation shown in (3) Figure 1 However, in some cases, the mapping relationship between three binary data and ternary symbol pairs can be other, for example... Figure 10 (1), (2), (4), (5) and (6), or Figure 7 The mapping relationship shown in the constellation diagram.

[0151] Furthermore, the 3B2T mapping relationships involved in different symbol partitions can be consistent. For example, different symbol partitions may correspond to the same eight ternary symbol pairs, and the three binary data mapped by the eight ternary symbol pairs are consistent. Alternatively, the 3B2T mapping relationships involved in different symbol partitions may also be inconsistent. For example, as shown in the above embodiment, different symbol partitions may correspond to different eight ternary symbol pairs, or although different symbol partitions may correspond to the same eight ternary symbol pairs, the ternary symbol pairs may be mapped to different three binary data in different symbol partitions.

[0152] For example, the symbol partition also has a first conversion relationship with the two binary data. The first conversion relationship is the conversion relationship from the two binary data in the first bit group to any symbol partition. There are four possible values ​​for the two binary data. Different values ​​are converted to different symbol partitions. For example, if the two binary data are the first value, they are converted to symbol partition 1; if the two binary data are the second value, they are converted to symbol partition 2; if the two binary data are the third value, they are converted to symbol partition 3; and if the two binary data are the fourth value, they are converted to symbol partition 4.

[0153] Optionally, the first, second, third, and fourth values ​​can be different values ​​from 00, 01, 10, and 11. For example... Figure 8 and Figure 9 As shown, the first value is 11, the second value is 00, the third value is 01, and the fourth value is 10. Or as... Figure 11 As shown, the first value is 11, the second value is 00, the third value is 10, and the fourth value is 01.

[0154] Through the first conversion relation, the second conversion relation, and the mapping relation, a conversion relationship between 5 binary data and 2 hexadecimal symbols can be constructed. If the first conversion relation is... Figure 11 As shown, the second conversion relationship is determined based on the conversion relationships shown in Table 4, and the mapping relationship is shown in Table 5. The conversion relationships between the five binary data and two hexadecimal symbols constructed based on the first conversion relationship, the second conversion relationship, and the mapping relationship are as follows: Figure 11 As shown.

[0155] Therefore, the encoding device can convert five binary data into two hexadecimal symbols based on the first conversion relationship, the second conversion relationship, and the mapping relationship, thus achieving 5B2S encoding. For cases where the mapping relationships involved in the four symbol partitions may be the same or different, the encoding device will use different encoding orders for encoding.

[0156] Case 1: The four symbol partitions involve different mapping relationships.

[0157] Because the four symbol partitions involve different mapping relationships, different symbol partitions will affect the two ternary symbols obtained by encoding the second bit group. In this case, after the encoding device divides the first bit group and the second bit group, it will first convert the first bit group into one of the four symbol partitions according to the first conversion relationship, and then use the mapping relationship corresponding to the converted symbol partition to encode the three binary data in the second bit group to obtain two ternary symbols.

[0158] For example, if the two binary data in the first bit group are the first value 11, the symbol partition to which 11 is converted is symbol partition 1, and the mapping relationship corresponding to symbol partition 1 is as follows: Figure 7 As shown. After determining the mapping relationship, the encoding device can encode the three binary data in the second bit group within the mapping relationship, obtaining two ternary symbols that have a mapping relationship with the three binary data. Taking the three binary data in the second bit group as 010 as an example, the encoding device can use... Figure 7 The encoding method shown results in two ternary symbols, +1 and -1, when 010 is encoded.

[0159] The above examples are intended to illustrate the process of encoding three binary data into two ternary symbols, and are not intended to limit the 3B2T encoding method. Besides direct conversion using combinational logic circuits as shown in the above embodiments, the encoding device can also use a lookup table (LUT) for encoding, or it can use a base conversion method, deriving the bit / trit conversion formulas for each bit field according to binary-decimal-ternary (Bdecimal-Trit) to achieve encoding. These conversion formulas can also be called bit field conversion rules in some cases. Alternatively, the encoding device can use an encoding method to encode the three binary data in the second bit group.

[0160] After encoding two ternary symbols, the encoding device will convert the two ternary symbols into a hexadecimal symbol pair based on the second conversion relationship, and then select the hexadecimal symbol pair located in symbol partition 1 from the converted hexadecimal symbol pair.

[0161] If the second conversion relationship is based on a holistic conversion relationship, the encoding device can convert two ternary symbols into corresponding hexadecimal symbol pairs. For example, based on the second conversion relationship shown in Table 3, the encoding device converts +1-1 into 53, 20, 23, and 50. If the second conversion relationship is a mapping relationship constructed at the single-symbol granularity, the encoding device can convert each ternary symbol separately to obtain hexadecimal symbols. Then, based on the correspondence between the bit fields of the ternary symbols in the ternary symbol pair and the bit fields of the hexadecimal symbols in the hexadecimal symbol pair, the two hexadecimal symbols are combined to obtain the hexadecimal symbol pairs obtained by converting the two ternary symbols. Taking the conversion relationship between ternary symbols and hexadecimal symbols as shown in Table 4, where S[1] corresponds to T[1] and S[0] corresponds to T[0] as an example, +1-1 is converted into 53, 52, 03, and 02 based on the second conversion relationship.

[0162] Although a ternary symbol pair may be converted into multiple hexadecimal symbol pairs based on the second conversion relationship, since these multiple hexadecimal symbol pairs are located in different symbol partitions, the encoding device can refer to the symbol partition obtained by converting two binary data in the first bit group based on the first conversion relationship, and select the hexadecimal symbol pair located in that symbol partition as the symbol sequence. Continuing with the example of symbol partition 1 obtained based on the first conversion relationship, since the hexadecimal symbols located in S[1] and S[0] of each hexadecimal symbol pair in symbol partition 1 will be {5, 4, 3}, the encoding device will select the hexadecimal symbol 53 located in symbol partition 1 from the four hexadecimal symbol pairs 53, 20, 23 and 50 as the symbol sequence obtained by encoding bit sequence 11010. Alternatively, it can select the hexadecimal symbol 53 located in symbol partition 1 from the four hexadecimal symbol pairs 53, 52, 03 and 02 as the symbol sequence obtained by encoding bit sequence 11010.

[0163] Case 2: The mapping relationships corresponding to the four symbol partitions are the same.

[0164] In this case, since different symbol partitions do not affect the process of encoding the second bit group to obtain two ternary symbols, the encoding device can, as shown in Case 1, first convert the first bit group based on the first conversion relationship to obtain the symbol partition, then perform 3B2T encoding based on the mapping relationship to obtain two ternary symbols, and finally convert the two ternary symbols into a hexadecimal symbol pair located in that symbol partition based on the second conversion relationship. Alternatively, the encoding device can simultaneously perform 3B2T encoding and symbol partition conversion, and then convert the two ternary symbols based on the symbol partition and the second conversion relationship to obtain two hexadecimal symbols.

[0165] The encoding device can also first perform 3B2T encoding on the three binary data in the second bit group based on the mapping relationship to obtain two ternary symbols, convert the two ternary symbols into a hexadecimal symbol pair based on the second conversion relationship, and then convert the first bit group based on the first conversion relationship to obtain a symbol partition, thereby selecting the hexadecimal symbol pair located in the symbol partition from the converted hexadecimal symbol pair.

[0166] With 5 binary data points, 11101, the first conversion relationship is as follows: Figure 11As shown, the second conversion relationship is determined based on Table 4, and the mapping relationship is shown in Table 5. Taking the two binary data in the first bit group as an example, the three binary data in the second bit group are 11, and the encoding device encodes 101 based on the mapping relationship shown in Table 5 to obtain two ternary symbols: +1 and -1. Then, the encoding device converts 11 to symbol partition 1 based on the first conversion relationship, and converts +1 and -1 based on the second conversion relationship to obtain 52, 53, 02, and 03. Since 53 is located in symbol partition 1, 52 is located in symbol partition 3, 02 is located in symbol partition 2, and 03 is located in symbol partition 4, the encoding device selects 53 from the four hexadecimal symbol pairs as the symbol sequence obtained by encoding 11101.

[0167] Regardless of the encoding method used by the encoding device to obtain the symbol sequence, it can send the symbol sequence to the decoding device so that the decoding device can decode the symbol sequence to obtain the bit sequence and perform corresponding operations based on the bit sequence. See also Figure 6 The encoding device can send symbol sequences to the decoding device configured in the physical medium attachment (PMA) sublayer via the transmitter.

[0168] S503, the decoding device acquires a symbol sequence, which includes two hexadecimal symbols.

[0169] Optionally, the decoding device can receive a sequence of symbols. For example... Figure 6 As shown, the decoding device receives the symbol sequence transmitted by the encoding device via the transmitter, based on the receiver. The symbol sequence received by the decoding device may be the same as the symbol sequence transmitted by the encoding device. However, in some cases, due to noise interference or intersymbol interference (ISI) during transmission, the two hexadecimal symbols in the symbol sequence received by the decoding device may differ from the two hexadecimal symbols in the symbol sequence transmitted by the encoding device.

[0170] Regardless of the type of symbol sequence received by the decoding device, the decoding device can decode the received symbol sequence. Since the process of decoding different symbol sequences is similar, we will take the example of the decoding device receiving the same symbol sequence as the encoding device sending the same symbol sequence to illustrate the process of the decoding device decoding the symbol sequence to obtain the bit sequence.

[0171] S504, the decoding device decodes two hexadecimal symbols into a bit sequence according to the decoding conversion relationship.

[0172] For example, after receiving a symbol sequence, the decoding device first performs signal detection on the symbol sequence to determine the signal level of each hexadecimal symbol in the symbol sequence. For instance, based on signal detection, it is determined that the signal level of the hexadecimal symbol located in the first bit field is 5, and the signal level of the hexadecimal symbol located in the second bit field is 3.

[0173] After determining the signal level of each hexadecimal symbol, the decoding device can decode two hexadecimal symbols according to the decoding conversion relationship. For example, the decoding conversion relationship includes a third conversion relationship and a fourth conversion relationship. The third conversion relationship is the conversion relationship from any symbol partition to two binary data in the first bit group, and the fourth conversion relationship is the conversion relationship from two hexadecimal symbols to two ternary symbols. In some cases, the decoding conversion relationship and the encoding conversion relationship are inverses of each other. For example, the first conversion relationship and the third conversion relationship are inverses of each other, and the second conversion relationship and the fourth conversion relationship are inverses of each other.

[0174] In some cases, the decoding device uses the symbol partition where the two hexadecimal symbols are located, and uses the third conversion relation to convert the symbol partition to obtain two binary data in the first bit group. After converting the two hexadecimal symbols to obtain two ternary symbols using the fourth conversion relation, the two ternary symbols are mapped to three binary data in the second bit group. Then, the bit sequence is obtained by combining the first bit group and the second bit group.

[0175] For example, the encoding device in S502 will use different encoding sequences for different situations, and the decoding device will also use different decoding sequences for different situations.

[0176] Case 3: The encoding device obtains the symbol sequence based on Case 1.

[0177] Case 3 corresponds to Case 1. It can be understood that if the encoding device encodes three binary data points using different mapping relationships across the four symbol partitions, the decoding device will also decode them using different mapping relationships across the four symbol partitions to obtain the three binary data points. In this case, the decoding device will first determine the symbol partition where the two hexadecimal symbols are located, and then perform 3B2T decoding.

[0178] Optionally, the decoding device can search for the two hexadecimal symbols and the eight hexadecimal symbol pairs included in each symbol partition. If one of the eight hexadecimal symbol pairs in any symbol partition is the same as the two hexadecimal symbols, the decoding device determines that the symbol partition is the symbol partition where the two hexadecimal symbols are located.

[0179] If the symbol partition is obtained by classifying the signals in the first and second bit fields, the decoding device can determine the level at which the two hexadecimal symbols are located, thereby determining the symbol partition in which the two hexadecimal symbols are located. For example, if the signal level of the hexadecimal symbol in the first bit field of two hexadecimal symbols is at the first level and the signal level of the hexadecimal symbol in the second bit field is at the second level, then any symbol partition where the two hexadecimal symbols are located is symbol partition 1 corresponding to the first and second levels; or, if the signal level of the hexadecimal symbol in the first bit field of two hexadecimal symbols is at the third level and the signal level of the hexadecimal symbol in the second bit field is at the fourth level, then any symbol partition where the two hexadecimal symbols are located is symbol partition 2 corresponding to the third and fourth levels; or, if the signal level of the hexadecimal symbol in the first bit field of two hexadecimal symbols is at the first level and the signal level of the hexadecimal symbol in the second bit field is at the fourth level, then any symbol partition where the two hexadecimal symbols are located is symbol partition 3 corresponding to the first and fourth levels; or, if the signal level of the hexadecimal symbol in the first bit field of two hexadecimal symbols is at the third level and the signal level of the hexadecimal symbol in the second bit field is at the second level, then any symbol partition where the two hexadecimal symbols are located is symbol partition 4 corresponding to the third and second levels.

[0180] Continuing with the example where the first and second levels are {5, 4, 3} as in the above embodiment, and the third and fourth levels are {2, 1, 0} as in the above embodiment, with the first bit field being S[1] and the second bit field being S[0], if the two hexadecimal symbols in the symbol sequence received by the decoding device are 53, since the signal level 5 of S[1] belongs to {5, 4, 3} and the signal level 4 of S[0] also belongs to {5, 4, 3}, then the symbol partition where the two hexadecimal symbols are located is... Figure 9 The symbol section 1 shown is marked with a white circle.

[0181] After determining the symbol partition where the two hexadecimal symbols are located, the decoding device can convert the symbol partition based on the third conversion relation to obtain two binary data. The two binary data obtained after conversion are the binary data included in the first bit group. The third conversion relation is as follows: Figure 8 As shown in the example, symbol partition 1 is converted to 11 based on the third conversion relationship, and the decoding device determines that the two binary data included in the first bit group are 11.

[0182] The decoding device also converts two hexadecimal symbols into two ternary symbols according to the fourth conversion relationship, corresponding to the process of converting two ternary symbols into two hexadecimal symbols according to the second conversion relationship. The decoding device can also directly convert two hexadecimal symbols into two ternary symbols at the whole-symbol granularity. As shown in Table 3, the fourth conversion relationship converts 53 into +1-1. Furthermore, the decoding device can also convert two hexadecimal symbols into two ternary symbols at the single-symbol granularity. For example, as shown in Table 4, the hexadecimal symbol 5 is converted into the ternary symbol +1, and the hexadecimal symbol 3 is converted into the ternary symbol -1, resulting in two ternary symbols +1-1.

[0183] Optionally, the decoding device can perform conversion synchronously based on the third conversion relationship and the fourth conversion relationship, or it can perform conversion asynchronously based on the third conversion relationship and the fourth conversion relationship. For example, it can first convert any symbol partition based on the third conversion relationship to obtain two binary data, and then convert two hexadecimal symbols based on the fourth conversion relationship to obtain two ternary symbols. Alternatively, it can first convert two hexadecimal symbols based on the fourth conversion relationship to obtain two ternary symbols, and then convert any symbol partition based on the third conversion relationship to obtain two binary data.

[0184] Regardless of the execution order by which the decoding device converts two hexadecimal symbols into two ternary symbols, the decoding device will, after determining the symbol partition where the two hexadecimal symbols are located, decode the two ternary symbols to obtain three binary data based on the mapping relationship corresponding to the symbol partition. The reason for this execution order limitation is that the mapping relationships corresponding to the four symbol partitions are different, and the decoding device needs to use the corresponding mapping relationship to decode based on the symbol partition where the two hexadecimal symbols are located. Corresponding to the encoding process, the decoding device can also use logic circuits to convert two ternary symbols into three binary data. For example, based on the two ternary symbols being +1 and -1, and the ternary symbol located at T[0] being -1, the conversion relationship is determined as follows: The decoding device determines that B[2] = 0, and since Therefore, B[1:0] = 10, and the three binary data obtained by converting +1 and -1 are 010. In addition, the decoding device can obtain the three binary data by looking up two ternary symbols using a lookup table method, or it can use a base conversion method to decode according to the mapping conversion rules of the encoded bit fields.

[0185] After determining that the first bit group includes two binary data and the second bit group includes three binary data, the decoding device can combine the decoded binary data according to the bit fields of the first and second bit groups in the five binary data to obtain a bit sequence. Continuing with the example where the first bit group has a bit field of B[4:3] in the five binary data as shown in the above embodiment, and the second bit group has a bit field of B[2:0] in the five binary data as shown in the above embodiment, the decoding device combines the decoded 11 and 010 to obtain the bit sequence 11010.

[0186] Case 4: The encoding device obtains the symbol sequence based on Case 2.

[0187] Case 4 corresponds to Case 2. Since different symbol partitions do not affect the process of decoding two ternary symbols to obtain the three binary data in the second bit group, the decoding device can determine the symbol partition first, as shown in Case 3, and then perform 3B2T encoding. Alternatively, it can perform 3B2T encoding first to obtain the three binary data included in the second bit group, and then determine the symbol partition to obtain the two binary data included in the first bit group. The difference between the decoding processes in Case 4 and Case 3 lies in the different execution order of each step, while the execution process of each step is similar. Please refer to the relevant description in Case 3, which will not be repeated here.

[0188] Next Figure 11 , Figure 10 Taking (3) and Table 4 as an example, and with the symbol sequence 53 as an example, the decoding process corresponding to case two is illustrated. The decoding device determines that the symbol partition where 53 is located is symbol partition 1 based on the fact that the signal voltages of the hexadecimal symbols in the first and second bit fields of 53 are both {5, 4, 3}. Based on the third conversion relationship, symbol partition 1 is converted into two binary data 11, and based on the fourth conversion relationship shown in Table 4, 53 is converted into two ternary symbols +1-1. After that, the decoding device... Figure 10 The mapping relationship shown in (3) is used to decode +1-1 to obtain three binary data 101. Combining 101 and 11 yields the bit sequence 11101.

[0189] based on Figure 11 It can be seen that if the three signal levels corresponding to the same bit field in a symbol partition are consecutive levels, even if the symbol sequence obtained by the decoding device changes compared to the symbol sequence sent by the encoding device, the number of error bits can be controlled. The number of error bits refers to the number of different binary data in the bit sequence decoded by the decoding device and the bit sequence encoded by the encoding device. For example, the encoding device is based on... Figure 11The conversion relationship shown shows that encoding 11101 results in a symbol sequence of 53. However, crosstalk occurs during the transmission of symbol sequence 53, causing the symbol sequence detected by the decoding device to be 52. The decoding device decodes 52 to obtain a symbol sequence of 10101. The number of error bits in 10101 is 1 compared to 11101.

[0190] In some cases, if the encoding device uses FEC encoding before encoding the bit sequence, the decoding device will also perform FEC decoding on the bit sequence after decoding it, for example... Figure 6 The decoding device shown obtains the bit sequence using PAM6 decoding and then performs RS FEC decoding on the bit sequence to obtain the data segment.

[0191] In summary, the data encoding and decoding methods provided in this application first encode the binary data in the second bit group using PAM3 to obtain two ternary symbols, and then convert the two encoded ternary symbols into two hexadecimal symbols based on the first bit group. This allows for the reuse of the PAM3 encoding circuit, which has a simple structure, low latency, and supports switching between PAM3 and hexadecimal encoding methods. Furthermore, the process of converting the two ternary symbols into two hexadecimal symbols based on the first bit group can be directly converted using logic circuits. Compared to related technologies that search the entire bit sequence in a table to obtain two hexadecimal symbols, this method has lower latency and higher encoding efficiency. In the process of converting the bit sequence into two hexadecimal symbols based on the encoding conversion relationship, this application splits the bit sequence into two bit groups, reducing the computational complexity involved in encoding and conversion based on the shorter bit groups. Compared to directly calculating the bit sequence, converting the entire bit sequence into two binary data based on the calculation results has lower computational complexity.

[0192] Furthermore, since the two hexadecimal symbols are derived from two ternary symbols and two binary data from the first bit group, they implicitly indicate the two ternary symbols and two binary data. This eliminates the need for separate signal encoding, enabling the transmission of information from the two binary data. This application does not limit the use of unused ternary symbol pairs or the method of encoding the two ternary symbols from the second bit group, allowing for flexible implementation and reuse of any 3B2T encoding. Moreover, the mapping relationship between the two ternary symbol pairs and the three binary data is constructed with a Hamming interval of 1 for the three binary data corresponding to two adjacent ternary symbol pairs. Furthermore, by using a mirrored arrangement to construct the second conversion relationship, the maximum 5-bit Hamming interval between the five binary data corresponding to two adjacent hexadecimal symbol pairs can be 1, minimizing the number of error bits and reducing encoding / decoding error tolerance.

[0193] It should be understood that the above examples are intended to illustrate the process of multiplexing PAM3 codecs to perform 5B2S codecs, and are not intended to limit the specific codec process. For example Figure 11 As shown in the embodiment of this application, the signal level of the hexadecimal symbol obtained by the 5B2S encoding can also be +5, +3, +1, -1, -3 and -5. In this case, among the hexadecimal symbol pairs included in symbol partition 1, the signal level of the hexadecimal symbol in the first bit field belongs to {+5, +3, +1}, and the signal level of the hexadecimal symbol in the second bit field belongs to {+5, +3, +1}; among the hexadecimal symbol pairs included in symbol partition 2, the signal level of the hexadecimal symbol in the first bit field belongs to {-5, -3, -1}, and the signal level of the hexadecimal symbol in the second bit field belongs to {-5, -3, -1}; among the hexadecimal symbol pairs included in symbol partition 3, the signal level of the hexadecimal symbol in the first bit field belongs to {+5, +3, +1}, and the signal level of the hexadecimal symbol in the second bit field belongs to {-5, -3, -1}; among the hexadecimal symbol pairs included in symbol partition 4, the signal level of the hexadecimal symbol in the first bit field belongs to {-5, -3, -1}, and the signal level of the hexadecimal symbol in the second bit field belongs to {+5, +3, +1}. There is a conversion relationship between symbol partition 1 and two binary data 11, symbol partition 2 and two binary data 00, symbol partition 3 and two binary data 10, and symbol partition 4 and two binary data 01.

[0194] Furthermore, the symbol partitioning and the conversion relationship between two binary data can also be... Figure 9 , Figure 11 different, Figure 12 This application provides another first and third transformation relationship in its embodiments. Figure 12 In the middle, 01 Symbol partition 3, 11 Symbol partitions 1, 10 Symbol partition 2,00 Symbol partition 4.

[0195] Furthermore, the three signal levels among the first, second, third, and fourth levels can be as follows: Figure 9 and Figure 11 The signal level shown can be continuous or discontinuous. Figure 13 This is a schematic diagram illustrating another signal level division provided in an embodiment of this application. Figure 13In the first bit group, the two binary data are located in B[3 / 1], and the three binary data are located in B[4 / 2 / 0]. The first bit field is S[1], the second bit field is S[0], the first level and the fourth level are discontinuous {5, 3, 1}, the third level and the second level are discontinuous {4, 2, 0}, the symbol partition 1 composed of the first level and the second level is marked with a square, the symbol partition 2 composed of the third level and the fourth level is marked with a black diagonal line, the symbol partition 3 composed of the first level and the fourth level is marked with a white diagonal line, and the symbol partition 4 composed of the third level and the second level is marked with a black mark. Figure 13 The diagram also shows the conversion relationships between each symbol partition and the two binary data, 11 Symbol partition 1, 00 Symbol partition 2, 01 Symbol partitions 3, 10 Symbol partition 4.

[0196] Figure 14 and Figure 15 This illustrates two other scenarios: when the signal levels corresponding to any bit field in a symbol partition are discontinuous, the distribution of hexadecimal symbol pairs in each symbol partition is shown, and... Figure 13 The difference is that, Figure 14 and Figure 15 The bit fields in the first and second bit groups are consecutive bit fields, while Figure 13 The bit fields in the first and second bit groups are discontinuous bit fields.

[0197] See Figure 14 When the first and fourth levels are discontinuous {5, 3, 1}, and the third and second levels are discontinuous {4, 2, 0}, the conversion relationship between the symbol partition and the two binary data is: Symbol partition 1 01. Symbol Partition 2 10, Symbolic Partition 3 00, Symbol partition 4 11. See also Figure 15 When the first and fourth levels are discontinuous {5, 3, 1}, and the third and second levels are discontinuous {4, 2, 0}, the conversion relationship between the symbol partition and the two binary data is: Symbol partition 1 11. Symbolic Partition 2 00, Symbol partition 3 01, Symbolic Partition 4 10.

[0198] because Figure 13 , Figure 14 and Figure 15 The corresponding encoding and decoding processes are similar, and the following will be based on... Figure 14 Using the hexadecimal symbol pair shown as an example, the encoding and decoding process is illustrated. Figure 14 Based on Figure 16 The 3B2T mapping relationship shown is encoded and then obtained through four rotations.

[0199] The encoding device acquires the bit sequence 00110, and based on B[4:3] and B[2:0], divides 00 into the first bit group and 110 into the second bit group. Then, the encoding device converts 00 to symbol partition 3 based on the first conversion relationship, and based on... Figure 16 The 3B2T mapping relationship shown is encoded as +1-1 in 110. Then, the encoding device converts +1-1 into four hexadecimal symbol pairs 51, 45, 10 and 04 based on the second conversion relationship. Since the signal level of the S[1] bit field of the hexadecimal symbol pair in symbol partition 3 is {5, 3, 1} and the signal level of the S[2] bit field is {5, 3, 1}, the encoding device selects 51 located in symbol partition 3 as the encoded bit sequence 00110 to obtain the symbol sequence.

[0200] After encoding the symbol sequence, the encoding device sends the symbol sequence to the decoding device. The decoding device performs signal detection on the symbol sequence and determines that the two hexadecimal symbols in the symbol sequence are 51. Based on Figure 14 It can be seen that the three signal levels in the first, second, third, and fourth levels are discontinuous. Compared to the continuous case, the level interval between adjacent hexadecimal symbol pairs within the same symbol partition is larger, and the probability of the signal level of a hexadecimal symbol in a hexadecimal symbol pair changing to an adjacent signal level is smaller. Furthermore, the discontinuity of the three signal levels can also control the number of error bits in certain adjacent hexadecimal symbol pairs. For example, a specific hexadecimal symbol pair might be... Figure 14 In the example, 32 and 33, the binary data obtained by decoding 32 is 01101, and the binary data obtained by decoding 33 is 00101.

[0201] After obtaining the symbol sequence 51, the decoding device determines that the symbol partition where the symbol sequence is located is symbol partition 3, corresponding to the first and fourth levels, based on the fact that the hexadecimal symbol located in S[1] is 5, belonging to the first level, and the hexadecimal symbol located in S[0] is 1, belonging to the fourth level. The decoding device is based on Figure 14 The third conversion relationship shown converts symbol partition 3 to 00, resulting in two binary data in the first bit group.

[0202] Furthermore, the decoding device will also convert 51 into two ternary symbols +1-1 based on the fourth conversion relation. Then, based on... Figure 16The mapping relationship shown is used to decode +1-1 to get 110, which consists of three binary data in the second bit group. Then, the decoding device combines 00 and 110 into 00110 based on the bit field of 00 being B[4:3] and the bit field of 110 being B[2:0], thus obtaining the bit sequence.

[0203] The data encoding and decoding methods provided in this application first encode the binary data in the second bit group using PAM3 to obtain two ternary symbols, and then convert the two ternary symbols obtained by encoding into two hexadecimal symbols based on the first bit group. The PAM3 encoding circuit can be reused. The PAM3 encoding circuit has a simple structure, low latency, and can support switching between PAM3 and 6 modulation modes.

[0204] The data encoding method of this application embodiment has been described above. Corresponding to the above method, this application embodiment also provides an encoding device. Figure 17 This is a schematic diagram of the structure of an encoding device provided in an embodiment of this application. Based on Figure 17 The following modules are shown. Figure 17 The encoding device shown is capable of performing the above. Figure 5 The illustrated encoding device can operate in whole or in part. It should be understood that the device may include more additional modules than those shown, or may omit some of the modules shown; this application does not limit this. Figure 17 As shown, the device includes:

[0205] The acquisition module 1701 is used to acquire a bit sequence, which includes two bit groups. The first bit group includes two binary data, and the second bit group includes three binary data.

[0206] The encoding module 1702 is used to encode the bit sequence according to the encoding conversion relationship to obtain the symbol sequence. The symbol sequence includes two hexadecimal symbols. The encoding conversion relationship is the conversion relationship from two binary data and two ternary symbols in the first bit group to two hexadecimal symbols. The two ternary symbols are obtained by encoding three binary data in the second bit group.

[0207] In one possible implementation, the acquisition module 1701 is used to acquire the data segment to be encoded; to perform FEC encoding on the data segment; and to obtain the bit sequence based on the encoding result.

[0208] In one possible implementation, the two ternary symbols are obtained based on a mapping relationship that indicates the mapping relationship between the three binary data in the second bit group and the two ternary symbols.

[0209] In one possible implementation, the encoding conversion relationship includes a first conversion relationship and a second conversion relationship. The first conversion relationship is the conversion relationship from two binary data in the first bit group to any symbol partition, where any symbol partition includes eight hexadecimal symbol pairs. The second conversion relationship is the conversion relationship from two ternary symbols to one of the eight hexadecimal symbol pairs.

[0210] In one possible implementation, in any pair of hexadecimal symbols included in a symbol partition, the signal level of the hexadecimal symbol in the first bit field is a first level, and the signal level of the hexadecimal symbol in the second bit field is a second level, and both the first and second levels include three signal levels; or, in any pair of hexadecimal symbols included in a symbol partition, the signal level of the hexadecimal symbol in the first bit field is a third level, and the signal level of the hexadecimal symbol in the second bit field is a fourth level, and the three signal levels included in the third level are different from the three signal levels included in the first level, and the three signal levels included in the fourth level are different from the three signal levels included in the second level; or, in any pair of hexadecimal symbols included in a symbol partition, the signal level of the hexadecimal symbol in the first bit field is a first level, and the signal level of the hexadecimal symbol in the second bit field is a fourth level; or, in any pair of hexadecimal symbols included in a symbol partition, the signal level of the hexadecimal symbol in the first bit field is a third level, and the signal level of the hexadecimal symbol in the second bit field is a second level.

[0211] In one possible implementation, at least one of the first level, second level, third level, or fourth level comprises three signal levels that are equally spaced.

[0212] In one possible implementation, the three signal levels included in the first level are the same as the three signal levels included in the second level, and the three signal levels included in the third level and the three signal levels included in the fourth level are the same.

[0213] In one possible implementation, at least one of the first level, second level, third level, or fourth level comprises three consecutive signal levels.

[0214] In one possible implementation, at least one of the first level, second level, third level, or fourth level comprises three discontinuous signal levels.

[0215] The two ternary symbols obtained by encoding the binary data in the second bit group are achieved through PAM3 encoding. First, PAM3 encoding is performed to obtain ternary symbols. Then, based on the binary data in the first bit group, the two ternary symbols obtained by encoding are converted into two hexadecimal symbols to achieve PAM6 encoding of the bit sequence. The above PAM6 encoding process can reuse the PAM3 encoding circuit, taking advantage of the simple structure and low latency of the PAM3 encoding circuit.

[0216] This application also provides another decoding device. Figure 18 This is a schematic diagram of a decoding device provided in an embodiment of this application. Based on Figure 18 The following modules are shown. Figure 18 The decoding device shown is capable of performing the above. Figure 5 The illustrated decoding device can operate in whole or in part. It should be understood that the device may include more additional modules than those shown, or may omit some of the modules shown; this application does not limit this. Figure 18 As shown, the device includes:

[0217] Module 1801 is used to acquire a symbol sequence, which includes two hexadecimal symbols;

[0218] The decoding module 1802 is used to decode two hexadecimal symbols into a bit sequence according to the decoding conversion relationship. The bit sequence includes two bit groups. The first bit group includes two binary data, and the second bit group includes three binary data.

[0219] The decoding conversion relationship is the conversion relationship between two hexadecimal symbols and two ternary symbols and two binary data in the first bit group. The two ternary symbols are obtained by encoding three binary data in the second bit group.

[0220] In one possible implementation, two hexadecimal symbols are located in any symbol partition, and the decoding conversion relationship includes a third conversion relationship and a fourth conversion relationship. The third conversion relationship is the conversion relationship from any symbol partition to two binary data in the first bit group, and the fourth conversion relationship is the conversion relationship from two hexadecimal symbols to two ternary symbols.

[0221] In one possible implementation, the signal level of the hexadecimal symbol located in the first bit field of the two hexadecimal symbols belongs to the first level, and the signal level of the hexadecimal symbol located in the second bit field belongs to the second level. Any symbol partition where the two hexadecimal symbols are located is the symbol partition corresponding to the first level and the second level, and both the first and second levels comprise three signal levels. Alternatively, the signal level of the hexadecimal symbol located in the first bit field of the two hexadecimal symbols belongs to the third level, and the signal level of the hexadecimal symbol located in the second bit field belongs to the fourth level. Any symbol partition where the two hexadecimal symbols are located is the symbol partition corresponding to the third and fourth levels, and the third level comprises the three signal levels and the first level. The three signal levels included in the first level are all different, and the three signal levels included in the second level are all different; or, the signal level of the hexadecimal symbol located in the first bit field of the two hexadecimal symbols belongs to the first level, and the signal level of the hexadecimal symbol located in the second bit field belongs to the fourth level, and any symbol partition in which the two hexadecimal symbols are located is the symbol partition corresponding to the first level and the fourth level; or, the signal level of the hexadecimal symbol located in the first bit field of the two hexadecimal symbols belongs to the third level, and the signal level of the hexadecimal symbol located in the second bit field belongs to the second level, and any symbol partition in which the two hexadecimal symbols are located is the symbol partition corresponding to the third level and the second level.

[0222] Since two ternary symbols are obtained by encoding three binary data in the second bit group, PAM3 decoding of two ternary symbols can obtain the three binary data in the second bit group. In the process of decoding the symbol sequence to obtain the bit sequence, the PAM3 decoding circuit is reused, taking advantage of the simple structure and low latency of the PAM3 decoding circuit.

[0223] It should be understood that the above Figure 17 or Figure 18 The provided device, in implementing its functions, is only illustrated by the division of the aforementioned functional modules. In practical applications, the functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. Furthermore, the device and method embodiments provided in the above embodiments belong to the same concept, and their specific implementation process is detailed in the method embodiments, which will not be repeated here. Figure 17 or Figure 18 The provided device can be a chip or a communication device; for example, the encoding device can be a network device as described below.

[0224] See Figure 19 , Figure 19 A schematic diagram of the structure of a network device 1900 provided in an exemplary embodiment of this application is shown. Figure 19The network device 1900 shown can perform the above-mentioned functions for the encoding device. Figure 5 The operations involved in the data encoding method shown can also be performed by the decoding device described above. Figure 5 The data decoding method shown involves the following operations. The network device 1900 is, for example, a switch, a router, etc., and can be implemented using a general bus architecture.

[0225] like Figure 19 As shown, the network device 1900 includes at least one processor 1901, a memory 1903, and at least one communication interface 1904.

[0226] Processor 1901 may be, for example, a general-purpose central processing unit (CPU), a digital signal processor (DSP), a network processor (NP), a graphics processing unit (GPU), a neural-network processing unit (NPU), a data processing unit (DPU), a microprocessor, or one or more integrated circuits for implementing the embodiments of this application. For example, processor 1901 includes an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A PLD may be, for example, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof. It can implement or execute the various logic blocks, modules, and circuits described in connection with the embodiments of this application. A processor may also be a combination that implements computational functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0227] Optionally, the network device 1900 also includes a bus. The bus is used to transfer information between the various components of the network device 1900. The bus can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 19 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0228] Memory 1903 may be, for example, read-only memory (ROM) or other types of static storage devices capable of storing static information and instructions; random access memory (RAM) or other types of dynamic storage devices capable of storing information and instructions; electrically erasable programmable read-only memory (EEPROM); compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed discs, laser discs, optical discs, digital universal discs, Blu-ray discs, etc.); magnetic disk storage media or other magnetic storage devices; or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited thereto. Memory 1903 may exist independently and be connected to processor 1901 via a bus. Memory 1903 may also be integrated with processor 1901.

[0229] Communication interface 1904 uses any transceiver-like device for communicating with other devices or communication networks, such as Ethernet, Radio Access Network (RAN), or Wireless Local Area Network (WLAN). Communication interface 1904 can include wired and wireless communication interfaces. Specifically, communication interface 1904 can be an Ethernet interface, a Fast Ethernet (FE) interface, a Gigabit Ethernet (GE) interface, an Asynchronous Transfer Mode (ATM) interface, a WLAN interface, a cellular network communication interface, or a combination thereof. The Ethernet interface can be an optical interface, an electrical interface, or a combination thereof. In this embodiment, communication interface 1904 can be used by network device 1900 to communicate with other devices.

[0230] In a specific implementation, as one example, the processor 1901 may include one or more CPUs, such as Figure 19 The CPU0 and CPU1 shown are examples of processors. Each of these processors can be a single-core processor or a multi-core processor. A processor here can refer to one or more devices, circuits, and / or processing cores used to process data (e.g., computer program instructions).

[0231] In a specific implementation, as one example, network device 1900 may include multiple processors, such as... Figure 19 The processors 1901 and 1905 are shown. Each of these processors can be a single-core processor or a multi-core processor. Here, "processor" can refer to one or more devices, circuits, and / or processing cores used to process data (such as computer program instructions).

[0232] In a specific implementation, as one example, network device 1900 may further include output devices and input devices. The output device communicates with processor 1901 and can display information in various ways. For example, the output device may be a liquid crystal display (LCD), a light-emitting diode (LED) display device, a cathode ray tube (CRT) display device, or a projector, etc. The input device communicates with processor 1901 and can receive user input in various ways. For example, the input device may be a mouse, keyboard, touchscreen device, or sensing device, etc.

[0233] In some embodiments, memory 1903 stores program code 1910 for executing the solution of this application, and processor 1901 can execute the program code 1910 stored in memory 1903. That is, network device 1900 can implement the data encoding method or data decoding method provided in the method embodiments through processor 1901 and program code 1910 in memory 1903. Program code 1910 may include one or more software modules. Optionally, processor 1901 itself may also store program code or instructions for executing the solution of this application.

[0234] In specific embodiments, the network device 1900 of this application embodiment may correspond to the encoding device or decoding device in the above-described method embodiments.

[0235] in, Figure 5 The steps of the data encoding and decoding methods shown are implemented through integrated logic circuits in the hardware or software instructions in the processor of the network device 1900. The steps of the methods disclosed in the embodiments of this application can be directly implemented by the hardware processor, or implemented by a combination of hardware and software modules in the processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. Since the storage medium is located in memory, the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above methods; to avoid repetition, these will not be described in detail here.

[0236] See Figure 20 , Figure 20 This application shows a schematic diagram of the structure of a network device 2000 provided in another exemplary embodiment. Figure 20 The network device 2000 shown can perform the above-mentioned functions as an encoding device. Figure 5 All or part of the operations involved in the data encoding method shown can also be performed as a decoding device. Figure 5The data decoding method shown involves all or part of the operations. The network device 2000 is, for example, a switch, a router, etc., and can be implemented using a general bus architecture.

[0237] like Figure 20 As shown, the network device 2000 includes: a main control board 2010 and an interface board 2030.

[0238] The main control board, also known as the main processing unit (MPU) or route processor card, is used to control and manage the various components in the network device 2000, including routing calculation, device management, device maintenance, and protocol processing functions. The main control board 2010 includes a central processing unit 2011 and a memory 2012.

[0239] The interface board 2030 is also known as a line processing unit (LPU), linecard, or service board. The interface board 2030 provides various service interfaces and implements packet forwarding. Service interfaces include, but are not limited to, Ethernet interfaces, POS (Packet over SONET / SDH) interfaces, etc., with Ethernet interfaces including, for example, Flexible Ethernet Clients (FlexE Clients). The interface board 2030 includes: a central processing unit 2031, a network processor 2032, a forwarding table entry memory 2034, and a physical interface card (PIC) 2033.

[0240] The central processing unit 2031 on the interface board 2030 is used to control and manage the interface board 2030 and communicate with the central processing unit 2011 on the main control board 2010.

[0241] The network processor 2032 is used to implement packet forwarding processing. The network processor 2032 can be in the form of a forwarding chip. The forwarding chip can be a network processor (NP). In some embodiments, the forwarding chip can be implemented using an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). Specifically, the network processor 2032 forwards received packets based on the forwarding table stored in the forwarding table entry memory 2034. If the destination address of the packet is the address of the network device 2000, the packet is sent to the CPU (such as the central processing unit 2031) for processing; if the destination address of the packet is not the address of the network device 2000, the next hop and outgoing interface corresponding to the destination address are looked up in the forwarding table according to the destination address, and the packet is forwarded to the outgoing interface corresponding to the destination address. Uplink packet processing may include: packet ingress interface processing, forwarding table lookup; downlink packet processing may include: forwarding table lookup, etc. In some embodiments, the central processing unit can also perform the functions of the forwarding chip, such as implementing software forwarding based on a general-purpose CPU, thus eliminating the need for a forwarding chip on the interface board.

[0242] The physical interface card 2033 is used to implement physical layer interfacing functions. Raw traffic enters the interface board 2030 through this card, and processed packets are sent out from the physical interface card 2033. The physical interface card 2033, also known as a daughter card, can be installed on the interface board 2030. It is responsible for converting photoelectric signals into packets, performing validity checks on the packets, and forwarding them to the network processor 2032 for processing. In some embodiments, the central processing unit 2031 can also perform the functions of the network processor 2032, such as implementing software forwarding based on a general-purpose CPU, thus eliminating the need for the network processor 2032 in the physical interface card 2033.

[0243] Optionally, the network device 2000 includes multiple interface boards. For example, the network device 2000 also includes an interface board 2040, which includes a central processing unit 2041, a network processor 2042, a forwarding table entry memory 2044, and a physical interface card 2043. The functions and implementation methods of the components in the interface board 2040 are the same as or similar to those in the interface board 2030, and will not be described in detail here.

[0244] Optionally, the network device 2000 also includes a switching fabric board 2020. The switching fabric board 2020 can also be called a switch fabric unit (SFU). When the network device 2000 has multiple interface boards, the switching fabric board 2020 is used to complete data exchange between the interface boards. For example, interface boards 2030 and 2040 can communicate through the switching fabric board 2020.

[0245] The main control board 2010 and the interface boards are coupled. For example, the main control board 2010, interface boards 2030 and 2040, and the switching network board 2020 communicate with each other via a system bus connected to the system backplane. In one possible implementation, an inter-process communication (IPC) channel is established between the main control board 2010 and interface boards 2030 and 2040, and communication between the main control board 2010 and interface boards 2030 and 2040 is achieved through the IPC channel.

[0246] Logically, network device 2000 includes a control plane and a forwarding plane. The control plane includes a main control board 2010 and a central processing unit 2011, while the forwarding plane includes various components that perform forwarding, such as a forwarding table entry memory 2034, a physical interface card 2033, and a network processor 2032. The control plane performs functions such as router operation, generating forwarding tables, processing signaling and protocol messages, and configuring and maintaining the status of network devices. The control plane distributes the generated forwarding tables to the forwarding plane. In the forwarding plane, the network processor 2032 forwards messages received by the physical interface card 2033 based on the forwarding tables distributed by the control plane. The forwarding tables distributed by the control plane can be stored in the forwarding table entry memory 2034. In some embodiments, the control plane and the forwarding plane can be completely separated and not on the same network device.

[0247] It's worth noting that a network device may have one or more main control boards, including a primary and a backup main control board. It may also have one or more interface boards; the more powerful the network device's data processing capabilities, the more interface boards it provides. Each interface board may also have one or more physical interface cards. A switching board may or may not exist; multiple boards can share the load and provide redundancy. In a centralized forwarding architecture, the network device may not need a switching board, as the interface boards handle the entire system's business data processing. In a distributed forwarding architecture, the network device can have at least one switching board, which enables data exchange between multiple interface boards, providing high-capacity data exchange and processing capabilities. Therefore, the data access and processing capabilities of a distributed architecture network device are greater than those of a centralized architecture network device. Alternatively, the network device can also be a single board, without a switching board. The functions of the interface board and the main control board are integrated on this one board. In this case, the central processing unit (CPU) on the interface board and the CPU on the main control board can be combined into a single CPU to perform the combined functions. This type of network device has lower data exchange and processing capabilities (e.g., low-end switches or routers). The specific architecture adopted depends on the specific network deployment scenario, and no restrictions are imposed here.

[0248] In a specific embodiment, network device 2000 corresponds to the above. Figure 17 The encoding device shown or Figure 18 The decoding device is shown. In some embodiments, Figure 17 The encoding module 1702 in the encoding device shown is equivalent to the central processing unit 2011 or network processor 2032 in the network device 2000.

[0249] This application embodiment also provides a communication device, which includes a transceiver, a memory, and a processor. The transceiver, the memory, and the processor communicate with each other via an internal connection path. The memory stores instructions, and the processor executes the instructions stored in the memory to control the transceiver to receive and transmit signals. When the processor executes the instructions stored in the memory, it causes the processor to perform... Figure 5 The data encoding or data decoding method shown.

[0250] It should be understood that the aforementioned processor can be a CPU, or other general-purpose processors, DSPs, ASICs, FPGAs, or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. General-purpose processors can be microprocessors or any conventional processor. It is worth noting that the processor can be a processor supporting the Advanced Reduced Instruction Set Computing (RISC) machine (ARM) architecture.

[0251] Furthermore, in an alternative embodiment, the memory described above may include read-only memory and random access memory, and provide instructions and data to the processor. The memory may also include non-volatile random access memory. For example, the memory may also store device type information.

[0252] The memory can be volatile or non-volatile, or may include both. Non-volatile memory can be ROM, programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), EEPROM, or flash memory. Volatile memory can be RAM, used as an external cache. Many forms of RAM are available by way of example, but not limitation. Examples include static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0253] This application embodiment also provides a data processing device, the device including a processor coupled to a memory, the memory for storing at least one instruction, and the processor for loading and executing the at least one instruction, so that the data processing device performs the following: Figure 5 The data encoding or decoding method shown. Optionally, the device also includes a memory.

[0254] This application also provides a computer-readable storage medium storing at least one instruction, which is loaded and executed by a processor to enable the computer to perform the following: Figure 5The data encoding or data decoding method shown.

[0255] This application also provides a computer program (product) that, when executed by a computer, causes the processor or computer to perform the corresponding steps and / or processes in the above method embodiments.

[0256] This application also provides a data processing system, which includes an encoding device and a decoding device, wherein the encoding device is used to perform... Figure 5 The data encoding method shown is used by the decoding device to perform... Figure 5 The data decoding method shown.

[0257] In some cases, the aforementioned communication device, encoding device, and decoding device can be chips.

[0258] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive).

[0259] It should be noted that all information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.), and signals involved in this application have been authorized by the user or fully authorized by all parties, and the collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. For example, the bit sequences involved in this application were obtained with full authorization.

[0260] Those skilled in the art will recognize that the method steps and modules described in conjunction with the embodiments disclosed herein can be implemented in software, hardware, firmware, or any combination thereof. To clearly illustrate the interchangeability of hardware and software, the steps and components of each embodiment have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0261] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0262] When implemented using software, it can be implemented wholly or partially as a computer program product. This computer program product includes one or more computer program instructions. As an example, the methods of this application embodiment can be described in the context of machine-executable instructions, such as program modules that execute on a device on a real or virtual processor of the target. Generally, program modules include routines, programs, libraries, objects, classes, components, data structures, etc., which perform specific tasks or implement specific abstract data structures. In various embodiments, the functionality of program modules can be combined or divided among the described program modules. The machine-executable instructions for the program modules can execute within a local or distributed device. In a distributed device, the program modules can reside on both local and remote storage media.

[0263] Computer program code used to implement the methods of the embodiments of this application may be written in one or more programming languages. This computer program code may be provided to the processor of a general-purpose computer, a special-purpose computer, or other programmable encoding or decoding apparatus, such that when executed by the computer or other programmable encoding or decoding apparatus, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a computer, partially on a computer, as a standalone software package, partially on a computer and partially on a remote computer, or entirely on a remote computer or server.

[0264] In the context of the embodiments of this application, computer program code or related data may be carried by any suitable carrier to enable a device, apparatus, or processor to perform the various processes and operations described above. Examples of carriers include signals, computer-readable media, etc.

[0265] Examples of signals may include electrical, optical, radio, sound, or other forms of propagation signals, such as carrier waves, infrared signals, etc.

[0266] A machine-readable medium can be any tangible medium that contains or stores programs for or relating to an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media can include, but are not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. More detailed examples of machine-readable storage media include electrical connections with one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0267] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and modules described above can be found in the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0268] In the embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the couplings or direct couplings or communication connections shown or discussed may be indirect couplings or communication connections through some interfaces, devices, or modules, or they may be electrical, mechanical, or other forms of connection.

[0269] The modules described as separate components may or may not be physically separate. Similarly, the components shown as modules may or may not be physical modules; they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of the embodiments of this application, depending on actual needs.

[0270] Furthermore, the functional modules in the various embodiments of this application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0271] If the integrated module is implemented as a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0272] In this application, the terms "first," "second," etc., are used to distinguish identical or similar items that have substantially the same function and purpose. It should be understood that there is no logical or temporal dependency between "first," "second," and "nth," nor does it limit the quantity or order of execution. It should also be understood that although the following description uses the terms "first," "second," etc., to describe various elements, these elements should not be limited by the terms. These terms are merely used to distinguish one element from another. For example, without departing from the various examples described, a first image can be referred to as a second image, and similarly, a second image can be referred to as a first image. Both the first image and the second image can be images, and in some cases, they can be separate and distinct images.

[0273] It should also be understood that, in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0274] In this application, the term "at least one" means one or more, and the term "multiple" means two or more. For example, multiple second messages refer to two or more second messages. The terms "system" and "network" are often used interchangeably in this document.

[0275] It should be understood that the terminology used in the description of the various examples herein is for the purpose of describing particular examples only and is not intended to be limiting. As used in the description of the various examples and the appended claims, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0276] It should also be understood that the term "and / or" as used herein refers to and covers any and all possible combinations of one or more of the associated listed items. The term "and / or" describes an association between related objects, indicating that three relationships can exist; for example, A and / or B can represent: A alone, A and B simultaneously, or B alone. Additionally, the character " / " in this application generally indicates that the preceding and following related objects are in an "or" relationship.

[0277] It should also be understood that the term “comprising” (also referred to as “includes”, “including”, “comprises” and / or “comprising”) as used in this specification specifies the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0278] It should also be understood that the terms “if” and “if” can be interpreted as meaning “when” or “upon”, or “in response to determination” or “in response to detection”. Similarly, depending on the context, the phrases “if determination…” or “if detection [the stated condition or event]” can be interpreted as meaning “when determination…”, or “in response to determination…”, or “when detection [the stated condition or event]” or “in response to detection [the stated condition or event]”.

[0279] It should be understood that determining B based on A does not mean determining B solely based on A; B can also be determined based on A and / or other information.

[0280] It should also be understood that the phrases "an embodiment," "an embodiment," and "a possible implementation" used throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment or implementation is included in at least one embodiment of this application. Therefore, the phrases "in an embodiment," "an embodiment," or "a possible implementation" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

Claims

1. A data encoding method, characterized in that, The method includes: Obtain a bit sequence, the bit sequence comprising two bit groups, the first bit group comprising two binary data, and the second bit group comprising three binary data; The bit sequence is encoded according to the encoding conversion relationship to obtain a symbol sequence, which includes two hexadecimal symbols. The encoding conversion relationship is the conversion relationship from two binary data and two ternary symbols in the first bit group to the two hexadecimal symbols. The two ternary symbols are obtained by encoding three binary data in the second bit group.

2. The method according to claim 1, characterized in that, The two ternary symbols are obtained based on a mapping relationship, which indicates the mapping relationship between the three binary data in the second bit group and the two ternary symbols.

3. The method according to claim 1 or 2, characterized in that, The encoding conversion relationship includes a first conversion relationship and a second conversion relationship. The first conversion relationship is the conversion relationship from two binary data in the first bit group to any symbol partition, and the any symbol partition includes eight hexadecimal symbol pairs. The second conversion relationship is the conversion relationship from the two ternary symbols to one of the eight hexadecimal symbol pairs.

4. The method according to claim 3, characterized in that, In any symbol partition, the signal level of the hexadecimal symbol located in the first bit field belongs to the first level, and the signal level of the hexadecimal symbol located in the second bit field belongs to the second level. The first level and the second level both include three signal levels. Alternatively, in any hexadecimal symbol pair included in the symbol partition, the signal level of the hexadecimal symbol located in the first bit field belongs to the third level, and the signal level of the hexadecimal symbol located in the second bit field belongs to the fourth level. The three signal levels included in the third level are different from the three signal levels included in the first level, and the three signal levels included in the fourth level are different from the three signal levels included in the second level. Alternatively, in any hexadecimal symbol pair included in the symbol partition, the signal level of the hexadecimal symbol located in the first bit field belongs to the first level, and the signal level of the hexadecimal symbol located in the second bit field belongs to the fourth level; Alternatively, in any of the hexadecimal symbol pairs included in the symbol partition, the signal level of the hexadecimal symbol located in the first bit field belongs to the third level, and the signal level of the hexadecimal symbol located in the second bit field belongs to the second level.

5. The method according to claim 4, characterized in that, The first level, the second level, the third level, or the fourth level comprise three signal levels that are equally spaced.

6. The method according to claim 4 or 5, characterized in that, The first level includes the same three signal levels as the second level, and the third level includes the same three signal levels as the fourth level.

7. The method according to any one of claims 4-6, characterized in that, The three signal levels included in at least one of the first level, the second level, the third level, or the fourth level are continuous levels.

8. The method according to any one of claims 4-6, characterized in that, The three signal levels included in at least one of the first level, the second level, the third level, or the fourth level are discontinuous levels.

9. The method according to any one of claims 1-8, characterized in that, The acquisition of the bit sequence includes: Obtain the data segment to be encoded; The data segment is subjected to forward error correction coding (FEC) encoding, and the bit sequence is obtained based on the encoding result.

10. A data decoding method, characterized in that, The method includes: Obtain a symbol sequence, the symbol sequence comprising two hexadecimal symbols; The two hexadecimal symbols are decoded into a bit sequence according to the decoding conversion relationship. The bit sequence includes two bit groups. The first bit group includes two binary data, and the second bit group includes three binary data. The decoding conversion relationship is the conversion relationship from the two hexadecimal symbols to the two ternary symbols and the two binary data in the first bit group. The two ternary symbols are obtained by encoding the three binary data in the second bit group.

11. The method according to claim 10, characterized in that, The two hexadecimal symbols are located in any symbol partition. The decoding conversion relationship includes a third conversion relationship and a fourth conversion relationship. The third conversion relationship is the conversion relationship from the any symbol partition to the two binary data in the first bit group. The fourth conversion relationship is the conversion relationship from the two hexadecimal symbols to the two ternary symbols.

12. The method according to claim 11, characterized in that, The signal level of the hexadecimal symbol located in the first bit field of the two hexadecimal symbols belongs to the first level, and the signal level of the hexadecimal symbol located in the second bit field belongs to the second level. The symbol partition in which the two hexadecimal symbols are located is the symbol partition corresponding to the first level and the second level. The first level and the second level both include three signal levels. Alternatively, the signal level of the hexadecimal symbol located in the first bit field of the two hexadecimal symbols belongs to the third level, and the signal level of the hexadecimal symbol located in the second bit field belongs to the fourth level. The symbol partition in which the two hexadecimal symbols are located is the symbol partition corresponding to the third level and the fourth level. The three signal levels included in the third level are different from the three signal levels included in the first level, and the three signal levels included in the fourth level are different from the three signal levels included in the second level. Alternatively, the signal level of the hexadecimal symbol located in the first bit field of the two hexadecimal symbols belongs to the first level, and the signal level of the hexadecimal symbol located in the second bit field belongs to the fourth level. The symbol partition in which the two hexadecimal symbols are located is the symbol partition corresponding to the first level and the fourth level. Alternatively, the signal level of the hexadecimal symbol located in the first bit field of the two hexadecimal symbols belongs to the third level, and the signal level of the hexadecimal symbol located in the second bit field belongs to the second level. The symbol partition in which the two hexadecimal symbols are located is the symbol partition corresponding to the third level and the second level.

13. A symbol sequence structure, characterized in that, The symbol sequence structure is a sequence structure obtained by encoding a bit sequence according to an encoding conversion relationship. The bit sequence includes two bit groups. The first bit group includes two binary data, and the second bit group includes three binary data. The symbol sequence structure includes two hexadecimal symbols. The encoding conversion relationship is the conversion relationship from the two binary data and two ternary symbols in the first bit group to the two hexadecimal symbols. The two ternary symbols are obtained by encoding the three binary data in the second bit group.

14. The sequence structure according to claim 13, characterized in that, When the three binary data in the second bit group are 101, the two ternary symbols are 1-1; When the three binary data in the second bit group are 100, the two ternary symbols are 10; When the three binary data in the second bit group are 110, the two ternary symbols are 11; When the three binary data in the second bit group are 001, the two ternary symbols are 0-1; When the three binary data in the second bit group are 111, the two ternary symbols are 01; When the three binary data in the second bit group are 000, the two ternary symbols are -1-1; When the three binary data in the second bit group are 010, the two ternary symbols are -10; When the three binary data in the second bit group are 011, the two ternary symbols are -11.

15. The sequence structure according to claim 13 or 14, characterized in that, The encoding conversion relationship includes a first conversion relationship and a second conversion relationship. The first conversion relationship is the conversion relationship from two binary data in the first bit group to any symbol partition, and the any symbol partition includes eight hexadecimal symbol pairs. The second conversion relationship is the conversion relationship from the two ternary symbols to one of the eight hexadecimal symbol pairs.

16. The sequence structure according to claim 15, characterized in that, In any hexadecimal symbol pair included in the symbol partition, the signal level of the hexadecimal symbol located in the first bit field belongs to {+5, +3, +1}, and the signal level of the hexadecimal symbol located in the second bit field belongs to {+5, +3, +1}. Alternatively, in any of the hexadecimal symbol pairs included in the symbol partition, the signal level of the hexadecimal symbol located in the first bit field belongs to {-5, -3, -1}, and the signal level of the hexadecimal symbol located in the second bit field belongs to {-5, -3, -1}. Alternatively, in any of the hexadecimal symbol pairs included in the symbol partition, the signal level of the hexadecimal symbol located in the first bit field belongs to {+5, +3, +1}, and the signal level of the hexadecimal symbol located in the second bit field belongs to {-5, -3, -1}. Alternatively, in any of the hexadecimal symbol pairs included in the symbol partition, the signal level of the hexadecimal symbol located in the first bit field belongs to {-5, -3, -1}, and the signal level of the hexadecimal symbol located in the second bit field belongs to {+5, +3, +1}.

17. The sequence structure according to claim 16, characterized in that, When the two binary data in the first bit group are 11, in any symbol partition obtained by converting the 11 based on the first conversion relationship, the signal level of the hexadecimal symbol located in the first bit field belongs to {+5, +3, +1}, and the signal level of the hexadecimal symbol located in the second bit field belongs to {+5, +3, +1}. Alternatively, if two binary data in the first bit group are 00, in any symbol partition obtained by converting the 00 based on the first conversion relationship, the signal level of the hexadecimal symbol located in the first bit field belongs to {-5, -3, -1}, and the signal level of the hexadecimal symbol located in the second bit field belongs to {-5, -3, -1}. Alternatively, if two binary data in the first bit group are 10, in any symbol partition obtained by converting the 10 based on the first conversion relationship, the signal level of the hexadecimal symbol located in the first bit field belongs to {+5, +3, +1}, and the signal level of the hexadecimal symbol located in the second bit field belongs to {-5, -3, -1}. Alternatively, if the two binary data in the first bit group are 0 and 1, in any symbol partition obtained by converting the 0 and 1 based on the first conversion relationship, the signal level of the hexadecimal symbol located in the first bit field belongs to {-5, -3, -1}, and the signal level of the hexadecimal symbol located in the second bit field belongs to {+5, +3, +1}.

18. The sequence structure according to claim 15, characterized in that, In any symbol partition, the signal level of the hexadecimal symbol in the first bit field belongs to {5, 4, 3}, and the signal level of the hexadecimal symbol in the second bit field belongs to {5, 4, 3}. Alternatively, in any hexadecimal symbol pair included in the symbol partition, the signal level of the hexadecimal symbol located in the first bit field belongs to {2, 1, 0}, and the signal level of the hexadecimal symbol located in the second bit field belongs to {2, 1, 0}. Alternatively, in any hexadecimal symbol pair included in the symbol partition, the signal level of the hexadecimal symbol located in the first bit field belongs to {5, 4, 3}, and the signal level of the hexadecimal symbol located in the second bit field belongs to {2, 1, 0}. Alternatively, in any hexadecimal symbol pair included in the symbol partition, the signal level of the hexadecimal symbol located in the first bit field belongs to {2, 1, 0}, and the signal level of the hexadecimal symbol located in the second bit field belongs to {5, 4, 3}.

19. The sequence structure according to claim 18, characterized in that, When the two binary data in the first bit group are 11, in any symbol partition obtained by converting the 11 based on the first conversion relationship, the signal level of the hexadecimal symbol located in the first bit field belongs to {5, 4, 3}, and the signal level of the hexadecimal symbol located in the second bit field belongs to {5, 4, 3}. Alternatively, if two binary data in the first bit group are 00, in any symbol partition obtained by converting the 00 based on the first conversion relationship, the signal level of the hexadecimal symbol located in the first bit field belongs to {2, 1, 0}, and the signal level of the hexadecimal symbol located in the second bit field belongs to {2, 1, 0}. Alternatively, if the two binary data in the first bit group are 10, in any symbol partition obtained by converting the 10 based on the first conversion relationship, the signal level of the hexadecimal symbol located in the first bit field belongs to {5, 4, 3}, and the signal level of the hexadecimal symbol located in the second bit field belongs to {2, 1, 0}. Alternatively, if the two binary data in the first bit group are 0 and 1, in any symbol partition obtained by converting the 0 and 1 based on the first conversion relationship, the signal level of the hexadecimal symbol located in the first bit field belongs to {2, 1, 0}, and the signal level of the hexadecimal symbol located in the second bit field belongs to {5, 4, 3}.

20. An encoding device, characterized in that, The encoding device is used to perform the data encoding method according to any one of claims 1-9.

21. A decoding device, characterized in that, The decoding device is used to perform the data decoding method according to any one of claims 10-12.

22. A data processing device, characterized in that, The device includes a processor configured to load and execute at least one instruction to cause the data processing device to implement the data encoding method as described in any one of claims 1-9, or the data decoding method as described in any one of claims 10-12.

23. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores at least one instruction, which is loaded and executed by a processor to implement the data encoding method as described in any one of claims 1-9, or the data decoding method as described in any one of claims 10-12.

24. A chip, characterized in that, The chip includes a processor for running program instructions or code that cause a device containing the chip to perform a data encoding method as described in any one of claims 1-9, or to implement a data decoding method as described in any one of claims 10-12.

25. A computer program product, characterized in that, The computer program product includes a computer program / instruction that is executed by a processor to cause a computer to perform the data encoding method as described in any one of claims 1-9, or to implement the data decoding method as described in any one of claims 10-12.

26. A data processing system, characterized in that, The system includes an encoding device and a decoding device, the encoding device being used to perform the data encoding method as described in any one of claims 1-9, and the decoding device being used to perform the data decoding method as described in any one of claims 10-12.

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