Method and apparatus for dynamic fcs insertion of high speed ethernet frames

Abstract

The application discloses a dynamic FCS insertion method and device for high-speed Ethernet frames, and relates to the technical field of Ethernet data processing. The method determines the number of parallel check calculation units and input delay periods according to the number of single-shot transmission bytes, a preset minimum effective data length and a cyclic redundancy check calculation delay. The to-be-transmitted Ethernet frame and control information are synchronously delayed, and continuous messages are distributed to the multiple parallel check calculation units according to frame polling to obtain a cyclic redundancy check result. The last-shot effective byte number is used to determine an in-place insertion mode or an extended insertion mode, and the delayed message data, the cyclic redundancy check result and the delayed control information are respectively buffered and synchronously scheduled. According to the delayed control information, correct FCS or error FCS is determined, and target FCS is inserted into the message tail. Thus, the check state crosstalk of continuous short frames can be avoided, the FCS can be accurately corresponded to the message, the tail space of different frame lengths can be adapted, and normal transmission and error detection testing can be considered.

Description

Technical Field

[0001] This application relates to the field of Ethernet data processing technology, and in particular to a method and apparatus for dynamic FCS insertion of high-speed Ethernet frames. Background Technology

[0002] With the rapid development of technologies such as 5G mobile communication, cloud computing, industrial internet, and data centers, Ethernet data transmission rates are continuously increasing and gradually moving towards higher speeds such as 100G and 400G. During Ethernet data transmission, a Frame Check Sequence (FCS) is typically appended to the Ethernet frame. The receiving end performs cyclic redundancy check on the received Ethernet frames to determine whether data errors have occurred during transmission. Therefore, the calculation and insertion of the FCS is a crucial step in ensuring the integrity and reliability of high-speed Ethernet data transmission.

[0003] In existing technologies, the CRC32 algorithm is typically used to calculate the data in Ethernet frames, and the obtained CRC32 calculation result is inserted as the FCS (Fault Code Result) at the end of the Ethernet frame. However, with the increase in Ethernet transmission rate and the parallel bandwidth of data paths, the input period of Ethernet frames is gradually shortening, while CRC32 calculation usually requires multiple clock cycles to complete. When multiple short Ethernet frames are input consecutively, the CRC32 calculation of the previous Ethernet frame may not be completed before the calculation of the next Ethernet frame begins, which can easily cause the calculated data between different Ethernet frames to interfere with each other. At the same time, the number of effective bytes occupied by Ethernet frames of different lengths in the last transmission cycle is different, and the remaining space available for inserting the FCS also varies. Using a fixed FCS insertion method may result in insufficient remaining space or require additional transmission cycles. In addition, during Ethernet device testing, it is sometimes necessary to send Ethernet frames carrying erroneous FCS to the device under test to verify its error detection capability, but existing FCS insertion methods are usually mainly for sending normal messages, making it difficult to meet the corresponding testing requirements.

[0004] Therefore, in the FCS processing of high-speed Ethernet frames, timing conflicts easily arise between CRC32 calculation delay and high-speed transmission of consecutive short frames, the available space at the tail of Ethernet frames of different lengths varies, and the requirements for FCS insertion methods differ between normal transmission and error detection tests, which are urgent problems to be solved. Summary of the Invention

[0005] This application provides a dynamic FCS insertion method and apparatus for high-speed Ethernet frames, aiming to solve the problems in the existing technology during the FCS processing of high-speed Ethernet frames, such as the timing conflict between CRC32 calculation delay and high-speed transmission of consecutive short frames, the difference in available space at the tail of Ethernet frames of different lengths, and the different requirements of normal transmission and error detection tests for FCS insertion methods.

[0006] In a first aspect, a method for dynamic FCS insertion of high-speed Ethernet frames, the method comprising: The system acquires the Ethernet frame to be transmitted and the corresponding control information, and determines the number of parallel verification calculation units and the input delay period based on the number of bytes transmitted per cycle, the preset minimum effective data length, and the cyclic redundancy check calculation delay. The Ethernet frames to be transmitted and the control information are synchronized and delayed according to the input delay period to obtain delayed message data and delayed control information. Based on the message boundary of the Ethernet frames to be transmitted, multiple consecutively input Ethernet frames to be transmitted are distributed to multiple parallel verification calculation units in a frame-by-frame polling manner to calculate the cyclic redundancy check result corresponding to each Ethernet frame to be transmitted. The time interval between two consecutive receptions of Ethernet frames to be transmitted by the same parallel verification calculation unit is not less than the sum of the cyclic redundancy check calculation delay and one clock cycle. The delayed message data and the corresponding cyclic redundancy check result satisfy a preset timing alignment relationship. Based on the number of valid bytes at the end of the delayed message data and the number of bytes transmitted per single frame, the FCS insertion mode corresponding to the Ethernet frame to be transmitted is determined. The FCS insertion mode includes in-place insertion mode and extended insertion mode. The delayed message data, the cyclic redundancy check result, and the delay control information are cached respectively, and the cached delayed message data, cyclic redundancy check result, and delay control information are synchronized and scheduled based on the message start flag and message end flag of the delayed message data. The target FCS is determined based on the delay control information. The target FCS is either a correct FCS obtained based on the cyclic redundancy check result or an incorrect FCS generated based on the cyclic redundancy check result. The target FCS is then inserted into the end of the Ethernet frame to be transmitted according to the FCS insertion mode, and the Ethernet frame after inserting the target FCS is output.

[0007] Optionally, in the above scheme, determining the number of parallel verification calculation units and the input delay period based on the number of bytes transmitted per cycle, the preset minimum effective data length, and the cyclic redundancy check calculation delay includes: Obtain the preset minimum effective data length S, the number of bytes transmitted per cycle N, and the cyclic redundancy check calculation delay M; Based on the preset minimum effective data length S and the number of bytes transmitted per frame N, the minimum number of transmission frames P corresponding to the shortest Ethernet frame is determined. The minimum number of transmission frames P is a positive integer obtained by rounding up the ratio of S to N. Based on the cyclic redundancy check calculation delay M and the minimum number of transmission cycles P, determine the smallest positive integer K that satisfies K×P≥M+1, and determine the smallest positive integer K as the number of parallel check calculation units; M+1 is defined as the input delay period L; Configure the parallel verification calculation path according to the number K of the parallel verification calculation units, and configure the input delay path according to the input delay period L.

[0008] Optionally, in the above scheme, the step of allocating multiple consecutively input Ethernet frames to be transmitted to multiple parallel verification calculation units in a frame-by-frame polling manner according to the message boundaries of the Ethernet frames to be transmitted includes: Detect the start flag of the current Ethernet frame to be transmitted, and when the start flag is detected, obtain the current polling schedule count value; Based on the current polling schedule count value, the target verification calculation unit corresponding to the current Ethernet frame to be transmitted is determined from among the multiple parallel verification calculation units, and the allocation relationship between the current Ethernet frame to be transmitted and the target verification calculation unit is locked. According to the allocation relationship, the data of each frame of the current Ethernet frame to be transmitted, from the start of the message to the corresponding end of the message, is continuously input into the target verification calculation unit to obtain the cumulative verification status corresponding to the current Ethernet frame to be transmitted. When the end-of-message flag of the current Ethernet frame to be transmitted is detected, the allocation relationship is released, and the current polling schedule count value is updated cyclically according to the number of parallel verification calculation units to obtain the polling schedule count value corresponding to the next Ethernet frame to be transmitted.

[0009] Optionally, in the above scheme, the step of calculating the cyclic redundancy check result corresponding to each Ethernet frame to be transmitted includes: The number of valid bytes in the current packet data is determined based on the packet length information, packet end flag, and number of bytes transmitted per packet corresponding to the current packet data. Based on the effective number of bytes, a target parallel computing width that matches the effective number of bytes is determined from a plurality of preset parallel computing widths; Obtain the cumulative check status of the Ethernet frame to be transmitted at the end of the previous valid data frame; According to the target parallel calculation width, the cyclic redundancy check status is updated based on the cumulative check status and the current captured message data to obtain the updated check status corresponding to the end of the current captured message data. When the end-of-message flag of the Ethernet frame to be transmitted is detected, and the update verification state completes the preset calculation delay, the cyclic redundancy check result corresponding to the Ethernet frame to be transmitted is determined according to the update verification state, and the cyclic redundancy check result and the corresponding verification result validity indication are output.

[0010] Optionally, in the above scheme, determining the FCS insertion mode corresponding to the Ethernet frame to be transmitted based on the number of valid bytes at the end of the delayed message data and the number of bytes transmitted per single frame includes: The number of remaining bytes in the last frame of the delayed message data is determined based on the number of bytes transmitted in a single frame and the number of valid bytes in the last frame. The remaining bytes at the last clock cycle are compared with the preset FCS byte count to obtain the remaining space comparison result; When the remaining space comparison result indicates that the number of remaining bytes in the last frame is greater than or equal to the preset FCS byte number, the FCS insertion mode is determined to be the in-place insertion mode; When the remaining space comparison result indicates that the number of remaining bytes in the last frame is less than the preset FCS byte number, the FCS insertion mode is determined to be the extended insertion mode, the number of remaining bytes in the last frame is determined to be the original last frame FCS fill byte number, and the difference between the preset FCS byte number and the original last frame FCS fill byte number is determined to be the extended frame FCS fill byte number.

[0011] Optionally, in the above scheme, the step of separately caching the delayed message data, the cyclic redundancy check result, and the delay control information includes: Obtain the empty / full status of the data cache queue, the verification result cache queue, and the control information cache queue, and determine the corresponding cache write permission status based on the empty / full status; The insertion mode flag corresponding to the FCS insertion mode is combined with the delayed message data to obtain message buffer data. When the data buffer queue is in the write-allowed state, the message buffer data is written into the data buffer queue in the order of data steps. When any of the parallel verification calculation units outputs the cyclic redundancy check result corresponding to the Ethernet frame to be transmitted, a verification result write instruction is generated, and when the verification result cache queue is in the write-allowed state, the cyclic redundancy check result is written into the verification result cache queue according to the verification result write instruction. When the packet start flag of the delayed packet data is detected, the packet length in the delayed control information is updated according to the preset FCS byte number to obtain the updated control information. When the control information cache queue is in the write-allowed state, the updated control information is written to the control information cache queue. Based on the writing order of the message cache data, the cyclic redundancy check result, and the updated control information, a message order correspondence is established among the three.

[0012] Optionally, in the above scheme, determining the target FCS based on the delay control information includes: Extract the FCS mode control flag from the delay control information, and determine the target FCS type based on the FCS mode control flag; When the target FCS type is a correct FCS type, the correct FCS is generated based on the cyclic redundancy check result, and the correct FCS is determined as the target FCS; When the target FCS type is an erroneous FCS type, at least one bit in the cyclic redundancy check result is transformed according to a preset bit transformation rule to obtain an error check result, and the erroneous FCS is generated based on the error check result, and the erroneous FCS is determined as the target FCS; The target FCS is associated with the corresponding delayed message data and FCS insertion mode to obtain message association data for which FCS insertion processing is to be performed.

[0013] Optionally, in the above scheme, inserting the target FCS into the tail of the Ethernet frame to be transmitted according to the FCS insertion mode includes: When the FCS insertion mode is the in-place insertion mode, the target FCS is written into the remaining byte position of the last frame of the Ethernet frame to be transmitted according to the preset FCS byte order to obtain the message end frame after in-place insertion, and the effective byte indication of the message end frame is updated according to the preset FCS byte number. When the FCS insertion mode is the extended insertion mode, the first FCS field is determined from the target FCS according to the original last FCS padding byte number, and the first FCS field is written into the last remaining byte position of the Ethernet frame to be transmitted according to the preset FCS byte order to obtain the modified original message end frame. Remove the message end marker carried by the original message end marker after modification; Based on the number of bytes filled in the extended FCS, the second FCS field is determined from the target FCS, and an extended data frame is generated based on the second FCS field. The effective number of bytes in the extended data frame is set to the number of bytes filled in the extended FCS, and the message end flag of the extended data frame is set. The modified original message end frame and the extended data frame are output sequentially to obtain the Ethernet frame after being extended and inserted into the target FCS.

[0014] Optionally, in the above scheme, the step of synchronizing and scheduling the cached delayed message data, cyclic redundancy check results, and delay control information based on the message start flag and message end flag of the delayed message data includes: When the data buffer queue is not empty and is not in a paused read state, a data read enable signal is generated, and the message buffer data is read from the data buffer queue according to the data read enable signal; When the read message cache data carries a message start flag, a control information read enable signal is generated, and the updated control information corresponding to the message cache data is read from the control information cache queue according to the control information read enable signal. When the read message cache data carries a message end marker, a verification result read enable signal is generated, and the cyclic redundancy check result corresponding to the message cache data is read from the verification result cache queue according to the verification result read enable signal. When the read insertion mode flag indicates that the FCS insertion mode is an extended insertion mode, a pause read flag is generated, and subsequent reading of the data cache queue is paused according to the pause read flag; After the extended data output is completed, the pause reading flag is cleared, the reading of the data buffer queue is resumed, and the message buffer data, cyclic redundancy check results, and updated control information are obtained by synchronously outputting the message buffer data, cyclic redundancy check results, and updated control information according to the message order correspondence.

[0015] Secondly, a dynamic FCS insertion device for high-speed Ethernet frames, the device comprising: The parameter adaptation module is used to obtain the number of bytes transmitted per cycle, the preset minimum effective data length, and the cyclic redundancy check calculation delay, and to determine the number of parallel verification calculation units and the input delay period based on the number of bytes transmitted per cycle, the preset minimum effective data length, and the cyclic redundancy check calculation delay. The input delay module is used to synchronously delay the Ethernet frame to be transmitted, the control information and data validity flag corresponding to the Ethernet frame to be transmitted, according to the input delay period, so as to obtain delayed message data, delayed control information and delayed validity flag. The parallel verification calculation module includes multiple parallel verification calculation units, which are used to distribute multiple consecutively input Ethernet frames to be transmitted to multiple parallel verification calculation units in a frame-by-frame polling manner according to the message boundary of the Ethernet frames to be transmitted, and calculate the corresponding cyclic redundancy check result according to the number of effective bytes of each Ethernet frame to be transmitted. The time interval between two consecutive receptions of Ethernet frames to be transmitted by the same parallel verification calculation unit is not less than the sum of the cyclic redundancy check calculation delay and one clock cycle. The dynamic insertion judgment module is used to determine the FCS insertion mode based on the number of valid bytes at the end of the delayed message data and the number of bytes transmitted per single frame. The FCS insertion mode includes in-place insertion mode and extended insertion mode. The multi-buffer scheduling module includes a data buffer queue, a verification result buffer queue, and a control information buffer queue. The data buffer queue is used to buffer the delayed message data and the corresponding insertion mode flag. The verification result buffer queue is used to buffer the cyclic redundancy check result. The control information buffer queue is used to buffer the delay control information after updating the message length. The multi-buffer scheduling module is also used to synchronously schedule the delayed message data, the cyclic redundancy check result, and the delay control information based on the message start flag and message end flag of the delayed message data. The FCS insertion output module is used to determine the correct FCS or incorrect FCS as the target FCS based on the FCS mode control flag in the delay control information. When the FCS insertion mode is in-place insertion mode, the target FCS is inserted into the remaining byte position of the last frame of the Ethernet frame to be transmitted. When the FCS insertion mode is extended insertion mode, the target FCS is inserted into the original message end frame and the newly added extended data frame of the Ethernet frame to be transmitted, respectively, and the Ethernet frame after inserting the target FCS is output.

[0016] Compared with the prior art, this application has at least the following beneficial effects: Based on further analysis and research of existing technical problems, this application recognizes that in the FCS processing of high-speed Ethernet frames, timing conflicts easily arise between the CRC32 calculation delay and the high-speed transmission of consecutive short frames; there are differences in the available tail space of Ethernet frames of different lengths; and the requirements for FCS insertion methods differ between normal transmission and error detection testing. This application determines the number of parallel verification calculation units and the input delay period based on the number of bytes transmitted per frame, the preset minimum effective data length, and the cyclic redundancy check (CRC) calculation delay. This ensures that the parallel verification calculation resources match the input rate of the Ethernet frames to be transmitted. Furthermore, by allocating multiple consecutively input Ethernet frames to be transmitted to multiple parallel verification calculation units in a frame-by-frame polling manner, the time interval between two adjacent receptions of Ethernet frames to be transmitted by the same parallel verification calculation unit can cover the time required for CRC calculation. This avoids crosstalk in the verification status caused by the subsequent Ethernet frame entering the same calculation path before the CRC calculation of the previous Ethernet frame is completed. Simultaneously, by synchronizing the Ethernet frames to be transmitted and their control information with the corresponding data, the delayed message data is synchronized with the corresponding... The Cyclic Redundancy Check (CRC) results satisfy the preset timing alignment relationship. By separately buffering and synchronously scheduling delayed message data, CRC results, and delay control information, each CRC result can accurately correspond to the corresponding Ethernet frame to be transmitted. Furthermore, by determining the in-situ insertion mode or extended insertion mode based on the number of valid bytes in the last frame and the number of bytes transmitted in a single frame, it is possible to avoid adding data frames when there is sufficient remaining space in the last frame, and to fully carry the target FCS using extended data frames when there is insufficient remaining space in the last frame. This adapts to the differences in tail space of Ethernet frames of different lengths and reduces unnecessary transmission overhead. In addition, by selecting the correct FCS based on the delay control information or generating an incorrect FCS based on the CRC results, the same processing flow can meet both the data integrity verification requirements of normal message transmission and the test requirements of the receiver's error detection capability. This solves the problems that are prone to timing conflicts between the CRC calculation delay and the transmission of consecutive short frames during high-speed Ethernet frame transmission, the differences in the available tail space of Ethernet frames of different lengths, and the different requirements of normal transmission and error detection tests for FCS insertion methods. Attached Figure Description

[0017] Figure 1 A flowchart illustrating a method for dynamic FCS insertion of high-speed Ethernet frames according to an embodiment of this application; Figure 2 A schematic diagram illustrating 100G Ethernet transmitting Ethernet frames at 48 bytes / frame, according to one embodiment of this application; Figure 3 A schematic diagram of the hardware architecture of a dynamic FCS insertion device for high-speed Ethernet frames provided in one embodiment of this application; Figure 4A schematic diagram of the module architecture of a dynamic FCS insertion device for high-speed Ethernet frames provided in one embodiment of this application; Figure 5 This is a schematic diagram of the module architecture of a parallel verification computing unit provided in one embodiment of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0019] In one embodiment, such as Figure 1 As shown, a dynamic FCS insertion method for high-speed Ethernet frames is provided. This method can be applied to high-speed Ethernet transmission paths built based on field-programmable gate arrays, application-specific integrated circuits, or other programmable logic devices, and is used to insert a frame check sequence (FCS) at the end of the Ethernet frame to be transmitted. The FCS can be denoted as FCS, and it can be generated based on the cyclic redundancy check (CRC) result corresponding to the Ethernet frame to be transmitted. The CRC can be calculated using the CRC32 method conforming to the Ethernet communication standard.

[0020] like Figure 2 As shown, in one embodiment, the high-speed Ethernet transmission path inputs the Ethernet frame to be transmitted in a manner that transmits 48 bytes of message data per clock cycle. Each frame of message data can be represented using a TX_DATA data structure. The TX_DATA data structure may include a 384-bit message content field, a 6-bit reserved information field, an 8-bit valid byte indicator field, a message start flag, and a message end flag. The total bit width of the TX_DATA data structure can be 400 bits. The message start flag indicates the first frame of the Ethernet frame to be transmitted, the message end flag indicates the last frame, and the valid byte indicator field indicates the number of valid bytes in the last frame.

[0021] The control information corresponding to the Ethernet frame to be transmitted can be represented using the TX_INFO_FCS data structure. The TX_INFO_FCS data structure may include an FCS mode control flag, a 14-bit payload length field, a signature validity flag, an 8-bit message type field, an 18-bit signature identifier field, and a 14-bit message length field. The total bit width of the TX_INFO_FCS data structure can be 56 bits. Specifically, the FCS mode control flag indicates whether a correct or incorrect FCS is inserted; the payload length field indicates the byte length of the payload; the signature validity flag indicates whether the Ethernet frame to be transmitted carries signature information; the message type field indicates the type of the Ethernet frame to be transmitted; the signature identifier field indicates the signature identifier corresponding to the Ethernet frame to be transmitted; and the message length field indicates the message length before the FCS is inserted.

[0022] First, the system acquires the Ethernet frame to be transmitted and its corresponding control information, and obtains the number of bytes transmitted per clock cycle in the high-speed Ethernet transmission path, the preset minimum valid data length, and the cyclic redundancy check (CRC) calculation delay. The preset minimum valid data length can be set according to the minimum valid data length of the Ethernet frame, for example, to 60 bytes. The CRC calculation delay characterizes the number of clock cycles required for the parallel CRC calculation unit to go from receiving the data to outputting a valid CRC result.

[0023] Based on the number of bytes transmitted per frame, the preset minimum effective data length, and the cyclic redundancy check (CRC) calculation delay, the number of parallel CRC calculation units and the input delay period are determined. The number of parallel CRC calculation units should ensure that the time interval between two consecutive receptions of the Ethernet frame to be transmitted by the same parallel CRC calculation unit is not less than the sum of the CRC calculation delay and one clock cycle. The input delay period can be set to the sum of the CRC calculation delay and one clock cycle to ensure that the Ethernet frame to be transmitted, after the delay, satisfies the preset timing alignment relationship with the corresponding CRC result.

[0024] Subsequently, the Ethernet frames to be transmitted, control information, and data validity flags are input into the corresponding delay register chains. The Ethernet frames to be transmitted, control information, and data validity flags are transmitted synchronously under the same clock drive, resulting in delayed message data, delayed control information, and delayed validity flags, respectively. Simultaneously with the input delay, the message boundaries of each Ethernet frame to be transmitted are identified based on the start and end flags of the Ethernet frames to be transmitted, and the multiple consecutively input Ethernet frames to be transmitted are distributed to multiple parallel verification calculation units in a frame-by-frame polling manner.

[0025] For the same Ethernet frame to be transmitted, the data frames from the start of the message marker to the end of the message marker are all assigned to the same parallel check calculation unit. The parallel check calculation unit updates the cumulative check status according to the number of valid bytes in each frame's data, using the corresponding parallel calculation width, and outputs the cyclic redundancy check result after the last frame of the Ethernet frame to be transmitted is processed.

[0026] When the delayed message data reaches the preset judgment stage, the number of valid bytes in the last frame of the delayed message data is extracted. Based on the number of bytes transmitted per frame and the number of valid bytes in the last frame, the number of remaining bytes in the last frame is calculated and compared with the number of bytes occupied by the FCS. When the number of remaining bytes in the last frame is sufficient to accommodate the complete FCS, the FCS insertion mode is determined to be in-place insertion mode; when the number of remaining bytes in the last frame is insufficient to accommodate the complete FCS, the FCS insertion mode is determined to be extended insertion mode.

[0027] Delayed message data and corresponding insertion mode flags are written to the data buffer queue, cyclic redundancy check (CRC) results are written to the check result buffer queue, and delayed control information is written to the control information buffer queue after the message length is updated. The data buffer queue stores delayed message data at the data granularity, while the check result buffer queue and control information buffer queue store CRC results and control information at the message granularity, respectively. Message start and end flags ensure that the information in the three buffer queues corresponds to the message order.

[0028] During the output phase, the target FCS is determined based on the FCS mode control flag in the delay control information. When the FCS mode control flag indicates normal transmission, a correct FCS is generated based on the cyclic redundancy check result; when the FCS mode control flag indicates error detection test, a preset bit transformation is performed on the cyclic redundancy check result, and an incorrect FCS is generated based on the transformed error check result.

[0029] In in-place insertion mode, the target FCS is directly written into the remaining bytes of the last frame of the Ethernet frame to be transmitted. In extended insertion mode, a portion of the target FCS is written into the remaining bytes of the original message's end frame, and the remaining portion of the target FCS is written into a newly added extended data frame, which is then set as the new message end frame. Other message data frames besides the message end frame can be passed through with their original content intact. After FCS insertion is complete, the Ethernet frame with the inserted target FCS and the updated control information are output.

[0030] Through the above implementation method, multiple parallel verification calculation units are configured according to the data path width and the cyclic redundancy check (CRC) calculation delay, and the continuously input Ethernet frames to be transmitted are allocated by message-level polling, so that the same parallel verification calculation unit has sufficient calculation and state recovery time. At the same time, the in-situ insertion mode or the extended insertion mode is selected according to the remaining space at the end of the frame, and the delayed message data, CRC results and delay control information are accurately matched through three buffer queues. This can reduce the possibility of CRC crosstalk when transmitting consecutive short frames, adapt to the FCS insertion requirements of Ethernet frames of different lengths, and take into account both normal message transmission and error detection testing.

[0031] In this embodiment, the preset minimum effective data length is S, the number of bytes transmitted per frame is N, and the cyclic redundancy check calculation delay is M. First, the minimum number of transmission frames P corresponding to the shortest Ethernet frame is determined based on the preset minimum effective data length S and the number of bytes transmitted per frame N. The minimum number of transmission frames P can be expressed as: P = S / N .

[0032] in, This indicates rounding up. The minimum number of transmission cycles P represents the number of clock cycles required to complete the input of the shortest Ethernet frame under the current number of bytes transmitted per cycle.

[0033] Furthermore, the smallest positive integer K satisfying K×P≥M+1 is determined, and K is set as the number of parallel check units. This relationship indicates that after multiple parallel check units have processed the shortest consecutively input Ethernet frames in sequence, at least M+1 clock cycles have elapsed before the same parallel check unit is assigned a new Ethernet frame to be transmitted.

[0034] The input delay period L can be expressed as: L = M + 1.

[0035] The input delay period L is used to configure the number of register stages in the input delay path, so that the delayed message data and the corresponding cyclic redundancy check result satisfy the preset timing relationship when entering the buffer scheduling stage.

[0036] In one specific implementation, the preset minimum effective data length S is 60 bytes, the number of bytes transmitted per cycle N is 48 bytes, and the cyclic redundancy check (CRC) calculation delay M is 7 clock cycles. Therefore, the minimum number of transmission cycles P is 2, the smallest positive integer K satisfying K×2≥8 is 4, and the input delay period L is 8. Thus, four parallel CRC calculation units and an eight-level input delay register can be configured.

[0037] When 100G Ethernet inputs the shortest consecutive Ethernet frames at 48 bytes / frame, each Ethernet frame to be transmitted occupies two input data frames. Four parallel check calculation units sequentially receive the four consecutive input Ethernet frames to be transmitted. The time interval between two consecutive receptions of Ethernet frames by the same parallel check calculation unit is eight clock cycles, which can cover the seven-clock-cycle cyclic redundancy check calculation delay.

[0038] When the number of bytes N transmitted per frame is greater than or equal to the preset minimum effective data length S, the shortest Ethernet frame can be input within one data frame. In this case, P is 1, and the number of parallel verification calculation units K is at least M+1. When M is 7, eight parallel verification calculation units can be configured.

[0039] The number of parallel parity check units can be increased based on the target Ethernet rate, the amount of logic resources, and timing margin. For example, in 400G or 800G Ethernet processing scenarios, eight or more parallel parity check units can be configured to increase multi-packet concurrent processing capabilities. Increasing the number of parallel parity check units will increase the consumption of register, combinational logic, and cyclic redundancy check (CRC) computing resources; therefore, a trade-off can be made based on throughput requirements and logic device resources.

[0040] By using the above implementation method, the minimum number of transmission cycles corresponding to the shortest Ethernet frame is used to uniformly describe the message input period under different data path widths, and the number of parallel verification calculation units is determined based on the input period and the cyclic redundancy check calculation delay. This avoids the limitation of applicability caused by configuring the number of parallel paths only for fixed data path widths, and makes the parallel computing resources match the message input rate.

[0041] In this embodiment, a polling scheduling counter is set to record the parallel parity calculation unit corresponding to the next Ethernet frame to be transmitted. The bit width of the polling scheduling counter can be set according to the number of parallel parity calculation units. When the number of parallel parity calculation units is 4, the polling scheduling counter can be a 2-bit counter, cycling between 0, 1, 2, and 3.

[0042] When the start-of-packet flag of the current Ethernet frame to be transmitted is detected, the current polling schedule counter value is read. Based on the current polling schedule counter value, a target check calculation unit is selected from multiple parallel check calculation units. For example, the first parallel check calculation unit is selected when the current polling schedule counter value is 0, the second parallel check calculation unit is selected when the current polling schedule counter value is 1, the third parallel check calculation unit is selected when the current polling schedule counter value is 2, and the fourth parallel check calculation unit is selected when the current polling schedule counter value is 3.

[0043] After selecting the target check unit, the allocation relationship between the current Ethernet frame to be transmitted and the target check unit is locked. Before detecting the end-of-frame marker of the current Ethernet frame to be transmitted, the parallel check unit is no longer switched based on the polling scheduler counter; instead, all data frames of the current Ethernet frame to be transmitted are continuously input into the target check unit. This avoids different data frames of the same Ethernet frame being assigned to different parallel check units.

[0044] In one implementation, a corresponding input validity indicator can be set for each parallel verification calculation unit. Multiple input validity indicators can constitute a set of parallel input validity indicators. When the current polling scheduler count points to one of the parallel verification calculation units, only the input validity indicator corresponding to that parallel verification calculation unit is set to valid, while the input validity indicators corresponding to other parallel verification calculation units remain invalid.

[0045] Upon receiving a start-of-message flag, the target check unit initializes the cumulative check status corresponding to the current Ethernet frame to be transmitted, and updates the cumulative check status step-by-step based on each subsequent frame of data. When an end-of-message flag is detected for the current Ethernet frame to be transmitted, the allocation relationship between the current Ethernet frame to be transmitted and the target check unit is released, and the polling schedule count is incremented by one. After the polling schedule count reaches the number of parallel check units, the initial count is returned to obtain the target check unit corresponding to the next Ethernet frame to be transmitted.

[0046] Taking four parallel verification calculation units as an example, the first to fourth Ethernet frames to be transmitted, which are input consecutively, are allocated to the first to fourth parallel verification calculation units respectively, while the fifth Ethernet frame to be transmitted is reassigned to the first parallel verification calculation unit. When each shortest Ethernet frame occupies two input data cycles, the first parallel verification calculation unit receives the fifth Ethernet frame to be transmitted only after eight clock cycles following the input of the first Ethernet frame to be transmitted.

[0047] When the reset signal is valid, the polling scheduler counter can be cleared, and the input validity indication and allocation lock status of each parallel verification calculation unit can be restored to their initial state. When the reset signal is invalid but the data validity flag is valid, the above message identification and polling allocation operations are performed.

[0048] By implementing the above methods, message-level allocation of Ethernet frames to be transmitted is performed using message start and message end markers as boundaries, and the corresponding parallel check calculation unit is locked during the processing of the same Ethernet frame to be transmitted. This ensures that the cumulative check status of the same Ethernet frame to be transmitted is continuously updated. At the same time, by using polling scheduling to increase the reuse interval of the same parallel check calculation unit, the possibility of check status crosstalk between consecutive messages is reduced.

[0049] like Figure 5 As shown, the parallel verification calculation unit may include a clock input terminal, a reset input terminal, a message data input terminal, a data validity input terminal, a message length input terminal, a message start flag input terminal, a message end flag input terminal, a cyclic redundancy check result output terminal, and a verification result validity indication output terminal.

[0050] In one specific implementation, the message data input terminal has a bit width of 384 bits and is used to receive the current message data; the message length input terminal has a bit width of 14 bits and is used to receive the message length of the Ethernet frame to be transmitted; the cyclic redundancy check result output terminal has a bit width of 32 bits and is used to output the CRC32 calculation result.

[0051] For the current frame's data, the number of valid bytes in the current frame's data is first determined based on the frame length information, the frame end marker, and the number of bytes transmitted per frame. For frames that are not the end of the frame, the number of valid bytes in the current frame is usually equal to the number of bytes transmitted per frame; for frames that are the end of the frame, the number of valid bytes in the last frame can be determined by taking the remainder of the total frame length divided by the number of bytes transmitted per frame, or by using the valid byte indicator field.

[0052] Based on the current number of valid bytes in the current frame, a target parallel computing width is selected from multiple preset parallel computing widths. The preset parallel computing width can include some or all of a width ranging from 1 byte to 48 bytes. Different target parallel computing widths can correspond to different parallel CRC32 status update functions. For example, when the current number of valid bytes in the current frame is 48 bytes, a 384-bit parallel CRC32 status update function can be called; when the current number of valid bytes in the current frame is 32 bytes, a 256-bit parallel CRC32 status update function can be called.

[0053] The parallel check calculation unit can first adjust the bit order within bytes of the current packet data according to the Ethernet CRC calculation specification, and then input the adjusted current packet data into the corresponding parallel CRC32 status update function. The byte order, bit order, initial check status, and output transformation method can be configured according to the adopted Ethernet communication specification.

[0054] When processing the first valid data frame of the Ethernet frame to be transmitted, a preset initial check state is obtained as the cumulative check state corresponding to the end of the previous valid data frame. For subsequent valid data frames, the cumulative check state saved after the processing of the previous valid data frame is obtained. According to the target parallel calculation width, the cyclic redundancy check state is updated based on the cumulative check state and the current frame data to obtain the updated check state corresponding to the end of the current frame data, and the updated check state is saved to the corresponding status register.

[0055] In one implementation, the number of bytes to be processed in the current frame can be indicated by the effective data length parameter, and the calculation delay corresponding to the end frame of the message can be tracked by a delay counter. When a message end flag is detected, the current message end event is recorded; after the preset calculation delay is completed for updating the verification status, a 32-bit cyclic redundancy check result is generated based on the final updated verification status, and the verification result validity indicator is set to valid.

[0056] When the number of bytes transmitted per frame is 48 and the cyclic redundancy check (CRC) calculation delay is 7 clock cycles, the delay threshold corresponding to the end frame of the message can be set to a count value that matches the number of hardware pipeline stages. Each parallel CRC calculation unit outputs the corresponding CRC result and a valid CRC result indication. Subsequently, based on the valid CRC result indication, the valid CRC result is written to the CRC result cache queue.

[0057] By implementing the above methods, the corresponding parallel computing width is selected based on the number of valid bytes in the current frame, and the current frame's verification status is updated using the cumulative verification status of the previous valid data frame. This can accurately handle situations where the number of valid bytes in the end frame of a message is insufficient to handle the number of bytes transmitted in a single frame, avoid invalid padding bytes from participating in CRC32 calculations, and adapt to Ethernet frames of different lengths and different data path widths.

[0058] In this embodiment, after the delayed message data passes through the input delay path, the message end flag and the number of valid bytes in the last frame are extracted at the preset delay level. Only when both the message end flag and the delay validity flag are valid is the FCS insertion mode judgment performed on the current delayed message data to avoid invalidating non-message end frames.

[0059] Let N be the number of bytes transmitted per clock cycle, and Q be the number of valid bytes in the last clock cycle. Then the number of remaining bytes R in the last clock cycle can be expressed as: R = NQ.

[0060] FCS typically occupies 4 bytes, so the default FCS byte count can be set to 4. Compare the remaining bytes R at the end of the last clock cycle with the default FCS byte count.

[0061] When R is greater than or equal to 4, it means that there is no less than 4 bytes of remaining space in the current message end timer, and a complete FCS can be inserted without increasing the data timer. At this time, the FCS insertion mode is determined to be the in-place insertion mode, and an insertion mode flag representing the in-place insertion mode is generated.

[0062] When R is less than 4, it indicates that the current message's last tick cannot accommodate the complete FCS, and an extended data tick is needed. In this case, the FCS insertion mode is determined to be the extended insertion mode, and an insertion mode flag representing the extended insertion mode is generated. The number of remaining bytes R in the last tick is determined as the number of bytes to fill the original last tick FCS, and 4-R is determined as the number of bytes to fill the extended tick FCS.

[0063] In the 48-byte / beat implementation, when the number of valid bytes in the last beat is no more than 44 bytes, the number of remaining bytes in the last beat is no less than 4 bytes, and the in-place insertion mode is adopted; when the number of valid bytes in the last beat is greater than 44 bytes, the number of remaining bytes in the last beat is less than 4 bytes, and the extended insertion mode is adopted.

[0064] For example, when the number of valid bytes in the last frame is 40, the number of bytes remaining in the last frame is 8, and the complete 4-byte FCS can be directly written into the original message's end frame. When the number of valid bytes in the last frame is 46, the number of bytes remaining in the last frame is 2, and the original message's end frame can only accommodate 2 bytes from the target FCS. The other 2 bytes from the target FCS need to be written into the extended data frame.

[0065] In the specific logic implementation, the insertion mode flag `add_pkt_flag` can be set. When the insertion mode flag is the first logical value, it indicates in-situ insertion mode; when the insertion mode flag is the second logical value, it indicates extended insertion mode. The insertion mode flag and the corresponding delayed message data are written together into the data buffer queue so that the FCS insertion output stage can identify the corresponding insertion method.

[0066] By implementing the above methods, the actual remaining space in the last frame of the message is calculated based on the number of valid bytes in the last frame, and an additional data frame is added only when the remaining space is insufficient. This avoids the bandwidth waste caused by using a fixed extension method for all Ethernet frames to be transmitted, and at the same time ensures that the target FCS is still fully inserted when the space in the last frame is insufficient.

[0067] In this embodiment, a data cache queue, a verification result cache queue, and a control information cache queue are set up. These three cache queues can be implemented using a synchronous first-in-first-out (FIFO) memory, and writing and reading are performed under the same clock domain. Each cache queue can output a queue full indicator, a queue empty indicator, an overflow indicator, and an underflow indicator to control data transmission based on the cache status.

[0068] The data buffer queue is used to store delayed message data and corresponding insertion mode flags in the order of data snapshots. In one specific implementation, the delayed message data is 400 bits, and the insertion mode flag is 1 bit; therefore, the storage width of the data buffer queue can be set to 401 bits. The write data to the data buffer queue is obtained by combining the insertion mode flag and the delayed message data.

[0069] When the delay validity flag is valid and the data buffer queue is not full, a data buffer write instruction is generated, and the buffered data is written to the data buffer queue. Each valid data frame of the Ethernet frame to be transmitted is written to the data buffer queue in the order of input, thereby maintaining the sequential relationship between data frames.

[0070] The verification result buffer queue is used to store cyclic redundancy check (CRC) results in message order. In one specific implementation, the CRC result is 32 bits, so the storage width of the verification result buffer queue can be set to 32 bits. When any parallel verification calculation unit outputs a valid CRC result, a verification result write instruction is generated according to the corresponding valid verification result indication, and the CRC result is written to the verification result buffer queue.

[0071] The control information buffer queue is used to store delayed control information in message order. When a start-of-message (FOM) flag of delayed message data is detected, the message length in the delayed control information is increased by a preset FCS byte number to obtain updated control information. When the preset FCS byte number is 4, the message length is increased by 4 bytes to ensure that the updated control information matches the Ethernet frame length after inserting the FCS.

[0072] In one implementation, the internal storage width of the control information buffer queue can be 56 bits to continue storing the FCS mode control flag for subsequent target FCS selection. After FCS insertion is complete, the FCS mode control flag can be removed from the updated control information, forming 55-bit output control information. The output control information may include a 14-bit payload length field, a signature validity flag, an 8-bit message type field, an 18-bit signature identifier field, and a 14-bit message length field with an additional 4 bytes.

[0073] The depths of the data cache queue, verification result cache queue, and control information cache queue can be set according to the maximum message length, the number of messages allowed to be cached, the cyclic redundancy check calculation latency, and the downstream output rate. The cache queues can be implemented using block storage resources in the logic device, and the storage resource type can be configured as block RAM, M10K, or M20K.

[0074] When any buffer queue is full, the writing of the corresponding information can be paused, and a backpressure indication can be sent upstream. In one implementation, to ensure the correspondence between the three types of information, when any buffer queue reaches a preset full threshold, the input of new Ethernet frames to be transmitted can be uniformly paused to avoid some information being successfully written while others fail to be written.

[0075] The three buffer queues establish a message correspondence through the order in which they are written. The data buffer queue stores data in batches, the control information buffer queue writes an updated control message at the time corresponding to the message start marker, and the checksum buffer queue writes a cyclic redundancy check result when the cyclic redundancy check result of the corresponding Ethernet frame to be transmitted is valid. As long as each buffer queue maintains a first-in, first-out (FIFO) order, the message correspondence between the three can be restored during output.

[0076] As an alternative implementation, the data cache queue and the verification result cache queue can be merged into a composite cache queue. The storage width of the composite cache queue can be set to 433 bits, including 401 bits of message cache data and 32 bits of cyclic redundancy check (CRC) result, and a result validity field can be added to indicate whether the current stored item carries a CRC result. The control information cache queue remains independently configured. Using a composite cache queue can reduce the number of cache instances, but it requires additional timing alignment and validity field control logic.

[0077] By implementing the above methods, setting up buffer queues according to the different generation frequencies of the three types of information, and establishing the correspondence between messages through first-in-first-out order and message boundaries, mismatches between cyclic redundancy check results, delayed message data, and delay control information can be avoided. At the same time, the empty / full detection and backpressure control of the buffer queues can reduce the possibility of data loss caused by buffer overflow or underflow.

[0078] In this embodiment, the delay control information includes an FCS mode control flag. The FCS mode control flag can be represented by a single bit. When the FCS mode control flag is a first logical value, it indicates that a correct FCS has been inserted; when the FCS mode control flag is a second logical value, it indicates that an incorrect FCS has been inserted. The FCS mode control flag is delayed synchronously with the Ethernet frame to be transmitted and is stored in the control information buffer queue to ensure that the target FCS type is consistent with the corresponding Ethernet frame to be transmitted.

[0079] After reading the updated control information from the control information cache queue, the FCS mode control flag is extracted, and the target FCS type is determined based on the FCS mode control flag.

[0080] When the target FCS type is the correct FCS type, the correct FCS is generated according to the cyclic redundancy check result output by the parallel check calculation unit, in accordance with the byte order and bit order required by the Ethernet FCS output, and the correct FCS is determined as the target FCS.

[0081] When the target FCS type is an incorrect FCS type, at least one bit in the cyclic redundancy check result is transformed according to the preset bit transformation rule to obtain the error check result. Then, according to the same output format as the correct FCS, the incorrect FCS is generated based on the error check result.

[0082] In one specific implementation, the preset bit transformation rule is to invert the bits of the 32-bit Cyclic Redundancy Check (CRC) result. When the FCS mode control flag indicates an incorrect FCS type, each bit of the CRC result is inverted to obtain the error check result.

[0083] In another implementation, a pseudo-random number generation module can be included. This module generates one or more flipped bit positions, randomly selects 1 to 3 bits from the cyclic redundancy check (CRC) result based on these positions, and flips the selected bits to obtain the error check result. By changing the pseudo-random number seed or the number of flipped bits, various different error FCSs can be generated to simulate different types of transmission errors.

[0084] After generating the target FCS, based on the packet order correspondence established by the three buffer queues, the target FCS is associated with the corresponding delayed packet data, updated control information, and FCS insertion mode to obtain the packet association data to be processed for FCS insertion. Subsequent insertion processing is only performed on target FCSs and delayed packet data with the same packet order.

[0085] Through the above implementation method, without changing the main message processing path, the correct FCS or incorrect FCS can be selected by using the FCS mode control flag. This can not only meet the requirements of normal high-speed Ethernet message transmission, but also actively construct Ethernet frames that cannot pass the receiver's verification, which can be used to verify the receiver's error identification, dropping, statistics or alarm functions.

[0086] In this embodiment, message cache data is read from the data cache queue, and the FCS insertion mode is determined based on the insertion mode flag in the message cache data. For data frames that do not carry a message end flag, the delayed message data is output with its original content intact. For data frames that carry a message end flag, the target FCS insertion is performed according to the FCS insertion mode.

[0087] When the FCS insertion mode is in-place insertion mode, the four bytes of the target FCS are sequentially written into the remaining bytes position of the last frame of the Ethernet frame to be transmitted, according to the preset FCS byte order, to obtain the message end frame after in-place insertion. The original message end flag remains valid, and the number of valid bytes in the last frame is updated to the sum of the original number of valid bytes in the last frame and 4.

[0088] For example, if the number of bytes transmitted per frame is 48, and the original number of valid bytes in the last frame is 40, a 4-byte target FCS can be written to the positions of bytes 41 to 44, and the updated number of valid bytes in the last frame can be set to 44 bytes. The remaining unused bytes are not output as valid message content.

[0089] When the FCS insertion mode is extended insertion mode, the first FCS field is determined from the target FCS based on the number of padding bytes in the original last FCS, and written into the remaining byte position of the original message end frame to form the modified original message end frame. Subsequently, the message end flag carried by the modified original message end frame is cleared, so that the modified original message end frame no longer indicates the end of the Ethernet frame to be transmitted.

[0090] Based on the number of bytes padded to the extended data frame's FCS, the second FCS field is determined from the target FCS, and the extended data frame is constructed based on the second FCS field. The number of valid bytes in the extended data frame is set to the number of bytes padded to the extended data frame's FCS. The end-of-message flag of the extended data frame is set to valid, while the start-of-message flag remains invalid.

[0091] For example, if the number of bytes transmitted in a single frame is 48, and the number of valid bytes in the original last frame is 46, the number of padding bytes for the original last frame's FCS is 2, and the number of padding bytes for the extended frame's FCS is 2. The first 2 bytes of the target FCS are written to the 47th and 48th bytes of the original message's end frame, the last 2 bytes of the target FCS are written to the extended data frame, and the number of valid bytes in the last frame of the extended data frame is set to 2.

[0092] By sequentially outputting the modified original message end frame and extended data frame, the Ethernet frame after extended insertion into the target FCS can be obtained. The message length in the updated control information is uniformly increased by 4 bytes. Regardless of whether in-place insertion mode or extended insertion mode is used, the output message length is consistent with the actual length after insertion into the target FCS.

[0093] In practical implementations, the number of valid bytes in the last frame can be converted into the corresponding number of free bytes or a byte mask based on the definition of the free byte indicator field in the sending interface. As long as this field can accurately represent the range of valid message content in the current data frame, it can be used by the receiving end to identify valid data.

[0094] Through the above implementation method, when there is sufficient space at the end of the last frame, the complete target FCS can be directly inserted using the end frame of the original message. When there is insufficient space at the end of the last frame, the target FCS is continuously filled across the end frame of the original message and the extended data frame. This ensures that the target FCS is completely inserted under different message lengths, and only adds a data frame when necessary, reducing unnecessary transmission overhead.

[0095] In this embodiment, the data buffer queue, the verification result buffer queue, and the control information buffer queue are respectively configured with a write enable signal, a read enable signal, write data, read data, a queue full indicator, and a queue empty indicator. The write data of the data buffer queue may include delayed message data and an insertion mode flag; the write data of the verification result buffer queue is the cyclic redundancy check result; and the write data of the control information buffer queue is the updated control information.

[0096] The input delay path can output multi-level delay signals. For example, with an input delay period of 8 clock cycles, it can generate eight levels of delayed message data, eight levels of delay control information, and eight levels of delay validity flags. Insertion mode determination can be performed at one of the preset delay levels, and the resulting insertion mode flag is combined with the delayed message data of the final delay level and written into the data buffer queue.

[0097] The parallel verification calculation module can output multiple cyclic redundancy check (CRC) results and corresponding multiple valid verification result indicators. When any valid verification result indicator is valid, the corresponding valid result is selected from the multiple CRC results and written to the verification result cache queue.

[0098] At the start of output scheduling, it checks whether the data buffer queue is empty and whether a pause read flag exists. If the data buffer queue is not empty and is not in a pause read state, a data read enable signal is generated, and message buffer data is read from the data buffer queue.

[0099] When the read packet buffer data carries a packet start flag, a control information read enable signal is generated, and the updated control information corresponding to the current Ethernet frame to be transmitted is read from the control information buffer queue. Since the control information is written in packet start order, one piece of control information is read for each detected packet start flag, thus maintaining the correspondence between the control information and the Ethernet frame to be transmitted.

[0100] When the read packet buffer data carries a packet end marker, a check result read enable signal is generated, and the cyclic redundancy check (CRC) result corresponding to the current Ethernet frame to be transmitted is read from the check result buffer queue. Since the CRC results are written in the packet completion order, reading one CRC result for each detected packet end marker ensures that the CRC results correspond to the Ethernet frames to be transmitted.

[0101] In one implementation, a data read enable delay register, a level 1 message data register, a level 2 message data register, a control information register, a target FCS register, and a target FCS delay register can be configured. The read data and control information are registered over one or more clock cycles to accommodate the read latency of the buffer queue and the processing latency of the FCS insertion combinational logic.

[0102] Based on the FCS mode control flag in the updated control information, a target FCS is generated from the cyclic redundancy check result and stored in the target FCS register. The target FCS can also be delayed by a preset number of levels to align with the end-of-message frame of the message entering the FCS insertion position.

[0103] When the read insertion mode flag indicates an extended insertion mode, a pause read flag is generated. While the pause read flag is active, subsequent reads from the data buffer queue are paused, reserving one or more clock cycles for the construction and output of the extended data phase. The pause read flag can be further delayed to obtain a pause read delay flag, used to coordinate the output of the extended data phase and the resumption of reads.

[0104] In a specific timing sequence, after completing eight levels of input delay and buffer writing, the data buffer queue is read in the first output read cycle, and the control information buffer queue is read synchronously at the start of the message, and the verification result buffer queue is read synchronously at the end of the message. In the next clock cycle, the read data is registered, and it is determined whether to generate a pause read flag according to the insertion mode flag. At the same time, the target FCS is determined according to the FCS mode control flag. In the following one or two clock cycles, the original message end-of-message is modified and the extended data is output.

[0105] After the extended data frame output is complete, the pause read flag is cleared, and the data buffer queue read resumes, allowing the next Ethernet frame to be transmitted or subsequent packet data to continue output in the original order. The valid data output indicator is output synchronously with the packet data inserted into the target FCS.

[0106] In one specific implementation, the internal control signals may include input delay signals, polling schedule counter values, input validity indicators for each parallel verification calculation unit, insertion mode flags, cyclic redundancy check (CRC) results and CRC result validity indicators for each parallel verification calculation unit, write enable signals for each buffer queue, read enable signals, queue full indicators, queue empty indicators, pause read flags, pause read delay flags, data read enable delay signals, level 1 message data, level 2 message data, level 1 control information, target FCS, and delayed target FCS. These control signals collectively perform input delay, CRC result selection, buffer queue read / write, message boundary identification, and FCS insertion / output.

[0107] Through the above implementation method, the control information reading is triggered by the message start flag, the cyclic redundancy check result reading is triggered by the message end flag, and the subsequent reading of the data buffer queue is paused during the extended insertion. This can coordinate the delayed message data stored by data tick with the cyclic redundancy check result and the updated control information stored by message, ensuring that the target FCS inserts the corresponding Ethernet frame to be transmitted, and preventing the next Ethernet frame to be transmitted from entering the output path before the extended data tick output is completed.

[0108] In this embodiment, as Figure 3 and Figure 4As shown, a dynamic FCS insertion device for high-speed Ethernet frames is provided. The device includes a parameter adaptation module, an input delay module, a parallel verification calculation module, a dynamic insertion judgment module, a multi-buffer scheduling module, and an FCS insertion output module.

[0109] The device can be configured with a single-pass byte count input terminal, a clock input terminal, a reset input terminal, a data valid input terminal, a message data input terminal, a control information input terminal, a data valid output terminal, a message data output terminal, and a control information output terminal.

[0110] The single-cycle byte count input is used to receive the number of bytes transmitted in each clock cycle of the data path; its bit width can be set to 11 bits. The message data input is used to receive Ethernet frames of type TX_DATA to be transmitted. The control information input is used to receive control information of type TX_INFO_FCS. The data valid output is used to output whether the Ethernet frame after insertion into the target FCS is valid. The message data output is used to output Ethernet frames of type TX_DATA. The control information output is used to output updated control information of type TX_INFO.

[0111] The parameter adaptation module is connected to both the single-pass byte count input terminal and the preset parameter storage unit. Based on the single-pass byte count, the preset minimum effective data length, and the cyclic redundancy check (CRC) calculation delay, the parameter adaptation module determines the number of parallel verification calculation units and the input delay period. It then sends the number of parallel verification calculation units to the parallel verification calculation module and the input delay period to the input delay module.

[0112] The input delay module includes a number of register levels corresponding to the input delay period. The input delay module simultaneously receives the Ethernet frame to be transmitted, control information, and a data validity flag, and synchronizes and delays these three components under the drive of a clock signal. When the input delay period is 8 clock cycles, the input delay module may include an eight-level message data register, an eight-level control information register, and an eight-level data validity register.

[0113] Figure 3 In the hardware architecture shown, the part where the latency length changes with the cyclic redundancy check calculation latency or the packet width can be set as a variable latency processing part, while the pipeline stages required for cache reading, registering, and FCS insertion can be set as a fixed latency processing part.

[0114] The parallel verification calculation module comprises multiple parallel verification calculation units with identical structures. The structure of each parallel verification calculation unit can adopt... Figure 4 The structure is shown. The parallel verification calculation module also includes a polling scheduler counter and input selection logic. The input selection logic allocates each Ethernet frame to be transmitted to the corresponding parallel verification calculation unit according to the polling scheduler counter value.

[0115] In the implementation of 100G Ethernet with 48 bytes / frame transmission and a cyclic redundancy check (CRC) calculation delay of 7 clock cycles, the parallel CRC calculation module includes four parallel CRC calculation units, a 2-bit polling scheduler, and an input delay module with eight register levels. Each parallel CRC calculation unit supports parallel CRC32 status updates ranging from 1 byte to 48 bytes.

[0116] The dynamic insertion judgment module is connected to the preset delay level of the input delay module. When the delayed message data carries the message end flag, it determines the number of remaining bytes in the last frame based on the number of valid bytes in the last frame and the number of bytes transmitted in a single frame, and generates an insertion mode flag based on the comparison result between the number of remaining bytes in the last frame and the preset FCS byte number.

[0117] The multi-buffer scheduling module includes a data buffer queue, a verification result buffer queue, and a control information buffer queue. The data buffer queue is connected to the input delay module and the dynamic insertion judgment module, respectively, and is used to store delayed message data and corresponding insertion mode flags; the verification result buffer queue is connected to the parallel verification calculation module and is used to store cyclic redundancy check results; the control information buffer queue is connected to the input delay module and is used to store delay control information after updating the message length.

[0118] The FCS insertion / output module is connected to the data buffer queue, the verification result buffer queue, and the control information buffer queue, respectively. The FCS insertion / output module reads the updated control information according to the message start flag, reads the cyclic redundancy check result according to the message end flag, generates the target FCS according to the FCS mode control flag, and performs in-situ insertion or extended insertion according to the insertion mode flag.

[0119] When the FCS mode control flag indicates an erroneous FCS, the FCS insertion output module can invert the cyclic redundancy check (CRC) result bit by bit using inversion logic. The FCS insertion output module can also be connected to a pseudo-random number generation module, which can then flip some bits in the CRC result based on the flip bit positions provided by the pseudo-random number generation module.

[0120] When the insert mode flag indicates extended insert mode, the FCS insert output module outputs a pause read control signal to the multi-buffer scheduling module, causing the data buffer queue to pause reading and resume reading after the extended data frame is output. This prevents subsequent Ethernet frames to be transmitted from overwriting the extended data frame.

[0121] Each buffer queue in the device can be implemented using field-programmable gate array (FPGA) memory resources from different manufacturers, and can be configured as block RAM, M10K, or M20K depending on the target device. The depth, full threshold, empty threshold, and warning threshold of the buffer queue can be configured according to the maximum message length and the number of consecutive messages.

[0122] This device is compatible with 10G, 100G, 400G, or other high-speed Ethernet data paths. For different single-pass byte counts and different cyclic redundancy check pipeline stages, the number of parallel check calculation units and input delay period can be redefined through the parameter adaptation module without changing the basic processing relationships of dynamic insertion judgment, multi-buffer scheduling, and FCS insertion output.

[0123] As an alternative implementation, the parallel verification calculation module may include eight parallel verification calculation units to adapt to higher message concurrency rates; as another alternative implementation, the data cache queue and the verification result cache queue may be merged into a composite cache queue; as yet another alternative implementation, various error verification result generation rules may be set in the FCS insertion output module to simulate different error types.

[0124] Through the above implementation method, parameter adaptation, input delay, parallel check calculation, dynamic insertion judgment, multi-buffer synchronization scheduling, and FCS insertion output are integrated into the same hardware device. It can adaptively configure calculation and delay resources according to the parallel width of the high-speed Ethernet data path and the cyclic redundancy check calculation delay, and ensure that the message data, cyclic redundancy check results and control information are accurately matched in the output stage, thereby improving the reliability of high-speed continuous message processing and the adaptability of FCS insertion with different frame lengths.

Claims

1. A method for dynamic FCS insertion of high-speed Ethernet frames, characterized in that, The method includes: The system acquires the Ethernet frame to be transmitted and the corresponding control information, and determines the number of parallel verification calculation units and the input delay period based on the number of bytes transmitted per cycle, the preset minimum effective data length, and the cyclic redundancy check calculation delay. The Ethernet frames to be transmitted and the control information are synchronized and delayed according to the input delay period to obtain delayed message data and delayed control information. Based on the message boundary of the Ethernet frames to be transmitted, multiple consecutively input Ethernet frames to be transmitted are distributed to multiple parallel verification calculation units in a frame-by-frame polling manner to calculate the cyclic redundancy check result corresponding to each Ethernet frame to be transmitted. The time interval between two consecutive receptions of Ethernet frames to be transmitted by the same parallel verification calculation unit is not less than the sum of the cyclic redundancy check calculation delay and one clock cycle. The delayed message data and the corresponding cyclic redundancy check result satisfy a preset timing alignment relationship. Based on the number of valid bytes at the end of the delayed message data and the number of bytes transmitted per single frame, the FCS insertion mode corresponding to the Ethernet frame to be transmitted is determined. The FCS insertion mode includes in-place insertion mode and extended insertion mode. The delayed message data, the cyclic redundancy check result, and the delay control information are cached respectively, and the cached delayed message data, cyclic redundancy check result, and delay control information are synchronized and scheduled based on the message start flag and message end flag of the delayed message data. The target FCS is determined based on the delay control information. The target FCS is either a correct FCS obtained based on the cyclic redundancy check result or an incorrect FCS generated based on the cyclic redundancy check result. The target FCS is then inserted into the end of the Ethernet frame to be transmitted according to the FCS insertion mode, and the Ethernet frame after inserting the target FCS is output.

2. The method according to claim 1, characterized in that, The process of determining the number of parallel verification calculation units and the input delay period based on the number of bytes transmitted per cycle, the preset minimum effective data length, and the cyclic redundancy check calculation delay includes: Obtain the preset minimum effective data length S, the number of bytes transmitted per cycle N, and the cyclic redundancy check calculation delay M; Based on the preset minimum effective data length S and the number of bytes transmitted per frame N, the minimum number of transmission frames P corresponding to the shortest Ethernet frame is determined. The minimum number of transmission frames P is a positive integer obtained by rounding up the ratio of S to N. Based on the cyclic redundancy check calculation delay M and the minimum number of transmission cycles P, determine the smallest positive integer K that satisfies K×P≥M+1, and determine the smallest positive integer K as the number of parallel check calculation units; M+1 is defined as the input delay period L; Configure the parallel verification calculation path according to the number K of the parallel verification calculation units, and configure the input delay path according to the input delay period L.

3. The method according to claim 1, characterized in that, The step of allocating multiple consecutively input Ethernet frames to be transmitted to multiple parallel verification calculation units in a frame-by-frame polling manner according to the message boundaries of the Ethernet frames to be transmitted includes: Detect the start flag of the current Ethernet frame to be transmitted, and when the start flag is detected, obtain the current polling schedule count value; Based on the current polling schedule count value, the target verification calculation unit corresponding to the current Ethernet frame to be transmitted is determined from among the multiple parallel verification calculation units, and the allocation relationship between the current Ethernet frame to be transmitted and the target verification calculation unit is locked. According to the allocation relationship, the data of each frame of the current Ethernet frame to be transmitted, from the start of the message to the corresponding end of the message, is continuously input into the target verification calculation unit to obtain the cumulative verification status corresponding to the current Ethernet frame to be transmitted. When the end-of-message flag of the current Ethernet frame to be transmitted is detected, the allocation relationship is released, and the current polling schedule count value is updated cyclically according to the number of parallel verification calculation units to obtain the polling schedule count value corresponding to the next Ethernet frame to be transmitted.

4. The method according to claim 1, characterized in that, The calculation of the cyclic redundancy check result for each Ethernet frame to be transmitted includes: The number of valid bytes in the current packet data is determined based on the packet length information, packet end flag, and number of bytes transmitted per packet corresponding to the current packet data. Based on the effective number of bytes, a target parallel computing width that matches the effective number of bytes is determined from a plurality of preset parallel computing widths; Obtain the cumulative check status of the Ethernet frame to be transmitted at the end of the previous valid data frame; According to the target parallel calculation width, the cyclic redundancy check status is updated based on the cumulative check status and the current captured message data to obtain the updated check status corresponding to the end of the current captured message data. When the end-of-message flag of the Ethernet frame to be transmitted is detected, and the update verification state completes the preset calculation delay, the cyclic redundancy check result corresponding to the Ethernet frame to be transmitted is determined according to the update verification state, and the cyclic redundancy check result and the corresponding verification result validity indication are output.

5. The method according to claim 1, characterized in that, The step of determining the FCS insertion mode corresponding to the Ethernet frame to be transmitted based on the number of valid bytes at the end of the delayed message data and the number of bytes transmitted per single frame includes: The number of remaining bytes in the last frame of the delayed message data is determined based on the number of bytes transmitted in a single frame and the number of valid bytes in the last frame. The remaining bytes at the last clock cycle are compared with the preset FCS byte count to obtain the remaining space comparison result; When the remaining space comparison result indicates that the number of remaining bytes in the last frame is greater than or equal to the preset FCS byte number, the FCS insertion mode is determined to be the in-place insertion mode; When the remaining space comparison result indicates that the number of remaining bytes in the last frame is less than the preset FCS byte number, the FCS insertion mode is determined to be the extended insertion mode, the number of remaining bytes in the last frame is determined to be the original last frame FCS fill byte number, and the difference between the preset FCS byte number and the original last frame FCS fill byte number is determined to be the extended frame FCS fill byte number.

6. The method according to claim 1, characterized in that, The step of respectively caching the delayed message data, the cyclic redundancy check result, and the delay control information includes: Obtain the empty / full status of the data cache queue, the verification result cache queue, and the control information cache queue, and determine the corresponding cache write permission status based on the empty / full status; The insertion mode flag corresponding to the FCS insertion mode is combined with the delayed message data to obtain message buffer data. When the data buffer queue is in the write-allowed state, the message buffer data is written into the data buffer queue in the order of data steps. When any of the parallel verification calculation units outputs the cyclic redundancy check result corresponding to the Ethernet frame to be transmitted, a verification result write instruction is generated, and when the verification result cache queue is in the write-allowed state, the cyclic redundancy check result is written into the verification result cache queue according to the verification result write instruction. When the packet start flag of the delayed packet data is detected, the packet length in the delayed control information is updated according to the preset FCS byte number to obtain the updated control information. When the control information cache queue is in the write-allowed state, the updated control information is written to the control information cache queue. Based on the writing order of the message cache data, the cyclic redundancy check result, and the updated control information, a message order correspondence is established among the three.

7. The method according to claim 1, characterized in that, Determining the target FCS based on the delay control information includes: Extract the FCS mode control flag from the delay control information, and determine the target FCS type based on the FCS mode control flag; When the target FCS type is a correct FCS type, the correct FCS is generated based on the cyclic redundancy check result, and the correct FCS is determined as the target FCS; When the target FCS type is an erroneous FCS type, at least one bit in the cyclic redundancy check result is transformed according to a preset bit transformation rule to obtain an error check result, and the erroneous FCS is generated based on the error check result, and the erroneous FCS is determined as the target FCS; The target FCS is associated with the corresponding delayed message data and FCS insertion mode to obtain message association data for which FCS insertion processing is to be performed.

8. The method according to claim 5, characterized in that, The step of inserting the target FCS into the tail of the Ethernet frame to be transmitted according to the FCS insertion mode includes: When the FCS insertion mode is the in-place insertion mode, the target FCS is written into the remaining byte position of the last frame of the Ethernet frame to be transmitted according to the preset FCS byte order to obtain the message end frame after in-place insertion, and the effective byte indication of the message end frame is updated according to the preset FCS byte number. When the FCS insertion mode is the extended insertion mode, the first FCS field is determined from the target FCS according to the original last FCS padding byte number, and the first FCS field is written into the last remaining byte position of the Ethernet frame to be transmitted according to the preset FCS byte order to obtain the modified original message end frame. Remove the message end marker carried by the original message end marker after modification; Based on the number of bytes filled in the extended FCS, the second FCS field is determined from the target FCS, and an extended data frame is generated based on the second FCS field. The effective number of bytes in the extended data frame is set to the number of bytes filled in the extended FCS, and the message end flag of the extended data frame is set. The modified original message end frame and the extended data frame are output sequentially to obtain the Ethernet frame after being extended and inserted into the target FCS.

9. The method according to claim 6, characterized in that, The synchronization and scheduling of cached delayed message data, cyclic redundancy check results, and delay control information based on the message start and message end flags of the delayed message data includes: When the data buffer queue is not empty and is not in a paused read state, a data read enable signal is generated, and the message buffer data is read from the data buffer queue according to the data read enable signal; When the read message cache data carries a message start flag, a control information read enable signal is generated, and the updated control information corresponding to the message cache data is read from the control information cache queue according to the control information read enable signal. When the read message cache data carries a message end marker, a verification result read enable signal is generated, and the cyclic redundancy check result corresponding to the message cache data is read from the verification result cache queue according to the verification result read enable signal. When the read insertion mode flag indicates that the FCS insertion mode is an extended insertion mode, a pause read flag is generated, and subsequent reading of the data cache queue is paused according to the pause read flag; After the extended data output is completed, the pause reading flag is cleared, the reading of the data buffer queue is resumed, and the message buffer data, cyclic redundancy check results, and updated control information are obtained by synchronously outputting the message buffer data, cyclic redundancy check results, and updated control information according to the message order correspondence.

10. A dynamic FCS insertion device for high-speed Ethernet frames, characterized in that, The device includes: The parameter adaptation module is used to obtain the number of bytes transmitted per cycle, the preset minimum effective data length, and the cyclic redundancy check calculation delay, and to determine the number of parallel verification calculation units and the input delay period based on the number of bytes transmitted per cycle, the preset minimum effective data length, and the cyclic redundancy check calculation delay. The input delay module is used to synchronously delay the Ethernet frame to be transmitted, the control information and data validity flag corresponding to the Ethernet frame to be transmitted, according to the input delay period, so as to obtain delayed message data, delayed control information and delayed validity flag. The parallel verification calculation module includes multiple parallel verification calculation units, which are used to distribute multiple consecutively input Ethernet frames to be transmitted to multiple parallel verification calculation units in a frame-by-frame polling manner according to the message boundary of the Ethernet frames to be transmitted, and calculate the corresponding cyclic redundancy check result according to the number of effective bytes of each Ethernet frame to be transmitted. The time interval between two consecutive receptions of Ethernet frames to be transmitted by the same parallel verification calculation unit is not less than the sum of the cyclic redundancy check calculation delay and one clock cycle. The dynamic insertion judgment module is used to determine the FCS insertion mode based on the number of valid bytes at the end of the delayed message data and the number of bytes transmitted per single frame. The FCS insertion mode includes in-place insertion mode and extended insertion mode. The multi-buffer scheduling module includes a data buffer queue, a verification result buffer queue, and a control information buffer queue. The data buffer queue is used to buffer the delayed message data and the corresponding insertion mode flag. The verification result buffer queue is used to buffer the cyclic redundancy check result. The control information buffer queue is used to buffer the delay control information after updating the message length. The multi-buffer scheduling module is also used to synchronously schedule the delayed message data, the cyclic redundancy check result, and the delay control information based on the message start flag and message end flag of the delayed message data. The FCS insertion output module is used to determine the correct FCS or incorrect FCS as the target FCS based on the FCS mode control flag in the delay control information. When the FCS insertion mode is in-place insertion mode, the target FCS is inserted into the remaining byte position of the last frame of the Ethernet frame to be transmitted. When the FCS insertion mode is extended insertion mode, the target FCS is inserted into the original message end frame and the newly added extended data frame of the Ethernet frame to be transmitted, respectively, and the Ethernet frame after inserting the target FCS is output.

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