Cyclic redundancy check hardware acceleration method and system based on programmable logic

Abstract

The application relates to the technical field of data communication error detection, in particular to a cyclic redundancy check hardware acceleration method and system based on programmable logic; the method comprises the following steps: oversampling differential serial bus differential signals according to multiple different clock phases in a programmable logic device to obtain multiple candidate bit streams; performing quality preliminary selection on the basis of statistical distribution characteristics of signal jump edges and selection weights of the sampling phases to determine candidate bit streams to be checked in a current frame; performing remainder operation of cyclic redundancy check on the candidate bit streams, determining whether the check is passed according to the result, and accumulating multiple frame passing results according to the sampling phases to obtain check reliability of the sampling phases; and taking the check reliability as a feedback quantity to correct the selection weights of the sampling phases in subsequent frames, so that the sampling phase selection and the cyclic redundancy check form a closed loop iteration. According to the application, the sampling time can be maintained in a bit stable interval with the change of bus timing, and the proportion of failed checks can be significantly reduced.

Description

Technical Field

[0001] This application relates to the field of data communication error detection technology, specifically to a hardware acceleration method and system for cyclic redundancy check based on programmable logic. Background Technology

[0002] Existing differential serial bus receivers typically, after determining the baud rate, take a fixed sampling time within each bit according to the bit period, extract the single-ended level value from the differential signal conversion, assemble the bit-by-bit values ​​into a frame, and then perform cyclic redundancy check (CRC) on the frame according to an agreed generator polynomial. The CRC result is used to determine whether the frame has been corrupted during transmission. However, in actual industrial operation, RS-485 bus receivers using fixed sampling times frequently report CRC failures even without obvious line faults, and these failures are intermittent and difficult to reproduce reliably.

[0003] For example, on a 485 link tens of meters long, field instruments periodically report data to the controller. Initially, the pass rate for verification was normal. However, when a nearby frequency converter started and the cable temperature rose, the controller began intermittently reporting failed cyclic redundancy checks. A thorough inspection of the cables and connectors revealed no poor contact or breaks, and replacing the transceiver chip did not significantly improve the situation. As another example, in a workshop, the 485 bus collected the same batch of sensor data in the early morning and afternoon. Verification was almost error-free in the early morning, but in the afternoon, as the ambient temperature rose, the number of frames failing verification with the same equipment and wiring increased significantly. The data returned to normal by evening after the temperature dropped.

[0004] If this problem is not effectively resolved, the differential serial bus receiver will misinterpret a large number of frames that could have been received correctly as failing verification and trigger retransmissions, consuming bus bandwidth and increasing communication latency. In industrial control applications with high real-time requirements, this can also cause data update delays. When troubleshooting, on-site maintenance personnel will find it difficult to pinpoint the true location of the increased verification failure rate because the cables and devices themselves are not faulty. They can only repeatedly retry or conservatively shorten the wiring distance. Therefore, it is necessary to solve the problem that the proportion of cyclic redundancy check failures increases with changing operating conditions at the differential serial bus receiver under conditions of coexisting interference sources and long-distance wiring, and cannot be eliminated by simply checking the cables and devices.

[0005] In view of this, this application proposes a hardware acceleration method and system for cyclic redundancy check based on programmable logic. Summary of the Invention

[0006] To achieve the above objectives, this application provides a hardware acceleration method and system for cyclic redundancy check based on programmable logic, the specific technical solution of which is as follows:

[0007] In a first aspect, this application provides a hardware acceleration method for cyclic redundancy check based on programmable logic, including:

[0008] In a programmable logic device, the differential signal of the differential serial bus is oversampled at multiple different clock phases to obtain multiple candidate bit streams corresponding to each sampling phase.

[0009] A sampling phase quality assessment strategy is constructed. Based on the statistical distribution characteristics of signal transition edges in each candidate bitstream and the selection weight of each sampling phase, the quality of multiple candidate bitstreams is initially selected to determine the candidate bitstream to be checked in the current frame.

[0010] Within the programmable logic device, a remainder operation for cyclic redundancy check is performed on the determined candidate bit stream. The result of the remainder operation is used to determine whether the check passes. The check pass results of multiple frames are accumulated according to the sampling phase to obtain the check reliability of each sampling phase.

[0011] A phase feedback tuning strategy is constructed, using the verification reliability of each sampled phase as the feedback quantity to correct the selection weight of each sampled phase in subsequent frames, so that the sampling phase selection stage and the cyclic redundancy check stage form a closed loop iteration.

[0012] Preferably, the oversampling according to multiple different clock phases includes:

[0013] The phase-locked loop configured inside the programmable logic device multiplies the reference clock to generate multiple sampling clocks. The multiple sampling clocks have the same frequency and their phases are staggered sequentially. The phase difference between two adjacent sampling clocks is fixed, and the phase stagger is evenly divided according to the bit period.

[0014] The single-ended received data signal output by the transceiver is fed in parallel into a group of sampling flip-flops driven by multiple sampling clocks. Each sampling clock samples the received data signal once on its own effective edge.

[0015] The sampling results are shifted into their respective shift registers in bit order. The bit timer and counter advance according to the baud rate after detecting the falling edge of the start bit, defining the boundary of each bit and completing the byte boundary alignment.

[0016] Preferably, the statistical distribution characteristics of signal transition edges in each candidate bitstream include:

[0017] The extraction of the transition edge is accomplished by XORing adjacent sample values. Different levels at two adjacent sampling times are marked as a transition edge.

[0018] Isolated transitions that last only a single sampling moment and have the same level before and after are discarded, while transition edges with different levels before and after are retained;

[0019] A bit period is divided into multiple time intervals along the time axis corresponding to the sampling phase. The number of times the transition edge falls into each time interval is counted bit by bit to obtain the transition edge distribution histogram of the current frame. The transition edge distribution histogram is reset at the beginning of each frame.

[0020] Preferably, after obtaining the histogram of the transition edges of the current frame, the method further includes:

[0021] The time interval with the largest number of jump edges in the jump edge distribution histogram is taken as the position of the jump edge concentration area, and the position of the jump edge concentration area is marked as the center of the jump edge aggregation within the bit period;

[0022] The sampling phase quality is evaluated based on the ring distance from each sampling phase to the position of the transition concentration area. The ring distance is determined by the ring metric of connecting the beginning and end of the bit period.

[0023] The maximum possible value of the ring distance is determined by half of the total number of sampled phases, and the ring distance is then normalized.

[0024] Preferably, the initial quality selection of the multiple candidate bitstreams includes:

[0025] Based on the normalized ring distance and the selection weight of each sampling phase, the quality score of each sampling phase is obtained by weighting it according to two complementary ratio coefficients. The selection weight represents the reliability of each sampling phase accumulated from previous frames.

[0026] The initial quality selection is implemented in the programmable logic device using a parallel comparison tree. The quality scores of each sampling phase are compared pairwise, and the sampling phase with the highest quality score is selected step by step.

[0027] The candidate bitstream corresponding to the sampling phase with the highest quality score is determined as the candidate bitstream to be checked in the current frame. When the quality scores are equal, the one with the smaller phase number is selected first.

[0028] Preferably, the remainder operation for performing cyclic redundancy check on the determined candidate bitstream includes:

[0029] The frame bit sequence carried by the determined candidate bit stream is regarded as the coefficient of a polynomial. Modulo 2 polynomial division is performed according to the set generator polynomial to obtain the remainder operation result.

[0030] Modulo-2 polynomial division is based on a linear feedback shift register, whose initial preset value is all 1s.

[0031] The result of the remainder operation is compared with a fixed value. If the result of the remainder operation is equal to the fixed value, the current frame is considered to have passed the verification. If the result of the remainder operation is not equal to the fixed value, the current frame is considered to have failed the verification. The fixed value is determined by the generator polynomial and the initial preset value.

[0032] Preferably, the linear feedback shift register includes:

[0033] The state transition of a single bit processed by a linear feedback shift register is denoted as a linear transformation. Multiple linear transformations that process multiple bits are combined into a fixed XOR relationship between the current register state and the input byte, and implemented as a byte-parallel XOR network.

[0034] After the byte-parallel XOR network, a register level is set up to divide the remainder operation into a pipeline, so that a new byte is received each clock tick;

[0035] The remainder operation does not use a serial structure with bit-by-bit shifting, but is expanded into combinational logic in parallel by bytes, processing one byte per clock cycle.

[0036] Preferably, the verification pass results accumulated across multiple frames according to the sampling phase include:

[0037] The verification result of the current frame is attributed to the sampling phase of the candidate bit stream determined for the current frame;

[0038] Two counters are maintained for each sampling phase. The first counter records the number of frames in the cumulative window that have a candidate bit stream provided by the corresponding sampling phase and have participated in the verification. The second counter records the number of frames that have a candidate bit stream provided by the corresponding sampling phase and have passed the verification.

[0039] After the statistics are completed within the cumulative window of a preset length, the ratio of the number of frames that pass the verification to the number of frames that participate in the verification is used as the verification reliability of the corresponding sampling phase. For sampling phases where the number of frames participating in the verification is lower than the minimum number of participating frames, the verification reliability of the previous window is used.

[0040] Preferably, the selection weights for each sampling phase in subsequent frames, as described in the feedback correction, include:

[0041] Calculate the average reliability of each sampling phase involved in the comparison. The sampling phase involved in the comparison is the sampling phase where the number of frames involved in the verification reaches the minimum number of participating frames.

[0042] For the sampling phases involved in the comparison, the selection weight of each sampling phase is updated based on the deviation between the verification reliability of each sampling phase and the average value. The selection weight of the sampling phases not involved in the comparison remains unchanged.

[0043] The correction magnitude for weight updates is controlled by the feedback tuning coefficient, and the deviation between the verification reliability and the average value is tuned by an arithmetic right shift.

[0044] Preferably, the selection weight update includes:

[0045] The updated selection weights are limited to a set range of values.

[0046] Set a lower limit for the selection weight of each sampling phase. When the selection weight of a sampling phase is lower than the lower limit after the update, raise the selection weight of the corresponding sampling phase back to the lower limit.

[0047] The lower limit of the weight is determined according to the set proportion of the uniformly distributed weight;

[0048] The selection weights are normalized after limiting the amplitude of all sampled phases and setting the lower limit of the selection weights, so that the sum of the selection weights of each sampled phase is restored to a constant value. The normalized selection weights are then written back to the selection weight register group.

[0049] Preferably, the closed-loop iteration of the sampling phase selection stage and the cyclic redundancy check stage includes:

[0050] The selection weights are updated once at the boundary of the cumulative window, while the selection weights of each sampling phase within the cumulative window remain unchanged.

[0051] The updated selection weights for each sampling phase are read in the next cumulative window and used in the quality score calculation. The candidate bitstreams for subsequent frames are determined based on the quality score. The candidate bitstreams are subjected to cyclic redundancy check to generate a new check reliability. The new check reliability drives the selection weights to be updated again.

[0052] When a programmable logic device is powered on, the selection weights of each sampling phase are reset to equal initial values.

[0053] Secondly, this application also provides a programmable logic-based cyclic redundancy check hardware acceleration system, which is used to implement the programmable logic-based cyclic redundancy check hardware acceleration method, including: an oversampling module, a quality initial selection module, a check operation module, and a feedback tuning module.

[0054] The oversampling module is used to oversample the differential signal of the differential serial bus in the programmable logic device according to multiple different clock phases to obtain multiple candidate bit streams corresponding to each sampling phase.

[0055] The quality initial selection module is used to construct a sampling phase quality evaluation strategy. Based on the statistical distribution characteristics of signal transition edges in each candidate bitstream and the selection weight of each sampling phase, it performs quality initial selection on multiple candidate bitstreams to determine the candidate bitstream to be checked in the current frame.

[0056] The verification operation module is used to perform a remainder operation of cyclic redundancy check on the determined candidate bit stream within the programmable logic device, determine whether the verification passes based on the remainder operation result, and accumulate the verification pass results of multiple frames according to the sampling phase to obtain the verification reliability of each sampling phase.

[0057] The feedback tuning module is used to construct a phase feedback tuning strategy, using the verification reliability of each sampled phase as the feedback quantity to correct the selection weight of each sampled phase in subsequent frames, so that the sampled phase selection stage and the cyclic redundancy check stage form a closed loop iteration.

[0058] The beneficial effects of this application are as follows: This application oversamples the differential signal of the differential serial bus according to multiple different clock phases to obtain multiple candidate bit streams. By replacing a single fixed sampling point with multi-phase parallel value taking, the same bit can be read at multiple time positions at the same time, solving the problem that there is no alternative value when the fixed sampling point falls into the transition interval.

[0059] This application performs initial quality selection based on the statistical distribution characteristics of signal transition edges and the selection weight of each sampling phase. By fusing the instantaneous edge quality of the current frame with the historical cumulative reliability, it determines the candidate bit stream to be checked in the current frame, thus solving the problem of selecting the best bit stream from multiple candidate bit streams for check.

[0060] This application performs a remainder operation of cyclic redundancy check on the determined candidate bit stream within a programmable logic device and determines whether the check passes. By accumulating the check pass results of multiple frames according to the sampled phase, the check reliability of each sampled phase is obtained, thus solving the problem of lacking phase feedback based on the check results.

[0061] This application constructs a phase feedback tuning strategy, using the verification reliability of each sampled phase as the feedback quantity to correct the selection weight of subsequent frames. By making the sampled phase selection stage and the cyclic redundancy check stage form a closed loop iteration, the problem that the sampled phase depends on the static setting and cannot be adjusted with the bus timing drift is solved.

[0062] The technical solution of this application connects multi-phase oversampling, quality initialization, cyclic redundancy check remainder operation and phase feedback tuning into a parallel hardware processing link within the same programmable logic device, so that the selection of sampling phase can be automatically adjusted according to the actual changes in the timing of the differential serial bus, and the frame check pass rate can be maintained under long-distance wiring conditions. Attached Figure Description

[0063] Figure 1 A flowchart of the hardware acceleration method for cyclic redundancy check based on programmable logic provided in this application;

[0064] Figure 2 This is a schematic diagram of an industrial application scenario for this application;

[0065] Figure 3 This is a schematic diagram of the multi-phase sampling time within the bit period of this application;

[0066] Figure 4 This is a schematic diagram of the annular position of the sampling phase relative jump concentration region in this application;

[0067] Figure 5 This is a schematic diagram showing the aggregation of the verification results of this application according to the sampling phase;

[0068] Figure 6 This is a schematic diagram of the phase feedback setting direction of this application;

[0069] Figure 7 The hardware acceleration system architecture diagram of Cyclic Redundancy Check (CRC) based on programmable logic provided in this application is shown. Detailed Implementation

[0070] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0071] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0072] Secondly, the term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of this application. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single embodiment or an embodiment selectively excluded from other embodiments.

[0073] Example 1

[0074] Reference Figures 1 to 6 This is the first embodiment of the present application, such as Figure 1 As shown, a hardware acceleration method for cyclic redundancy check based on programmable logic is provided.

[0075] The differential serial bus in this embodiment is exemplified as a RS-485 bus. The RS-485 bus is a differential serial communication bus built according to the RS-485 standard, also known as the RS-485 bus. The RS-485 bus transmits data using a pair of differential signal lines, with the logic level represented by the level difference between the differential line pairs. It features long transmission distance, strong common-mode interference immunity, and support for multi-node connection, and is widely used in industrial fields between instruments, sensors, and controllers. The RS-485 bus typically transmits and receives data in half-duplex mode and organizes data at the link layer according to a pre-defined frame format. For example, the MODBUS-RTU frame format commonly used in industrial fields is one of the RS-485 bus link layer conventions.

[0076] The Cyclic Redundancy Check (CR) described in this embodiment refers to an error detection method in which the transmitting end calculates a checksum for the data to be transmitted according to an agreed generator polynomial and appends it to the data, and the receiving end performs a division verification on the received data along with the checksum according to the same generator polynomial to detect transmission errors. The CR uses modulo-2 polynomial division as the core operation, and the operation process can be implemented by a linear feedback shift register, which refers to a shift register circuit composed of XOR feedback.

[0077] The programmable logic device (PLD) described in this embodiment refers to a digital integrated circuit whose internal logic functions can be configured by the user. For example, the PLD is a field-programmable gate array (FPGA), which is a PLD composed of configurable logic units, programmable interconnects, and input / output units, capable of implementing specified digital functions using parallel hardware logic. The hardware environment for the method operation is centered around the PLD, forming the signal processing circuit of the 485 bus receiver. Differential signals are transmitted on the 485 bus. The level difference on the differential line pairs is converted to a single-ended logic level by a half-duplex transceiver and introduced into the device through the input pins of the PLD. Bit sampling, frame assembly, remainder calculation for cyclic redundancy check, and feedback tuning of the sampling phase are all completed internally within the PLD using parallel hardware logic; the bit-by-bit processing is not handled by an external processor.

[0078] Before detailing the steps of this embodiment, the clock and data paths upon which the method of this application relies are explained. A field-programmable gate array (FPGA) is internally configured with a phase-locked loop (PLL). The PLL is a circuit capable of generating multiple clocks of the same frequency by multiplying a reference clock and fixing the phase relationship of each clock. The PLL generates the multiple sampling clocks required by the method after multiplying the reference clock. These multiple sampling clocks have the same frequency and their phases are sequentially staggered, with a fixed phase difference between adjacent sampling clocks. Once the 485 bus baud rate is determined, the time length occupied by a single bit is also determined. The phase stagger of the multiple sampling clocks is evenly divided according to the bit period, resulting in multiple sampling moments with different time positions within one bit period. The transceiver is equipped with a fail-safe bias. This fail-safe bias refers to a bias measure that maintains the single-ended logic level at a determined high level even in the idle state where the bus is not driven, facilitating the stable identification of the falling edge of the start bit. The single-ended level obtained from the differential signal conversion passes through two synchronous flip-flops before entering the sampling flip-flop, in order to reduce the impact of metastability introduced by the asynchronous signal on the sampling result; the metastability refers to the phenomenon that the output of the flip-flop remains at an uncertain level for a long time when the input signal violates the setup and hold time constraint.

[0079] In industrial environments, the RS-485 bus often coexists with interference sources such as frequency converters and motors. Under long-distance cabling conditions, signal edges become slower, and the stable sampling window within a bit period narrows, making it easy for a fixed single sampling point to fall into the transition range between bits. This method addresses the conditions of coexisting interference sources and long-distance cabling by combining multi-phase oversampling with verification result feedback within the device, ensuring that the sampling timing is adapted to the actual edge position of the RS-485 bus signal.

[0080] Figure 2 This is a schematic diagram illustrating an industrial application scenario for this method. Figure 2 The pair of parallel lines in the middle represent the 485 bus (differential twisted pair), and each end of the bus is equipped with a terminating matching resistor; multiple nodes such as instrument nodes and sensor nodes are connected to the bus. Figure 2 The boxes above, representing the frequency converter and motor, point to the bus via a broken-line arrow and are labeled with interference, indicating interference sources in the industrial field. Figure 2 The box on the right is the 485 bus receiver, which contains a half-duplex transceiver and a field-programmable gate array (FPGA) (signal processing circuit). The transceiver output is sent to the FPGA via the arrow, and the FPGA is then connected to the bus.

[0081] This embodiment provides a specific implementation of the hardware acceleration method for cyclic redundancy check based on programmable logic, and elaborates on the specific contents of steps S1 to S4 in sequence. For ease of explanation, this embodiment uses unified notation for the parameters and variables appearing in each step, and gives their meaning and definition when each parameter is first introduced.

[0082] Step S1: In the programmable logic device, the differential signal of the differential serial bus is oversampled according to multiple different clock phases to obtain multiple candidate bit streams corresponding to each sampling phase.

[0083] Oversampling the 485 bus differential signal at multiple different clock phases within a Field-Programmable Gate Array (FPGA) is the fundamental step in implementing this method. The single-ended received data signal output from the transceiver is fed in parallel into a group of sampling flip-flops driven by multiple sampling clocks within the device. Each sampling clock samples the received data signal once at its effective edge. Thus, the same bit is repeatedly read at different time positions, forming multiple candidate bit streams corresponding to each sampling phase. Let the number of sampling phases be... The phase number is denoted as , From 0 to . No. The phase offset of the sampling clock of the first sampling channel relative to the sampling clock of the 0th channel can be expressed as: ;in, For the first The phase offset of the sampling clock, in degrees; This represents the total number of sampled phases; This is the sequence number of the sampling phase; where one bit period corresponds to 360 degrees.

[0084] like Figure 3 As shown, Figure 3 This is a schematic diagram of the multi-phase sampling time within a bit period. Figure 3 Two vertical dashed lines define a bit period, with a double-headed arrow above indicating the bit period. The broken line represents the received data signal level within that bit period; the sloping edges on both sides correspond to bit transition regions, and the flat section in the middle corresponds to the stable bit interval. Several solid dots are evenly distributed along the time axis within the bit period, marking multiple sampling times (phases staggered). Adjacent dots are spaced evenly, and are grouped together below by curly braces. Sampling times near the edges fall within transition regions, while those in the middle fall within stable intervals, indicating that the same bit is repeatedly read at multiple time points. Figure 3 This can be explained by replacing a single fixed sampling point with multi-phase oversampling in step S1.

[0085] Total number of sampling phases Numerically, it is equal to the number of sampling moments evenly distributed along the time axis within one bit period, that is, the number of multiple sampling clocks. The value needs to be determined by a trade-off between the time resolution within the bit period and the device clock resources and dynamic power consumption. When the phase is too small, the number of sampling times within one bit period is too few, which limits the room for maneuver in subsequent phase selection; When the baud rate is too high, the number of phase paths in the phase-locked loop output and the size of the sampling trigger group increase accordingly. For example, for common industrial baud rates, the baud rate can be... The value is 8, which means that 8 sampling moments are evenly arranged along the time axis within one bit period. According to the above phase offset relationship, the adjacent sampling moments are 45 degrees out of phase, which corresponds to a time difference of 1 / 8 of the bit period.

[0086] Termination matching resistors are configured at both ends of the 485 bus to suppress signal reflections, and bias resistors are configured on the transceiver side to determine the idle level. For example, the termination matching resistor can be 120 ohms, matching the characteristic impedance of the 485 bus; the bias resistor value is chosen to maintain the differential voltage above the transceiver's receive threshold during idle. After termination matching and bias are determined, the single-ended receive data signal output by the transceiver has a defined high and low level range within a bit period, and multi-phase oversampling takes values ​​within this defined level range.

[0087] The sampling results corresponding to each sampling clock are shifted into their respective shift registers in bit order. After detecting the falling edge of the start bit, the bit timer / counter advances according to the baud rate, defining the boundary of each bit on the time axis and completing byte boundary alignment. This ensures that the sampled bits obtained by each sampling clock at its respective phase are assigned to the candidate byte sequence corresponding to that sampling phase in bit order. For example, a single character is organized in the format of a start bit, 8 data bits, and a stop bit. Multiple candidate byte sequences are concatenated according to a 485-frame field format to obtain candidate frames corresponding to each sampling phase. Multiple candidate bit streams are obtained by sampling the same received data signal, sharing the same falling edge of the start bit and the same bit timing reference. Each candidate bit stream is aligned to the same frame structure at the byte level; the differences between them only arise from the different positions of the sampling time within the bit period.

[0088] Step S1 replaces the single fixed sampling point method with multi-phase parallel sampling, allowing the same bit to be read simultaneously at multiple time positions. When the fixed sampling point happens to fall within the signal transition interval, it is easy to read incorrectly. Multi-phase oversampling retains the values ​​at multiple sampling times, providing comparable material for subsequent selection from multiple candidate bit streams.

[0089] Step S2: Construct a sampling phase quality assessment strategy. Based on the statistical distribution characteristics of signal transition edges in each candidate bitstream and the selection weight of each sampling phase, perform initial quality selection on multiple candidate bitstreams to determine the candidate bitstream to be checked in the current frame.

[0090] After completing multi-phase oversampling, a selection needs to be made among multiple candidate bitstreams to choose the one most suitable for verification in the current frame. From the perspective of sampling reliability, the sampling time should ideally fall within the stable range of the bits, far from the transition edges between bits; the level in the region near the transition edge is in a transitional state, and taking values ​​in this region is prone to misreading due to insufficient setup and hold time. Based on the positional relationship between the sampling time and the transition edge, the sampling phase quality evaluation strategy uses the statistical distribution characteristics of signal transition edges in each candidate bitstream as one of the criteria.

[0091] Edge transitions are extracted within the device via an XOR operation on adjacent sample values. When the levels of two adjacent sampling moments are different, the XOR result is 1, which is marked as an edge transition. To avoid glitches on the bus being misjudged as edges transitions, isolated edges that last only a single sampling moment and have consistent levels before and after are discarded, retaining only edges where the levels before and after a genuine change. The basis for discarding isolated edges is that a valid bit transition will maintain the new level for several subsequent sampling moments, while glitches only deviate within a single sampling moment. For the current frame, a bit period is divided along the time axis into segments corresponding to the sampling phase. For each time interval, the number of times the transition edge falls into each time interval is counted bit by bit to obtain the transition edge distribution histogram of the current frame.

[0092] The transition edge distribution histogram is accumulated bit-by-bit across the current frame. For each received bit, the detected transition edge is included in the corresponding time interval, resulting in a transition edge distribution covering the entire frame at the end of the frame. The transition edge distribution histogram is reset at the beginning of each frame, ensuring that the sampled phase quality assessment reflects the edge distribution of the current frame without mixing in the previous frame. Since a frame contains multiple bits, bit-by-bit accumulation allows the estimation of transition edge cluster positions to be based on the transition edges of the entire frame, making it more stable than judging individual bits.

[0093] The histogram of transition edges depicts the clustering locations of transition edges within a bit period, and can be used to represent the first... The number of edge jumps within a time interval is denoted as . ,in, For the current frame to fall into the first Number of transition edges in each time interval This represents the sequence number of the time interval, which corresponds one-to-one with the sampling phase number. Under correct data transmission, transition edges are concentrated in time intervals near bit boundaries, and the transition edge distribution histogram shows a count peak in the time interval corresponding to the bit boundary. The transition edge count is then calculated. The largest time interval index is the location of the transition concentration region, denoted as , The center of the clustering of transition edges within a bit period is determined.

[0094] To measure whether a given sampling phase is far from the transition concentration region, a circular distance from the sampling phase to the transition concentration region is introduced. Bit periods are contiguous in time, and the distance is measured using a circular metric, meaning the distance between two indices is the shorter of the forward and reverse spans. This can be represented as... The ring distance of each sampled phase is defined as: ;in, For the first The annular distance from each sampling phase to the location of the transition concentration region; This refers to the sampling phase number; The location of the transition concentration zone; This represents the total number of sampled phases. Indicates taking and The smaller of the two; express and The absolute value of the difference, i.e. and The interval along the direction of increasing sequence number. This definition takes... and The smaller one, that is, in "by Counting forward to ” and “by Count backwards to "Choose the shorter of the two paths to obtain the shortest distance in the sense of a loop."

[0095] Figure 4 This is a schematic diagram of the annular position of the sampling phase relative transition concentration region. Figure 4 A circle represents the bit period, with the beginning and end of the bit period marked at the center. The top sector of the circle is filled with light gray and marked as the transition concentration area. Several hollow dots are distributed on the circumference to indicate the position of each sampling phase. One dot, roughly opposite the transition concentration area, is marked with a solid dot, and the selected sampling phase is marked downwards: it is far from the transition concentration area and falls within the bit stable interval, with the bit stable interval marked nearby. Figure 4 The circular metric is used to characterize the positional relationship between the sampling phase and the transition concentration region. The sampling phase that is far away from the transition concentration region is more likely to fall in the bit stable region. Figure 4 This explains that step S2 selects the sampling phase that is far from the transition concentration area according to the ring distance.

[0096] The maximum possible value of the ring distance is denoted as . Its value is Half of it is rounded down, that is: ;in, The maximum possible value of the ring distance; symbol This indicates rounding down to the nearest integer, meaning taking the largest integer not greater than the value within the parentheses. For example, It was 8 o'clock. The value is 4. The larger the ring distance, the farther the sampling time of the corresponding sampling phase is from the transition edge, and the higher the probability of it falling within the bit stable region.

[0097] Judging solely based on the transition edge distribution of the current frame is easily affected by noise fluctuations in a single frame. Therefore, in addition to the statistical distribution characteristics of the transition edges, the sampling phase quality evaluation strategy introduces the selection weight of each sampling phase as another criterion. The selection weight represents the reliability of each sampling phase accumulated from previous frames. The value of the selection weight is given by the phase feedback tuning strategy in step S4 and updated with the accumulation window. In step S2, it is used as a known quantity in the calculation.

[0098] By combining the statistical distribution characteristics of the jump with the selection weight, the first jump can be... The quality score for each sampling phase is defined as: ;in, For the first Quality score for each sampling phase; For the first The ring distance of each sampling phase; The ratio is the maximum possible value of the ring distance. Normalize the ring distance to between 0 and 1; For the first The selection weight for each sampling phase ranges from 0 to 1. and The matching coefficients for the two criteria.

[0099] Mixing ratio coefficient and This is used to determine the respective weights of the current frame transition edge distribution and the historical cumulative weights in the quality score, both of which satisfy constraints. and , All values ​​are taken between 0 and 1; under this constraint and Only one of them is a free quantity, which is determined. That is, by Sure . and The value of can be determined based on the relative confidence level between the instantaneous edge quality of the current frame and the historical cumulative reliability. For example, one method of determination is as follows: First let and Equal values ​​are all set to 0.5; the percentage of verification failures is statistically analyzed in actual tests. If there are too many misselections due to instantaneous interference in a single frame, the percentage is increased. , correspondingly decrease This makes the quality score more focused on historical reliability; if the tracking of bus timing drift is slow or the selection of a new stable interval is not timely, it will increase the risk. , correspondingly decrease This makes the quality score more focused on the instantaneous edge quality of the current frame; this adjustment continues until the failure rate of the verification is minimized, thus obtaining a score suitable for the current working condition. and . When the value is too large, the quality score focuses more on the instantaneous edge quality of the current frame and is sensitive to single-frame perturbations. When the value is too large, the quality score tends to rely more on historical reliability, making it less sensitive to single-frame disturbances but resulting in slower tracking. For example, it can be determined in the manner described above. 0.6 A value of 0.4 makes the edge quality of the current frame slightly dominant, while the historical weight plays a role in smoothing out fluctuations in a single frame.

[0100] To illustrate the initial quality selection process in step S2, we will use... 8. Location of the jump concentration area 2. Proportioning coefficient 0.6 Taking 0.4 as an example, the eight sampling phases (sequence numbers) are calculated using the definition of the ring distance. The circular distance from 0 to 7) The values ​​are 2, 1, 0, 1, 2, 3, 4, 3, and the corresponding normalized ring distances are... The values ​​are 0.50, 0.25, 0, 0.25, 0.50, 0.75, 1.00, and 0.75, respectively; the selection weights for the eight sampling phases within this cumulative window are set. The values ​​are 0.10, 0.10, 0.05, 0.10, 0.15, 0.15, 0.20, and 0.15, respectively. The quality scores for the eight sampling phases are then calculated using the definition of quality scoring. The values ​​are 0.34, 0.19, 0.02, 0.19, 0.36, 0.51, 0.68, and 0.51, respectively.

[0101] As can be seen from the above values, the ring distance of the 6th sampling phase is the largest. It is 4, which is exactly equal to Its normalized circular distance is 1, and the quality score is calculated by adding a higher selection weight. The value is 0.68, the highest among the eight sampling phases. Therefore, the candidate bitstream corresponding to the sixth sampling phase is determined as the candidate bitstream to be checked in the current frame. This result is consistent with the original intention that "the sampling time should be far away from the transition concentration area and fall within the bit stability interval".

[0102] The quality scoring is performed within the device using fixed-point calculations. Normalized ring distance. exist When taking integer powers of 2, it is achieved by bit shifting; the matching coefficient. and Represented by a fixed-point constant, multiplication and addition are performed by the multiplier and adder within the device, while the comparison process is implemented using a fixed-point comparator. The fixed-point bit width is determined by the accuracy of the selected weights and the ring distance normalization value, ensuring that the quantization error in the quality score does not alter the high-low order between adjacent sampling phases.

[0103] The initial quality selection is implemented within the device using a parallel comparison tree. The quality scores of each sampling phase are compared pairwise, and the sampling phase with the highest quality score is selected step by step. The candidate bitstream corresponding to the sampling phase with the highest quality score is determined as the candidate bitstream to be checked in the current frame. If two sampling phases have the same quality score, the one with the smaller phase number is selected first to ensure that the comparison result is unique. The comparison tree is expanded in a pipelined manner, and the comparison result is output within the same clock cycle interval after the frame is assembled, without occupying additional processing time in subsequent verification stages.

[0104] Step S2 characterizes the instantaneous sampling quality of the current frame using the statistical distribution features of transition edges, selects weights to carry the reliability of historical accumulation, and fuses the two according to a matching coefficient to complete the initial quality selection of multiple candidate bit streams. The initial quality selection increases the probability that the candidate bit streams entering the verification stage come from the bit stable interval, reduces the invalid verification caused by sending erroneous values ​​from the adjacent regions of the transition edge into the verification, and also provides a single-path input with a clear phase for the verification stage.

[0105] Step S3: Perform a remainder operation for cyclic redundancy check on the determined candidate bit stream within the programmable logic device. Determine whether the check passes based on the remainder operation result. Accumulate the check pass results of multiple frames according to the sampling phase to obtain the check reliability of each sampling phase.

[0106] After the candidate bitstreams to be checked in the current frame are determined, a remainder operation for cyclic redundancy check (CRC) is performed on the determined candidate bitstreams within the field-programmable gate array (FPGA). A check field is appended to the data field of the 485 frame; the check field is calculated by the sender using an agreed-upon generator polynomial on the data field. The receiver sends the data field along with the check field into the remainder operation logic, and uses the remainder result to determine whether an error occurred during the transmission of the current frame.

[0107] The 485 frame is divided into fields according to the link layer convention. For example, a frame sequentially includes an address field, a function code field, a data field, and a 16-bit check field. The check field covers the address field, function code field, and data field. The remainder operation logic sends the bits in the order of field concatenation, and the byte order of the check field is arranged according to the convention of least byte first. Frame boundaries are defined by bit timing and byte counting. The remainder operation result is given after all fields of the frame have been sent.

[0108] The remainder operation is based on a linear feedback shift register. The frame bit sequence carried by the determined candidate bitstream is considered as the coefficients of a polynomial, denoted as... According to the agreed generator polynomial Perform modulo 2 polynomial division, and denote the remainder as . The operational relationship of modulo 2 polynomial division can be expressed as: ;in, For example, the formal variables of a polynomial; The frame polynomial corresponding to the determined candidate bitstream; To generate polynomials; The quotient polynomial of modulo 2 division; Remainder polynomial; symbol This represents modulo-2 addition, i.e., bitwise XOR operation. The degree of the generator polynomial determines the bit width of the check field. For example, the generator polynomial commonly used in industrial 485 links for cyclic redundancy check (CRC) can be: The generator polynomial corresponds to a 16-bit check field. The initial preset value of the linear feedback shift register is all 1s, meaning each bit is preset to 1. The remainder operation represents the correspondence of the modulo-2 polynomial division. The remainder operation result of the actual comparison at the receiving end takes into account the effect of the all-1 preset value on the basis of this modulo-2 division. The remainder operation result corresponding to the correct frame is equal to the fixed value jointly determined by the generator polynomial and the initial preset value.

[0109] The byte-parallel XOR network is derived recursively from the bit-by-bit state transition relationship. The state transition of a linear feedback shift register processing one bit is denoted as one linear transformation. Processing eight bits consecutively constitutes a composite of eight linear transformations. The composite linear transformation corresponds to a fixed XOR relationship between the current register state and the input byte, which is then synthesized into combinational logic. To meet timing constraints, a register stage is set after the byte-parallel XOR network, dividing the remainder operation into a pipeline stage, ensuring that a new byte is received each clock cycle without violating timing margins.

[0110] To match the parallel data throughput brought about by multi-phase oversampling, the remainder operation does not employ a serial structure with bit-by-bit shifting, but rather uses combinational logic that expands in parallel per byte. One byte is processed per clock cycle, matching the processing speed of the remainder operation to the byte assembly speed. After all the data and check fields of a frame are fed into the remainder operation logic, the result is compared with a fixed value: if the remainder equals the fixed value, the current frame passes the check; otherwise, it fails the check. The fixed value is determined by the generator polynomial and the initial preset value, and is a known constant at the receiving end. Frames that fail the check are processed according to the link layer convention, and the check circuit provides the phase feedback tuning with statistics of passes and failures accumulated based on the sampled phase.

[0111] To accumulate the pass / fail status of a single frame into an understanding of each sampling phase, the verification process accumulates the verification results of multiple frames separately according to the sampling phase. The verification result of the current frame is attributed to the sampling phase determined for the current frame in step S2. Two counters are maintained for each sampling phase: one records the number of frames that provided candidate bitstreams from the corresponding sampling phase and participated in the verification within the accumulation window, denoted as . Another record is the number of frames for which the candidate bitstream provided by the corresponding sampling phase passes the check, denoted as . In length of After the cumulative statistics within the window are completed, the first... The reliability of the verification of each sampled phase is defined as: ;in, For the first The reliability of each sampled phase is verified, with a value between 0 and 1. For the cumulative window containing the first Each sampling phase provides the candidate bitstream and the number of frames that pass the check; For the cumulative window containing the first Each sampling phase provides the candidate bitstream and the number of frames participating in the verification; the above formula requires Greater than 0, When the value is 0, the reliability of the sampled phase verification will be based on the result of the previous window, as described below, without division.

[0112] Figure 5 This is a schematic diagram showing how the verification results are aggregated according to the sampling phase. Figure 5 The diagram shows several boxes arranged side-by-side, each labeled with the sampling phase above it. Inside each box are several small squares, with solid and hollow squares representing passes and failures, respectively. Below each box is an arrow indicating the verification reliability, meaning that the verification reliability of that sampling phase is derived from the accumulated pass and failure results. Figure 5 Each sampling phase in the process is assigned a collection box, and the verification result of the current frame is included in the box corresponding to the sampling phase determined in step S2. Figure 5The explanation in step S3 is that the verification process accumulates the pass and fail results of multiple frames according to the sampling phase, and then obtains the verification reliability of each sampling phase.

[0113] Verification of reliability Calculated within the device by a fixed-point divider, the numerator is the number of frames that passed the checksum. The denominator is the number of frames participating in the verification. The quotient is expressed as a fixed-point decimal. During the cumulative window settlement, the two counters of each sampling phase are read first, and then the verification reliability of each sampling phase is calculated for use in phase feedback tuning. The counters are cleared after the verification reliability is calculated, and the next cumulative window statistics are entered.

[0114] Verification reliability reflects the proportion of frames that pass verification when a certain sampling phase is used. A higher proportion indicates that the data sampled at the corresponding sampling phase is more resistant to cyclic redundancy checks. Cumulative window length. The number of frames counted in a single settlement needs to be determined by a trade-off between statistical stability and tracking speed. When the error is small, the reliability of the verification is affected by the random results of a few frames, and the estimation is unstable. When the value is too large, the reliability of the verification will be slow to track the slow drift of the bus timing. The required accuracy for reliability estimation can be determined based on the calculated accuracy. The standard deviation of the proportional estimation decreases as the number of participating frames increases, and is approximately inversely proportional to the square root of the number of participating frames. Therefore, the minimum number of frames that results in the estimated standard deviation being below a set threshold can be taken as the threshold. For example, it can be... The value is set to 64, meaning the reliability of each sampled phase is calculated every 64 frames. The counter bit width is set according to... Configure and clear the count after window settlement to prevent count overflow.

[0115] The number of frames selected for certain sampling phases within the cumulative window may be too small, and the proportion calculated with too few samples is prone to distortion. To avoid proportion distortion, a minimum number of participating frames is set, and the number of frames participating in the verification is adjusted accordingly. Sampling phases with a sample size lower than the minimum number of participating frames will not have their verification reliability included in subsequent comparisons; the results from the previous window will be used instead. The minimum number of participating frames must be chosen to ensure that the proportional estimate has a minimum amount of sample support. It can be set to the minimum number of frames that makes the relative fluctuation of the proportional estimate lower than a set limit; for example, the minimum number of participating frames can be set to 4.

[0116] Step S3 performs cyclic redundancy check within the device using byte-parallel remainder operations. The processing rate matches the frame data assembly rate, avoiding the path overhead and latency caused by transferring the bit stream to an external processor for verification. By accumulating the sampling phases, the pass / fail status of each frame is recorded as the verification reliability of each sampling phase, providing feedback based on the verification results for phase feedback tuning.

[0117] Step S4: Construct a phase feedback tuning strategy, using the verification reliability of each sampled phase as the feedback quantity to correct the selection weight of each sampled phase in subsequent frames, so that the sampled phase selection stage and the cyclic redundancy check stage form a closed loop iteration.

[0118] After obtaining the verification reliability of each sampling phase, the verification reliability of each sampling phase is used as a feedback quantity to adjust the selection weight of each sampling phase in subsequent frames. The starting point of the phase feedback tuning strategy is that sampling phases with high verification reliability indicate that the data obtained by sampling with the corresponding phase is more resistant to cyclic redundancy check and should have a higher chance of being selected in the initial quality selection of subsequent frames; sampling phases with low verification reliability should have a lower chance of being selected. The selection weight is precisely the criterion for carrying historical reliability in the quality scoring of step S2. The phase feedback tuning strategy adjusts the selection weight with verification reliability and sends the conclusion of the verification stage back to the phase selection stage.

[0119] Figure 6 This is a schematic diagram of the phase feedback tuning direction. Figure 6 The two boxes on the left are labeled with the sampling phases with high verification reliability and the sampling phases with low verification reliability, respectively. Figure 6 The two boxes on the right indicate whether the chance of being selected in the subsequent quality preliminary selection is increased or decreased. The corresponding boxes on the left and right are connected by horizontal arrows. The upward arrow indicates that the weight is increased, and the downward arrow indicates that the weight is decreased. Figure 6 The following explains how phase feedback tuning adjusts the selection probability of each sampling phase in subsequent frames to verify reliability, reflecting the directional correspondence of increasing the selection of phases with high reliability and decreasing the selection of phases with low reliability.

[0120] The weighting adjustment is driven by the deviation of the verification reliability relative to the average level of each sampled phase. First, the average verification reliability of each sampled phase participating in the comparison within the cumulative window is calculated, which can be expressed as: ;in, (mark The horizontal line above indicates that the average value is taken, which is the average value of the reliability of each sampled phase verification involved in the comparison; The set of sampled phases that achieves the minimum number of participating frames in the verification process; Represents a set The number of elements in the middle, that is, the number of sampling phases required to reach the minimum number of participating frames; For the first The reliability of the verification of each sampled phase; symbol Represents a set All serial numbers Summation, that is, summing the sets The reliability of each sampled phase is summed. The above formula adds up the set. The arithmetic mean of the verification reliability of each sampled phase is obtained by summing the verification reliability of each sampled phase and dividing by the number of phases.

[0121] Then, the selection weights are updated by using the difference between the verification reliability and the average value for the set. The sampling phase in the equation can be used to represent the update relationship of the selection weights as follows: ;in, For the updated version The selection weights for each sampling phase; For the first time before the update The selection weights for each sampling phase; For feedback tuning coefficients; For the first Verification reliability of each sampling phase; This is the average reliability of each sampled phase verification. Not in the set. The sampling phase in the set retains the selection weights from before the update in this update. If the set If the value is empty, meaning the number of participating frames for the sampling phase has reached the minimum number of participating frames, then the selection weights of this cumulative window will not be updated, and the selection weights of each sampling phase will remain unchanged.

[0122] Weight updates are performed within the device using fixed-point computation. The difference between the reliability and the average value is verified. The feedback tuning coefficient is expressed as a signed fixed-point number. When taking the negative integer power of 2, the difference and The product is achieved through an arithmetic right shift, and the updated selection weights are obtained by adding the original selection weights to the shift result, thus eliminating the need for a multiplier. Feedback tuning coefficients. The adjustment magnitude of the selection weight for each cumulative window can be controlled, and its value can be determined based on closed-loop stability and tracking speed: Take the negative integer power of 2 so that multiplication can be replaced by a bit shift, and make The product of the reliability deviation of each window verification does not exceed the set upper limit of a single weight adjustment, thereby avoiding the selection weight from swinging back and forth between adjacent windows; When the weight is too large, the response to changes in verification reliability is fast, but it is prone to fluctuations due to accidental results in individual windows. When the selection weight is small, the change is smooth, but the tracking speed for bus timing drift is slow. For example, it can be... The value is set to 0.125, which is 2 to the power of negative 3. This corresponds to an arithmetic right shift of 3 bits, ensuring that the adjustment range of the selection weight for each cumulative window is within a moderate range.

[0123] The updated selection weights are first constrained to between 0 and 1. To prevent the selection weights from continuously concentrating on a few sampling phases, thus preventing other sampling phases from being selected for an extended period and thus failing to update their verification reliability, a phase feedback tuning strategy sets a lower limit for the selection weights of each sampling phase. When the selection weight of a certain sampling phase falls below the lower limit after updating, the selection weight of the corresponding sampling phase is raised back to the lower limit, ensuring that the corresponding sampling phase retains the opportunity to be selected in subsequent frames, thereby continuously obtaining new verification reliability. The value of the lower limit for the selection weights needs to be balanced between preserving trial opportunities and not interfering with the dominant phase; a uniformly distributed weight can be chosen. A fraction of this ensures that the non-dominant phase still has a chance of being selected with no less than the minimum number of participating frames within a cumulative window; for example, When the weight is 8, the uniform distribution weight is 0.125, and the lower limit of the weight can be chosen as 0.02.

[0124] The normalization of selection weights is performed after the limiting and setting of the lower limit of selection weights. First, the selection weights after limiting and setting the lower limit of selection weights for all sampling phases are summed. Then, the selection weight of each sampling phase is divided by the sum to restore the sum of selection weights for all sampling phases to 1. This avoids the selection weights from changing their actual proportion in the quality score due to the overall rise or fall of the selection weights as the window progresses. Normalization is achieved by fixed-point division. The normalized selection weights are written back to the selection weight register group for reading in step S2 of the next accumulation window.

[0125] Feedback setting coefficient With cumulative window length To determine the closed-loop response: The sample size for each feedback is determined. The step size for each feedback is determined; a sufficient sample size with a slow step size results in a stable closed loop, while a small sample size with a rapid step size makes the closed loop prone to oscillation. For example, Take 64, When the value is 0.125, the closed loop can track the slow drift of the bus timing within several windows.

[0126] The selection weights are updated all at once at the boundary of the accumulation window. Within the accumulation window, the selection weights for each sampling phase remain unchanged, ensuring that step S2 reads stable selection weights within the window. The updated selection weights for each sampling phase are read in step S2 of the next accumulation window and participate in the calculation of a new quality score. Initial quality selection data determines the candidate bitstream for subsequent frames. After verification in step S3, the candidate bitstream generates a new verification reliability. The new verification reliability then drives step S4 to update the selection weights. The sampling phase selection stage and the cyclic redundancy check stage are interconnected through the two variables of selection weights and verification reliability, forming a closed-loop iteration.

[0127] Upon power-up of the field-programmable gate array (FPGA), the selection weights of each sampling phase are reset to equal initial values, and the quality score initially exhibits a statistical distribution characteristic of transition edges. As the cumulative window is calculated, the selection weights of sampling phases with high verification reliability are increased window by window, while the selection weights of sampling phases with low verification reliability are decreased window by window. After several windows, the selection weights tend to stabilize. A lower limit for the selection weights ensures that sampling phases not selected in the initial stage still have a chance to be selected, preventing accidental results in the initial stage from excluding certain sampling phases for an extended period.

[0128] As the cumulative window advances, the selection weights of sampling phases with high verification reliability tend to stabilize at a higher level, the initial quality selection results become more consistent, and the closed loop enters a stable state. When the bus timing slowly shifts due to temperature drift or load changes, and the location of the transition concentration area moves over time, the verification reliability of the previously selected sampling phase decreases. The change in verification reliability, through phase feedback tuning, causes the selection weights to redistribute, and the initial quality selection is subsequently changed to the sampling phase corresponding to the new stable interval, and the closed loop reconverges.

[0129] Step S4 uses the verification reliability as feedback to correct the selection weights, so that the selection of the sampling phase no longer depends on a one-time static setting, but adjusts itself based on the actual results of the cyclic redundancy check. The sampling phase selection stage and the cyclic redundancy check stage thus form a closed-loop iteration, keeping the verification failure rate at a low level even when the bus timing drifts slowly.

[0130] The method provided in this embodiment integrates multi-phase oversampling, initial selection of sampled phase quality, cyclic redundancy check remainder calculation, and phase feedback tuning into a parallel hardware processing link within a field-programmable gate array (FPGA). Bit sampling and verification are completed in a pipelined manner within the same device, and bit-by-bit processing does not require external processor intervention. The verification throughput matches the frame assembly rate. The result of the cyclic redundancy check is fed back to the phase selection stage via phase feedback tuning, enabling the selection of the sampled phase to adaptively adjust with changes in bus timing. This maintains the frame verification pass rate even when the 485 bus timing drifts due to operating conditions.

[0131] Compared to the cyclic redundancy check (CRC) method with a fixed single sampling point, the method in this embodiment takes values ​​in parallel at multiple time positions within a bit period during the sampling stage. The actual pass result of the CRC check then guides the selection of the sampling phase, forming a closed loop. The selection of the sampling phase does not rely on manual pre-setting but adjusts automatically according to the actual changes in bus timing. Therefore, even in long-distance cabling conditions where edge smoothing and the stable sampling window narrows, the sampling time can still be maintained within the stable bit range, reducing the proportion of check failures caused by the sampling time falling into the transition range. Furthermore, the four stages of multi-phase oversampling, quality initial selection, remainder calculation, and feedback tuning are all implemented in a pipelined manner using parallel hardware logic within the same field-programmable gate array. The bit-by-bit processing does not consume the computing resources of an external processor or bus bandwidth. The check throughput matches the assembly rate of 485 frames, making it suitable for deployment at 485 bus receivers in industrial environments where both real-time performance and reliability are required.

[0132] Example 2

[0133] Reference Figure 7 This is a second embodiment of the present application, providing a hardware acceleration system for cyclic redundancy check (CRC) based on programmable logic. The system includes: an oversampling module, a quality initialization module, a CRC calculation module, and a feedback tuning module.

[0134] The oversampling module is used to oversample the differential signal of the differential serial bus in the programmable logic device according to multiple different clock phases to obtain multiple candidate bit streams corresponding to each sampling phase.

[0135] The quality initial selection module is used to construct a sampling phase quality evaluation strategy. Based on the statistical distribution characteristics of signal transition edges in each candidate bitstream and the selection weight of each sampling phase, it performs initial quality selection on multiple candidate bitstreams to determine the candidate bitstream to be verified in the current frame.

[0136] The verification operation module is used to perform a remainder operation of cyclic redundancy check on the determined candidate bit stream within the programmable logic device, determine whether the verification passes based on the remainder operation result, and accumulate the verification pass results of multiple frames according to the sampling phase to obtain the verification reliability of each sampling phase.

[0137] The feedback tuning module is used to construct a phase feedback tuning strategy, using the verification reliability of each sampled phase as the feedback quantity to correct the selection weight of each sampled phase in subsequent frames, so that the sampled phase selection stage and the cyclic redundancy check stage form a closed loop iteration.

[0138] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the displayed or discussed mutual couplings or direct couplings or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0139] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments under the guidance of this application without departing from the spirit and scope of protection of the claims. All of these variations are within the protection scope of this application.

[0140] It should be noted that the collection, storage, and use of all personal information involved in the technical solution of this application must be carried out only after obtaining the explicit authorization and separate consent of the information subject. The processing of personal information-related data strictly complies with the requirements of currently effective national laws, regulations, and relevant standards and specifications. The collected personal information is limited to use within the specific purpose necessary to achieve the technical solution of this application, and no processing beyond that purpose will be performed. Necessary technical and management measures will be taken to ensure the security of personal information.

Claims

1. A hardware acceleration method for cyclic redundancy check based on programmable logic, characterized in that, include: In a programmable logic device, the differential signal of the differential serial bus is oversampled at multiple different clock phases to obtain multiple candidate bit streams corresponding to each sampling phase. A sampling phase quality assessment strategy is constructed. Based on the statistical distribution characteristics of signal transition edges in each candidate bitstream and the selection weight of each sampling phase, the quality of multiple candidate bitstreams is initially selected to determine the candidate bitstream to be checked in the current frame. Within the programmable logic device, a remainder operation for cyclic redundancy check is performed on the determined candidate bit stream. The result of the remainder operation is used to determine whether the check passes. The check pass results of multiple frames are accumulated according to the sampling phase to obtain the check reliability of each sampling phase. A phase feedback tuning strategy is constructed, using the verification reliability of each sampled phase as the feedback quantity to correct the selection weight of each sampled phase in subsequent frames, so that the sampling phase selection stage and the cyclic redundancy check stage form a closed loop iteration.

2. The hardware acceleration method for cyclic redundancy check based on programmable logic according to claim 1, characterized in that, The oversampling based on multiple different clock phases includes: The phase-locked loop configured inside the programmable logic device multiplies the reference clock to generate multiple sampling clocks. The multiple sampling clocks have the same frequency and their phases are staggered sequentially. The phase difference between two adjacent sampling clocks is fixed, and the phase stagger is evenly divided according to the bit period. The single-ended received data signal output by the transceiver is fed in parallel into a group of sampling flip-flops driven by multiple sampling clocks. Each sampling clock samples the received data signal once on its own effective edge. The sampling results are shifted into their respective shift registers in bit order. The bit timer and counter advance according to the baud rate after detecting the falling edge of the start bit, defining the boundary of each bit and completing the byte boundary alignment.

3. The hardware acceleration method for cyclic redundancy check based on programmable logic according to claim 1, characterized in that, The statistical distribution characteristics of signal transition edges in each candidate bitstream include: The extraction of the transition edge is accomplished by XORing adjacent sample values. Different levels at two adjacent sampling times are marked as a transition edge. Isolated transitions that last only a single sampling moment and have the same level before and after are discarded, while transition edges with different levels before and after are retained; A bit period is divided into multiple time intervals along the time axis corresponding to the sampling phase. The number of times the transition edge falls into each time interval is counted bit by bit to obtain the transition edge distribution histogram of the current frame. The transition edge distribution histogram is reset at the beginning of each frame.

4. The hardware acceleration method for cyclic redundancy check based on programmable logic according to claim 3, characterized in that, After obtaining the histogram of transition edges for the current frame, the following steps are also included: The time interval with the largest number of jump edges in the jump edge distribution histogram is taken as the position of the jump edge concentration area, and the position of the jump edge concentration area is marked as the center of the jump edge aggregation within the bit period; The sampling phase quality is evaluated based on the ring distance from each sampling phase to the position of the transition concentration region. The ring distance is determined by the ring metric of connecting the beginning and end of the bit period. The maximum possible value of the ring distance is determined by half of the total number of sampled phases, and the ring distance is then normalized.

5. The hardware acceleration method for cyclic redundancy check based on programmable logic according to claim 4, characterized in that, The initial quality selection of multiple candidate bitstreams includes: Based on the normalized ring distance and the selection weight of each sampling phase, the quality score of each sampling phase is obtained by weighting it according to two complementary ratio coefficients. The selection weight represents the reliability of each sampling phase accumulated from previous frames. The initial quality selection is implemented in the programmable logic device using a parallel comparison tree. The quality scores of each sampling phase are compared pairwise, and the sampling phase with the highest quality score is selected step by step. The candidate bitstream corresponding to the sampling phase with the highest quality score is determined as the candidate bitstream to be checked in the current frame. When the quality scores are equal, the one with the smaller phase number is selected first.

6. The hardware acceleration method for cyclic redundancy check based on programmable logic according to claim 1, characterized in that, The remainder operation for performing cyclic redundancy check on the determined candidate bitstream includes: The frame bit sequence carried by the determined candidate bit stream is regarded as the coefficient of a polynomial. Modulo 2 polynomial division is performed according to the set generator polynomial to obtain the remainder operation result. Modulo-2 polynomial division is based on a linear feedback shift register, whose initial preset value is all 1s. The result of the remainder operation is compared with a fixed value. If the result of the remainder operation is equal to the fixed value, the current frame is considered to have passed the verification. If the result of the remainder operation is not equal to the fixed value, the current frame is considered to have failed the verification. The fixed value is determined by the generator polynomial and the initial preset value.

7. The hardware acceleration method for cyclic redundancy check based on programmable logic according to claim 6, characterized in that, The linear feedback shift register includes: The state transition of a linear feedback shift register processing a single bit is denoted as a linear transformation. Multiple linear transformations that process multiple bits in succession are combined into a fixed XOR relationship between the current register state and the input byte, and implemented as a byte-parallel XOR network. After the byte-parallel XOR network, a register level is set up to divide the remainder operation into a pipeline, so that a new byte is received each clock tick; The remainder operation does not use a serial structure with bit-by-bit shifting, but is expanded into combinational logic in parallel by bytes, processing one byte per clock cycle.

8. The hardware acceleration method for cyclic redundancy check based on programmable logic according to claim 1, characterized in that, The verification results accumulated over multiple frames based on the sampling phase include: The verification result of the current frame is attributed to the sampling phase of the candidate bit stream determined for the current frame; Two counters are maintained for each sampling phase. The first counter records the number of frames in the cumulative window that have a candidate bit stream provided by the corresponding sampling phase and have participated in the verification. The second counter records the number of frames that have a candidate bit stream provided by the corresponding sampling phase and have passed the verification. After the statistics are completed within the cumulative window of a preset length, the ratio of the number of frames that pass the verification to the number of frames that participate in the verification is used as the verification reliability of the corresponding sampling phase. For sampling phases where the number of frames participating in the verification is lower than the minimum number of participating frames, the verification reliability of the previous window is used.

9. The hardware acceleration method for cyclic redundancy check based on programmable logic according to claim 1, characterized in that, The selection weights for each sampling phase in subsequent frames, as described in the feedback correction, include: Calculate the average reliability of each sampling phase involved in the comparison. The sampling phase involved in the comparison is the sampling phase where the number of frames involved in the verification reaches the minimum number of participating frames. For the sampling phases involved in the comparison, the selection weight of each sampling phase is updated based on the deviation between the verification reliability of each sampling phase and the average value. The selection weight of the sampling phases not involved in the comparison remains unchanged. The correction magnitude for weight updates is controlled by the feedback tuning coefficient, and the deviation between the verification reliability and the average value is tuned by an arithmetic right shift.

10. The hardware acceleration method for cyclic redundancy check based on programmable logic according to claim 9, characterized in that, The selection weight update includes: The updated selection weights are limited to a set range of values. Set a lower limit for the selection weight of each sampling phase. When the selection weight of a sampling phase is lower than the lower limit after the update, raise the selection weight of the corresponding sampling phase back to the lower limit. The lower limit of the weight is determined according to the set proportion of the uniformly distributed weight; The selection weights are normalized after limiting the amplitude of all sampled phases and setting the lower limit of the selection weights, so that the sum of the selection weights of each sampled phase is restored to a constant value. The normalized selection weights are then written back to the selection weight register group.

11. The hardware acceleration method for cyclic redundancy check based on programmable logic according to claim 1, characterized in that, The closed-loop iteration between the sampling phase selection stage and the cyclic redundancy check stage includes: The selection weights are updated once at the boundary of the cumulative window, while the selection weights of each sampling phase within the cumulative window remain unchanged. The updated selection weights for each sampling phase are read in the next cumulative window and used in the quality score calculation. The candidate bitstreams for subsequent frames are determined based on the quality score. The candidate bitstreams are subjected to cyclic redundancy check to generate a new check reliability. The new check reliability drives the selection weights to be updated again. When a programmable logic device is powered on, the selection weights of each sampling phase are reset to equal initial values.

12. A hardware acceleration system for Cyclic Redundancy Check (CRC) based on programmable logic, used to implement the hardware acceleration method for CRC based on programmable logic as described in any one of claims 1 to 11, characterized in that, include: The module includes an oversampling module, a quality initial selection module, a verification calculation module, and a feedback tuning module. The oversampling module is used to oversample the differential signal of the differential serial bus in the programmable logic device according to multiple different clock phases to obtain multiple candidate bit streams corresponding to each sampling phase. The quality initial selection module is used to construct a sampling phase quality evaluation strategy. Based on the statistical distribution characteristics of signal transition edges in each candidate bitstream and the selection weight of each sampling phase, it performs quality initial selection on multiple candidate bitstreams to determine the candidate bitstream to be checked in the current frame. The verification operation module is used to perform a remainder operation of cyclic redundancy check on the determined candidate bit stream within the programmable logic device, determine whether the verification passes based on the remainder operation result, and accumulate the verification pass results of multiple frames according to the sampling phase to obtain the verification reliability of each sampling phase. The feedback tuning module is used to construct a phase feedback tuning strategy, using the verification reliability of each sampled phase as the feedback quantity to correct the selection weight of each sampled phase in subsequent frames, so that the sampled phase selection stage and the cyclic redundancy check stage form a closed loop iteration.

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