Bit synchronization method, device and storage medium of satellite signal

Abstract

The application relates to a bit synchronization method of a satellite signal and relates to the technical field of satellite positioning. When bit synchronization is performed, the n kinds of working conditions of the received satellite signal are determined based on the original bit length n of the original ephemeris corresponding to the satellite signal to be synchronized, and the n kinds of working conditions respectively represent different timing offsets of the initial sampling unit relative to the ephemeris bit edge when the satellite signal is received; the bit synchronization of the satellite signal under the n kinds of working conditions is sequentially performed to obtain the bit synchronization results corresponding to the n kinds of working conditions, wherein, during the bit synchronization execution process of the i-1th kind of working condition, if bit synchronization fails in any one round under the working condition, the bit synchronization is switched to the i kind of working condition for execution, and 1 The bit edge of the satellite signal to be synchronized is determined based on the bit synchronization results under the n kinds of working conditions, and the bit synchronization of the satellite signal to be synchronized is performed based on the determined bit edge. In this way, the bit synchronization success rate of the satellite signal is effectively improved, and the pseudorange observation value accuracy is guaranteed.

Description

Technical Field

[0001] This article relates to the field of satellite positioning technology, and in particular to a method, device and storage medium for bit synchronization of satellite signals. Background Technology

[0002] In recent years, low-Earth orbit (LEO) satellite signals have attracted widespread attention in satellite navigation basic messages and differential correction information broadcasting scenarios due to their advantages of carrying higher information rates and supporting larger signal bandwidths. However, these signals have characteristics such as special modulation methods and high message transmission rates, posing a severe challenge to bit synchronization. When using traditional power accumulation and polarity decision-based bit synchronization schemes, millisecond-level synchronization deviations are prone to occur, leading to significant pseudorange errors. Therefore, how to achieve reliable bit synchronization for LEO navigation enhancement signals, improve the bit synchronization success rate, and ensure the accuracy of pseudorange observations has become an urgent technical problem to be solved. Summary of the Invention

[0003] This application provides a method, device, and storage medium for bit synchronization of satellite signals, which can improve the success rate of bit synchronization of satellite signals and ensure the accuracy of pseudorange observations.

[0004] This application provides a bit synchronization method for satellite signals. The satellite signal includes a first modulated signal component and a second modulated signal component. The message transmission rate of the first modulated signal component is lower than that of the second modulated signal component. The first and second modulated signal components are transmitted alternately in units of a single PRN code period. The method includes: receiving the satellite signal to be synchronized; then, determining n operating conditions for receiving the satellite signal based on the original message bit length n corresponding to the satellite signal, wherein the n operating conditions respectively characterize the initial sampling unit relative to the edge of the message bit when receiving the satellite signal. Different timing offsets are used, where n is a natural number greater than or equal to 2. Next, the satellite signals under n different operating conditions are bit synchronized sequentially to obtain the bit synchronization results for the corresponding n operating conditions. In the bit synchronization process of the i-th operating condition, if any round of bit synchronization fails under this operating condition, the bit synchronization result of the i-th operating condition is marked as a synchronization failure result, and the bit synchronization is switched to the (i+1)-th operating condition, where 1≤i<n. Finally, based on the bit synchronization results under the n operating conditions, the bit edges of the satellite signal to be synchronized are determined, and bit synchronization of the satellite signal to be synchronized is performed based on the determined bit edges.

[0005] In this embodiment, when performing bit synchronization on a satellite signal (such as a low-Earth orbit satellite signal) that includes a first modulation signal component and a second modulation signal component, and the two types of modulation signal components are transmitted alternately in a single PRN code period, the corresponding receiving conditions are determined based on the timing offset difference between the initial sampling unit and the edge of the message bit during reception. The bit edges of the satellite signal are calculated according to different receiving conditions, which effectively reduces the interference caused by the second modulation signal component, improves the bit synchronization success rate of low-Earth orbit satellite signals, and ensures the accuracy of pseudorange observations.

[0006] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the embodiments described in the description and the accompanying drawings. Attached Figure Description

[0007] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0008] Figure 1 This is a schematic diagram showing the correspondence between GNSS signal correlation values ​​and messages. Figure 2 A schematic diagram illustrating the correspondence between low-Earth orbit satellite signal correlation values ​​and messages, provided as an embodiment of this application; Figure 3 A schematic diagram illustrating the correspondence between satellite signal correlation values ​​and messages received under a first operating condition, provided as an embodiment of this application; Figure 4 A schematic diagram illustrating the correspondence between satellite signal correlation values ​​and messages received under a second operating condition, provided as an embodiment of this application. Figure 5 A schematic diagram illustrating the correspondence between satellite signal correlation values ​​and messages received under a third operating condition, provided as an embodiment of this application; Figure 6 A schematic diagram illustrating the correspondence between satellite signal correlation values ​​and messages received under the fourth operating condition, provided as an embodiment of this application; Figure 7 A flowchart illustrating a satellite signal bit synchronization method provided in this application embodiment; Figure 8 A schematic diagram of a satellite signal bit synchronization device provided in an embodiment of this application; Figure 9 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application. Detailed Implementation

[0009] This application describes several embodiments, but these descriptions are exemplary and not limiting, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0010] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application can also be combined with any conventional features or elements to form unique inventive solutions. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this application can be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes can be made within the scope of the appended claims.

[0011] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and / or process should not be limited to the steps performed in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.

[0012] The following sections will introduce the relevant solutions of this application from different aspects.

[0013] Low-Earth orbit (LEO) satellites can serve as carriers for broadcasting navigation signals and relaying enhanced information, thereby strengthening the capabilities of existing Global Navigation Satellite Systems (GNSS). LEO satellites possess advantages such as rapid changes in spatial geometry, high ground signal reception power, and the ability to achieve global space-based monitoring coverage. They can complement the strengths of GNSS constellations, comprehensively improving the accuracy, integrity, availability, and anti-interference capabilities of satellite navigation and positioning services, making them an important development direction for the next generation of satellite navigation systems.

[0014] Current low-Earth orbit (LEO) satellite signals employ a PRN code periodic time-division transmission method, using a single PRN code period as the time slot unit, with all time slots dedicated to transmitting low-speed navigation messages. Bit synchronization for LEO satellite signals can be achieved using either a histogram bit synchronization method or a traditional power accumulation synchronization method. Taking a message bit equal to 20ms as an example, the histogram bit synchronization method counts 20 candidate positions by statistically analyzing the sign transitions of adjacent 1ms integral values. When the peak value at a certain position exceeds a set threshold, that position is determined to be the message bit edge. The histogram bit synchronization method is simple to implement and suitable for signals with a carrier-to-noise ratio greater than 30dB-Hz. The traditional power accumulation synchronization method, on the other hand, accumulates the correlation values ​​of the I and Q branches within a single-bit message over multiple milliseconds to calculate the power. Multiple sets of accumulated power values ​​are obtained through sliding calculations with a 1ms step size, and the position corresponding to the maximum accumulated power value is taken as the message bit edge.

[0015] For example, Figure 1 This diagram illustrates the correspondence between correlation values ​​of GNSS signals and messages using PRN code periodic time-division transmission. For example... Figure 1 As shown, a single sampling unit at the receiver corresponds to a 1ms PRN code period. Each sampling unit outputs a correlation value L of a 1ms GNSS message signal. The end time of the 4th sampling unit corresponds to the rising edge position of the message level curve.

[0016] Continue to refer to Figure 1 ,based on Figure 1 The receiver shown in the diagram receives the relevant values ​​of the message signal. Bit synchronization is performed using the traditional power accumulation synchronization method. Assuming a single message bit duration of 4ms, the sliding window length is configured to 4ms. Using the first sampling unit as the starting point of the window, and following a 1ms step size, four different calculation windows are obtained. Figure 1 In 1. 2. 3. 4. The power accumulation value corresponding to each window is calculated based on each window.

[0017] Understandably, the traditional power accumulation method sums the I-branch and Q-branch signals of the four sampling units within a calculation window, then squares the sums and adds them together to obtain the power accumulation value corresponding to the window. In this embodiment, the power accumulation value of each sliding window is calculated under ideal, clean signal conditions: noise and interference from Code Shift Keying (CSK) are ignored, all signal energy is concentrated in the in-phase I-branch, and the Q-branch output is approximately zero. In this case, the power calculation formula can be simplified equivalently, i.e. After obtaining the power accumulation values ​​corresponding to the four calculation windows, the largest power accumulation value and its corresponding index are selected. Then, a histogram search is used to determine the bit edges, ultimately completing bit synchronization, extraction of the original message and observations, followed by frame synchronization, and finally, location calculation. That is, from... 1. 2. 3. Filter the maximum power accumulation value from the power accumulation values ​​corresponding to 4. 1, The calculation window corresponding to 1 is sampling units 1 to 4, that is, the rising edge position of the message level curve at the end of the 4th sampling unit, which is exactly the same as... Figure 1 The rising edge positions of the text message level curves are the same.

[0018] When transmitting low-Earth orbit (LEO) signals, a periodic time-division multiplexing modulation scheme using PRN code is employed to alternately transmit low-speed and high-speed messages in units of a single PRN code cycle. The low-speed message signal uses Binary Phase-Shift Keying (BPSK) modulation, while the high-speed message signal uses CSK modulation. Therefore, this LEO signal requires the low-speed message signal for bit synchronization and tracking. In this case, the correlation value of the high-speed message signal is essentially accumulated noise; that is, the millisecond correlation values ​​within each bit of the message are not necessarily true correlation peaks. While traditional power accumulation methods can achieve bit synchronization for LEO signals, there is a certain probability of millisecond-level bit synchronization errors, rendering pseudorange observations unusable.

[0019] For example, such as Figure 2 As shown, assuming the duration of a single message bit is 4ms, the sliding window length is configured to 4ms. Using the first sampling unit as the starting point of the window, and following a 1ms step size, four different calculation windows are obtained. Figure 2 In 1. 2. 3. 4. Based on each window, the cumulative power value corresponding to that window is calculated. Since the modulation signal component corresponding to the high-speed message uses CSK modulation, its correlation value H is a random quantity with a statistical expectation close to zero. Therefore, under the statistical average meaning, the H term can be approximately ignored, and only the modulation signal component L corresponding to the low-speed message is retained.

[0020] from 1. 2. 3. 4. Filter out the maximum cumulative power value and index. The maximum cumulative power value obtained at this point may be... 1 could also be 4. Reference Figure 2 It can be seen that if the maximum power accumulation value selected is... 1. This allows for bit synchronization of the low-orbit signal and the calculation of the correct pseudorange observation; if the selected maximum power accumulation value is... 4. Although bit synchronization of low-orbit signals can still be achieved, pseudorange observation errors of milliseconds may occur.

[0021] Therefore, neither the histogram bit synchronization method nor the traditional power accumulation synchronization method is suitable for bit synchronization processing of satellite signals that simultaneously carry BPSK low-speed messages and CSK high-speed messages.

[0022] Therefore, this application provides a bit synchronization method for satellite signals, which can be used to synchronize low-Earth orbit (LEO) satellite signals. When synchronizing received satellite signals, based on the original message bit length *n* corresponding to the satellite signal to be synchronized, *n* operating conditions for receiving the satellite signal to be synchronized are determined. These *n* operating conditions represent different timing offsets of the initial sampling unit relative to the message bit edge when receiving the satellite signal, where *n* is a natural number greater than or equal to 1. Then, the satellite signals under the *n* operating conditions are sequentially synchronized to obtain the bit synchronization results for each of the *n* operating conditions. Next, based on the bit synchronization results under the *n* operating conditions, the bit edge of the satellite signal to be synchronized is determined, and bit synchronization is performed on the satellite signal to be synchronized based on the determined bit edge. This avoids problems such as bit decision errors and synchronization probability misjudgments in satellite signals, and enables rapid bit synchronization of satellite signals simultaneously carrying BPSK low-speed messages and CSK high-speed messages, while ensuring the bit synchronization success rate and the accuracy of pseudorange observations.

[0023] Next, continue to combine Figure 2 The technical concept of a satellite signal bit synchronization method provided in the embodiments of this application is introduced.

[0024] The core objective of bit synchronization is to locate the bit edges of the message, thereby completing the demodulation of the original message and the extraction of pseudorange observations. Figure 2 Taking the message signal shown as an example, the symbol rate of the low-speed message signal after time-division multiplexing of the code period is 250 sps, corresponding to a duration of 4 ms for a single original message bit. Under this condition, the message signal received by the receiving end has four corresponding bit edge situations, that is, the message signal received by the receiving end can be divided into four working conditions. In the first working condition, the receiving end starts receiving the signal from the sampling unit corresponding to index 1, where the start time of the sampling unit corresponding to index 1 corresponds to the message bit edge; in the second working condition, the receiving end starts receiving the signal from the sampling unit corresponding to index 2; in the third working condition, the receiving end starts receiving the signal from the sampling unit corresponding to index 3; in the fourth working condition, the receiving end starts receiving the signal from the sampling unit corresponding to index 4, where the end time of the sampling unit corresponding to index 4 corresponds to the message bit edge.

[0025] After receiving the message signal, the receiving end performs a bit synchronization calculation for the message signal, which includes bit synchronization calculations under four different operating conditions. The bit synchronization calculation is executed sequentially according to the first, second, third, and fourth operating conditions: if the bit synchronization calculation in the previous operating condition fails, it switches to the next operating condition; if the calculation in the fourth operating condition also fails, it returns to the first operating condition and repeats the process until the current bit synchronization calculation succeeds, fails, or the runtime of the current bit synchronization calculation exceeds a preset time threshold.

[0026] A successful bit synchronization calculation means that the number of successful bit synchronizations under any given operating condition is greater than or equal to a preset success threshold; a failed bit synchronization calculation means that the number of successful bit synchronizations under at least two operating conditions is greater than or equal to a preset failure threshold. During bit synchronization under any operating condition, if a round of bit synchronization calculation is successful, the number of successful bit synchronizations under that condition is incremented by 1, and subsequent rounds of bit synchronization calculations under that condition continue. If a round of bit synchronization calculation fails, the process switches to the next operating condition for bit synchronization calculation.

[0027] For example, threshold values ​​for successful or failed bit synchronization can be preset based on the low-Earth orbit satellite message rate. For instance, a success threshold of successTh = 7 and a failure threshold of failTh = 3 can be set, with a time limit of 3 seconds for each bit synchronization operation.

[0028] like Figure 3 As shown, in the first operating condition, the receiver receives at least the correlation values ​​from the 1st to the 8th millisecond. Taking the sampling unit corresponding to index 1 as the starting point of the window, and following a step size of 1ms, four different calculation windows are obtained, namely... Figure 3 In 1. 2. 3 and 4. Based on each window, the cumulative power value corresponding to that window is calculated, where, Next, from 1. 2. 3 and From the power accumulation values ​​corresponding to 4, select the maximum power accumulation value, the second largest power accumulation value, the minimum power accumulation value, and their corresponding indices, namely maxPower=2L, maxIndex=0; secondMaxPower =2L, secondMaxIndex=3; minPower =0, minIndex=2.

[0029] Next, based on the selected minimum power accumulation value, the synchronization power threshold for this bit synchronization is set. Set the initial value of the index count toggleCnt to 0.

[0030] Next, the message bit synchronization determination conditions are set for the first operating condition. Condition 1: maxPower > And secondMaxPower > ; Judgment condition 2: maxIndex=0 and secondMaxIndex=3, or maxIndex=3 and secondMaxIndex=0. Only when the maximum power accumulation value, the second largest power accumulation value and their index are simultaneously satisfied with conditions 1 and 2, index 0 is transmitted to the histogram for detection, and the index count toggleCnt [0] in the histogram is incremented by 1.

[0031] If the maximum power accumulation value, the second largest power accumulation value, and their corresponding indices obtained in this round of calculation simultaneously satisfy conditions 1 and 2, then the next round of bit synchronization calculation for the first operating condition continues. The bit synchronization calculation process for each round is consistent with the first round, and the starting position of the first sliding window in the next round is the next sampling unit after the starting position of the last sliding window in the previous round. For example, in the first operating condition, the starting point of the first sliding window in the second round of bit synchronization calculation is the sampling unit corresponding to index 5.

[0032] If the maximum power accumulation value, the second largest power accumulation value and their corresponding index obtained in this round of calculation fail to satisfy both conditions 1 and 2 at the same time, then the bit synchronization calculation under the second working condition will be performed.

[0033] After each round of bit synchronization calculation, it is necessary to determine whether the index count toggleCnt[0] in the histogram is equal to the success threshold value successTh, whether there are at least two index counts toggleCnt in the histogram that are greater than or equal to the failure threshold value failureTh, and whether the bit synchronization time exceeds the time limit.

[0034] For example, first determine whether the index count toggleCnt[0] in the histogram is equal to the success threshold value successTh. If the index count toggleCnt[0] in the histogram is equal to the success threshold value successTh, then the bit synchronization can be considered successful, the bit synchronization can be stopped, and the end time of the last sampling unit of the calculation window corresponding to index 0 in the first working condition can be taken as the edge of the message bit.

[0035] If the index count toggleCnt[0] in the histogram is not equal to the success threshold successTh, continue to determine if there are at least two index counts toggleCnt greater than or equal to the failure threshold failureTh in the histogram. If so, the current bit synchronization is considered to have failed, and bit synchronization needs to be performed again. If the number of index counts toggleCnt greater than or equal to the failure threshold failureTh in the histogram is less than 2, it is necessary to continue to determine if the current bit synchronization time has exceeded the preset time limit. If the current bit synchronization time has exceeded the preset time limit, the current bit synchronization has failed, the channel needs to be reported as unlocked, and a new bit synchronization needs to be performed.

[0036] like Figure 4 As shown, in the second operating condition, the receiver receives at least the correlation values ​​from the 2nd to the 9th millisecond. Taking the sampling unit corresponding to index 2 as the starting point of the window, and with a step size of 1ms, four different calculation windows are obtained, namely... Figure 4 In 1. 2. 3 and 4. Based on each window, the cumulative power value corresponding to that window is calculated, where, Next, from 1. 2. 3 and From the power accumulation values ​​corresponding to 4, select the maximum power accumulation value, the second largest power accumulation value, the minimum power accumulation value, and their corresponding indices, namely maxPower=2L, maxIndex=2; secondMaxPower =2L, secondMaxIndex=3; minPower =0, minIndex=0.

[0037] Next, based on the selected minimum power accumulation value, the synchronization power threshold for this bit synchronization is set. Set the initial value of the index count toggleCnt to 0.

[0038] Next, the message bit synchronization determination condition for the second operating condition is set. Condition 3: maxPower > And secondMaxPower > ; Judgment condition 4: maxIndex=2 and secondMaxIndex=3, or maxIndex=3 and secondMaxIndex=2. Only when the maximum power accumulation value, the second largest power accumulation value and their index are simultaneously satisfied with conditions 3 and 4, index 3 is transmitted to the histogram for detection, and the index count toggleCnt [3] in the histogram is incremented by 1.

[0039] If the maximum power accumulation value, the second largest power accumulation value, and their corresponding indices obtained in this round of calculation simultaneously satisfy conditions 3 and 4, then the next round of bit synchronization calculation for the second operating condition continues. The bit synchronization calculation process for each round is consistent with the first round, and the starting position of the first sliding window in the next round is the next sampling unit after the starting position of the last sliding window in the previous round. For example, in the second operating condition, the starting point of the first sliding window in the second round of bit synchronization calculation is the sampling unit corresponding to index 6.

[0040] If the maximum power accumulation value, the second largest power accumulation value and their corresponding index obtained in this round of calculation fail to simultaneously satisfy conditions 3 and 4, then bit synchronization calculation under the third working condition will be performed.

[0041] After each round of bit synchronization calculation, it is necessary to determine whether the index count toggleCnt[3] in the histogram is equal to the success threshold value successTh, whether there are at least two index counts toggleCnt in the histogram that are greater than or equal to the failure threshold value failureTh, and whether the bit synchronization time exceeds the time limit.

[0042] For example, first determine whether the index count toggleCnt [3] in the histogram is equal to the success threshold value successTh. If the index count toggleCnt [3] in the histogram is equal to the success threshold value successTh, then the bit synchronization can be considered successful, the bit synchronization can be stopped, and the end time of the last sampling unit of the calculation window corresponding to index 3 in the second working condition can be taken as the edge of the message bit.

[0043] If the index count toggleCnt [3] in the histogram is not equal to the success threshold value successTh, continue to determine whether there are at least two index counts toggleCnt in the histogram that are greater than or equal to the failure threshold value failTh. If so, it can be considered that the current bit synchronization has failed and bit synchronization needs to be performed again. If the number of index counts toggleCnt in the histogram that are greater than or equal to the failure threshold value failTh is less than 2, it is necessary to continue to determine whether the current bit synchronization time has exceeded the preset time limit. If the current bit synchronization time has exceeded the preset time limit, the current bit synchronization has failed, the channel needs to be reported as lost, and a new bit synchronization needs to be performed.

[0044] like Figure 5 As shown, in the third operating condition, the receiver receives at least the correlation values ​​from the 3rd to the 10th millisecond. Using the sampling unit corresponding to index 3 as the starting point of the window, and following a 1ms step size, four different calculation windows are obtained. Figure 5 In 1. 2. 3 and 4. Based on each window, the cumulative power value corresponding to that window is calculated, where, Next, from 1. 2. 3 and From the power accumulation values ​​corresponding to 4, select the maximum power accumulation value, the second largest power accumulation value, the minimum power accumulation value, and their corresponding indices, namely maxPower=2L, maxIndex=1; secondMaxPower =2L, secondMaxIndex=2; minPower =0, minIndex=0.

[0045] Next, based on the selected minimum power accumulation value, the synchronization power threshold for this bit synchronization is set. Set the initial value of the index count toggleCnt to 0.

[0046] Next, the message bit synchronization determination condition for the third operating condition is set. Condition 5: maxPower > And secondMaxPower > ; Judgment condition 6: maxIndex=1 and secondMaxIndex=2, or maxIndex=2 and secondMaxIndex=1. Only when the maximum power accumulation value, the second largest power accumulation value and their index are simultaneously satisfied with conditions 5 and 6, index 2 is transmitted to the histogram for detection, and the index count toggleCnt [2] in the histogram is incremented by 1.

[0047] If the maximum power accumulation value, the second largest power accumulation value, and their corresponding indices obtained in this round of calculation simultaneously satisfy conditions 5 and 6, then the next round of bit synchronization calculation under this condition continues. The bit synchronization calculation process for each round is consistent with the first round, and the starting position of the first sliding window in the next round is the next sampling unit after the starting position of the last sliding window in the previous round. For example, in the third condition, the starting point of the first sliding window in the second round of bit synchronization calculation is the sampling unit corresponding to index 7.

[0048] If the maximum power accumulation value, the second largest power accumulation value and their corresponding index obtained in this round of calculation fail to simultaneously satisfy conditions 5 and 6, then bit synchronization calculation under the fourth operating condition will be performed.

[0049] After each round of bit synchronization calculation, it is necessary to determine whether the index count toggleCnt[2] in the histogram is equal to the success threshold value successTh, whether there are at least two index counts toggleCnt in the histogram that are greater than or equal to the failure threshold value failureTh, and whether the bit synchronization time exceeds the time limit.

[0050] For example, first determine whether the index count toggleCnt [2] in the histogram is equal to the success threshold value successTh. If the index count toggleCnt [2] in the histogram is equal to the success threshold value successTh, then the bit synchronization can be considered successful, the bit synchronization can be stopped, and the end time of the last sampling unit of the calculation window corresponding to index 2 in the third working condition can be taken as the edge of the message bit.

[0051] If the index count toggleCnt [2] in the histogram is not equal to the success threshold value successTh, continue to determine whether there are at least two index counts toggleCnt in the histogram that are greater than or equal to the failure threshold value failTh. If so, the bit synchronization can be considered to have failed and bit synchronization needs to be performed again. If the number of index counts toggleCnt in the histogram that are greater than or equal to the failure threshold value failTh is less than 2, it is necessary to continue to determine whether the bit synchronization time has exceeded the preset time limit. If the bit synchronization time has exceeded the preset time limit, the bit synchronization has failed and the channel needs to be reported as lost, and a new bit synchronization needs to be performed.

[0052] like Figure 6 As shown, in the fourth operating condition, the receiver receives at least the correlation values ​​from the 4th to the 11th millisecond. Using the sampling unit corresponding to index 4 as the starting point of the window, and following a 1ms step size, four different calculation windows are obtained. Figure 6 In 1. 2. 3 and 4. Based on each window, the cumulative power value corresponding to that window is calculated, where, Next, from 1. 2. 3 and From the power accumulation values ​​corresponding to 4, select the maximum power accumulation value, the second largest power accumulation value, the minimum power accumulation value, and their corresponding indices, namely maxPower=2L, maxIndex=0; secondMaxPower =2L, secondMaxIndex=1; minPower =0, minIndex=2.

[0053] Next, based on the selected minimum power accumulation value, the synchronization power threshold for this bit synchronization is set. Set the initial value of the index count toggleCnt to 0.

[0054] Next, the message bit synchronization determination condition for the second operating condition is set. Condition 7: maxPower > And secondMaxPower > ; Judgment condition 8: maxIndex=0 and secondMaxIndex=1, or maxIndex=1 and secondMaxIndex=0. Only when the maximum power accumulation value, the second largest power accumulation value and their index are simultaneously satisfied with conditions 7 and 8, index 1 is transmitted to the histogram for detection, and the index count toggleCnt [1] in the histogram is incremented by 1.

[0055] If the maximum power accumulation value, the second largest power accumulation value, and their corresponding indices obtained in this round of calculation simultaneously satisfy conditions 7 and 8, then the next round of bit synchronization calculation under this condition continues. The bit synchronization calculation process for each round is consistent with the first round, and the starting position of the first sliding window in the next round is the next sampling unit after the starting position of the last sliding window in the previous round. For example, in the fourth condition, the starting point of the first sliding window in the second round of bit synchronization calculation is the sampling unit corresponding to index 8.

[0056] If the maximum power accumulation value, the second largest power accumulation value and their corresponding index obtained in this round of calculation fail to simultaneously satisfy conditions 7 and 8, then the bit synchronization calculation under the first working condition will be performed.

[0057] After each round of bit synchronization calculation, it is necessary to determine whether the index count toggleCnt[1] in the histogram is equal to the success threshold value successTh, whether there are at least two index counts toggleCnt in the histogram that are greater than or equal to the failure threshold value failureTh, and whether the bit synchronization time exceeds the time limit.

[0058] For example, first determine whether the index count toggleCnt [1] in the histogram is equal to the success threshold value successTh. If the index count toggleCnt [1] in the histogram is equal to the success threshold value successTh, then the bit synchronization can be considered successful, the bit synchronization can be stopped, and the end time of the last sampling unit of the calculation window corresponding to index 3 in the second working condition can be taken as the edge of the message bit.

[0059] If the index count toggleCnt [1] in the histogram is not equal to the success threshold value successTh, continue to determine whether there are at least two index counts toggleCnt in the histogram that are greater than or equal to the failure threshold value failTh. If so, the bit synchronization can be considered to have failed and bit synchronization needs to be performed again. If the number of index counts toggleCnt in the histogram that are greater than or equal to the failure threshold value failTh is less than 2, it is necessary to continue to determine whether the bit synchronization time has exceeded the preset time limit. If the bit synchronization time has exceeded the preset time limit, the bit synchronization has failed, the channel needs to be reported as lost, and a new bit synchronization needs to be performed.

[0060] It is understood that the above technical concept, in which the duration of a single original message bit received by the receiving end is 4ms and the message signal has 4 bit edge corresponding conditions, is only an illustrative example and not a limitation on the embodiments of this application. In the embodiments of this application, the duration of the original message bit can be extended to N milliseconds, where N takes any reasonable value. In this case, the message signal received by the receiving end corresponds to N bit edge conditions.

[0061] It is understood that in the above technical concept, setting the duration of a single original message bit to 4ms and configuring the length of the sliding window used for bit synchronization to 4ms, corresponding to 4 sampling units, is merely an illustrative example and not a limitation on the embodiments of this application. In the embodiments of this application, the length of the sliding window can be set to be less than or equal to the duration of a single original message bit, for example, it can be configured as 1ms (1 sampling unit), 2ms (2 sampling units), 3ms (3 sampling units), or 4ms (4 sampling units). When the length of the sliding window is set to be equal to the duration of a single original message bit, each round of bit synchronization calculation can cover the complete message bit time interval, thus providing a larger range of signal data for analysis and comparison. This allows for full utilization of the signal accumulation information within the complete bit period, accelerating the identification speed of message bit edges and achieving faster bit synchronization.

[0062] Next, based on the above technical concept, a bit synchronization method for satellite signals provided in an embodiment of this application will be described. It is understood that this method can be executed by any device, equipment, or platform with computing and processing capabilities. For example, this method can be executed by a first computing device. For ease of description, the first computing device will be used as the execution subject in the following description. Figure 7 As shown, the engine fault diagnosis method includes steps 710 to 740.

[0063] Step 710: Receive the satellite signal to be synchronized.

[0064] In this step, the satellite signal to be synchronized received by the first computing device includes a first modulation signal component and a second modulation signal component. The message transmission rate of the first modulation signal component is less than that of the second modulation signal component. The first modulation signal component and the second modulation signal component are transmitted alternately in units of a single PRN code period. That is, the first modulation signal component corresponds to the low-speed signal in the above embodiment, and the second modulation signal component corresponds to the high-speed signal in the above embodiment.

[0065] In one possible example, the first modulation signal component is a low-speed message signal modulated by BPSK, and the second modulation signal component is a high-speed message signal modulated by CSK.

[0066] Step 720: Based on the original message bit length n corresponding to the satellite signal to be synchronized, determine n operating conditions for receiving the satellite signal to be synchronized.

[0067] In this step, the n operating conditions represent different timing offsets of the initial sampling unit relative to the edge of the message bits when receiving satellite signals, where n is a natural number greater than or equal to 2.

[0068] It is understandable that when n equals 1, there is only one receiving condition, so there is no need to execute the condition switching logic in step 730, and bit synchronization processing can be performed directly based on this unique condition.

[0069] For example, if the original message bit length corresponding to the satellite signal to be synchronized is 4 sampling units, then the message signal received by the receiving end can be divided into 4 operating conditions. Among them, in operating condition 1, the receiving end starts receiving the signal from the sampling unit corresponding to index 1, where the start time of the sampling unit corresponding to index 1 corresponds to the edge of the message bit; in operating condition 2, the receiving end starts receiving the signal from the sampling unit corresponding to index 2; in operating condition 3, the receiving end starts receiving the signal from the sampling unit corresponding to index 3; in operating condition 4, the receiving end starts receiving the signal from the sampling unit corresponding to index 4, where the end time of the sampling unit corresponding to index 4 corresponds to the edge of the message bit.

[0070] Step 730: Perform bit synchronization on the satellite signal under n different operating conditions in sequence to obtain the bit synchronization results for the corresponding n operating conditions. In the bit synchronization process of the i-th operating condition, if any round of bit synchronization fails under the operating condition, the bit synchronization result of the i-th operating condition is marked as a synchronization failure result, and the bit synchronization is switched to the (i+1)-th operating condition, where 1≤i<n.

[0071] In this step, the first computing device can perform at least one bit synchronization on the satellite signal to be synchronized based on n operating conditions. In any bit synchronization process, for the i-th operating condition in the n-th operating condition, at least one round of bit synchronization is performed.

[0072] For example, consider any round of bit synchronization under the i-th operating condition. During this round of bit synchronization, the initial sampling unit is used as the starting position of the sliding window, and the length of the sliding window is L sampling units, where L is a natural number and 1≤L≤n. The sliding window is obtained by sliding with a step size of one sampling unit, resulting in n calculation windows. Next, the first computing device calculates the power accumulation value of each calculation window and performs bit synchronization based on the power accumulation value of each calculation window. If bit synchronization is successful, the hit count value corresponding to the edge position of the message bit under the i-th operating condition is incremented by 1, and a new round of bit synchronization under the i-th operating condition is executed; if bit synchronization fails, the system switches to the (i+1)-th operating condition and performs at least one round of bit synchronization under the (i+1)-th operating condition.

[0073] Understandably, the length of the sliding window can be set to be less than or equal to the duration of a single original message bit. When the length of the sliding window is equal to the duration of a single original message bit, each round of bit synchronization calculation can cover the entire message bit time interval. Therefore, the range of signal data available for analysis and comparison is larger, enabling full utilization of the signal accumulation information within the complete bit period, accelerating the identification speed of message bit edges, and achieving faster bit synchronization.

[0074] In one possible example, the first computing device calculates the power accumulation value for each computing window by: for any given computing window, the first computing device accumulates the I-branch and Q-branch corresponding to the first modulated signal component in the received satellite signal within that computing window, respectively, to obtain the accumulated sums corresponding to the I-branch and the Q-branch. Then, the first computing device squares the accumulated sums of the I-branch and the Q-branch respectively, and adds the squared results of the I-branch and Q-branch to obtain the power accumulation value for that computing window. Based on the minimum power accumulation value, the synchronization power threshold is determined. In one possible example, bit synchronization by the first computing device based on the power accumulation value of each computing window includes: the first computing device filtering out the maximum power accumulation value, the second largest power accumulation value, and the minimum power accumulation value from the power accumulation values ​​of each window. Next, the first computing device determines a synchronization power threshold value based on the minimum power accumulation value. Then, the first computing device determines whether the maximum power accumulation value and the second largest power accumulation value are both greater than the synchronization power threshold value, and whether the starting positions of the computing windows corresponding to the maximum power accumulation value and the second largest power accumulation value satisfy a preset position condition. The preset position condition is a pre-configured window index correspondence relationship for different operating conditions, used to limit the correspondence constraints between the computing window indices corresponding to the maximum power accumulation value and the second largest power accumulation value. For example, in the above embodiment, under operating condition 1, the preset position condition is that the window index corresponding to the maximum power accumulation value and the window index corresponding to the second largest power accumulation value are 0 and 3, or 3 and 0, respectively.

[0075] It is understood that, in the embodiments of this application, the window index refers to the number assigned to each calculation window obtained by multiple sliding according to the order in which the sliding was generated, and is used to identify different calculation windows.

[0076] If both the maximum power accumulation value and the second largest power accumulation value are greater than the synchronization power threshold, and the starting positions of the calculation windows corresponding to the maximum power accumulation value and the second largest power accumulation value respectively meet the preset position conditions, the bit synchronization is determined to be successful; then, the first calculation device selects the calculation window with the earlier starting position between the calculation window corresponding to the maximum power accumulation value and the calculation window corresponding to the second largest power accumulation value, and takes the end time of the last sampling unit of the calculation window as the edge of the message bit obtained in this round of bit synchronization; If either the maximum power accumulation value or the second largest power accumulation value is not greater than the synchronization power threshold, or if either the starting position of the calculation window corresponding to the maximum power accumulation value or the second largest power accumulation value does not meet the preset position condition, then bit synchronization is determined to have failed.

[0077] In one possible example, the synchronous power threshold is equal to the minimum power accumulation value plus the preset proportional component corresponding to the minimum power accumulation value.

[0078] In one possible example, the hit count is the histogram statistics count.

[0079] Step 740: Based on the bit synchronization results under n operating conditions, determine the bit edges of the satellite signal to be synchronized, and perform bit synchronization on the satellite signal to be synchronized based on the determined bit edges.

[0080] In this step, after each round of bit synchronization under each operating condition, the first computing device needs to determine whether the bit synchronization hit count under each operating condition is successful and compare it with the preset bit synchronization success threshold and bit synchronization failure threshold.

[0081] In one possible example, the first computing device determines whether the hit count value corresponding to the edge position of the message bit for the i-th operating condition is equal to a preset bit synchronization success threshold.

[0082] If the hit count value corresponding to the message bit edge position of the i-th working condition is equal to the preset bit synchronization success threshold, the first computing device takes the message bit edge position corresponding to the i-th working condition as the bit edge of the satellite signal to be synchronized, and performs bit synchronization on the satellite signal to be synchronized based on the determined bit edge position. If the hit count value corresponding to the edge position of the message bit in the i-th working condition is less than the preset bit synchronization success threshold, the first computing device determines whether there are at least two working conditions whose hit count values ​​are greater than or equal to the preset bit failure threshold. If there are at least two operating conditions whose hit count values ​​are greater than or equal to the preset bit failure threshold, the first computing device determines that the bit synchronization has failed. If the hit count value corresponding to the two working conditions is greater than or equal to the preset bit failure threshold, the first computing device determines whether the bit synchronization time is greater than the preset time threshold. If the total bit synchronization time is greater than the preset time threshold, the first computing device determines that the bit synchronization has failed. If the total bit synchronization time is not greater than the preset time threshold, perform a new round of bit synchronization under the i-th working condition, or switch to the (i+1)-th working condition and perform at least one round of bit synchronization under the (i+1)-th working condition.

[0083] When performing bit synchronization on a satellite signal containing a first modulation signal component and a second modulation signal component, and the two types of modulation signal components are transmitted alternately in a single PRN code period, the corresponding receiving conditions are determined based on the timing offset difference between the initial sampling unit and the edge of the message bit during reception. The bit edges of the satellite signal are calculated according to different receiving conditions, which effectively reduces the interference caused by the second modulation signal component, improves the success rate of satellite signal bit synchronization, and ensures the accuracy of pseudorange observations.

[0084] In one possible example, the bit synchronization success threshold could be set to 7, and the bit failure threshold could be set to 3.

[0085] Next, a specific example will be used to illustrate the performance of the satellite signal bit synchronization of the transmission component provided in this application.

[0086] For example, Table 1 shows the pseudorange residuals calculated after bit synchronization based on the traditional power accumulation bit synchronization method. Understandably, when bit synchronization is accurate, the receiver clock error, as a common bias, can be absorbed by the positioning calculation, and the residual value is relatively small when the clock error component is retained in the pseudorange residual. However, if a millisecond-level error occurs in bit synchronization, it will introduce a pseudorange bias unique to each satellite. This bias cannot be compensated for by the clock error, resulting in a significant increase in the pseudorange residual. As shown in Table 1, the traditional power accumulation-based bit synchronization method is prone to millisecond-level errors in pseudorange observations. As shown in Table 1, a total of 6 satellites were acquired, of which PRN1 and PRN38 experienced bit synchronization errors.

[0087] For example, Table 2 shows the pseudorange residuals calculated after bit synchronization based on the bit synchronization method provided in the embodiments of this application. As can be seen from Table 2, the bit synchronization method for satellite signals provided in this application was used to verify the bit synchronization of multiple low-orbit satellite signals, and the aforementioned pseudo-range error of milliseconds did not occur.

[0088] Based on the methods in the above embodiments, this application also provides a bit synchronization device for satellite signals.

[0089] For example, Figure 8 A schematic diagram of a fault diagnosis device for a transmission component provided in an embodiment of this application is shown. Figure 8 As shown, the fault diagnosis device 800 includes a receiving module 801 and a synchronization module 802. The receiving module 801 receives the satellite signal to be synchronized. The synchronization module 802 determines n operating conditions for receiving the satellite signal based on the original message bit length n corresponding to the satellite signal. Each of the n operating conditions represents a different timing offset of the initial sampling unit relative to the message bit edge when receiving the satellite signal, where n is a natural number greater than or equal to 2. Next, the synchronization module 802 sequentially performs bit synchronization on the satellite signal under each of the n operating conditions, obtaining the bit synchronization results for each of the n operating conditions. During the bit synchronization execution of the i-th operating condition, if any round of bit synchronization fails under that condition, the bit synchronization result for that i-th operating condition is marked as a synchronization failure, and the process switches to the (i+1)-th operating condition for bit synchronization, where 1 ≤ i < n. Finally, based on the bit synchronization results under the n operating conditions, the synchronization module 802 determines the bit edges of the satellite signal to be synchronized and performs bit synchronization on the satellite signal to be synchronized based on the determined bit edges.

[0090] In one possible example, when synchronization unit 802 sequentially performs bit synchronization on satellite signals under n operating conditions, synchronization unit 802 performs bit synchronization on the satellite signals at least once based on the n operating conditions. During any bit synchronization process, synchronization unit 802 performs at least one round of bit synchronization for the i-th operating condition among the n operating conditions. Specifically, during any round of bit synchronization, synchronization unit 802 uses the initial sampling unit as the starting position of the sliding window, the length of the sliding window is L sampling units, and one sampling unit is used as the step size. The process proceeds sequentially to obtain n calculation windows, where L is a natural number, 1≤L≤n. Next, the synchronization unit 802 calculates the power accumulation value of each calculation window and performs bit synchronization based on the power accumulation value of each calculation window. If bit synchronization is successful, the synchronization unit 802 increments the hit count value corresponding to the edge position of the message bit in the i-th working condition by 1 and performs a new round of bit synchronization in the i-th working condition. If bit synchronization fails, the synchronization unit 802 switches to the (i+1)-th working condition and performs at least one round of bit synchronization in the (i+1)-th working condition.

[0091] In one possible example, the first modulation signal component is a low-speed message signal modulated by binary phase shift keying (BPSK), and the second modulation signal component is a high-speed message signal modulated by code shift keying (CSK). When the synchronization unit 802 calculates the power accumulation value for each calculation window, for any calculation window, the synchronization unit 802 accumulates the I-branch and Q-branch corresponding to the first modulation signal component in the received satellite signal within the calculation window, respectively, to obtain the accumulation sums corresponding to the I-branch and Q-branch; then, the synchronization unit squares the accumulation sums of the I-branch and Q-branch respectively, and adds the squared results of the I-branch and Q-branch to obtain the power accumulation value of the calculation window.

[0092] In one possible example, when the synchronization unit 802 performs bit synchronization based on the power accumulation value of each calculation window, the synchronization unit 802 filters out the maximum power accumulation value, the second largest power accumulation value, and the minimum power accumulation value from the power accumulation values ​​of each window; then, the synchronization unit 802 determines a synchronization power threshold value based on the minimum power accumulation value; next, the synchronization unit 802 determines whether the maximum power accumulation value and the second largest power accumulation value are both greater than the synchronization power threshold value, and whether the starting position of the calculation window corresponding to the maximum power accumulation value and the second largest power accumulation value meets the preset position conditions; If both the maximum power accumulation value and the second largest power accumulation value are greater than the synchronization power threshold, and the starting positions of the calculation windows corresponding to the maximum power accumulation value and the second largest power accumulation value respectively meet the preset position conditions, the synchronization unit 802 determines that the bit synchronization is successful; then, the synchronization unit 802 selects the calculation window with the earlier starting position between the calculation window corresponding to the maximum power accumulation value and the calculation window corresponding to the second largest power accumulation value, and takes the end time of the last sampling unit of the calculation window as the edge of the message bit obtained in this round of bit synchronization; If either the maximum power accumulation value or the second largest power accumulation value is not greater than the synchronization power threshold, or if either the starting position of the calculation window corresponding to the maximum power accumulation value or the second largest power accumulation value does not meet the preset position condition, the synchronization unit 802 determines that bit synchronization has failed.

[0093] In one possible example, the synchronous power threshold is equal to the minimum power accumulation value plus the preset proportional component corresponding to the minimum power accumulation value.

[0094] In one possible example, before performing a new round of bit synchronization under the i-th operating condition, or switching to the (i+1)-th operating condition and performing at least one round of bit synchronization under the (i+1)-th operating condition, the synchronization unit 802 is further configured to determine whether the hit count value corresponding to the message bit edge position corresponding to the i-th operating condition is equal to a preset bit synchronization success threshold; if the hit count value corresponding to the message bit edge position corresponding to the i-th operating condition is equal to the preset bit synchronization success threshold, the message bit edge position corresponding to the i-th operating condition is used as the bit edge of the satellite signal to be synchronized, and bit synchronization is performed on the satellite signal to be synchronized based on the determined bit edge position; if the hit count value corresponding to the message bit edge position corresponding to the i-th operating condition is less than the preset threshold, the synchronization unit 802 is further configured to determine whether the hit count value corresponding to the message bit edge position is equal to the preset threshold. The system determines whether there are at least two working conditions whose hit counts are greater than or equal to a preset bit synchronization failure threshold. If there are at least two working conditions whose hit counts are greater than or equal to the preset bit synchronization failure threshold, the current bit synchronization is determined to have failed. If there are less than two working conditions whose hit counts are greater than or equal to the preset bit synchronization failure threshold, the system determines whether the current bit synchronization time is greater than a preset time threshold. If the total bit synchronization time is greater than the preset time threshold, the current bit synchronization is determined to have failed. If the total bit synchronization time is not greater than the preset time threshold, the system executes a new round of bit synchronization under the i-th working condition, or switches to the (i+1)-th working condition and executes at least one round of bit synchronization under the (i+1)-th working condition before executing the pending operation.

[0095] In one possible example, the hit count is the histogram statistics count.

[0096] This application also provides a computing device 700. For example... Figure 9As shown, the computing device 900 includes a bus 902, a processor 904, a memory 906, and a communication interface 908. The processor 904, the memory 906, and the communication interface 908 communicate with each other via the bus 902. The computing device 900 can be a server or an electronic device. It should be understood that this application does not limit the number of processors and memories in the computing device 900.

[0097] The 902 bus can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of representation, Figure 9 The bus 902 may be represented by a single line, but this does not mean that there is only one bus or one type of bus. The bus 902 may include a path for transmitting information between various components of the computing device 900 (e.g., memory 906, processor 904, communication interface 908).

[0098] Processor 904 may include any one or more processors such as a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), or a digital signal processor (DSP).

[0099] Memory 906 may include volatile memory, such as random access memory (RAM). Memory 906 may also include non-volatile memory, such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid state drive (SSD).

[0100] The memory 906 stores executable program code, and the processor 904 executes the executable program code to implement the aforementioned functions respectively. Figure 8 The receiving module 801 and the synchronization module 802 perform their functions to implement the bit synchronization method for satellite signals described in the above embodiments. That is, the memory 906 stores instructions for executing the bit synchronization method for satellite signals described in the above embodiments.

[0101] The communication interface 908 uses transceiver modules, such as, but not limited to, network interface cards and transceivers, to enable communication between the computing device 900 and other devices or communication networks.

[0102] Based on the methods in the above embodiments, this application provides a computer-readable storage medium storing a computer program that, when run on a processor, causes the processor to execute the methods in the above embodiments.

[0103] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term "computer storage medium" includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0104] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A method for bit synchronization of satellite signals, characterized in that, The satellite signal includes a first modulated signal component and a second modulated signal component. The message transmission rate of the first modulated signal component is less than that of the second modulated signal component. The first modulated signal component and the second modulated signal component are transmitted alternately in units of a single PRN code period. The method includes: Receive satellite signals to be synchronized; Based on the original message bit length n corresponding to the satellite signal, n working conditions for receiving the satellite signal are determined. The n working conditions respectively characterize the different timing offsets of the initial sampling unit relative to the edge of the message bit when receiving the satellite signal, where n is a natural number greater than or equal to 2. The satellite signals under the n working conditions are sequentially bit synchronized to obtain the bit synchronization results corresponding to the n working conditions. In the bit synchronization process of the i-th working condition, if any round of bit synchronization fails under the working condition, the bit synchronization result of the i-th working condition is marked as a synchronization failure result, and the bit synchronization is switched to the (i+1)-th working condition, 1≤i<n. Based on the bit synchronization results under the n operating conditions, the bit edges of the satellite signal to be synchronized are determined, and bit synchronization of the satellite signal to be synchronized is performed based on the determined bit edges.

2. The method according to claim 1, characterized in that, The step of sequentially performing bit synchronization of satellite signals under the n operating conditions includes: Based on the n operating conditions, at least one bit synchronization is performed on the satellite signal. During any bit synchronization process, for the i-th operating condition among the n operating conditions, at least one round of bit synchronization is performed. In any round of bit synchronization, the initial sampling unit is used as the starting position of the sliding window, the length of the sliding window is L sampling units, and the sliding window is slid with one sampling unit as the step size to obtain n calculation windows in sequence, where L is a natural number and 1≤L≤n; Calculate the power accumulation value for each calculation window, and perform bit synchronization based on the power accumulation value for each calculation window; If bit synchronization is successful, increment the hit count value corresponding to the edge position of the message bit in the i-th working condition by 1, and execute a new round of bit synchronization in the i-th working condition. If bit synchronization fails, switch to the (i+1)th working condition and perform at least one round of bit synchronization under the (i+1)th working condition.

3. The method according to claim 2, characterized in that, The first modulation signal component is a low-speed message signal modulated by binary phase shift keying (BPSK), and the second modulation signal component is a high-speed message signal modulated by code shift keying (CSK). The calculation of the power accumulation value for each calculation window includes: For any calculation window, the I-branch and Q-branch corresponding to the first modulation signal component in the satellite signal received within the calculation window are accumulated respectively to obtain the accumulated sums corresponding to the I-branch and Q-branch respectively; The sums of the I-branch and the Q-branch are squared respectively, and the squared results of the I-branch and the Q-branch are added together to obtain the power accumulation value of the calculation window.

4. The method according to claim 2, characterized in that, The bit synchronization based on the power accumulation value of each calculation window includes: Based on the power accumulation value of each window, the maximum power accumulation value, the second largest power accumulation value, and the minimum power accumulation value are selected. Based on the minimum power accumulation value, determine the synchronization power threshold value; Determine whether the maximum power accumulation value and the second maximum power accumulation value are both greater than the synchronization power threshold value, and whether the starting position of the calculation window corresponding to the maximum power accumulation value and the second maximum power accumulation value meets the preset position conditions; If both the maximum power accumulation value and the second maximum power accumulation value are greater than the synchronization power threshold, and the starting positions of the calculation windows corresponding to the maximum power accumulation value and the second maximum power accumulation value respectively meet the preset position conditions, the bit synchronization is determined to be successful; between the calculation window corresponding to the maximum power accumulation value and the calculation window corresponding to the second maximum power accumulation value, the calculation window with the earlier starting position is selected, and the end time of the last sampling unit of the calculation window is taken as the edge of the message bit obtained in this round of bit synchronization; If either the maximum power accumulation value or the second maximum power accumulation value is not greater than the synchronization power threshold, or if either the starting position of the calculation window corresponding to the maximum power accumulation value or the second maximum power accumulation value does not meet the preset position condition, then the bit synchronization is determined to have failed.

5. The method according to claim 4, characterized in that, The synchronization power threshold is equal to the minimum power accumulation value plus the preset proportional component corresponding to the minimum power accumulation value.

6. The method according to claim 2, characterized in that, After determining whether bit synchronization was successful or failed in claim 2, and before executing the corresponding subsequent actions, a pre-judgment is performed; the pre-judgment includes: Determine whether the hit count value corresponding to the message bit edge position of the i-th working condition is equal to the preset bit synchronization success threshold. If the hit count value corresponding to the message bit edge position of the i-th working condition is equal to the preset bit synchronization success threshold, the message bit edge position corresponding to the i-th working condition is taken as the bit edge of the satellite signal to be synchronized, and bit synchronization of the satellite signal to be synchronized is performed based on the determined bit edge position. If the hit count value corresponding to the message bit edge position of the i-th working condition is less than the preset bit synchronization success threshold, determine whether there are at least two working conditions whose hit count values ​​are greater than or equal to the preset bit synchronization failure threshold. If there are at least two operating conditions whose hit count values ​​are greater than or equal to the preset bit synchronization failure threshold, the bit synchronization is determined to have failed. If the hit count value corresponding to the two working conditions is greater than or equal to the preset bit synchronization failure threshold, determine whether the bit synchronization time is greater than the preset time threshold. If the total bit synchronization time is greater than a preset time threshold, the bit synchronization is determined to have failed. If the total bit synchronization time is not greater than a preset time threshold, a new round of bit synchronization is performed under the i-th working condition, or the process is switched to the (i+1)-th working condition and at least one round of bit synchronization is performed under the (i+1)-th working condition.

7. The method according to any one of claims 2-6, characterized in that, The hit count value is the histogram statistical count value.

8. A bit synchronization device for satellite signals, characterized in that, The satellite signal includes a first modulated signal component and a second modulated signal component. The message transmission rate of the first modulated signal component is less than that of the second modulated signal component. The first modulated signal component and the second modulated signal component are transmitted alternately in units of a single PRN code period. The bit synchronization device includes: The receiving module is used to receive satellite signals to be synchronized. The synchronization module is used to determine n operating conditions for receiving the satellite signal based on the original message bit length n corresponding to the satellite signal. The n operating conditions respectively characterize the different timing offsets of the initial sampling unit relative to the edge of the message bit when receiving the satellite signal, where n is a natural number greater than or equal to 2. The synchronization module is also used to sequentially perform bit synchronization on the satellite signals under the n working conditions to obtain the bit synchronization results corresponding to the n working conditions. In the bit synchronization process of the i-th working condition, if any round of bit synchronization fails under the working condition, the bit synchronization result of the i-th working condition is marked as a failure result, and the bit synchronization is switched to the (i+1)-th working condition, where 1≤i<n. The synchronization module is further configured to determine the bit edge of the satellite signal to be synchronized based on the bit synchronization results under the n operating conditions, and to perform bit synchronization on the satellite signal to be synchronized based on the determined bit edge.

9. A computing device, characterized in that, Including processor and memory; The memory is used to store instructions; The processor is configured to execute instructions stored in the memory to cause the computing device to perform the bit synchronization method for satellite signals as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, Used to store computer programs; wherein the computer programs, when executed by a processor, implement the bit synchronization method for satellite signals as described in any one of claims 1 to 7.

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