A source network load storage terminal quantum security module integrated device

Abstract

The application relates to the field of power terminal quantum security technology and discloses a source network load storage terminal quantum security module integrated device which comprises an edge side quantum security board card and a terminal side embedded quantum security chip, and an electrical communication interface and a miniature photoelectric coupling channel are arranged in parallel between the two. The board card constructs a dynamic key pool, and sends an optical pulse sequence carrying quantum characteristics to the chip through the miniature photoelectric coupling channel. The chip decodes the quantum state of the sequence and calculates a quantum error code rate, when the error code rate is greater than a preset threshold, the chip bottom layer hardware directly disconnects the electrical communication interface and triggers key zero clearing; when the error code rate is normal, the chip acquires the key through the electrical communication interface and encrypts and decrypts business data. The application constructs a physical layer photoelectric isolation and hardware blocking linkage mechanism, effectively prevents side channel attacks such as probe wire connection, supports key connection and space light charging in a network disconnection and offline environment, and guarantees the safety of terminal scheduling and business continuity.

Description

Technical Field

[0001] This invention relates to the field of quantum security technology for power terminals, specifically to an integrated device for a quantum security module of a source-grid-load-storage terminal. Background Technology

[0002] In the process of modern power grids evolving into new power systems, a large number of distributed power sources, energy storage facilities, and adjustable load nodes are widely connected to the dispatch network. In order to cope with the increasingly complex network eavesdropping threats, quantum secure communication technology, which uses the principles of quantum mechanics to generate and distribute truly random keys, has been introduced into the underlying node devices. In conventional practice, cryptographic boards or security chips are usually integrated inside the devices, and external fiber optic networks are used to continuously receive keys to perform encryption and decryption operations on business messages.

[0003] The existing terminal internal architecture design exposes blind spots in the underlying protection when dealing with multi-dimensional composite attacks and extreme operating conditions. At the physical architecture level, internal components generally use conventional exposed electrical buses to exchange plaintext keys and context parameters. When encountering physical attacks such as intrusive probe wiring and electromagnetic bypass eavesdropping, conventional software-layer logic defense mechanisms cannot detect the anomalies in the physical channel, often resulting in the side channel loss of core keys during component transfer. At the same time, the traditional quantum key exchange mechanism is absolutely dependent on stable fiber optic links. In harsh service environments, communication optical cables are often blocked due to geological disasters or external damage, making it difficult for terminals to obtain fresh external keys. After the local cache resources are exhausted, without an underlying secure connection mechanism, the terminal is very likely to go offline or degrade to a plaintext transmission state, breaking the continuity of service scheduling. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides an integrated device for a quantum security module of a source-network-load-storage terminal, which solves the problems of existing terminals being susceptible to physical eavesdropping on internal key interactions and lacking a key continuation mechanism that leads to service interruption in communication outages or network-free conditions.

[0005] To achieve the above objectives, the present invention provides the following technical solution: an integrated device for a source-grid-load-storage terminal quantum security module, comprising an edge-side quantum security board and a terminal-side embedded quantum security chip communicatively connected to the edge-side quantum security board. An electrical communication interface and a micro-optocoupler channel are provided between the two. The edge-side quantum security board receives an external raw key stream to construct a dynamic key pool and sends a sequence of light pulses carrying quantum state characteristics to the terminal-side embedded quantum security chip via the micro-optocoupler channel. The terminal-side embedded quantum security chip receives and parses the light pulse sequence, controls the connection and disconnection of the electrical communication interface based on the parsing result, and obtains the key when connected to encrypt and decrypt terminal service data.

[0006] Furthermore, in order to control the on / off state of the electrical communication interface, the embedded quantum-safe chip on the terminal side, after receiving the optical pulse sequence, performs decoding measurement in conjunction with preset basis information, and performs bit-level comparison between the actual received sequence and the expected sequence, calculating the quantum bit error rate using the following formula. : in, This represents the total number of bits in the optical pulse sequence, obtained according to the communication frame format specification. The first output of the hardware physical detector The actual received sequence number; For local storage The expected sequence of bits; This is an inherent error correction term for the miniature optocoupler channel, obtained based on factory anechoic chamber calibration data. The hardware circuitry within the embedded quantum safety chip on the terminal side will... The error rate is compared with a quantum error rate tolerance threshold set based on historical experience data. If the error rate is not greater than the threshold, the electrical communication interface is connected; if it is greater than the threshold, the electrical communication interface is disconnected, and a hardware-level key clearing operation is triggered simultaneously.

[0007] Furthermore, when encrypting and decrypting terminal service data, the embedded quantum security chip on the terminal side extracts a working key from the dynamic key pool and uses a symmetric encryption algorithm to encrypt the plaintext service data to generate ciphertext. Then, using a hash authentication function, the ciphertext is combined with the working key to calculate a message authentication code used for integrity verification. Finally, the ciphertext and message authentication code are encapsulated and output.

[0008] Furthermore, when the external fiber optic link is interrupted and the remaining valid key quantity in the dynamic key pool is less than the set exhaustion alarm threshold, the device triggers a hybrid key continuation mode. In this mode, the terminal-side embedded quantum security chip activates its internal true random number generator to generate a local random number, and the edge-side quantum security board provides the remaining valid key as the base key. The terminal-side embedded quantum security chip uses a built-in hash generation function to concatenate the base key, the local random number, the system's current timestamp, and the chip's physical device identifier to generate a one-time pad session key, which is used to encrypt service data and transmit it back via the wireless communication module.

[0009] Furthermore, in environments without external communication network coverage, the edge-side quantum security board utilizes its free-space optical quantum transceiver components to establish a short-range line-of-sight optical link with an external offline key injection terminal to perform spatial quantum key distribution. After completing substrate alignment and error correction, a security amplification process is performed, such as using the Toplitz matrix to compress the error-corrected residual key sequence to eliminate potential information leakage. Finally, a high-security offline injection key is generated and written into the secure storage unit inside the embedded quantum security chip on the terminal side as a preset key.

[0010] Furthermore, the edge-side quantum security board has a PCIe bus interface and adopts a plug-in installation structure. Its internally integrated hot-swappable control unit supports online upgrades or fault replacement of the board without stopping the system.

[0011] Furthermore, the edge-side quantum security board is equipped with a quantum key processing unit, which is used to perform protocol parsing, relay buffering and verification on the received raw key stream; the electrical communication interface can integrate multiple standard interfaces such as UART, SPI or USB.

[0012] This invention provides an integrated device for a quantum security module of source-grid-load-storage terminal. It has the following advantages: 1. In this invention, a miniature optocoupler channel is set between the edge side and the terminal side. The single-photon detection array obtains the bit error rate of the optical pulse sequence and inputs it into the hardware comparator. When the value exceeds the threshold, it outputs a low level, which in turn controls the analog switch in the electrical communication interface to physically cut off the data link, thereby realizing the underlying hardware blocking of probe wiretapping.

[0013] 2. In this invention, when the hardware comparator determines that the bit error rate exceeds the threshold, it synchronously sends a clear trigger pulse to the storage block, pulls the power supply of the volatile storage unit to 0 volts within a specified clock cycle, and performs a full-coverage write operation in conjunction with the physical disconnection of the link to erase the resident working key and context parameters, thereby avoiding the loss of side channel data.

[0014] 3. When the link is interrupted and the key balance is below the threshold, the hardware interruption is triggered. The true random entropy, timestamp, physical identifier and the remaining base key are extracted and concatenated. The hash engine is linked to generate the evolution key, which is encrypted by the cryptographic coprocessor. The wireless communication module is then used to establish an air link to complete the message relay and backhaul.

[0015] 4. In a network-free charging environment, the circuit board receives single-photon pulses from a free-space beam and generates an offline key through Toplitz matrix operations. The linked chip then hard-encodes the key into a one-time-use electric fuse storage unit, relying on the irreversible melting characteristic of the electric fuse to prevent secondary tampering and abnormal voltage probe reading. Attached Figure Description

[0016] Figure 1 This is a diagram of the overall architecture topology of the present invention; Figure 2 This is a schematic diagram of the physical structure of the miniature optocoupler channel and electrical communication interface of the present invention; Figure 3 This is a block diagram of the hardware-level key clearing control logic of the present invention; Figure 4 This is a flowchart of the hybrid key connection mode of the present invention; Figure 5 This is a schematic diagram of an offline charging scenario for a free-space short-range line-of-sight optical link according to the present invention; Detailed Implementation The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0017] Please see the appendix Figure 1 To be continued Figure 5 This invention provides an integrated device for a quantum security module of a source-grid-load-storage terminal. The device includes an edge-side quantum security board and a terminal-side embedded quantum security chip that is communicatively connected to the edge-side quantum security board.

[0018] The edge-side quantum safety board features a PCIe 2.0x1 bus interface and a plug-in installation structure. Internally, it integrates a hot-swappable control unit, including power management, bus isolation, and status indication subunits. The stepped power-on sequence is as follows: first, connect the 3.3V auxiliary power supply (delayed 100ms), then connect the 12V main power supply (delayed 200ms), and finally enable the PCIe bus. Bus isolation is achieved using an ADG1414 analog switch. During fault replacement, a hot-swap interrupt signal is sent to the main control device via the I2C bus for status synchronization, enabling stepped power-on when the board is inserted, rapid power-off when removed, and bus level isolation. This supports online upgrades or fault replacement of external devices without downtime. The edge-side quantum safety board physically connects to the motherboard of the external source-grid-load-storage main control device via its plug-in installation structure and PCIe bus interface for power supply and low-level data interaction.

[0019] An electrical communication interface and a miniature optocoupler channel are provided between the edge-side quantum security board and the terminal-side embedded quantum security chip. The electrical communication interface integrates a UART serial interface, an SPI synchronous communication interface, or a USB serial bus interface. The electrical communication interface undertakes the bidirectional transmission of classical electrical signals between the edge-side quantum security board and the terminal-side embedded quantum security chip. The miniature optocoupler channel is arranged independently of the above-mentioned electrical communication interface. Its physical medium is a transparent optical resin waveguide or microlens array with an air gap of 0.4-0.6 mm. It is fixed in the reserved groove between the edge-side quantum security board and the terminal-side embedded quantum security chip using a board-level surface mount process. The optical alignment accuracy is controlled within ±5μm. The package uses a metal shield to isolate electromagnetic and stray light, forming a spatial optical isolation path for transmitting single photons or weakly coherent light pulses. The working wavelength is 1550nm, the optical transmission loss does not exceed 3dB, and the single photon transmission efficiency is not less than 50%.

[0020] The edge-side quantum security board is equipped with a quantum key processing unit, which receives the raw key stream from the external quantum network. The quantum key processing unit performs protocol parsing, relay buffering, and error checking on the received raw key stream based on the BB84 protocol. The raw key stream adopts a fixed 1024-bit frame structure, with the frame header containing a 16-bit synchronization word, an 8-bit frame sequence number, and an 8-bit checksum. Error checking uses LDPC code with a code rate of 0.5 and 10 iterations. A dynamic key pool is established, and the usable keys that pass the verification are stored in the dynamic key pool for maintenance.

[0021] The system calculates the total number of currently valid keys in the dynamic key pool. The process unfolds according to the following formula: In the formula, This indicates the total number of data frames in the original key stream received by the system. The main control program obtains this value by reading the physical frame count register of the communication receiving port. Indicates the first The system reads the bit length of the original key stream of the frame according to the fixed frame length set in the standard quantum key distribution protocol; The usable key retention rate after the quantum key processing unit performs error checking is expressed by the following formula: ,in The average quantum error rate is calculated in real time based on historical error data from the most recent 1000 key frames, reflecting the current code generation quality of the physical channel. This indicates the total amount of keys that have been extracted and consumed in the current system operations. The control unit obtains this value by reading the hardware-level key consumption counter set in the edge-side quantum security board.

[0022] The edge-side quantum-safe board transmits a sequence of light pulses carrying quantum state characteristics to the terminal-side embedded quantum-safe chip via a miniature optocoupler channel. The terminal-side embedded quantum-safe chip has an optical receiving port, which receives the aforementioned light pulse sequence and performs quantum state analysis via the miniature optocoupler channel. Based on the analysis result, the terminal-side embedded quantum-safe chip outputs a level control command to directly control the on / off state of the electrical communication interface hardware path.

[0023] When the electrical communication interface is connected, the terminal-side embedded quantum-safe chip establishes a data access connection with the edge-side quantum-safe board. The terminal-side embedded quantum-safe chip sends an extraction command to the edge-side quantum-safe board via the electrical communication interface to obtain the working key from the dynamic key pool and stores it in the volatile storage area inside the terminal-side embedded quantum-safe chip. The external source-grid-load-storage master control device inputs the collected terminal service data to the terminal-side embedded quantum-safe chip. The terminal-side embedded quantum-safe chip uses the obtained working key to encrypt and decrypt the received terminal service data. Finally, the terminal-side embedded quantum-safe chip outputs the encrypted and decrypted terminal service data to the external source-grid-load-storage master control device for communication backhaul or local command execution.

[0024] In this embodiment, the edge-side quantum security board and the terminal-side embedded quantum security chip collaboratively perform on / off state control operations of the electrical communication interface. The edge-side quantum security board internally houses a light source array and a quantum state modulation unit. The light source array employs a 1550nm distributed feedback laser, with output optical power controlled within the range of -60dBm to -50dBm and a pulse width of 1ns. The light source array emits an initial weak coherent optical signal; the quantum state modulation unit receives the initial weak coherent optical signal.

[0025] During the device's factory initialization phase, the pre-shared handshake seed is directly burned by a trusted cryptographic machine using a dedicated physical probe into the one-time-use electric fuse storage unit or the physically clonable secure area inside the edge-side quantum security board and the terminal-side embedded quantum security chip. This hardware-level physical isolation burning method ensures the absolute security of the seed during the initial sharing process, preventing it from being stolen by external probes or network links. To ensure the long-term security of the device, the pre-shared handshake seed has a dynamic update mechanism: when the external fiber optic link is normal, the edge-side quantum security board and the terminal-side embedded quantum security chip extract the latest synchronization quantum key issued by the external quantum network according to a set time period or communication interaction threshold, and perform iterative derivation calculations on the current handshake seed using the built-in national cryptographic SM3 or SHA-256 hash algorithm to achieve synchronous rotation and update of the seed.

[0026] The quantum state modulation unit performs polarization encoding or phase encoding on the initial weakly coherent optical signal based on the pseudo-random sequence generated by the internal pre-shared handshake seed. The polarization state modulation is achieved by using a lithium niobate electro-optic modulator with a modulation extinction ratio ≥20dB, generating an optical pulse sequence in a preset polarization state or preset phase state. The edge-side quantum security board continuously transmits the generated optical pulse sequence to the terminal-side embedded quantum security chip via a micro optocoupler channel.

[0027] The embedded quantum-safe chip on the terminal side internally incorporates a single-photon detector array and a substrate demodulation unit. The single-photon detector array employs an InGaAs avalanche photodiode (APD). The substrate demodulation unit, based on extracted preset substrate information, configures the measurement channel parameters of the single-photon detector array by switching the angle of the polarization beam splitter at the front end of the single-photon detector array. The embedded quantum-safe chip on the terminal side utilizes the configured single-photon detector array to decode and measure the received light pulse sequence, obtaining the actual received sequence containing several bits of binary data.

[0028] The embedded quantum-safe chip on the terminal side calls upon its internal secure microcontroller to generate a corresponding expected sequence using a hash expansion algorithm based on the same pre-shared handshake seed. The actual received sequence is then compared bit-by-bit with the expected sequence to calculate the quantum bit error rate. The system calculates the quantum bit error rate. The process unfolds according to the following formula: In the formula, This indicates the total number of valid pulse bits in the measured optical pulse sequence. The system obtains this value based on the length field defined in the frame header of the underlying communication protocol. Indicates the first in the actual received sequence The system obtains this value by performing analog-to-digital conversion on the physical electrical pulse signal output by the single-photon detector array. Represents the first in the expected sequence The terminal-side embedded quantum security chip reads the binary bit value directly from its internal secure storage area. This represents the XOR operator, used to determine whether the corresponding bit data has been flipped. This represents the inherent error correction term introduced by the system's optical background noise. The specific calibration steps are as follows: For each batch of miniature optocouplers, the ambient background light power is strictly controlled at an extremely low level (e.g., less than 10). -9 In a shielded anechoic chamber (W), a sequence of light pulses in a known state is transmitted and subjected to multiple (e.g., at least 1000) independent, interference-free detection cycles. The dark count of the hardware detector itself and the inherent flip bits caused by optical crosstalk are statistically analyzed, and the average bit error rate of multiple tests is taken as the fixed compensation value for this batch of devices. This is to eliminate individual manufacturing variations in components. The value ranges from 0.1% to 0.5%.

[0029] The embedded quantum-safe chip on the terminal side incorporates hardware comparator logic circuitry. The embedded quantum-safe chip on the terminal side will then calculate the quantum bit error rate. The input hardware comparator logic circuit compares the value with a preset quantum error rate tolerance threshold. Based on the inherent bit error rate of the micro-optocoupler channel (approximately 1.5%) plus a 3% anti-eavesdropping security margin, the system determines a typical quantum error rate tolerance threshold of 4.5%, which can be adjusted within the range of 3% to 6% depending on the security level: a 3% threshold is used for high-security scenarios (such as substation core terminals), a 4.5% threshold is used for medium-security scenarios (such as ordinary photovoltaic inverters), and a 6% threshold is used for low-security scenarios (such as residential smart meters).

[0030] When the hardware comparator logic circuit determines that the quantum error rate is not greater than the preset quantum error rate tolerance threshold, the terminal-side embedded quantum safety chip determines that the current micro optocoupler channel has not been invaded by external probes or bypassed for listening. The terminal-side embedded quantum safety chip outputs a high-level enable signal to the physical layer control pin of the electrical communication interface. The hardware switching circuit of the electrical communication interface responds to the high-level enable signal, closes the internal signal transmission link, connects the electrical communication interface, and thus allows classical electrical data interaction between the edge-side quantum safety board and the terminal-side embedded quantum safety chip.

[0031] When the hardware comparator logic circuit determines that the quantum error rate is greater than the preset quantum error rate tolerance threshold, the embedded quantum security chip on the terminal side determines that there is an anomaly in the physical defense. The embedded quantum security chip on the terminal side outputs a low-level blocking signal to the physical layer control pin of the electrical communication interface. The hardware switching circuit of the electrical communication interface responds to the low-level blocking signal, physically disconnects the signal transmission link, and disconnects the electrical communication interface. At the same time, the embedded quantum security chip on the terminal side triggers an internal hardware-level key clearing operation. The clearing scope includes the working key, temporary session data, and system context state, but does not erase the preset key and firmware in the non-volatile storage area.

[0032] During the hardware-level key clearing operation, the embedded quantum security chip on the terminal side generates a clearing trigger pulse. The key storage block in the embedded quantum security chip on the terminal side receives the clearing trigger pulse and pulls the power supply voltage of the static random access memory unit down to 0V (below the data holding voltage of the memory unit) within 5 to 15 system clock cycles. It then performs at least two all-zero overwrite operations to all secure storage addresses and finally performs one all-1 overwrite operation to ensure that the data cannot be recovered by physical means, erases the resident working key and system context state parameters, and blocks the loss of side-channel data at the physical layer.

[0033] In this embodiment, with the electrical communication interface in a connected state, the terminal-side embedded quantum security chip performs encryption and decryption processing of terminal service data. The external terminal device generates plaintext service data; the terminal-side embedded quantum security chip receives the plaintext service data input from the terminal device through its peripheral data pins and latches the plaintext service data into its internal data receiving register. The main control microprocessor of the terminal-side embedded quantum security chip responds to the data receiving status and generates a key extraction request command; the terminal-side embedded quantum security chip sends the key extraction request command to the edge-side quantum security board via the connected electrical communication interface.

[0034] The edge-side quantum security board parses the key retrieval request command and extracts the working key from the dynamic key pool. The edge-side quantum security board then transmits the working key back to the embedded quantum security chip on the terminal side via an electrical communication interface. The embedded quantum security chip on the terminal side loads the obtained working key into the key-specific register of its internal hardware cryptographic coprocessor.

[0035] The embedded quantum-safe chip on the terminal side activates the hardware cryptographic coprocessor. The hardware cryptographic coprocessor calls the symmetric encryption algorithm instruction set embedded in the silicon mask read-only memory, and uses the working key in the dedicated key register to perform block cipher operations on the plaintext business data in the data receiving register. The hardware cryptographic coprocessor performs corresponding iterative obfuscation and diffusion operations according to the selected specific cryptographic standard. For example, when using the Chinese national cryptographic SM4 algorithm or the AES-128 / 256 standard, it performs multiple rounds of byte substitution, row shifting, column obfuscation, and round key addition logic operations to generate ciphertext, which is then output to the internal data transmission buffer.

[0036] The embedded quantum-safe chip on the terminal side utilizes its internal hashing engine. The hashing engine employs a hash authentication function to perform a digest hash calculation on the ciphertext and the working key, generating a message authentication code. The system then calculates the message authentication code. The process unfolds according to the following formula: In the formula, This indicates the one-way cryptographic hash operation function selected by the system. The embedded quantum security chip on the terminal side directly calls the corresponding algorithm model from the internal firmware according to the configuration of the main control program. This indicates the working key extracted from the dynamic key pool. The processing engine obtains this parameter by addressing and reading the key-specific register. This represents the bitwise XOR logical operator; This represents the outer hash padding constant. During the system development phase, a fixed hexadecimal sequence is generated according to the standard hash message authentication code protocol specification and stored in a non-volatile storage area. This represents the inner hash filling constant. Technicians also generate the corresponding sequence according to the standard protocol specifications and write it into the hardware. This indicates the data concatenation operator, which the microprocessor uses to sequentially merge two parts of data in a contiguous memory address space. This indicates the ciphertext generated in the preceding encryption step. The processing engine directly reads this data block from the internal data sending buffer for processing.

[0037] The data packet assembly logic unit within the embedded quantum-safe chip on the terminal side extracts the ciphertext from the internal data transmission buffer and the message authentication code output by the hash engine in parallel. According to the business communication protocol, the data packet assembly logic unit concatenates the ciphertext and message authentication code into a data frame structure. The embedded quantum-safe chip on the terminal side outputs the concatenated ciphertext and message authentication code externally via an external communication port. The external source-network-load-storage master control device obtains the output ciphertext and message authentication code, activates its onboard network communication routing unit, and sends the ciphertext and message authentication code to the remote master station. After obtaining the data frame, the remote master station schedules the corresponding working key to perform reverse decryption and hash digest comparison verification operations.

[0038] In this embodiment, a true random number generator circuit is built into the silicon wafer of the embedded quantum security chip on the terminal side; a wireless communication module circuit is embedded on the printed circuit board of the edge-side quantum security board. The main control processing unit in the edge-side quantum security board periodically polls the optical power detection feedback port of the physical layer of the external optical fiber network to monitor the connectivity status of the external optical fiber link; simultaneously, the main control processing unit reads the memory address pointer offset of the dynamic key pool and calculates the remaining valid key quantity in real time. The system calculates the key exhaustion alarm threshold based on the product of the historical average network fault repair time parameter and the terminal's average key throughput rate, and pre-writes it into the system configuration register of the edge-side quantum security board.

[0039] The state decision logic gate within the edge-side quantum security board compares the current remaining valid key quantity with the key depletion alarm threshold. When the main control processing unit detects that the optical power has dropped to zero and thus determines that the external fiber optic link is disconnected, and the state decision logic gate determines that the remaining valid key quantity is less than the key depletion alarm threshold, the edge-side quantum security board generates a mode switching interrupt level signal. The edge-side quantum security board sends mode switching interrupt level signals to each relevant functional unit via the internal bus, triggering the entire device to switch to hybrid key continuation mode.

[0040] In hybrid key continuation mode, the embedded quantum security chip on the terminal side detects a mode switching command, and its internal control logic outputs an enable level to the true random number generator circuit. The true random number generator circuit is activated and operates, acquiring internal physical entropy source signals such as semiconductor thermal noise or diode quantum shot noise. The true random number generator circuit, after amplification, analog-to-digital conversion, and von Neumann debiasing processing, generates a true random number sequence with a rate of not less than 1 Mbps.

[0041] The edge-side quantum security board locks the dynamic key pool, suspending key distribution to regular external business processes. It then extracts a preset length of remaining valid keys from the remaining valid address space of the dynamic key pool, using this as the base key. The edge-side quantum security board encapsulates this base key into a data bus transmission frame and sends it to the terminal-side embedded quantum security chip via the currently connected electrical communication interface. The terminal-side embedded quantum security chip receives and parses the transmission frame, storing the extracted base key in its internal high-speed cache.

[0042] The key derivation logic unit of the embedded quantum-safe chip on the terminal side reads the base key from the cache, the local random number sequence output by the true random number generator circuit, the system's current timestamp recorded by the chip's internal real-time clock module, and the physical device identifier code read from the one-time programmable read-only memory via the internal bus. The embedded quantum-safe chip then calls the hash generation function in the firmware to perform the concatenation and hash calculation of the above parameters. The system calculates and generates the session key. The process unfolds according to the following formula: In the formula, KDF represents the message authentication code key derivation function based on a hash algorithm. To ensure the security strength of the generated key, this invention preferably adopts the standard HKDF algorithm, whose underlying hash function is configured as the national cryptographic SM3 or SHA-256 algorithm. The main control program of the embedded quantum security chip on the terminal side calls the HKDF instruction set of the built-in hardware cryptographic coprocessor, takes the above-mentioned concatenated and spliced ​​data block as the input key material, and combines it with the preset random salt value in the chip's internal secure read-only memory to perform extraction and expansion two-stage operations in sequence, finally outputting a high-strength generated key with a length of 256 bits; This represents the base key, and the key derivation logic unit directly addresses and reads the cache to obtain this parameter. This represents a local random number sequence, which the key derivation logic unit obtains by reading the output buffer register of the true random number generator circuit. This indicates the current timestamp of the system. The key deduction logic unit sends a clock synchronization read request to the internal real-time clock module to obtain this count value. This indicates that the chip has a unique physical device identifier code, which is laser-burned into a one-time programmable read-only memory by the wafer manufacturer when it leaves the factory. The key deduction logic unit reads the code word by addressing a fixed physical address. This indicates the bit string concatenation operator. The key derivation logic unit uses this operator to concatenate the four data blocks bit by bit in a consecutive memory address space in a preset order.

[0043] During periods when the external fiber optic link is disconnected, the embedded quantum-safe chip on the terminal side continuously acquires plaintext service data to be transmitted back from the application layer data input port. The embedded quantum-safe chip then activates its hardware cryptographic engine, loading a derived session key calculated using a formula. The hardware cryptographic engine uses this derived session key to perform symmetric encryption on the plaintext service data, generating the corresponding ciphertext. The embedded quantum-safe chip then serially encapsulates the generated ciphertext and outputs it to the edge-side quantum-safe board via the electrical communication interface. The edge-side quantum-safe board extracts the ciphertext from the encapsulated data packet and establishes a data transmission channel with the internal wireless communication module. The wireless communication module receives the ciphertext, activates its RF front-end circuitry, and establishes an over-the-air (OTA) link with the external wireless base station. Finally, the edge-side quantum-safe board utilizes this wireless communication module to transmit encrypted communication data back to the remote master station via the OTA link, maintaining data continuity in the service communication channel even under extreme network outage conditions. When the external fiber optic link is restored and the remaining valid key quantity in the dynamic key pool recovers to more than twice the alarm threshold, and optical power ≥ -30dBm is detected three times consecutively (each time with an interval of 1 second), the system automatically switches back to the conventional quantum key encryption mode. During the switching process, the currently incomplete encryption session is retained, and the remaining data transmission is completed using the evolved session key before switching to the new quantum key.

[0044] In this embodiment, a free-space quantum transceiver is installed on the physical edge of the printed circuit board of the edge-side quantum security board. In an operating environment without external communication network coverage, the edge-side quantum security board initiates its internal offline maintenance process, activating the free-space quantum transceiver. External personnel arrive at the deployment site of the terminal equipment carrying an offline key charging terminal; the edge-side quantum security board controls the free-space quantum transceiver to emit a probe beacon light for spatial beam scanning. The offline key charging terminal responds to the probe beacon light, completes optical axis spatial alignment, and establishes a short-range line-of-sight optical link with the edge-side quantum security board with a transmission distance of 0.5–5 m and an alignment accuracy of ±1° to perform short-range spatial quantum offline charging operations.

[0045] The edge-side quantum security board and the external offline key injection terminal negotiate spatial quantum key distribution via an established short-range line-of-sight optical link. The external offline key injection terminal prepares single-photon pulses and performs polarization modulation, then sends them to the edge-side quantum security board via the short-range line-of-sight optical link. The microprocessor on the edge-side quantum security board generates local random numbers, randomly selects a single-photon measurement substrate based on these local random numbers, and drives the single-photon detector within the free-space optical quantum transceiver component to perform a detection response operation, recording the timestamp of each pulse arrival and the status of the response port.

[0046] The edge-side quantum-safe board controls a multiplexed wavelength laser within the free-space optical quantum transceiver assembly, establishing a classical optical signal channel independent of single-photon pulses. The edge-side quantum-safe board interacts with an external offline key-filling terminal via this classical optical signal channel for substrate comparison. The edge-side quantum-safe board compares its randomly selected measurement substrate with the preparation substrate used by the external offline key-filling terminal to transmit data, discarding probe data at sites where the measurement and preparation substrates differ, retaining probe results identical to those on the measurement substrate, and obtaining the original sieved key sequence.

[0047] The edge-side quantum security board receives parity check matrix data sent by an external offline key injection terminal via a classical optical signal channel. The edge-side quantum security board runs an error correction algorithm to correct errors in the acquired sieved key sequence, repairing bit-flip errors caused by space optical transmission, and generating an error-free corrected key sequence. The pre-shared random seed is a unique 256-bit sequence, written by the key management center into the edge-side quantum security board's one-time programmable non-volatile memory before the device leaves the factory. The edge-side quantum security board uses this pre-shared random seed to perform secure amplification processing on the error-free corrected key sequence, employing a 256×N-dimensional Toplitz matrix (N being the length of the error-corrected key sequence). The first row and first column of the matrix are generated by expanding the pre-shared random seed using SHA-256 hashing, ultimately generating a 256-bit offline injection key. This eliminates some information leaked to space eavesdroppers during the base interaction stage, generating the final offline injection key. The system calculates the offline injection key. The process unfolds according to the following formula: In the formula, This represents the column vector of the generated offline key matrix. The edge-side quantum security board stores the result of this operation in its internal transmission buffer for maintenance. This indicates a pre-shared random seed, and the edge-side quantum security board reads this factory-programmed data from a fixed physical address in its internal non-volatile memory. This indicates that the edge-side quantum security board constructs a universal hash toplitz matrix using an extracted pre-shared random seed. The system's underlying program uses this seed data sequence to sequentially fill the first row and first column elements of the matrix to determine the entire matrix. This represents the transposed column vector of the aforementioned error-free error correction key sequence, which the edge-side quantum security board reads from the working memory area of ​​the error correction processing module; This represents the matrix multiplication operator in the binary Galois field. The hardware multiplier logic uses this operator to perform matrix dot product calculations based on modulo-2 addition.

[0048] The embedded quantum security chip on the terminal side integrates a secure storage unit within its silicon wafer area. This unit uses a one-time programmable storage medium with an electric fuse, and has a total capacity of 4KB. It only supports read and write access via the chip's internal hardware cryptographic engine; external buses cannot directly address it. Write operations require dedicated hardware instructions and verification of the chip's physical device identifier. After completing the aforementioned security amplification process and obtaining the offline charging key, the edge-side quantum security board assembles an offline write key instruction data frame. The edge-side quantum security board sends this offline write key instruction data frame, carrying the offline charging key, to the embedded quantum security chip on the terminal side via its currently connected electrical communication interface. The instruction parsing logic within the embedded quantum security chip on the terminal side obtains this data frame and extracts the offline charging key from the payload segment. The main control microprocessor of the embedded quantum security chip on the terminal side activates the internal storage control bus, increases the programming operation voltage, and directly writes the offline charging key into the internal secure storage unit, which serves as a preset key for system network restart or obfuscation operations.

[0049] In this embodiment, technicians physically deploy the source-grid-load-storage terminal quantum security module integrated device at the edge node of the new power system. The source-grid-load-storage terminal includes underlying industrial control equipment such as energy storage converters, photovoltaic inverters, and smart meters. The edge-side quantum security board of the device is inserted into the PCIe expansion slot of the main control backplane of the energy storage converter through a plug-in installation structure, obtains DC power supply, and establishes a system data bus connection within the main control backplane. The data acquisition unit of the energy storage converter acquires the terminal voltage, charging and discharging current, and status of the underlying temperature sensor of the battery cluster, generates plaintext service data, and then inputs this plaintext service data to the edge-side quantum security board via the PCIe bus, and transmits it transparently to the embedded quantum security chip on the terminal side for cryptographic processing.

[0050] To address threats such as probe wiretapping and side-channel physical intrusion at lower-level nodes, a miniature optocoupler channel forms an optical isolation zone within the circuit board-level physical space. When an external probe contacts the transmission medium surface of the miniature optocoupler channel, it causes a sudden change in optical refractive index and photon scattering loss. The single-photon detection array within the embedded quantum security chip on the terminal side detects this decrease in photon count rate, and the quantum error rate calculated according to the aforementioned formula subsequently rises and exceeds the preset quantum error rate tolerance threshold. The internal logic circuit of the embedded quantum security chip on the terminal side then cuts off the electrical communication interface, lowers the power supply voltage of the key storage block, and performs a hardware-level key clearing operation. This process blocks the path for external probes to obtain bus level signals and erases residual context data in the silicon-level working memory.

[0051] Under normal operating conditions, the device performs encryption and authentication processes on terminal service data. The system's main control unit calculates the total processing latency for a single service interaction based on the execution time parameters of the underlying hardware. The system calculates the total processing latency for a single service data packet. The process unfolds according to the following formula: In the formula, This represents the total time required for the system to process a single frame of service data. The system performance monitoring module calculates this value by reading the start and end clock ticks of the internal hardware timer. This indicates the addressing and transmission time of the embedded quantum security chip on the terminal side to extract the working key from the dynamic key pool via the electrical communication interface. The microprocessor inside the chip reads the fixed value of the corresponding period according to the peripheral bus clock frequency. This parameter represents the total length of binary bits in the terminal service data. The data packet assembly logic unit obtains this parameter by reading the byte counter in the receive buffer. This indicates the data processing throughput of the symmetric encryption algorithm executed by the internal hardware cryptographic coprocessor of the embedded quantum security chip on the terminal side. The system main control program extracts the solidified constant from the configuration table of the factory wafer test results to determine this value. The binary bit length of the working key is indicated by the key specification field in the key extraction request command, which is obtained by the system main control program. This indicates the processing throughput of the hash engine in performing hash digest calculations. The system main control program also extracts this parameter from a fixed address in the system configuration table. This indicates the queuing and transmission time of the final concatenated ciphertext and message authentication code sent by the edge-side quantum security board to the external network via the physical layer port. The network communication routing unit calculates this parameter in real time based on the current underlying channel occupancy ratio.

[0052] The device integrates optoelectronic dual-channel quantum state handshake, hardware-level key extraction, and a hybrid key continuation mechanism to complete the encryption and decryption flow of underlying data from the terminal equipment. Based on the ciphertext, message authentication code, and derived session key identifier output by the device, the source-grid-load-storage master control equipment establishes an end-to-end encrypted transmission tunnel on the source-grid-load-storage communication network side. The remote master station receives telemetry and tele-signaling data packets with the aforementioned cryptographic features, calls the server cluster for reverse decryption and message digest verification, and then generates downlink data frames containing scheduling control commands, which are sent to the source-grid-load-storage terminal, realizing bidirectional closed-loop control of underlying new power system equipment data acquisition and control command issuance.

Claims

1. A quantum security module integration device for source-grid-load-storage terminal, characterized in that, This includes an edge-side quantum security board and a terminal-side embedded quantum security chip that is communicatively connected to the edge-side quantum security board; An electrical communication interface and a micro optocoupler channel are provided between the edge-side quantum security board and the terminal-side embedded quantum security chip; The edge-side quantum security board is used to receive the raw key stream from the external quantum network to build a dynamic key pool, and to send a sequence of light pulses carrying quantum state characteristics to the terminal-side embedded quantum security chip through the micro optocoupler channel. The terminal-side embedded quantum security chip is used to receive the optical pulse sequence through the micro optocoupler channel and perform quantum state analysis. Based on the analysis result, it controls the on / off state of the electrical communication interface. When the electrical communication interface is in the connected state, it obtains the key from the dynamic key pool from the edge-side quantum security board through the electrical communication interface to encrypt and decrypt the received terminal service data.

2. The source-grid-load-storage terminal quantum security module integrated device according to claim 1, characterized in that, To control the on / off state of the electrical communication interface, the edge-side quantum security board and the terminal-side embedded quantum security chip are configured to perform the following operations in concert: The edge-side quantum security board sends a sequence of light pulses in a preset polarization state or a preset phase state to the terminal-side embedded quantum security chip; The terminal-side embedded quantum security chip combines preset substrate information to decode and measure the received optical pulse sequence, and compares the actual received sequence with the expected sequence to calculate the quantum error rate; When the quantum error rate is not greater than the preset quantum error rate tolerance threshold, the electrical communication interface is connected; When the quantum error rate exceeds the quantum error rate tolerance threshold, the electrical communication interface is disconnected, and the hardware-level key clearing operation inside the embedded quantum security chip on the terminal side is triggered.

3. The source-grid-load-storage terminal quantum security module integrated device according to claim 1, characterized in that, The terminal-side embedded quantum security chip is configured to perform the following operations to encrypt and decrypt the terminal's service data: When plaintext service data is received from the terminal device, the embedded quantum security chip on the terminal side extracts the working key from the dynamic key pool from the edge-side quantum security board via the electrical communication interface. The plaintext business data is encrypted using the working key using a symmetric encryption algorithm to generate ciphertext; The ciphertext and the working key are calculated using a hash authentication function, and the ciphertext and the message authentication code are output for transmission to the remote master station.

4. The source-grid-load-storage terminal quantum security module integrated device according to claim 1, characterized in that, The embedded quantum security chip on the terminal side also integrates a true random number generator; the quantum security board on the edge side integrates a wireless communication module. The edge-side quantum security board is also used to monitor the status of the external fiber optic link and the remaining valid key quantity of the dynamic key pool in real time; when the external fiber optic link is disconnected and the remaining valid key quantity is less than the set key depletion alarm threshold, the hybrid key continuation mode is triggered.

5. The source-grid-load-storage terminal quantum security module integrated device according to claim 4, characterized in that, In the hybrid key connection mode, the device is configured to perform the following operations: The embedded quantum security chip on the terminal side activates the true random number generator to generate a local random number sequence based on the internal physical entropy source; The edge-side quantum security board extracts a preset length of remaining valid keys from the dynamic key pool as the base key, and sends them to the terminal-side embedded quantum security chip via the electrical communication interface. The terminal-side embedded quantum security chip uses a hash generation function to concatenate and concatenate the base key, the local random number sequence, the system's current timestamp, and the physical device identifier of the terminal-side embedded quantum security chip to generate a session key. During the period when the external fiber optic link is disconnected, the terminal-side embedded quantum security chip uses the evolved session key to encrypt the service data to generate ciphertext, and outputs it to the edge-side quantum security board via the electrical communication interface. The edge-side quantum security board then transmits the communication data back through the wireless communication module.

6. The source-grid-load-storage terminal quantum security module integrated device according to claim 1, characterized in that, The edge-side quantum security board is also equipped with a free-space optical quantum transceiver component; The free-space optical quantum transceiver component is used to establish a spatial optical physical link with an external offline key filling terminal in an environment without external communication network coverage, so as to perform short-distance spatial optical quantum offline filling.

7. The source-grid-load-storage terminal quantum security module integrated device according to claim 6, characterized in that, The edge-side quantum security board is configured to perform the following operations to complete the short-range spatial photonic quantum offline charging: The free-space optical quantum transceiver component is used to establish a short-range line-of-sight optical link with the external offline key filling terminal, and spatial quantum key distribution negotiation is performed. Probes are performed based on a randomly selected measurement base, and the base is compared with the external offline key filling terminal. Probes with the same measurement base are retained to obtain the remaining key sequence. Error correction is performed on the sieved key sequence through the classical optical signal channel established by the free-space optical quantum transceiver component, and a secure amplification process is performed using a pre-shared random seed to generate an offline filling key. The offline charging key is written into the secure storage unit of the embedded quantum security chip on the terminal side as a preset key.

8. The source-grid-load-storage terminal quantum security module integrated device according to claim 7, characterized in that, The secure storage unit is integrated inside the terminal-side embedded quantum security chip; the offline charging key is sent from the edge-side quantum security board to the terminal-side embedded quantum security chip via the electrical communication interface, and then written into the secure storage unit by the terminal-side embedded quantum security chip.

9. The source-grid-load-storage terminal quantum security module integrated device according to claim 1, characterized in that, The edge-side quantum security board has a PCIe bus interface and a plug-in installation structure, and integrates a hot-swap control unit inside. The hot-swap control unit is used to support online upgrades or fault replacements of the edge-side quantum security board without shutting down the system.

10. The source-grid-load-storage terminal quantum security module integration device according to claim 1, characterized in that, The edge-side quantum security board is also equipped with a quantum key processing unit, which is used to perform protocol parsing, relay buffering and error checking on the received raw key stream and store it in the dynamic key pool; the electrical communication interface integrates a UART serial interface, an SPI synchronous communication interface or a USB serial bus interface.

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