A universal train redundancy TRDP ethernet board and device

Abstract

The application provides a universal train redundancy TRDP Ethernet board, which comprises a first processor, a second processor, a first Ethernet chip, a second Ethernet chip and an FPGA bridge chip; the first operating system and the second operating system independently operate with each other; the first processor and the second processor are respectively configured with independent watchdog circuits; after power-on, the first processor and the second processor independently start the operating systems respectively and receive port configuration information issued by an external main CPU board through the FPGA bridge chip, and independently complete port initialization; after successful initialization, the first processor and the second processor independently perform TRDP data transmission and reception through the respective Ethernet interfaces; if any processor is initialized incorrectly, the corresponding watchdog circuit triggers the processor to restart independently; during the data transmission and reception process, the first processor and the second processor continuously detect the health state of the external main CPU board, and stop sending data to the Ethernet when the health state is abnormal.

Description

Technical Field

[0001] This application relates to the field of rail transit control technology, and in particular to a general-purpose Train Real-time Data Protocol (TRDP) Ethernet board and device. Background Technology

[0002] In recent years, urban rail transit train network control systems have increasingly adopted Ethernet as the data transmission technology. Redundant isolated dual Ethernet, with its high redundancy, high anti-interference capabilities, and high stability, has become an industry consensus and a standard configuration for Ethernet projects. However, in actual design and use, the lack of unified standards and the various design units' considerations regarding cost and understanding have resulted in products with multiple problems, leading to numerous unnecessary train operation failures.

[0003] Currently, redundant Ethernet has become a standard configuration on trains, but the following problems exist: Dual Ethernet networks use a common central processing unit (CPU) chip. When a network storm or a large data surge occurs on a single network, the CPU may crash, which in turn can cause the redundant Ethernet network to also be unable to send and receive data in a timely manner. Summary of the Invention

[0004] The purpose of this application is to provide a universal train redundancy TRDP Ethernet board and system to address the shortcomings of existing technologies and solve the problems existing in the prior art.

[0005] To achieve the above objectives, this application provides a general-purpose train redundancy TRDP Ethernet board, the method comprising: a first processor, a second processor, a first Ethernet chip, a second Ethernet chip, and a field-programmable gate array (FPGA) bridge chip; The first processor is loaded with a first operating system and a first TRDP protocol stack running on the first operating system; the second processor is loaded with a second operating system and a second TRDP protocol stack running on the second operating system; the first operating system and the second operating system run independently of each other; The first processor and the second processor are each equipped with an independent watchdog circuit; After power-on, the first processor and the second processor independently start their respective operating systems and receive port configuration information from the external main CPU board through the FPGA bridge chip, and each completes port initialization independently. After successful initialization, they independently transmit and receive TRDP data through their respective Ethernet interfaces. If any processor fails to initialize, the corresponding watchdog circuit independently triggers the processor to restart. During data transmission and reception, the first processor and the second processor continuously monitor the health status of the external main CPU board, and stop sending data to the Ethernet when the health status is abnormal.

[0006] In one possible implementation, the FPGA bridging chip is used for data bridging and signal pass-through between the first processor, the second processor, and the external main CPU board, without performing TRDP protocol processing; and receives a reset signal sent by the external main CPU board and sends the reset signal to the first processor and the second processor.

[0007] In one possible implementation, the first operating system and the second operating system each include: a u-boot bootloader, a Linux kernel, a file system, a startup script, and a TRDP application; after the system is powered on, each processor sequentially executes u-boot booting, Linux kernel loading, and file system mounting, and automatically starts the TRDP application through the startup script.

[0008] In one possible implementation, the first processor sends the TRDP data received by the first Ethernet chip to the FPGA bridge chip and uploads it to the external main CPU board; after the external main CPU board performs logical processing on the uploaded TRDP data, it sends the data to be sent to the FPGA bridge chip; the FPGA bridge chip bridges the data to be sent to the first processor and the second processor respectively; and the first processor and the second processor convert the data to be sent into TRDP data and send it to the local area network through the first Ethernet chip and the second Ethernet chip respectively.

[0009] In one possible implementation, the initialization and data transmission / reception process of the first processor and the second processor includes: After the system is powered on, each processor performs system initialization and receives configuration information from the external main CPU board through the FPGA bridge chip to initialize the Ethernet port. If initialization fails, the watchdog circuit of the corresponding processor is triggered, and an independent restart is performed on that processor. If initialization is successful, the receiving thread and the sending thread will be started respectively. When the receiving period timer on the TRDP port is triggered, the receiving thread will send the TRDP data received by the Ethernet interface to the external main CPU board via the FPGA bridge chip. When the sending period timer on the TRDP port is triggered, the sending thread will send the data sent by the external main CPU board to the local area network via the Ethernet interface.

[0010] In one possible implementation, the first Ethernet chip is connected to a first Ethernet interface, and the second Ethernet chip is connected to a second Ethernet interface; the first Ethernet interface and the second Ethernet interface are physically isolated from each other, and the first Ethernet chip and the second Ethernet chip are physically isolated from each other.

[0011] In one possible implementation, the health status of the external main CPU board is: a heartbeat signal or a level signal periodically sent by the external main CPU board; when the first processor and the second processor do not receive the heartbeat signal or detect the level signal change within a preset time, the health status of the external main CPU board is determined to be abnormal, and data transmission to the Ethernet is stopped.

[0012] In one possible implementation, the first processor is connected to the first Ethernet chip via a first high-speed peripheral component interconnect express (PCIe) interface, and the second processor is connected to the second Ethernet chip via a second PCIe interface.

[0013] In one possible implementation, when the first processor and the second processor receive TRDP data through their respective Ethernet interfaces, they support three data reception modes: unicast, multicast, and broadcast.

[0014] Secondly, the present invention provides a universal train redundant TRDP Ethernet device, which can enable any CPU host with a PCI bus to transmit and receive train TRDP data through the board. The Ethernet device includes a chassis, a backplane, and the Ethernet board described in any one of the first aspects. The Ethernet board is plugged into the backplane and communicates with an external main CPU board through the backplane.

[0015] By applying the general-purpose train redundancy TRDP Ethernet board provided in this application, and through dual processors running the operating system and TRDP protocol stack independently respectively, coupled with dual-path Ethernet physical isolation and dual independent watchdogs, end-to-end dual-path redundancy is achieved from the physical layer to the protocol layer. When one path suffers a lightning strike, network storm, or processor / operating system failure, the other path remains completely unaffected and can continue to operate. If either processor experiences initialization or operational abnormalities, the independent watchdog accurately triggers the restart of that processor without affecting the other path, effectively avoiding board failure caused by a single point of failure and significantly improving the reliability and availability of the train communication network in harsh electromagnetic environments.

[0016] Meanwhile, this invention employs an architecture where the FPGA is used solely for data bridging, while protocol processing is entirely implemented by the processor software. Protocol version upgrades only require software updates without modifying the FPGA. The first and second processors are solely responsible for TRDP communication, while train control logic is independently completed by an external main CPU board. The two processors do not interfere with each other, ensuring real-time performance at both ends. Furthermore, the device adopts a modular board structure, facilitating on-site plug-and-play maintenance. This invention comprehensively improves the reliability, real-time performance, and maintainability of train TRDP Ethernet communication from multiple dimensions, including physical isolation, independent fault tolerance, architecture separation, software upgrades, health monitoring, and modular structure. Attached Figure Description

[0017] Figure 1 A schematic diagram of the hardware architecture of a general train redundancy TRDP Ethernet board provided for embodiments of the present invention; Figure 2 A schematic diagram illustrating the connection relationship between a general train redundancy TRDP Ethernet board and an external main CPU board, provided for embodiments of the present invention. Figure 3 A general train redundancy TRDP Ethernet board software system architecture diagram provided for embodiments of the present invention; Figure 4 A general data processing flowchart for a train redundancy TRDP Ethernet board provided for embodiments of the present invention; Figure 5 A general data transmission and reception flowchart for a train redundant TRDP Ethernet board provided for embodiments of the present invention; Figure 6 A flowchart for monitoring the health status of the main CPU of a train redundant TRDP Ethernet board, provided for embodiments of the present invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0019] The technical solution of this application will be further described in detail below with reference to the accompanying drawings and embodiments.

[0020] Example 1 Figure 1 This is a schematic diagram of the hardware architecture of a general train redundancy TRDP Ethernet board provided in an embodiment of the present invention. Figure 2 This is a schematic diagram illustrating the connection relationship between a general-purpose train redundancy TRDP Ethernet board and an external main CPU board, as provided in an embodiment of the present invention.

[0021] like Figure 1 and Figure 2 As shown, the general-purpose train redundancy TRDP Ethernet board includes: a first processor, a second processor, a first Ethernet chip, a second Ethernet chip, and an FPGA bridge chip.

[0022] The first and second processors are the same type of ARM processor, each driving an Ethernet chip via a PCIe interface to achieve Ethernet communication. Figure 2 As shown, this application achieves communication isolation between the two Ethernet paths by separately configuring the Ethernet circuits of the first and second processors, avoiding the situation where data anomalies such as network storms in one network affect the other Ethernet path. The first and second processors respectively use the open-source TRDP library to implement TRDP processing functions. The first and second processors interact with the external main CPU board through an FPGA bridging chip. The external main CPU board and the FPGA bridging chip are connected via a backplane trace. During initialization, the external main CPU board configures parameters such as the data port number, port size, and communication cycle of the first and second processors, and then periodically acquires the Ethernet data received by the first and second processors and sends the data back to the first and second processors, which then convert it into TRDP data and send it to the Ethernet local area network.

[0023] The first processor is loaded with a first operating system and a first TRDP protocol stack running on the first operating system; the second processor is loaded with a second operating system and a second TRDP protocol stack running on the second operating system. The first and second operating systems run independently of each other, making the two TRDP communications completely isolated at the software level.

[0024] The first and second processors are each equipped with independent watchdog circuits. Upon power-up, each processor independently boots its own operating system and receives port configuration information from the external main CPU board via the FPGA bridge chip, completing port initialization independently. After successful initialization, each processor independently transmits and receives TRDP data via its respective Ethernet interface. If either processor fails to initialize, the corresponding watchdog circuit independently triggers a restart of that processor. During data transmission and reception, both processors continuously monitor the health status of the external main CPU board; if the health status is abnormal, they stop sending data to the Ethernet.

[0025] The FPGA bridging chip is used for data bridging and signal pass-through between the first processor, the second processor, and the external main CPU board, but it does not perform TRDP protocol processing. The FPGA bridging chip also receives reset signals from the external main CPU board and passes these reset signals through to the first and second processors. Because the FPGA bridging chip does not participate in TRDP protocol processing, when the TRDP protocol version is upgraded, only the software on the first and second processors needs to be updated; the hardware logic of the FPGA bridging chip does not need to be modified, thus providing good maintainability and upgrade flexibility.

[0026] The first processor connects to the first Ethernet chip via the first PCIe interface, and the second processor connects to the second Ethernet chip via the second PCIe interface. Using PCIe interfaces to connect the Ethernet chips provides a high-bandwidth, low-latency data transmission channel, meeting the TRDP protocol's requirements for 100 Mbps / 1 Gbps data transmission rates.

[0027] The first Ethernet chip is connected to the first Ethernet interface, and the second Ethernet chip is connected to the second Ethernet interface. The first Ethernet interface and the second Ethernet interface are physically isolated from each other, as are the first Ethernet chip and the second Ethernet chip. Specifically, the first Ethernet interface and the second Ethernet interface are independent of each other in both power and signal circuits. When the first Ethernet interface is damaged by an external lightning surge or network storm, causing damage to the first Ethernet chip, the second Ethernet interface and the second Ethernet chip are completely unaffected and can continue to operate normally, thus achieving true interface-level physical isolation redundancy.

[0028] When the first and second processors receive TRDP data through their respective Ethernet interfaces, they support three data reception modes: unicast, multicast, and broadcast, which can flexibly adapt to different data distribution scenarios in the train communication network.

[0029] Example 2 Figure 3 A schematic diagram of the software system architecture of a general train redundancy TRDP Ethernet board provided for embodiments of the present invention.

[0030] like Figure 3 As shown, the first and second operating systems respectively include: a u-boot bootloader, a Linux kernel, a file system, a startup script, and a TRDP application. After the system powers on, each processor sequentially executes u-boot booting, Linux kernel loading, file system mounting, and automatically starts the TRDP application through the startup script.

[0031] Since the first and second processors each run independent Linux operating systems and independent TRDP protocol stack instances, when one processor's operating system or TRDP protocol stack experiences a software failure, the other processor remains unaffected and can still independently complete the sending and receiving of TRDP data, thus achieving system-level software redundancy.

[0032] Example 3 Figure 4 This is a schematic diagram of the data processing flow of a general train redundancy TRDP Ethernet board provided for embodiments of the present invention.

[0033] like Figure 4 As shown, the first processor sends the TRDP data received by the first Ethernet chip to the FPGA bridge chip, and then uploads it to the external main CPU board via the backplane. The external main CPU board performs logical processing on the uploaded TRDP data and then sends the data to be sent down to the FPGA bridge chip via the backplane. The FPGA bridge chip bridges the data to be sent to the first processor and the second processor respectively, and the first processor and the second processor convert the data to be sent into TRDP data via the first Ethernet chip and the second Ethernet chip respectively, and send it to the local area network.

[0034] The data processing flow described above indicates that the first and second processors act as TRDP communication coprocessors in the system, responsible only for packaging and unpacking TRDP protocols and sending and receiving data. The main control logic for train operation, such as logical operations, condition judgments, and control decisions, is handled independently by the external main CPU board. This architecture, separating logical operations from communication processing, ensures that the main CPU board's computing resources are not consumed by TRDP protocol processing, guaranteeing the real-time performance of the train control logic. Simultaneously, the real-time performance of TRDP communication is not affected by fluctuations in the main CPU board's load.

[0035] Example 4 Figure 5 This is a flowchart illustrating the initialization and data transmission / reception process of a general train redundancy TRDP Ethernet board provided for embodiments of the present invention.

[0036] like Figure 5 As shown, the initialization and data transmission / reception process of the first and second processors includes the following steps: Step S1: After the system is powered on, each processor performs system initialization and receives configuration information from the external main CPU board through the FPGA bridge chip to initialize the Ethernet port.

[0037] Step S2: If initialization fails, the watchdog circuit of the corresponding processor is triggered, and the processor is independently restarted. This independent restart mechanism ensures that when the first processor fails to initialize, only the first processor restarts, while the second processor continues to operate normally, without affecting B-channel TRDP communication; similarly, when the second processor fails to initialize, only the second processor restarts, without affecting A-channel communication.

[0038] Step S3: If initialization is successful, start the receiving thread and the sending thread respectively. When the TRDP port receive period timer is triggered, the receiving thread sends the TRDP data received by the Ethernet interface to the external main CPU board via the FPGA bridge chip; when the TRDP port send period timer is triggered, the sending thread sends the data sent by the external main CPU board to the local area network via the Ethernet interface.

[0039] Through the above initialization and fault-tolerance process, this application realizes independent startup and fault isolation of dual-channel TRDP communication. The initialization failure of any processor will not cause the entire board to fail, which significantly improves the reliability and availability of the train communication system.

[0040] Example 5 Figure 6 A flowchart illustrating the main CPU health status detection process for a general train redundancy TRDP Ethernet board provided in this embodiment of the invention.

[0041] like Figure 6 As shown, the health status of the external main CPU board is characterized by a heartbeat signal or a level signal periodically sent by the external main CPU board. When the first processor and the second processor do not receive a heartbeat signal or detect a level signal transition within a preset time, the health status of the external main CPU board is determined to be abnormal, and data transmission to the Ethernet is stopped.

[0042] This health status detection mechanism can effectively prevent the first and second processors from continuing to send invalid or erroneous data to the train network when the external main CPU board malfunctions, such as crashing or program crashing, thereby avoiding the spread of the fault and protecting the communication security of the train backbone network.

[0043] By applying the general-purpose train redundancy TRDP Ethernet board provided in this application, and through dual processors running the operating system and TRDP protocol stack independently respectively, coupled with dual-path Ethernet physical isolation and dual independent watchdogs, end-to-end dual-path redundancy is achieved from the physical layer to the protocol layer. When one path suffers a lightning strike, network storm, or processor / operating system failure, the other path remains completely unaffected and can continue to operate. If either processor experiences initialization or operational abnormalities, the independent watchdog accurately triggers the restart of that processor without affecting the other path, effectively avoiding board failure caused by a single point of failure and significantly improving the reliability and availability of the train communication network in harsh electromagnetic environments.

[0044] Meanwhile, this invention employs an architecture where the FPGA is used solely for data bridging, while protocol processing is entirely implemented by the processor software. Protocol version upgrades only require software updates without modifying the FPGA. The first and second processors are solely responsible for TRDP communication, while train control logic is independently completed by an external main CPU board. The two processors do not interfere with each other, ensuring real-time performance at both ends. Furthermore, the device adopts a modular board structure, facilitating on-site plug-and-play maintenance. This invention comprehensively improves the reliability, real-time performance, and maintainability of train TRDP Ethernet communication from multiple dimensions, including physical isolation, independent fault tolerance, architecture separation, software upgrades, health monitoring, and modular structure.

[0045] Example 6 This application also includes a general-purpose train redundancy TRDP Ethernet device, which includes a chassis, a backplane, and an Ethernet board as described in any of the above embodiments. The Ethernet board is plugged into the backplane and communicates with an external main CPU board through the backplane. A power module supplies power to the Ethernet board through the backplane.

[0046] This Ethernet device adopts a standard board-type structure, with the Ethernet boards being pluggable and detachable within the chassis, facilitating on-site installation, maintenance, and replacement. It is suitable for the maintainability requirements of rail transit vehicles.

[0047] By applying the universal train redundancy TRDP device provided in this application, the universal dual-redundancy TRDP Ethernet device of the present invention integrates the TRDP communication function onto an independent pluggable board. Any CPU host with a PCI bus can directly transmit and receive train TRDP data through this board. Each onboard device no longer needs to repeatedly develop for the TRDP protocol. It can directly call this universal board to access the train Ethernet communication network, which greatly shortens the R&D cycle for different vehicle models and different equipment manufacturers, and reduces development costs and communication protocol adaptation risks.

[0048] Meanwhile, the device achieves end-to-end isolation of dual Ethernet networks from the physical layer to the protocol layer. When one network experiences a network storm or external interference, the other Ethernet network remains completely unaffected and can continue to independently complete data transmission and reception. This overcomes the defect of a single-path failure affecting the overall communication, ensuring the real-time performance and security of train data communication. The device adopts a modular structure of chassis, backplane, and circuit boards. The circuit boards are pluggable, and maintenance and replacement do not require disassembling the entire unit, reducing the difficulty of on-site operation and maintenance.

[0049] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0050] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented in hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0051] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this application. It should be understood that the above description is only a specific embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A universal train redundancy TRDP Ethernet board, characterized in that, include: The system comprises a first processor, a second processor, a first Ethernet chip, a second Ethernet chip, and an FPGA bridge chip. The first processor is loaded with a first operating system and a first TRDP protocol stack running on the first operating system; the second processor is loaded with a second operating system and a second TRDP protocol stack running on the second operating system; the first operating system and the second operating system run independently of each other; The first processor and the second processor are each equipped with an independent watchdog circuit; After power-on, the first processor and the second processor independently start their respective operating systems and receive port configuration information from the external main CPU board through the FPGA bridge chip, and each completes port initialization independently. After successful initialization, they independently transmit and receive TRDP data through their respective Ethernet interfaces. If any processor fails to initialize, the corresponding watchdog circuit independently triggers the processor to restart. During data transmission and reception, the first processor and the second processor continuously monitor the health status of the external main CPU board, and stop sending data to the Ethernet when the health status is abnormal.

2. The Ethernet board according to claim 1, characterized in that, The FPGA bridging chip is used for data bridging and signal pass-through between the first processor, the second processor and the external main CPU board, and does not perform TRDP protocol processing; and receives a reset signal sent by the external main CPU board and sends the reset signal to the first processor and the second processor.

3. The Ethernet board according to claim 1, characterized in that, The first operating system and the second operating system each include: a u-boot bootloader, a Linux kernel, a file system, a startup script, and a TRDP application; after the system is powered on, each processor sequentially executes u-boot booting, Linux kernel loading, and file system mounting, and automatically starts the TRDP application through the startup script.

4. The Ethernet board according to claim 1, characterized in that, The first processor sends the TRDP data received by the first Ethernet chip to the FPGA bridge chip and uploads it to the external main CPU board. After the external main CPU board performs logical processing on the uploaded TRDP data, it sends the data to be sent to the FPGA bridge chip. The FPGA bridge chip bridges the data to be sent to the first processor and the second processor respectively. The first processor and the second processor convert the data to be sent into TRDP data and send it to the local area network through the first Ethernet chip and the second Ethernet chip respectively.

5. The Ethernet board according to claim 1, characterized in that, The initialization and data transmission / reception process of the first and second processors includes: After the system is powered on, each processor performs system initialization and receives configuration information from the external main CPU board through the FPGA bridge chip to initialize the Ethernet port. If initialization fails, the watchdog circuit of the corresponding processor is triggered, and an independent restart is performed on that processor. If initialization is successful, the receiving thread and the sending thread will be started respectively. When the receiving period timer on the TRDP port is triggered, the receiving thread will send the TRDP data received by the Ethernet interface to the external main CPU board via the FPGA bridge chip. When the sending period timer on the TRDP port is triggered, the sending thread will send the data sent by the external main CPU board to the local area network via the Ethernet interface.

6. The Ethernet board according to claim 1, characterized in that, The first Ethernet chip is connected to the first Ethernet interface, and the second Ethernet chip is connected to the second Ethernet interface; the first Ethernet interface and the second Ethernet interface are physically isolated from each other, and the first Ethernet chip and the second Ethernet chip are physically isolated from each other.

7. The Ethernet board according to claim 1, characterized in that, The health status of the external main CPU board is defined as follows: the external main CPU board periodically sends a heartbeat signal or a level signal; when the first processor and the second processor do not receive the heartbeat signal or detect the level signal change within a preset time, the health status of the external main CPU board is determined to be abnormal, and data transmission to the Ethernet is stopped.

8. The Ethernet board according to claim 1, characterized in that, The first processor is connected to the first Ethernet chip via a first PCIe interface, and the second processor is connected to the second Ethernet chip via a second PCIe interface.

9. The Ethernet board according to claim 1, characterized in that, When the first processor and the second processor receive TRDP data through their respective Ethernet interfaces, they support three data reception modes: unicast, multicast, and broadcast.

10. A universal train redundancy TRDP Ethernet device, characterized in that, The Ethernet device includes a chassis, a backplane, and an Ethernet board as described in any one of claims 1-9. The Ethernet board is plugged into the backplane and communicates with an external main CPU board through the backplane.

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