Differential envelope detector circuit with common mode noise rejection

Abstract

The present disclosure relates to a differential envelope detector circuit with common mode noise rejection. In some examples, the differential envelope detector circuit includes a differential transconductance circuit configured to receive a first voltage signal and a second voltage signal of a differential signal and generate a first output current signal based on the first voltage signal and the second voltage signal, a common mode detection circuit configured to generate a common mode current signal indicative of common mode noise present in the first voltage signal and the second voltage signal of the differential signal, and a summing circuit configured to generate a second output current signal by removing the common mode current signal from the first output current signal.

Description

Technical Field

[0001] This disclosure relates to differential envelope detector circuits, such as differential envelope detector circuits used in receiver circuits configured to receive differentially coded data through an electrical isolation barrier. Background Technology

[0002] Differential envelope detector circuits are used for data communication between circuits. For example, a differential envelope detector circuit can be used to decode information encoded using On-Off Keying (OOK) with a differential carrier signal. In OOK and other encoding techniques, the envelope detector circuit is expected to be used to decode information from one or more coded signals. OOK is very useful in many cases due to its high noise immunity to common-mode noise. A useful application of OOK with a differential carrier is data communication through electrical isolation barriers, such as for communicating information between different voltage domains.

[0003] Electrical isolation can be used in electronic devices to separate two voltage domains within a circuit package. For example, a microcontroller can generate control signals and transmit them to low-side and high-side gate drivers to control low-side and high-side power switches arranged in a half-bridge circuit. Electrical isolation may be desirable to ensure that the microcontroller is protected from the high voltage domain associated with one or both gate drivers. One or both of the microcontroller and gate drivers can be configured to operate in different power domains.

[0004] Gate drivers used in power switches are just one example of the use of electrical isolation, but it can be used for many other purposes and applications. Generally, when electrical isolation is desired, a circuit package can be defined as having two electrically isolated circuits. Data communication across electrical isolation barriers (e.g., within the circuit package) may be expected to aid in circuit control or for other reasons. Summary of the Invention

[0005] This disclosure describes a differential envelope detector circuit and a method of operating the differential envelope detector circuit. This disclosure also describes devices comprising two circuits separated by an electrical isolation barrier, which can use the differential envelope detector circuit to decode information communicated through the electrical isolation barrier.

[0006] In some examples, this disclosure describes an apparatus arranged to include an electrical isolation barrier between a first voltage domain and a second voltage domain. The apparatus may include transmitter circuitry in the first voltage domain and receiver circuitry in the second voltage domain. The receiver circuitry may include a differential envelope detector circuitry comprising: a differential transconductance circuit configured to receive a first voltage signal and a second voltage signal of differential signals, and to generate a first output current signal based on the first voltage signal and the second voltage signal; a common-mode detection circuit configured to generate a common-mode current signal indicating the presence of common-mode noise in the first voltage signal and the second voltage signal of the differential signals; and a summing circuit configured to generate a second output current signal by removing the common-mode current signal from the first output current signal.

[0007] In some examples, this disclosure describes a differential envelope detector circuit comprising: a differential transconductance circuit configured to receive a first voltage signal and a second voltage signal of differential signals, and to generate a first output current signal based on the first voltage signal and the second voltage signal; a common-mode detection circuit configured to generate a common-mode current signal indicating the presence of common-mode noise in the first voltage signal and the second voltage signal of the differential signals; and a summing circuit configured to generate a second output current signal by removing the common-mode current signal from the first output current signal.

[0008] In some examples, this disclosure describes a method performed by an envelope detector circuit. The method may include: receiving a first voltage signal and a second voltage signal at a differential transconductance circuit, wherein the first voltage signal and the second voltage signal define a differential signal via the differential transconductance circuit; generating a first output current signal based on the first voltage signal and the second voltage signal; generating a common-mode current signal indicating the presence of common-mode noise in the first voltage signal and the second voltage signal via a common-mode detection circuit; and generating a second output current signal by removing the common-mode current signal from the first output current signal via a summing circuit.

[0009] Details of one or more examples are set forth in the accompanying drawings and the description below. Other features, objects, and advantages will become apparent from the description, the drawings, and the claims. Attached Figure Description

[0010] Figure 1 It is a block diagram of an apparatus consistent with this disclosure.

[0011] Figure 2A and Figure 2B Is with Figure 1 A conceptual illustration of an example circuit package device consistent with this disclosure.

[0012] Figure 3This is a set of diagrams illustrating an example of differential coding using On-Off Keying (OOK) with a differential carrier signal.

[0013] Figure 4 It shows that it can be used Figure 1 A block diagram of an example differential envelope detector circuit in a device or other device or circuit.

[0014] Figure 5 This is another set of diagrams illustrating differential signaling and decoding consistent with this disclosure.

[0015] Figure 6 This is a circuit diagram illustrating an example device with a differential envelope detector circuit consistent with this disclosure.

[0016] Figure 7 It is a flowchart consistent with one or more examples of this disclosure. Detailed Implementation

[0017] This disclosure describes a differential envelope detector circuit and a method of operating the differential envelope detector circuit. This disclosure also describes devices comprising two circuits separated by an electrical isolation barrier, which can use the differential envelope detector circuit to decode information communicated through the electrical isolation barrier.

[0018] In large equipment or systems such as electric vehicles, there is a growing demand for electrically isolated devices. Electrical isolation requires a very high level of robustness while allowing data communication across the isolation barrier. For this purpose, circuits can be configured to perform differential coding using on-off keying (OOK) with a differential carrier signal. OOK with a differential carrier signal is desirable because it offers relatively high common-mode transient immunity (CMTI).

[0019] However, in addition to high CMTI, common-mode immunity to electromagnetic noise is also desired for modern devices or systems such as electric vehicles. Electromagnetic noise injection tests can be performed on devices or systems to measure common-mode immunity beyond CMTI. System-level electromagnetic noise injection tests are sometimes performed up to 6 GHz. At such high frequencies, circuitry using OOK with differential carrier signals may not achieve sufficient common-mode immunity for some devices or systems. In one or more examples of this disclosure, the described circuitry and techniques address these issues and can achieve electromagnetic noise common-mode immunity up to or above 6 GHz. In some examples, the circuitry and techniques described in this disclosure can achieve significant improvements in CMTI suppression over the frequency range of 1 GHz to 6 GHz.

[0020] Electrical isolation of a circuit can be achieved by using a transformer (e.g., a coreless transformer) or other isolation elements (e.g., a capacitor) to electrically isolate the low-voltage domain of a first circuit from the high-voltage domain of a second circuit. In some examples, this disclosure describes circuit package devices and techniques for data communication within a circuit package device. In particular, this disclosure describes techniques for communication via an electrical isolation barrier formed between two different circuits within a circuit package. To achieve improved common-mode immunity, this disclosure also describes improvements to an envelope detector circuit that can be used on the receiving side of communication via an electrical isolation barrier. In some examples, the described envelope detector circuit can also be used in other systems or devices, including communication systems without electrical isolation.

[0021] In some examples, when electrical isolation is used, the first and second circuits can be embedded in molding material within the circuit package, and the first and second circuits can be mechanically separated from each other by less than 5 mm, less than 3 mm, or less than 1 mm within the circuit package. The electrical isolation barrier can be implemented using one or more inductors and / or one or more capacitors. The one or more inductors and / or one or more capacitors defining the electrical isolation can also form a communication channel for data communication between two different circuits within the circuit package.

[0022] The communication channel across the electrical isolation barrier between the first and second circuits may include a differential communication channel. According to this disclosure, in some examples, the first and second circuits may be configured to encode data across the differential communication channel using on-off keying (OOK) with a differential carrier signal.

[0023] Figure 1This is a block diagram of device 10 consistent with one or more examples of this disclosure. Device 10 is arranged to include an electrical isolation barrier 150 between a first voltage domain (e.g., on the left side of barrier 150) and a second voltage domain (on the right side of barrier 150). Device 10 includes transmitter circuitry 102 in the first voltage domain and receiver circuitry 104 in the second voltage domain. According to some examples of this disclosure, receiver circuitry 104 includes differential envelope detector circuitry 120 configured to remove common-mode noise from a received differential signal. As described in the examples below, differential envelope detector circuitry 120 may include: a differential transconductance circuit configured to receive a first voltage signal and a second voltage signal of the differential signal, and generate a first output current signal based on the first voltage signal and the second voltage signal; a common-mode detection circuit configured to generate a common-mode current signal indicating the presence of common-mode noise in the first voltage signal and the second voltage signal of the differential signal; and a summing circuit configured to generate a second output current signal by removing the common-mode current signal from the first output current signal. The following describes additional circuit details and examples that can be used in the differential envelope detector circuit 120.

[0024] Figure 2A This is a conceptual cross-sectional side view of a device including a circuit package 200A. The circuit package 200A includes a first circuit 202A and a second circuit 212A, the first circuit 202A being configured to operate in a first voltage domain and the second circuit 212A being configured to operate in a second voltage domain. The first voltage domain and the second voltage domain are different. For example, the first voltage domain may include a low voltage domain of less than 40 volts, and the second voltage domain may include a high voltage domain of greater than 100 volts. Figure 2A In the example, the first circuit 202A and the second circuit 212A are formed on different circuit dies, and the device 200A includes a molding compound 208A formed around the different circuit dies of the first circuit 202A and the second circuit 212A.

[0025] In the circuit package 200A, one or more isolation elements (e.g., multiple inductors or multiple capacitors) can be configured to define an electrical isolation barrier 206A between a first voltage domain and a second voltage domain. This is in Figure 2AThe diagram is conceptually illustrated using inductor and capacitor symbols. For example, inductors may be arranged to define a transformer, such as a coreless transformer. The one or more isolation elements (e.g., multiple inductors or multiple capacitors) may also define a differential communication channel 250A configured to communicate data between a first circuit 202A and a second circuit 212A via an electrical isolation barrier 206A. In some examples, a grounded protective strip may surround the isolation element, and in some examples, the grounded protective strip may also surround circuit 202A operating in a low-voltage domain. The grounded protective strip (not shown) can improve electrical isolation between two different circuits. A molding material 208A (such as a molding compound) may encapsulate circuits 202A and 212A to define a circuit package 200A. Other devices or circuits may be connected to the circuit package 200A via external conductors (not shown), which provide electrical access to circuits 202A and 212A through the molding material 208A.

[0026] As described in more detail below, the first circuit 202A and the second circuit 212A can be configured to communicate encoded data across the differential communication channel 250A within the circuit package 200A using differential coding techniques. Furthermore, as described herein, the second circuit 212A may include an envelope detector to achieve improved common-mode noise immunity.

[0027] Figure 2B This is a conceptual cross-sectional side view of the device 200B, which includes the circuit package 200B. Figure 2B The 200B circuit package is similar to in many ways to Figure 2A The circuit package 200A is very similar. The circuit package 200B includes a first circuit 202B configured to operate in a first voltage domain and a second circuit 212B configured to operate in a second voltage domain. The first voltage domain differs from the second voltage domain. Similarly, for example, the first voltage domain may include a low voltage domain below 40 volts, and the second voltage domain may include a high voltage domain above 100 volts. Figure 2B In the example, the first circuit 202B and the second circuit 212B are formed on the same circuit die during the semiconductor manufacturing process, having a trench 206B formed in the circuit die. The trench 206B can electrically isolate the first voltage domain from the second voltage domain. The device 200B may include a molding material (such as a molding compound) formed around the common circuit die including the first circuit 202B and the second circuit 212B.

[0028] One or more external conductors may be electrically connected to the first circuit 202B and the second circuit 212B. Insulating material may be formed on the common circuit die. Within the circuit package 200B, one or more isolation elements (e.g., multiple inductors or multiple capacitors illustrated by inductor and capacitor symbols) may be configured to define an electrical isolation barrier between a first voltage domain and a second voltage domain separated by trench 206B. The one or more isolation elements (e.g., multiple inductors or multiple capacitors) also define a differential communication channel 250B configured to communicate data between the first circuit 202B and the second circuit 212B across the electrical isolation barrier defined by trench 206B. In some examples, a grounded protective strip may surround the isolation elements, and in some examples, the grounded protective strip may also surround one or both of circuits 202B and 212B. Molding material 208B may encapsulate circuits 202B and 212B to define the circuit package 200B. Other devices or circuits may be connected to the circuit package 200B via external conductors (not shown), which provide electrical access to the first circuit 202B and the second circuit 212B through molding material 208A.

[0029] and Figure 2A As shown in the example, in Figure 2B In this circuit, the second circuit 212B may include an envelope detector as described herein to achieve improved common-mode noise immunity. (Reference) Figure 2A and Figure 2B In various examples, the first circuits 202A and 202B can operate in low-voltage domains, such as the voltage domains associated with microcontrollers, such as 5 volts, 3.3 volts, or other voltages typically used for low-voltage microcontrollers. The second circuits 212A and 212B can operate in high-voltage domains, such as the voltage domains associated with high-voltage power switches, such as 400-6000 volts associated with insulated-gate bipolar transistors (IGBTs), 600-1200 volts associated with silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs), 600-1200 volts associated with gallium nitride (GaN) field-effect transistors (FETs), or even higher voltages associated with gate turn-off (GTO) thyristors, other types of thyristors, or other types of power switches.

[0030] In other examples, the techniques and circuits of this disclosure can be used in any circuit-packaged device that performs communication through an electrical isolation barrier within the circuit package device. Electrical isolation may be desirable for controlling various types of field-effect transistors (FETs), including metal-oxide-semiconductor field-effect transistors (MOSFETs), bipolar junction transistors (BJTs), insulated-gate bipolar transistors (IGBTs), junction field-effect transistors (JFETs), high electron mobility transistors (HEMTs), or any other type of element using voltage or current for control. Such transistors can be formed from various material compounds, such as silicon, silicon carbide, gallium nitride, or any other combination of one or more semiconductor materials. In some examples, silicon carbide switches may experience lower switching power losses. Magnetic improvements and faster switching, such as gallium nitride switches, may allow the power transistor to draw short-duration current pulses. These higher-frequency devices may require control signals (e.g., voltage signals transmitted to the control terminals of the power transistor) to be sent with more precise timing compared to lower-frequency devices.

[0031] Figure 3 This is a set of charts illustrating the differential OOK consistent with this disclosure. Figure 3 In contrast, OOK refers to a form of amplitude shift keying (ASK) modulation that modulates digital data (e.g., ...). Figure 3 The input data 302 shown is represented as a carrier (e.g., Figure 3 The presence or absence of “A” 304 and “B” 306 shown in the diagram. For differential OOK, carrier “A” can be phase-shifted relative to carrier “B”. Differential carrier data (e.g. Figure 3 A and B in the diagram can be transmitted from transmitter circuit 102 and received by receiver circuit 104, and then decoded to generate... Figure 3 The output data is shown in the figure. The output data can represent binary bits similar to the input data, where time t1 represents, for example, data generated by an envelope detector circuit based on differential carrier data (e.g., ...). Figure 3 The disclosure describes the delay time required to reconstruct the data (A and B) in the diagram. This disclosure also describes improvements to the envelope detector circuitry that may be useful in these or other applications.

[0032] Figure 4 This is a block diagram illustrating an example of a differential envelope detector circuit 420, which can be used in... Figure 1 equipment Figure 2A The second circuit 212A, Figure 2B In the second circuit 212B or other devices or circuits. For example... Figure 4As shown, the differential envelope detector circuit 420 includes a differential transconductance circuit 430, which may include a gain stage (also referred to as a differential transconductance stage). The differential envelope detector circuit 420 can be configured to receive a first voltage signal (In+) and a second voltage signal (In-) of the differential signal, and generate a first output current signal based on the first and second voltage signals. The differential transconductance circuit 430 may include a transconductance amplifier used as an active rectifier. For example, as... Figure 5 As shown, the differential transconductance circuit 430 can receive signals from... Figure 5 The first voltage signal (In+) corresponding to signal 502 and the... Figure 5 The second voltage signal (In-) corresponding to the intermediate signal 504. The output of the differential transconductance circuit 430 is... Figure 5 The rectified signal corresponding to signal 506. According to this disclosure, the differential envelope detector circuit 420 can be configured to remove common-mode noise from signal 506, i.e., noise present in both the first input signal 502 and the second input signal 504.

[0033] The differential envelope detector circuit 420 includes a common-mode detection circuit 440 configured to generate a common-mode current signal indicating the presence of common-mode noise in a first voltage signal (In+) and a second voltage signal (In-) of the differential signals; and a summing circuit 450 configured to generate a second output current signal by removing the common-mode current signal from the first output current signal. A signal identification circuit 460 can be configured to determine a high or low state associated with the second output current signal. Specifically, for example, the signal identification circuit 460 can be configured to respond to an output current signal 506 exceeding a threshold (I0). reference )508 outputs logic signal 510 (logic high). Similarly, when the output current signal 506 does not exceed the threshold (I reference In the case of 508, a logic low signal 512 can be output. Figure 5 The time "t1" shown corresponds to the delay time from when the differential envelope detector circuit 420 receives the input voltage signal to when it outputs the logic signal 510. Threshold (I reference )508 can be with Figure 4 The “Ref” shown corresponds to this.

[0034] In various examples, the signal identification circuit 460 can be implemented using capacitors, comparators, Schmitt triggers, and analog-to-digital converters (ADCs) or other circuit elements. In a more detailed circuit example described below, a current mirror and capacitors can be arranged to implement the summing circuit 450 to remove common-mode current noise from the output of the differential transconductance circuit 430. This improves the ability of the signal identification circuit 460 to accurately identify whether the differential signal corresponds to a logic high or a logic low.

[0035] In some examples, the differential transconductance circuit 430 may include two half-bridge circuits: a first high-side transistor and a first low-side transistor arranged in a first half-bridge; and a second high-side transistor and a second low-side transistor arranged in a second half-bridge. The two voltage signals of the differential signal may be routed to the high side and low side in a complementary manner. That is, the first high-side transistor and the second low-side transistor may be configured to receive the first voltage signal of the differential signal, while the second high-side transistor and the first low-side transistor may be configured to receive the second voltage signal of the differential signal. In this case, the common-mode detection circuit 440 may include a third high-side transistor and a third low-side transistor arranged in a third half-bridge, both connected to the circuit nodes that receive both the first and second voltage signals of the differential signal. The circuit node that receives both the first and second voltage signals of the differential signal may be a node located between two resistors electrically connected to the inputs of the first voltage signal (In+) and the second voltage signal (In-) of the differential signal.

[0036] The first low-side transistor may have an inverted input relative to the first high-side transistor, the second low-side transistor may have an inverted input relative to the second high-side transistor, and the third low-side transistor may have an inverted input relative to the third high-side transistor. As a half-bridge circuit, the output of the first high-side transistor may be connected to the input of the first low-side transistor to form a first half-bridge, the output of the second high-side transistor may be connected to the input of the second low-side transistor to form a second half-bridge, and the output of the third high-side transistor may be connected to the input of the third low-side transistor to form a third half-bridge. Figure 6 Provided in conjunction with the above Figure 4 An example circuit that is consistent in many aspects of the description.

[0037] Figure 6 It is a circuit diagram of a device consistent with one or more examples of this disclosure. Figure 6 The device is arranged to include an electrical isolation barrier 650 between a first voltage domain (e.g., on the left side of the isolation barrier 650) and a second voltage domain (on the right side of the isolation barrier 650). Figure 6The device includes a transmitter circuit 602 in a first voltage domain and an envelope detector circuit 620 in a second voltage domain. In some examples, the envelope detector circuit 620 may include the front end portion of a larger receiver circuit. Figure 6 The arrangement of the circuit elements shown is an example of implementing a differential envelope detector circuit configured to remove common-mode noise from the received differential signal.

[0038] like Figure 6 As shown, the differential voltage signal can be received on input lines 692 and 694. Specifically, the first voltage signal is received by the receiver circuit on line 692, and the second voltage signal is received by the receiver circuit on line 694. The first and second voltage signals define the differential signal.

[0039] Component 630 may define a portion of a differential transconductance circuit that receives a first voltage signal and a second voltage signal on lines 692 and 694. The differential envelope detector circuit 620 includes a common-mode detection circuit, which may be implemented using a half-bridge 640, transistors M1 682 and M2 684, and capacitor 686, along with corresponding input capacitors 625 and 626 and output resistors 675 and 676 associated with transistors 642 and 644 of the half-bridge 640.

[0040] The differential transconductance circuit may include two half-bridge circuits within element 630. The output of the first high-side transistor 632 is connected to the input of the first low-side transistor 634 to define the first half-bridge. Similarly, the output of the second high-side transistor 636 is connected to the input of the second low-side transistor 644 to define the second half-bridge.

[0041] The two voltage signals of the differential signal (e.g., on lines 692, 694) can be routed to the high and low sides in a complementary manner. That is, the first high-side transistor 632 and the second low-side transistor 638 are configured to receive the first voltage signal of the differential signal, while the second high-side transistor 636 and the first low-side transistor 634 are configured to receive the second voltage signal of the differential signal. Capacitors 622, 624, 628, 629 and resistors 672, 674, 678, 679 are arranged to appropriately control the voltage signals applied to the control terminals (e.g., gates) of transistors 632, 636, 638, 634 and transistors 652, 654, thereby realizing a transconductance circuit. Current sources 656, 658 provide current sources and current sinks through transistors 652, 654. A voltage bias (“Vbias”) can be set or controlled at the node between transistors 652, 654. Capacitors 622, 624, 628, and 629 can operate as high-pass filters to remove low-frequency common-mode noise. Therefore, in some examples, capacitors 622, 624, 628, and 629 can define a first common-mode filter for the envelope detector circuit 620, and the common-mode detection circuit portion of the envelope detector circuit 620 (described below) can define a second common-mode filter. In this case, the first filter defined by capacitors 622, 624, 628, and 629 can define a low-frequency filter for the envelope detector circuit 620, and the common-mode detection circuit portion of the envelope detector circuit 620 can define a high-frequency filter.

[0042] The first half-bridge defined by transistors 632 and 634 defines a first parasitic capacitance 637, and the second half-bridge defined by transistors 636 and 638 defines a second parasitic capacitance 635. To some extent, the presence of parasitic capacitances 637 and 635 may help to solve the problems and high-frequency common-mode noise problems that the present disclosure and its circuitry aim to address.

[0043] Similarly, the differential envelope detector circuit 620 includes a common-mode detection circuit, which can be implemented by a half-bridge 640 (hereinafter referred to as the third half-bridge), transistors M1 682 and M2 684, and capacitor 686, together with corresponding input capacitors 625 and 626 and output resistors 675 and 676 associated with transistors 642 and 644 of the third half-bridge 640.

[0044] The third half-bridge 640 includes a third high-side transistor 642 and a third low-side transistor 644 arranged in a half-bridge configuration, both connected to a circuit node that receives both a first voltage signal and a second voltage signal, representing differential signals. In this case, the circuit node receiving both the first and second voltage signals can be a node located between resistors 612 and 614, electrically connected to the first voltage signal input on line 692 and the second voltage signal input on line 694. The third high-side transistor 642 and the third low-side transistor 644 generate a third parasitic capacitance 645, which can be configured to be the same as the first parasitic capacitance 637 and the second parasitic capacitance 635.

[0045] To achieve complementary operation of the first, second, and third half-bridges in the envelope detector circuit 620, the first low-side transistor 634 may have an inverted input relative to the first high-side transistor 632, the second low-side transistor 638 may have an inverted input relative to the second high-side transistor 636, and the third low-side transistor 644 may have an inverted input relative to the third high-side transistor 642. The third half-bridge 640 generates a common-mode current signal indicating common-mode noise present in the first voltage signal (on line 692) and the second voltage signal (on line 694) of the differential signals. Transistors 682, 684, and capacitor 686 may define a summing circuit configured to generate a second output current signal (“output”) by removing the common-mode current signal from the first output current signal (i.e., the current flowing through the two half-bridge circuits within element 630).

[0046] Capacitor 686 can be connected to a first output current signal (e.g., the first output current signal of the outputs of the two half-bridge circuits within element 630). Capacitor 686 can store a mirror indication of the common-mode current signal generated by the common-mode detection circuit described herein. The common-mode current signal may flow through transistor M1 682 to ground, and a mirror of this common-mode current signal flows from capacitor 686 through transistor M2 684 to ground. With this arrangement, the common-mode current signal is caused to flow from the output node of envelope detector circuit 620 ( Figure 6 The first current signal at the "output" position is removed. Therefore, Figure 6 The output is defined as a second current signal, which is the first current signal (from component 630) minus the common-mode current signal (from the output of half-bridge 640).

[0047] Then, the signal identification circuit ( Figure 6 (Not shown) can be configured to determine a high or low state associated with the second output current signal. Specifically, refer again... Figure 5 For example, the signal identification circuit can be configured to respond to the output current signal 506 exceeding a threshold (I reference)508 outputs logic signal 510 (logic high). Similarly, when the output current signal 506 does not exceed the threshold (I reference In the case of 508, a logic low signal 512 can be output. Similarly, Figure 5 The time "t1" shown may correspond to the delay time from when the differential envelope detector circuit receives its input voltage signal to when it outputs the logic signal 510. Threshold (I reference )508 can be limited in various ways or can be pre-limited. In some examples, the threshold (I reference )508 and Figure 4 The “Ref” shown corresponds to this.

[0048] Signal identification circuit ( Figure 6 (Not shown) can be connected to the “output” and implemented using additional capacitors, comparators, Schmitt triggers, analog-to-digital converters (ADCs) or other circuit elements.

[0049] Compared to certain circuits, the circuit described herein can be viewed as a common-mode detection circuit with a specific circuit section (e.g., half-bridge 640) that replicates the common-mode transfer function of the gain stage (e.g., element 630 comprising two half-bridges). The output of the replicated section (e.g., half-bridge 640) is then subtracted from the overall transfer function of the gain stage (e.g., element 630 comprising two half-bridges), which can completely or substantially eliminate the common-mode signal in the output.

[0050] Figure 7 This is a flowchart consistent with one or more examples of this disclosure. It will be from... Figure 4 The differential envelope detector circuit 420 is described in Figure 7 Although other circuits can also achieve this Figure 7 The technology shown.

[0051] like Figure 7 As shown, the differential transconductance stage 430 (i.e., the differential transconductance circuit) receives a first voltage signal (In+) and a second voltage signal (IN-) defining the differential signal (701). The differential transconductance stage 430 generates a first output current signal (702) based on the first and second voltage signals. Simultaneously, the common-mode detection circuit 440 generates a common-mode current signal indicating the common-mode noise present in the first voltage signal (In+) and the second voltage signal (IN-). The summing circuit 450 removes the common-mode current signal from the first output current signal to generate a second output current signal (702). Figure 4 (marked as "OUT" in the diagram). Then, the signal identification circuit 460 can determine the high or low state associated with the second output current signal, and the performance of the signal identification circuit 460 may be improved relative to conventional circuits due to the removal of common-mode noise.

[0052] The techniques described in this disclosure can be implemented, at least in part, in circuits, hardware, software, firmware, or any combination thereof. Such hardware, software, and firmware can be implemented within the same device or in separate devices to support the various operations and functions described in this disclosure. Furthermore, any described unit, module, or component can be implemented together or separately as discrete but interoperable circuits or devices. Describing different features as modules or units is intended to highlight different functional aspects and does not necessarily mean that such modules or units must be implemented by separate components. Rather, the functions associated with one or more modules or units can be performed by separate components or circuits, or can be integrated into common components or circuits. One or more aspects of this disclosure may also be implemented in software, in which case the technical aspects described in this disclosure may also be embodied in or encoded on a computer-readable medium.

[0053] The following numbered aspects illustrate one or more aspects of this disclosure.

[0054] Clause 1: A device arranged to include an electrical isolation barrier between a first voltage domain and a second voltage domain, the device comprising: a transmitter circuit in the first voltage domain; and a receiver circuit in the second voltage domain, wherein the receiver circuit includes a differential envelope detector circuit comprising: a differential transconductance circuit configured to receive a first voltage signal and a second voltage signal of the differential signals, and to generate a first output current signal based on the first voltage signal and the second voltage signal; a common-mode detection circuit configured to generate a common-mode current signal indicating the presence of common-mode noise in the first voltage signal and the second voltage signal of the differential signals; and a summing circuit configured to generate a second output current signal by removing the common-mode current signal from the first output current signal.

[0055] Clause 2: The device according to Clause 1, wherein the first circuit and the second circuit are formed on different circuit dies, and the device includes a molding compound formed around the different circuit dies.

[0056] Clause 3: The device according to Clause 1 or 2, wherein the first circuit and the second circuit are formed on the same circuit die during a semiconductor manufacturing process, having trenches formed in the circuit die to isolate the first voltage domain from the second voltage domain, and wherein the device includes a molding compound formed around the circuit die.

[0057] Clause 4: The device according to any one of Clauses 1-3, wherein the electrical isolation barrier is formed via a coreless transformer that electrically isolates the first voltage domain and the second voltage domain.

[0058] Clause 5: The device according to any one of Clauses 1-4, wherein an electrical isolation barrier is formed via one or more capacitors that electrically isolate a first voltage domain from a second voltage domain.

[0059] Clause 6: The device according to any one of Clauses 1-5, wherein the differential envelope detector circuit further includes a signal identification circuit configured to determine a high state or a low state associated with the second output current signal.

[0060] Clause 7: The device according to any one of Clauses 1-6, wherein the differential transconductance circuit comprises: a first high-side transistor and a second low-side transistor configured to receive a first voltage signal of the differential signal; and a second high-side transistor and a first low-side transistor configured to receive a second voltage signal of the differential signal, and wherein the common-mode detection circuit comprises a third high-side transistor and a third low-side transistor, both of which are connected to the circuit nodes of the first voltage signal and the second voltage signal of the differential signal.

[0061] Clause 8: The device according to Clause 7, wherein the circuit node is located between two resistors electrically connected to the inputs of the first voltage signal and the second voltage signal of the differential signal.

[0062] Clause 9: The device according to any one of Clauses 1-8, wherein the summing circuit comprises: a current mirror circuit configured to generate a mirror of the common-mode current signal; and a capacitor connected to the first output current signal and configured to form a subtraction node that causes the common-mode current signal to be removed from the first output current signal and stores an output voltage signal indicating a second output current signal.

[0063] Clause 10: The device according to any one of Clauses 7-9, wherein the first low-side transistor has an input that is inverted relative to the first high-side transistor, wherein the second low-side transistor has an input that is inverted relative to the second high-side transistor, and wherein the third low-side transistor has an input that is inverted relative to the third high-side transistor.

[0064] Clause 11: The device according to any one of Clauses 7-10, wherein the output of the first high-side transistor is connected to the input of the first low-side transistor, wherein the output of the second high-side transistor is connected to the input of the second low-side transistor, and wherein the output of the third high-side transistor is connected to the input of the third low-side transistor.

[0065] Clause 12: A differential envelope detector circuit, comprising: a differential transconductance circuit configured to receive a first voltage signal of a differential signal and a second voltage signal of a differential signal, and to generate a first output current signal based on the first voltage signal and the second voltage signal; a common-mode detection circuit configured to generate a common-mode current signal indicating common-mode noise present in the first voltage signal and the second voltage signal of the differential signal; and a summing circuit configured to generate a second output current signal by removing the common-mode current signal from the first output current signal.

[0066] Clause 13: The differential envelope detector circuit according to Clause 12 further includes a signal identification circuit configured to determine a high state or a low state associated with the second output current signal.

[0067] Clause 14: The differential envelope detector circuit according to Clause 12 or 13, wherein the differential transconductance circuit includes: a first high-side transistor and a second low-side transistor configured to receive a first voltage signal of the differential signal; and a second high-side transistor and a first low-side transistor configured to receive a second voltage signal of the differential signal, and wherein the common-mode detection circuit includes a third high-side transistor and a third low-side transistor, both of which are connected to the circuit nodes of the first voltage signal and the second voltage signal of the differential signal.

[0068] Clause 15: The differential envelope detector circuit according to Clause 14, wherein the circuit node is located between two resistors electrically connected to the inputs of the first voltage signal and the second voltage signal of the differential signal.

[0069] Clause 16: A differential envelope detector circuit according to any one of Clauses 12-15, wherein the summing circuit comprises: a current mirror circuit configured to generate a mirror of the common-mode current signal; and a capacitor connected to the first output current signal and configured to form a subtraction node that removes the common-mode current signal from the first output current signal and stores an output voltage signal indicating a second output current signal.

[0070] Clause 17: A differential envelope detector circuit according to any one of Clauses 14-16, wherein a first low-side transistor has an input that is inverted relative to a first high-side transistor, wherein a second low-side transistor has an input that is inverted relative to a second high-side transistor, and wherein a third low-side transistor has an input that is inverted relative to a third high-side transistor.

[0071] Clause 18: A differential envelope detector circuit according to any one of Clauses 14-17, wherein the output of a first high-side transistor is connected to the input of a first low-side transistor, wherein the output of a second high-side transistor is connected to the input of a second low-side transistor, and wherein the output of a third high-side transistor is connected to the input of a third low-side transistor.

[0072] Clause 19: A method performed by an envelope detector circuit, the method comprising: receiving a first voltage signal and a second voltage signal at a differential transconductance circuit, wherein the first voltage signal and the second voltage signal define a differential signal; generating a first output current signal based on the first voltage signal and the second voltage signal via the differential transconductance circuit; generating a common-mode current signal indicating the presence of common-mode noise in the first voltage signal and the second voltage signal via a common-mode detection circuit; and generating a second output current signal by removing the common-mode current signal from the first output current signal via a summing circuit.

[0073] Clause 20: The method described in Clause 19 further includes: determining a high state or a low state associated with the second output current signal.

[0074] Various examples of this disclosure have been described. Any combination of the described systems, operations, or functions is within the scope of consideration. These and other examples are within the scope of the following claims.

Claims

1. A device arranged to include an electrical isolation barrier between a first voltage domain and a second voltage domain, the device comprising: The transmitter circuit in the first voltage domain; as well as The receiver circuit in the second voltage domain, wherein the receiver circuit includes a differential envelope detector circuit, the differential envelope detector circuit comprising: A differential transconductance circuit is configured to receive a first voltage signal and a second voltage signal of the differential signal, and to generate a first output current signal based on the first voltage signal and the second voltage signal. A common-mode detection circuit is configured to generate a common-mode current signal that indicates the presence of common-mode noise in the first voltage signal and the second voltage signal of the differential signal; as well as The summing circuit is configured to generate a second output current signal by removing the common-mode current signal from the first output current signal.

2. The device of claim 1, wherein the first circuit and the second circuit are formed on different circuit dies, and the device comprises a molding compound formed around the different circuit dies.

3. The device of claim 1, wherein the first circuit and the second circuit are formed on the same circuit die during a semiconductor manufacturing process, having trenches formed in the circuit die to isolate the first voltage domain from the second voltage domain, and wherein the device comprises a molding compound formed around the circuit die.

4. The device of claim 1, wherein the electrical isolation barrier is formed via a coreless transformer that electrically isolates the first voltage domain and the second voltage domain.

5. The device of claim 1, wherein the electrical isolation barrier is formed via one or more capacitors, the one or more capacitors electrically isolating the first voltage domain and the second voltage domain.

6. The device of claim 1, wherein the differential envelope detector circuit further comprises a signal identification circuit configured to determine a high state or a low state associated with the second output current signal.

7. The device of claim 1, wherein the differential transconductance circuit comprises: A first high-side transistor and a second low-side transistor are configured to receive the first voltage signal of the differential signal; as well as The second high-side transistor and the first low-side transistor are configured to receive the second voltage signal of the differential signal, and The common-mode detection circuit includes a third high-side transistor and a third low-side transistor, both of which are connected to circuit nodes that receive the first voltage signal and the second voltage signal of the differential signal.

8. The device of claim 7, wherein the circuit node is located between two resistors electrically connected to the inputs of the first voltage signal and the second voltage signal of the differential signal.

9. The apparatus of claim 7, wherein the summing circuit comprises: A current mirror circuit is configured to generate a mirror image of the common-mode current signal; as well as A capacitor, connected to the first output current signal, is configured to form a subtraction node, which causes the common-mode current signal to be removed from the first output current signal and stores an output voltage signal indicating the second output current signal.

10. The device according to claim 7, The first low-side transistor has an inverting input relative to the first high-side transistor. The second low-side transistor has an inverting input relative to the second high-side transistor, and The third low-side transistor has an inverting input relative to the third high-side transistor.

11. The device according to claim 10, The output of the first high-side transistor is connected to the input of the first low-side transistor. The output of the second high-side transistor is connected to the input of the second low-side transistor, and The output of the third high-side transistor is connected to the input of the third low-side transistor.

12. A differential envelope detector circuit, comprising: A differential transconductance circuit is configured to receive a first voltage signal and a second voltage signal of the differential signal, and to generate a first output current signal based on the first voltage signal and the second voltage signal. A common-mode detection circuit is configured to generate a common-mode current signal that indicates the presence of common-mode noise in the first voltage signal and the second voltage signal of the differential signal; as well as The summing circuit is configured to generate a second output current signal by removing the common-mode current signal from the first output current signal.

13. The differential envelope detector circuit of claim 12 further includes a signal identification circuit configured to determine a high state or a low state associated with the second output current signal.

14. The differential envelope detector circuit according to claim 12, wherein the differential transconductance circuit comprises: A first high-side transistor and a second low-side transistor are configured to receive the first voltage signal of the differential signal; as well as The second high-side transistor and the first low-side transistor are configured to receive the second voltage signal of the differential signal, and The common-mode detection circuit includes a third high-side transistor and a third low-side transistor, both of which are connected to a circuit node that receives the first voltage signal and the second voltage signal of the differential signal.

15. The differential envelope detector circuit of claim 14, wherein the circuit node is located between two resistors electrically connected to the inputs of the first voltage signal and the second voltage signal of the differential signal.

16. The differential envelope detector circuit of claim 15, wherein the summing circuit comprises: A current mirror circuit is configured to generate a mirror image of the common-mode current signal; as well as A capacitor is connected to the first output current signal and configured to form a subtraction node, the subtraction node causing the common-mode current signal to be removed from the first output current signal and storing an output voltage signal indicating the second output current signal.

17. The differential envelope detector circuit according to claim 14, The first low-side transistor has an inverting input relative to the first high-side transistor. The second low-side transistor has an inverting input relative to the second high-side transistor, and The third low-side transistor has an inverting input relative to the third high-side transistor.

18. The differential envelope detector circuit according to claim 17, The output of the first high-side transistor is connected to the input of the first low-side transistor. The output of the second high-side transistor is connected to the input of the second low-side transistor, and The output of the third high-side transistor is connected to the input of the third low-side transistor.

19. A method performed by an envelope detector circuit, the method comprising: A first voltage signal and a second voltage signal are received at a differential transconductance circuit, wherein the first voltage signal and the second voltage signal define a differential signal; A first output current signal is generated based on the first voltage signal and the second voltage signal via the differential transconductance circuit; A common-mode current signal, indicating the common-mode noise present in the first voltage signal and the second voltage signal, is generated via a common-mode detection circuit. as well as The second output current signal is generated by removing the common-mode current signal from the first output current signal via a summing circuit.

20. The method of claim 19, further comprising: Determine the high or low state associated with the second output current signal.

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