Voltage demodulation circuit, wireless charging chip, transmitter and system

Abstract

The application provides a voltage demodulation circuit, a wireless charging chip, a transmitter and a system. The voltage demodulation circuit comprises an envelope detection unit configured to perform envelope detection on a received modulated signal to obtain an envelope signal; a hysteresis comparator configured to output a decision signal according to a comparison result of the envelope signal and a reference signal; and a digital verification unit configured to recover communication data according to the decision signal. The hysteresis comparator comprises a comparison module and a feedback adjustment module. The feedback adjustment module is connected to the comparison module in a feedback mode and is configured to adjust an upper flip threshold and a lower flip threshold of the hysteresis comparator respectively, so that the hysteresis comparator is adapted to envelope signals with different amplitude ranges. The voltage demodulation circuit can improve the demodulation accuracy of ASK signals in the wireless charging communication process and reduce the bit error rate.

Description

Technical Field

[0001] This application belongs to the field of wireless charging technology, specifically relating to a voltage demodulation circuit, a wireless charging chip, a transmitter, and a system. Background Technology

[0002] With the widespread adoption of smartphones, wearable devices, and other electronic products, wireless charging technology has become widely used due to its convenience and lack of interface corrosion. A wireless charging system typically includes a transmitter (TX, such as a charging dock) and a receiver (RX, such as a mobile phone or other electronic device). The TX and RX transfer energy through electromagnetic induction. During energy transfer, the RX sends authentication, power control requests, or charging status information to the TX via amplitude shift keying (ASK) modulation. The voltage demodulation circuit at the TX detects voltage changes in its own coil and restores the modulated signal to a digital bitstream.

[0003] A voltage demodulation circuit typically includes an envelope detector circuit, a hysteresis comparator, and a digital verification circuit. The envelope detector circuit converts the ASK modulated signal into a fundamental signal; the hysteresis comparator determines the fundamental signal and outputs a high or low level signal; and the digital verification circuit codes and verifies the high and low levels.

[0004] However, in practical applications, due to the complex electromagnetic environment and power transmission conditions, traditional voltage demodulation circuits suffer from problems such as weak modulation signals, low signal-to-noise ratio, and wide dynamic range of transmission power, which affect the bit error rate of the voltage demodulation circuit.

[0005] It should be noted that the above statements are only used to provide background information related to this application and do not necessarily constitute prior art. Summary of the Invention

[0006] This application proposes a voltage demodulation circuit, a wireless charging chip, a transmitter, and a system, which can improve the demodulation accuracy of ASK signals and reduce the bit error rate during wireless charging communication.

[0007] The first aspect of this application provides a voltage demodulation circuit, comprising: The envelope detection unit is used to perform envelope detection on the received modulated signal to obtain the envelope signal; A hysteresis comparator is used to output a decision signal based on the comparison result between the envelope signal and the reference signal; A digital verification unit is used to recover communication data based on the decision signal; The hysteresis comparator includes a comparison module and a feedback adjustment module. The feedback adjustment module is connected to the comparison module and is used to adjust the upper and lower flip thresholds of the hysteresis comparator respectively, so that the hysteresis comparator can adapt to envelope signals with different amplitude ranges.

[0008] In some optional embodiments, the feedback adjustment module includes a first feedback branch and a second feedback branch, wherein the first feedback branch is used to adjust the upward flip threshold and the second feedback branch is used to adjust the downward flip threshold.

[0009] In some optional embodiments, the first feedback branch includes a PMOS current mirror circuit and provides a first bias current to the comparison module; the second feedback branch includes an NMOS current mirror circuit and provides a second bias current to the comparison module.

[0010] In some optional embodiments, the feedback adjustment module further includes a first adjustment unit and a second adjustment unit; the first adjustment unit is used to adjust the feedback amount provided by the first feedback branch; and the second adjustment unit is used to adjust the feedback amount provided by the second feedback branch.

[0011] In some optional embodiments, the PMOS current mirror circuit includes a plurality of PMOS mirror branches arranged in parallel; the NMOS current mirror circuit includes a plurality of NMOS mirror branches arranged in parallel. The first adjustment unit and the second adjustment unit respectively adjust the feedback amount provided by the corresponding feedback branch by controlling the conduction state of the corresponding mirror branch.

[0012] In some optional embodiments, both the first adjustment unit and the second adjustment unit include a plurality of control bits, the plurality of control bits respectively corresponding to at least a portion of the mirror branches of the PMOS mirror branch and the NMOS mirror branch.

[0013] In some optional embodiments, the feedback adjustment module further includes a feedback control unit; the feedback control unit controls at least one of the first feedback branch and the second feedback branch to provide feedback to the comparison module according to the output state of the hysteresis comparator.

[0014] In some optional embodiments, the feedback control unit includes a switching unit connected to the output of the hysteresis comparator; the switching unit is used to control the conduction state of the first feedback branch and the second feedback branch.

[0015] In some optional embodiments, when the hysteresis comparator outputs a first logic state, the switching unit controls the first feedback branch to be turned on and the second feedback branch to be turned off. When the hysteresis comparator outputs the second logic state, the switching unit controls the first feedback branch to turn off and the second feedback branch to turn on.

[0016] In some optional embodiments, the switching unit includes a first switching branch and a second switching branch; the first switching branch is disposed in the feedback path of the first feedback branch, and the second switching branch is disposed in the feedback path of the second feedback branch.

[0017] In some optional embodiments, the first switching branch includes a first switching transistor, the second switching branch includes a second switching transistor, and the control terminals of the first and second switching transistors are both connected to the output terminal of the hysteresis comparator.

[0018] An embodiment of the second aspect of this application provides a wireless charging chip that integrates the voltage demodulation circuit described in the first aspect.

[0019] An embodiment of the third aspect of this application provides a wireless charging transmitter, including a transmitting coil, a driving circuit, and the voltage demodulation circuit described in the first aspect.

[0020] An embodiment of the third aspect of this application provides a wireless charging system, including the wireless charging transmitter and wireless charging receiver described in the third aspect.

[0021] The technical solutions provided in this application embodiment have at least the following technical effects or advantages: The voltage demodulation circuit provided in this application embodiment includes a hysteresis comparator comprising a comparison module and a feedback adjustment module. The feedback adjustment module is connected to the comparison module and is used to adjust the upper and lower flip thresholds of the hysteresis comparator respectively, so that the hysteresis comparator can adapt to envelope signals with different amplitude ranges. Thus, by setting a feedback adjustment module in the hysteresis comparator, the upper and lower flip thresholds of the hysteresis comparator can be adjusted, enabling the hysteresis comparator to adapt to envelope signals with different amplitude ranges. This improves the demodulation accuracy of ASK signals during wireless charging communication, reduces the bit error rate, and enhances system compatibility and communication stability. Attached Figure Description

[0022] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings: Figure 1 A schematic diagram of the circuit structure of a traditional voltage demodulation hysteresis comparator is shown. Figure 2A schematic diagram of the framework structure of a voltage demodulation circuit provided in an embodiment of this application is shown; Figure 3 A schematic diagram of the hysteresis comparator in the voltage demodulation circuit of this application is shown; Figure 4 A schematic diagram showing the simulation results of the voltage demodulation circuit provided in one embodiment of this application is shown. Detailed Implementation

[0023] Exemplary embodiments of this application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of this application are shown in the drawings, it should be understood that this application may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of this application and to fully convey the scope of this application to those skilled in the art.

[0024] It should be noted that, unless otherwise stated, the technical or scientific terms used in this application shall have the ordinary meaning as understood by one of ordinary skill in the art to which this application pertains.

[0025] In related technologies, the envelope amplitude of the modulated signal is very small, typically only tens to hundreds of millivolts. System switching noise and electromagnetic interference both reduce the signal-to-noise ratio of the modulated signal. During power transmission, the placement of the TX and RX coils, the PWM wave frequency of the wireless transmission system, and the requested power level of the RX all vary. These factors can cause changes in the envelope amplitude at the TX end. Traditional hysteresis comparators are prone to failure under these conditions. A high hysteresis setting can lead to the inability to detect small signals. A low hysteresis setting can cause glitches in the envelope signal to cause the hysteresis comparator to mis-twitch, resulting in demodulation failure.

[0026] Traditional voltage demodulation hysteresis comparator schemes, such as Figure 1 As shown, C6 is a DC blocking capacitor, VDM is the envelope detector output signal, R3 / R5=R4 / R6, and the common-mode level of the comparator input signal is increased through a resistor divider. COMP is a hysteresis comparator. The comparator's upper threshold voltage is Vthp, and the lower threshold voltage is Vthn, and Vthp-VREF=VREF-Vthn. However, in practical applications, non-ideal factors such as switching noise, the placement of TX and RX, power adjustment, and component mismatch can all affect the signal quality of VDM, causing the comparator output result to be inconsistent with the target result. The scenarios that lead to comparator output errors can be categorized as follows: 1) When the upper threshold Vthp is greater than the maximum value of VDM and the lower threshold Vthn is less than the minimum value of VDM, the comparator output is indeterminate.

[0027] 2) If the upper threshold Vthp is greater than the maximum value of VDM and the lower threshold Vthn is greater than the minimum value of VDM, the comparator cannot output a high level correctly.

[0028] 3) If the upper threshold Vthp is less than the maximum value of VDM and the lower threshold Vthn is less than the minimum value of VDM, the comparator cannot output a low level correctly.

[0029] To address the above issues, adjusting the upper limit thresholds Vthp and Vthn flexibly can resolve comparator output errors.

[0030] To address the aforementioned problems, embodiments of this application provide a voltage demodulation circuit, a wireless charging chip, a transmitter, and a system, wherein the voltage demodulation circuit framework structure is as follows: Figure 2 As shown, the system includes an envelope detection unit, a hysteresis comparator, and a digital verification unit. The envelope detection unit performs envelope detection on the received modulated signal to obtain the envelope signal. The hysteresis comparator outputs a decision signal based on the comparison result between the envelope signal and a reference signal. The digital verification unit recovers the communication data based on the decision signal. The hysteresis comparator includes a comparison module and a feedback adjustment module. The feedback adjustment module is connected to the comparison module and is used to adjust the upper and lower flip thresholds of the hysteresis comparator to adapt it to envelope signals with different amplitude ranges. The feedback adjustment module is also connected to the comparison module AMP and is used to adjust the upper flip threshold Vthp and the lower flip threshold Vthn of the hysteresis comparator.

[0031] This voltage demodulation circuit can be used, but is not limited to, in wireless charging transmitters. A wireless charging system includes a transmitter (TX) and a receiver (RX). Energy transfer between TX and RX is achieved through electromagnetic coupling. During charging, RX sends authentication information, power control information, and charging status information to TX via Amplitude Shift Keying (ASK) modulation. The voltage demodulation circuit on the TX side demodulates the ASK communication signal.

[0032] For traditional fixed hysteresis comparators, misjudgments can easily occur when the hysteresis window and the envelope signal amplitude do not match. For example, when Vthn < Vmin_VDM < Vmax_VDM < Vthp, the comparator output is indeterminate; when Vthn < Vmin_VDM < Vthp < Vmax_VDM, the comparator cannot correctly output a high level; and when Vmin_VDM < Vthn < Vmax_VDM < Vthp, the comparator cannot correctly output a low level.

[0033] This embodiment incorporates a feedback adjustment module within the hysteresis comparator to adjust the upper and lower flip thresholds of the hysteresis comparator. This allows the hysteresis comparator to adapt to envelope signals with different amplitude ranges, thereby improving the demodulation accuracy of the ASK signal during wireless charging communication, reducing the bit error rate, and enhancing system compatibility and communication stability.

[0034] During wireless charging, the amplitude of the envelope signal VDM changes due to variations in transmission power, operating frequency, coil coupling coefficient, and receiver power request. For traditional fixed-hysteresis comparators, demodulation failure occurs when the hysteresis window of the comparator does not match the envelope signal amplitude. This embodiment incorporates a feedback adjustment module to regulate the hysteresis characteristics of the comparator, enabling dynamic adjustment of the hysteresis window to adapt the comparator to envelope signals with different amplitude ranges.

[0035] In some alternative embodiments, such as Figure 3 As shown, the feedback adjustment module includes a first feedback branch and a second feedback branch. The first feedback branch is used to adjust the upward flip threshold, and the second feedback branch is used to adjust the downward flip threshold.

[0036] In this embodiment, the first feedback branch corresponds to the upward flip threshold adjustment, and the second feedback branch corresponds to the downward flip threshold adjustment, so that the upward flip threshold and the downward flip threshold each have independent adjustment paths and can be adjusted according to different envelope waveforms. This avoids the problem of insufficient adjustment freedom caused by the synchronous change of the two thresholds in the traditional scheme and improves the flexibility of threshold configuration.

[0037] The first feedback branch may include a PMOS current mirror circuit and provide a first bias current to the comparator module; the second feedback branch includes an NMOS current mirror circuit and provides a second bias current to the comparator module.

[0038] For the comparator, gm·ΔV>Ibias, where gm is the equivalent input transconductance, ΔV is the flip threshold offset, and Ibias is the feedback bias current. Therefore, ΔV∝Ibias, and the hysteresis threshold can be adjusted by regulating the feedback current. Furthermore, using the injected current and the extracted current to form the feedback bias allows for hysteresis threshold adjustment with a smaller area overhead.

[0039] Furthermore, the feedback adjustment module also includes a first adjustment unit and a second adjustment unit. The first adjustment unit is used to adjust the feedback amount provided by the first feedback branch; the second adjustment unit is used to adjust the feedback amount provided by the second feedback branch.

[0040] This embodiment sets up a first adjustment unit and a second adjustment unit to adjust the feedback amount provided by the first feedback branch and the second feedback respectively, thereby realizing independent adjustment of the up and down flip threshold.

[0041] Specifically, the PMOS current mirror circuit includes multiple PMOS mirror branches connected in parallel; the NMOS current mirror circuit includes multiple NMOS mirror branches connected in parallel; and the first adjustment unit and the second adjustment unit adjust the feedback amount provided by the corresponding feedback branch by controlling the conduction state of the corresponding mirror branch.

[0042] Furthermore, both the first adjustment unit and the second adjustment unit include multiple control bits, which correspond to at least a portion of the mirror branches in the PMOS mirror branch and the NMOS mirror branch, respectively.

[0043] In this embodiment, when multiple mirror branches are connected in parallel, Itotal = I1 + I2 + ... + In. The adjustment unit controls the conduction state of each mirror branch. Increasing the number of conducting branches increases the feedback current and hysteresis; conversely, decreasing the number of branches decreases the feedback current and hysteresis, thereby achieving threshold adjustment. Thus, by setting up the adjustment unit and configurable mirror branches, the feedback current can be digitally configured, improving production consistency and field adaptability.

[0044] In some implementations, the first tuning unit adjusts the flip-up threshold by regulating the TRIM_N configuration. For example, when the TRIM_N<2:0> configuration is increased, the number of active PMOS mirror branches increases. As the number of IPMOS increases, ΔVp increases, and Vthp also increases, thus shifting the flip-up threshold upwards. When the wireless charging system operates in a highly coupled or high-power output state, the envelope signal amplitude is typically large. Increasing the flip-up threshold improves the system's noise immunity and prevents erroneous flips.

[0045] Similarly, the second adjustment unit adjusts the down-flip threshold by modifying the TRIM_P configuration. For example, when the TRIM_P<2:0> configuration is increased, the number of NMOS mirror branches that are turned on increases. As the number of INMOS increases, ΔVn increases, causing Vthn to decrease, thus shifting the down-flip threshold downward.

[0046] The above methods can expand the adjustment range of the lower boundary of the hysteresis window and improve the system's adaptability.

[0047] In some optional embodiments, the feedback adjustment module further includes a feedback control unit, which controls the operating state of the first feedback branch and the second feedback branch according to the output state of the hysteresis comparator.

[0048] The feedback control unit includes a switching unit connected to the output of the hysteresis comparator; the switching unit is used to control the conduction state of the first feedback branch and the second feedback branch.

[0049] When the hysteresis comparator outputs the first logic state, the switching unit controls the first feedback branch to be turned on and the second feedback branch to be turned off; when the hysteresis comparator outputs the second logic state, the switching unit controls the first feedback branch to be turned off and the second feedback branch to be turned on.

[0050] In this embodiment, when the comparator outputs a high level, the first feedback path is closed and the second feedback path is open, forming a first hysteresis state. When the comparator outputs a low level, the first feedback path is open and the second feedback path is closed, forming a second hysteresis state. By controlling the feedback state through the output state, a hysteresis loop is formed. Thus, by controlling the operating state of different feedback branches through the feedback control unit, the comparator automatically switches the feedback path under different output states, thereby forming a stable hysteresis characteristic.

[0051] In some optional embodiments, the switching unit may include a first switching branch and a second switching branch; the first switching branch is disposed in the feedback path of the first feedback branch, and the second switching branch is disposed in the feedback path of the second feedback branch.

[0052] Specifically, the first switching branch includes a first switching transistor, the second switching branch includes a second switching transistor, and the control terminals of the first and second switching transistors are both connected to the output terminal of the hysteresis comparator.

[0053] In some specific embodiments, such as Figure 3 As shown, the feedback control unit includes a first switching transistor M7 and a second switching transistor M8. The first feedback branch includes a PMOS current mirror circuit. The second feedback branch includes an NMOS current mirror circuit. The PMOS current mirror circuit includes M9 to M15. The NMOS current mirror circuit includes M16 to M22. A first adjustment unit is used to adjust the feedback current generated by the PMOS current mirror. The second adjustment unit is used to adjust the feedback current generated by the NMOS current mirror.

[0054] In this embodiment, the first trimming unit receives the trimming signal TRIM_N<2:0>; the second trimming unit receives the trimming signal TRIM_P<2:0>. The magnitude of the feedback current can be changed by altering the on / off state of the corresponding mirror transistor.

[0055] like Figure 3 The diagram shows the internal hysteresis comparator of the voltage demodulation circuit. AMP is the comparator, M1~M8 are Schmitt triggers, M9~M12 are PMOS current mirrors, TRIM_N<2:0> is the PMOS current mirror adjustment port, M19~M22 are NMOS current mirrors, and TRIM_P<2:0> is the NMOS current mirror adjustment port. Vthp and Vthn are adjusted by configuring RIM_N<2:0> and TRIM_P<2:0>.

[0056] As shown in the figure below, VREF is the reference voltage of the comparator, and VDM is the envelope detector output signal, which is a low-frequency signal of 2KHz.

[0057] M1~M6 are Schmitt triggers that shape the output signal of the AMP and improve its anti-interference capability. M7~M22 are hysteresis tuning circuits. The drains of M7 and M8 are connected to the AMP output. The output stage of the AMP is a common-source amplifier with a current source load. The output VOUT of the hysteresis comparator controls the gates of M7 and M8. When VOUT=1, M7 is off and M8 is on. The NMOS current mirror composed of M16~M22 draws current from the AMP through M8. When VOUT=0, M7 is on and M8 is off. The PMOS current mirror composed of M9~M15 sinks current into the AMP through M7. The output of the AMP controls the conduction state of M7 and M8, and the conduction state of M7 and M8 controls the current state of the AMP output stage. This feedback loop forms the hysteresis voltage of the comparator. By adjusting the gate voltages of M13~M15 and M20~M22, the magnitude of the extracted current and the sink current are adjusted, thus changing the magnitude of the hysteresis voltage.

[0058] Taking TRIM_N<2:0>=111 and TRIM_P<2:0>=000 as an example, the working process of the voltage demodulation comparator is introduced. When VDM is much smaller than VREF, the gate voltages of M1~M4 are 1, VOUT=0, M7 is turned on, M8 is turned off, and the current of M9 flows into the AMP through M7. When VDM=VREF, due to the Schmitt trigger composed of M1~M6 and the bias current IBIASP introduced by M9, the AMP output voltage remains at 1. When VDM continues to increase, and VDM-VREF>ΔV, at this time gm*ΔV>IBIASP, the output state of the AMP is broken, the AMP output is adjusted from 1 to 0, VOUT=1, M7 is turned off, M8 is turned on, and M19 draws current IBIASN from the AMP through M8.

[0059] Similarly, when VDM is much greater than VREF, the gate voltages of M1~M4 are 0, VOUT=1, M7 is off, M8 is on, and the current from M19 draws current IBIASN from the AMP through M8. As VDM decreases and VDM=VREF, the output voltage of the AMP remains at 0 due to the Schmitt trigger composed of M1~M6 and the bias current IBIASN drawn by M19. When VDM continues to decrease and VREF-VDM>ΔV, then gm*ΔV>IBIASN, the output state of the AMP is broken, the AMP output changes from 0 to 1, VOUT=0, M7 is on, M8 is off, and the current from M9 flows into the AMP through M7.

[0060] The above describes a complete comparison process for the VDM signal, where Vthp = VREF + ΔV and Vthn = VREF - ΔV. Based on gm*ΔV > IBIASP and gm*ΔV > IBIASN, Vthp and Vthn can be changed by adjusting IBIASP and IBIASN.

[0061] The following describes this embodiment with an example of a specific working process.

[0062] When VDM is much smaller than VREF, the comparator module AMP outputs a high level; the hysteresis comparator output VOUT is low; M7 is turned on; M8 is turned off; the feedback current generated by the PMOS current mirror flows into the comparator module AMP. As VDM gradually increases, when VDM approaches VREF, the comparator module AMP maintains its original output state due to the feedback current. When gm×ΔV>IBIASP, the comparator module AMP flips; VOUT changes from low to high; M7 is turned off; M8 is turned on; the NMOS current mirror begins to draw feedback current IBIASN from the comparator module AMP. At this time, the upper flip threshold is formed: Vthp=VREF+ΔV. Subsequently, as VDM continues to increase and remains at a high level, the comparator module AMP maintains its output state. When VDM begins to decrease, the comparator module AMP maintains its current state due to the feedback provided by the NMOS current mirror. When gm×ΔV>IBIASN, the comparator module AMP flips again; VOUT changes from high to low; M8 is turned off; M7 is turned on; the PMOS current mirror resumes providing feedback current to the comparator module AMP. At this point, the down-flip threshold is formed: Vthn = VREF - ΔV. This results in a complete hysteresis loop.

[0063] According to the formula gm×ΔV≈IBIAS, ΔV is positively correlated with the magnitude of the feedback current. Therefore, increasing the PMOS current mirror feedback current can raise the up-flip threshold; decreasing the PMOS current mirror feedback current can lower the up-flip threshold; increasing the NMOS current mirror feedback current can lower the down-flip threshold; and decreasing the NMOS current mirror feedback current can raise the down-flip threshold.

[0064] like Figure 4 As shown, when envelope signals under different operating conditions are detected, the feedback current magnitudes of the PMOS and NMOS current mirrors can be changed by adjusting the TRIM_N and TRIM_P configurations, thereby achieving hysteresis window adjustment. Ideally, the following condition should be met: Vmin_VDM < Vthn < Vthp < Vmax_VDM. When the above relationship holds, the hysteresis comparator can accurately demodulate the ASK signal. Therefore, this embodiment can effectively adapt to envelope signal fluctuations caused by coupling changes, power changes, and noise interference during wireless charging, improving demodulation accuracy and reducing communication error rate.

[0065] Specifically, Figure 4 wherein (1) is the waveform under ideal working conditions, (2), (3) and (4) are the waveforms under non-ideal working conditions, and the corresponding trimming schemes are provided. The following are several comparator trimming schemes under non-ideal working conditions: wherein the VDM signal is a varying square wave signal, Vthp and Vthn are the hysteresis voltages of the comparator, and for an ideal VDM signal, it is required to satisfy Vmin_VDM<Vthn<Vthp<Vmax_VDM so that the system can correctly identify the VDM signal. All conditions that do not meet this constraint are non-ideal working conditions. In order to improve the compatibility of the demodulator, it is necessary to perform trimming configuration on Vthp and Vthn.

[0066] When Vthn<Vmin_VDM<Vmax_VDM<Vthp, the signal peak-to-peak value Vpp of VDM is less than (Vthp-Vthn); the comparator will output an indeterminate state. By reducing the number of turned-on M13 to M15, the ΔV of the system becomes smaller at this time, and Vthp decreases. By reducing the number of turned-on M16 to M18, the ΔV of the system becomes smaller at this time, and Vthn rises. Finally, the signal peak-to-peak value Vpp of VDM is greater than (Vthp-Vthn). The trimmed Vthp and Vthn satisfy the range of Vmin_VDM<Vthn<Vthp<Vmax_VDM. When Vthn<Vmin_VDM<Vthp<Vmax_VDM, since Vthn is constantly less than VDM, the state of the output voltage of the AMP cannot be broken when VDM changes, the output of the AMP will remain at a low level, and VOUT will remain at a high level. Vthp can be increased by reducing the number of turned-on M16 to M18. The trimmed Vthp and Vthn satisfy the range: Vmin_VDM<Vthn<Vthp<Vmax_VDM. When Vmin_VDM<Vthn<Vmax_VDM<Vthp, since Vthp is constantly greater than VDM, the state of the output voltage of the AMP cannot be broken when VDM changes, the output of the AMP will remain at a high level, and VOUT will remain at a low level. Vthp can be reduced by reducing the number of turned-on M13 to M15. The trimmed Vthp and Vthn satisfy the range: Vmin_VDM<Vthn<Vthp<Vmax_VDM. In this way, the magnitudes of Vthp and Vthn can be flexibly controlled by adjusting the bias currents of the PMOS and NMOS.

[0067] Based on the same concept as the above voltage demodulation circuit, this embodiment further provides a wireless charging chip, which includes the voltage demodulation circuit according to any one of the above embodiments. The voltage demodulation circuit is configured to receive communication data sent by the wireless charging receiving end.

[0068] In some embodiments, the communication data includes at least one of authentication information, power control information, and charging status information.

[0069] The wireless charging chip provided in this embodiment is based on the same concept as the voltage demodulation circuit described above. Therefore, it can at least achieve the beneficial effects that the voltage demodulation circuit can achieve. Furthermore, any implementation of the voltage demodulation circuit described above can be applied to the chip provided in this embodiment, and will not be described in detail here.

[0070] Based on the same concept as the voltage demodulation circuit described above, this embodiment also provides a wireless charging transmitter. The wireless charging device includes: a voltage demodulation circuit; a transmitting coil; and a driving circuit. The voltage demodulation circuit can be any of the voltage demodulation circuits described in the above embodiments.

[0071] The wireless charging transmitter provided in this embodiment is based on the same concept as the voltage demodulation circuit described above. Therefore, it can at least achieve the beneficial effects that the voltage demodulation circuit can achieve. Furthermore, any implementation of the voltage demodulation circuit can be applied to the chip provided in this embodiment, and will not be described in detail here.

[0072] Based on the same concept as the voltage demodulation circuit described above, this embodiment also provides a wireless charging system, which includes a wireless charging transmitter and a wireless charging receiver. The wireless charging transmitter employs the voltage demodulation circuit of any of the above embodiments.

[0073] The wireless charging system provided in this embodiment is based on the same concept as the voltage demodulation circuit described above. Therefore, it can at least achieve the beneficial effects that the voltage demodulation circuit can achieve. Furthermore, any implementation of the voltage demodulation circuit can be applied to the chip provided in this embodiment, and will not be described in detail here.

[0074] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application, and they should all be covered within the scope of the claims and specification of this application. In particular, as long as there is no structural conflict, the various technical features mentioned in the embodiments can be combined in any way. This application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A voltage demodulation circuit, characterized in that, include: The envelope detection unit is used to perform envelope detection on the received modulated signal to obtain the envelope signal; A hysteresis comparator is used to output a decision signal based on the comparison result between the envelope signal and the reference signal; A digital verification unit is used to recover communication data based on the decision signal; The hysteresis comparator includes a comparison module and a feedback adjustment module. The feedback adjustment module is connected to the comparison module and is used to adjust the upper and lower flip thresholds of the hysteresis comparator respectively, so that the hysteresis comparator can adapt to envelope signals with different amplitude ranges.

2. The voltage demodulation circuit according to claim 1, characterized in that, The feedback adjustment module includes a first feedback branch and a second feedback branch. The first feedback branch is used to adjust the upward flip threshold, and the second feedback branch is used to adjust the downward flip threshold.

3. The voltage demodulation circuit according to claim 2, characterized in that, The first feedback branch includes a PMOS current mirror circuit and provides a first bias current to the comparison module; the second feedback branch includes an NMOS current mirror circuit and provides a second bias current to the comparison module.

4. The voltage demodulation circuit according to claim 3, characterized in that, The feedback adjustment module further includes a first adjustment unit and a second adjustment unit; the first adjustment unit is used to adjust the feedback amount provided by the first feedback branch; the second adjustment unit is used to adjust the feedback amount provided by the second feedback branch.

5. The voltage demodulation circuit according to claim 4, characterized in that, The PMOS current mirror circuit includes multiple PMOS mirror branches connected in parallel; the NMOS current mirror circuit includes multiple NMOS mirror branches connected in parallel. The first adjustment unit and the second adjustment unit respectively adjust the feedback amount provided by the corresponding feedback branch by controlling the conduction state of the corresponding mirror branch.

6. The voltage demodulation circuit according to claim 5, characterized in that, The first adjustment unit and the second adjustment unit each include a plurality of control bits, which correspond to at least a portion of the mirror branches of the PMOS mirror branch and the NMOS mirror branch, respectively.

7. The voltage demodulation circuit according to claim 2, characterized in that, The feedback adjustment module further includes a feedback control unit; the feedback control unit controls at least one of the first feedback branch and the second feedback branch to provide feedback to the comparison module according to the output state of the hysteresis comparator.

8. The voltage demodulation circuit according to claim 7, characterized in that, The feedback control unit includes a switching unit connected to the output of the hysteresis comparator; the switching unit is used to control the conduction state of the first feedback branch and the second feedback branch.

9. The voltage demodulation circuit according to claim 8, characterized in that, When the hysteresis comparator outputs the first logic state, the switching unit controls the first feedback branch to be turned on and the second feedback branch to be turned off. When the hysteresis comparator outputs the second logic state, the switching unit controls the first feedback branch to turn off and the second feedback branch to turn on.

10. The voltage demodulation circuit according to claim 8, characterized in that, The switching unit includes a first switching branch and a second switching branch; the first switching branch is disposed in the feedback path of the first feedback branch, and the second switching branch is disposed in the feedback path of the second feedback branch.

11. The voltage demodulation circuit according to claim 10, characterized in that, The first switching branch includes a first switching transistor, and the second switching branch includes a second switching transistor. The control terminals of the first switching transistor and the second switching transistor are both connected to the output terminal of the hysteresis comparator.

12. A wireless charging chip, characterized in that, It integrates the voltage demodulation circuit according to any one of claims 1-11.

13. A wireless charging transmitter, characterized in that, The transmitting coil, the driving circuit, and the voltage demodulation circuit according to any one of claims 1-11.

14. A wireless charging system, characterized in that, It includes the wireless charging transmitter and wireless charging receiver as described in claim 13.

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