Signal processing method and apparatus, electronic device, and computer program product

Abstract

The present disclosure relates to a signal processing method and device, electronic equipment and computer program product, belonging to the technical field of communication. The method comprises: obtaining a channel number from an original channel selection signal, and encoding the channel number to convert the channel number into a corresponding Gray code channel value; writing the Gray code channel value into a channel selection register, wherein the channel selection register contains a plurality of independent flip-flops, and the number of flip-flops is odd; sampling the Gray code channel value through each flip-flop respectively, and obtaining a target Gray code channel value based on the Gray code sampling value output by each flip-flop; and decoding the target Gray code channel value to convert the target Gray code channel value into a corresponding target channel selection signal. The present disclosure can effectively identify and suppress the influence of bit jump on channel selection output, thereby guaranteeing the reliability and stability of signal channel switching.

Description

Technical Field

[0001] This disclosure relates to the field of communication technology, and more specifically, to a signal processing method, a signal processing apparatus, an electronic device, and a computer program product. Background Technology

[0002] In network switching devices, CPLDs (Complex Programmable Logic Devices) are widely used to implement I2C (Inter-Integrated Circuit) multiplexing functionality. The CPLD's internal channel selection register, composed of FFs (Flip-Flops), is responsible for dynamically switching data transmission channels based on input signals.

[0003] However, in actual operation, these triggers are susceptible to environmental factors such as power supply noise and electromagnetic interference, causing unexpected flipping of a single bit in the register, i.e., a BIT (Binary Digit) transition. This transition directly causes errors in the channel selection signal output, leading to serious faults such as downstream I2C device access errors, data packet loss, and communication link interruption. Simply rewriting the register after a transition cannot restore normal operation; a CPLD reset must be triggered to restore normal function.

[0004] Therefore, there is an urgent need in the field for a signal processing method that can effectively identify and suppress the impact of bit transitions on channel selection output, thereby ensuring the reliability and stability of signal channel switching.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this disclosure is to provide a signal processing method, a signal processing device, an electronic device, and a computer program product, which can at least to some extent effectively identify and suppress the impact of bit transitions on channel selection output, thereby ensuring the reliability and stability of signal channel switching.

[0007] According to a first aspect of this disclosure, a signal processing method is provided, applied to a complex programmable logic device, comprising: Obtain the channel number from the original channel selection signal, encode the channel number, and convert the channel number into the corresponding Gray code channel value; The Gray code channel value is written into the channel selection register, wherein the channel selection register contains multiple independent triggers, and the number of triggers is odd. The Gray code channel value is sampled by each of the aforementioned triggers, and the target Gray code channel value is obtained based on the Gray code sampled value output by each of the aforementioned triggers; The target Gray code channel value is decoded and converted into a corresponding target channel selection signal, so as to determine the signal output channel through the target channel selection signal.

[0008] In one exemplary embodiment of this disclosure, obtaining the target Gray code channel value based on the Gray code sampled values ​​output by each of the triggers includes: Obtain the value corresponding to each bit in the Gray code sample value output by each of the triggers; The value that appears most frequently among the values ​​corresponding to the bit is determined as the target value of the bit, and the target Gray code channel value is obtained based on the target values ​​of each bit.

[0009] In one exemplary embodiment of this disclosure, the method further includes: The target Gray code channel value is input into the first-level register, and each bit in the target Gray code channel value is filtered out by the first-level register to obtain the target Gray code channel value after first-level filtering.

[0010] In one exemplary embodiment of this disclosure, the step of performing glitch filtering processing on each bit of the target Gray code channel value through the first-level register includes: The first-stage register delays the sampling of each bit in the target Gray code channel value by one clock cycle at the rising edge of the clock, and uses the bit value sampled at the rising edge of the clock as the bit value after the first-stage filtering.

[0011] In one exemplary embodiment of this disclosure, the method further includes: The target Gray code channel value after the first-stage filtering is input into the second-stage register. The second-stage register performs signal stabilization processing on each bit of the target Gray code channel value to obtain the target Gray code channel value after the second-stage filtering.

[0012] In one exemplary embodiment of this disclosure, the step of performing signal stabilization processing on each bit of the target Gray code channel value through the second-level register includes: Based on the first-level register, a clock cycle is delayed, and the value of each bit in the target Gray code channel value after the first-level filtering is sampled at the rising edge of the clock through the second-level register, and the value of the bit sampled at the rising edge of the clock is used as the value of the bit after the second-level filtering.

[0013] In one exemplary embodiment of this disclosure, the method further includes: When the complex programmable logic device is powered on and reset, the initial channel values ​​of the flip-flops in the first-level register, the second-level register, and the channel selection register are set to the default Gray code values.

[0014] In one exemplary embodiment of this disclosure, the method further includes: Determine whether the Gray code sample values ​​output by each of the aforementioned triggers are the same; If the Gray code sample values ​​are different, the error detection flag corresponding to the bit with different values ​​in the Gray code sample values ​​is set as the first flag.

[0015] In one exemplary embodiment of this disclosure, each of the flip-flops is distributed in different logic cell regions of the complex programmable logic device.

[0016] According to a second aspect of this disclosure, a signal processing apparatus is provided, applied to a complex programmable logic device, comprising: The Gray code encoding module is configured to retrieve the channel number from the original channel selection signal, encode the channel number, and convert the channel number into the corresponding Gray code channel value. The Gray code writing module is configured to write the Gray code channel value into a channel selection register, wherein the channel selection register contains multiple independent triggers, and the number of triggers is odd. The trigger sampling module is configured to sample the Gray code channel values ​​through each of the triggers respectively, and obtain the target Gray code channel value based on the Gray code sampled values ​​output by each of the triggers; The Gray code decoding module is configured to decode the target Gray code channel value, convert the target Gray code channel value into a corresponding target channel selection signal, and determine the signal output channel through the target channel selection signal.

[0017] In one exemplary embodiment of this disclosure, the trigger sampling module includes: The bit value acquisition unit is configured to acquire the value of each bit in the Gray code sample value output by each of the triggers; The numerical occurrence comparison unit is configured to determine the value that appears most frequently among the values ​​corresponding to the bit as the target value of the bit, and obtain the target Gray code channel value based on the target values ​​of each bit.

[0018] In one exemplary embodiment of this disclosure, the signal processing apparatus further includes: The first-stage filtering module is configured to input the target Gray code channel value into the first-stage register, and perform glitch filtering on each bit of the target Gray code channel value through the first-stage register to obtain the target Gray code channel value after first-stage filtering.

[0019] In one exemplary embodiment of this disclosure, the first-stage filtering module includes: The rising edge sampling unit is configured to sample the value of each bit in the target Gray code channel value at the rising edge of the clock by delaying for one clock cycle through the first-stage register, and use the value of the bit sampled at the rising edge of the clock as the value of the bit after the first-stage filtering.

[0020] In one exemplary embodiment of this disclosure, the signal processing apparatus further includes: The second-stage filtering module is configured to input the target Gray code channel value after the first-stage filtering into the second-stage register, and perform signal stabilization processing on each bit of the target Gray code channel value through the second-stage register to obtain the target Gray code channel value after the second-stage filtering.

[0021] In one exemplary embodiment of this disclosure, the second-stage filtering module includes: The rising edge sampling unit is configured to perform a process that delays by one clock cycle based on the first-level register, samples the value of each bit in the target Gray code channel value after the first-level filtering through the second-level register at the rising edge of the clock, and uses the value of the bit sampled at the rising edge of the clock as the value of the bit after the second-level filtering.

[0022] In one exemplary embodiment of this disclosure, the signal processing apparatus further includes: The initial value setting module is configured to set the initial channel value of the flip-flops in the first-level register, the second-level register, and the channel selection register to the default Gray code value when the complex programmable logic device is powered on and reset.

[0023] In one exemplary embodiment of this disclosure, the signal processing apparatus further includes: The error detection module is configured to determine whether the Gray code sample values ​​output by each of the triggers are the same; if the Gray code sample values ​​are different, the error detection flag corresponding to the bit with different values ​​in the Gray code sample values ​​is set as the first flag.

[0024] In one exemplary embodiment of this disclosure, each of the flip-flops is distributed in different logic cell regions of the complex programmable logic device.

[0025] According to a third aspect of this disclosure, an electronic device is provided, comprising: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to execute the instructions to implement the signal processing method described in any one of the preceding claims.

[0026] According to a fourth aspect of this disclosure, a computer program product is provided, comprising a computer program that, when executed by a processor, implements the signal processing method described in any one of the preceding claims.

[0027] The exemplary embodiments disclosed herein can have the following beneficial effects: In the signal processing method of the exemplary implementation of this disclosure, on the one hand, by adopting Gray code encoding conversion, it is ensured that only one bit changes each time during multi-bit switching, which can eliminate transient combination hazards during multi-bit switching; on the other hand, by using odd-numbered trigger sampling and majority voting mechanism, multiple independent triggers store the same channel control value, and the final channel selection signal is output through majority voting logic, which can shield single bit jumps in real time, exponentially reducing the probability of failure. It is applicable to channel selection registers with arbitrary width, and the protection delay is only the propagation time of combinational logic (nanosecond level), which is far superior to the millisecond-level response of software detection schemes, realizing real-time source protection; furthermore, no external hardware modification is required, multiplexing services are not interrupted, and no software intervention is required, which fundamentally improves the reliability of the multiplexing system in the noise interference environment, and ensures the accuracy of signal channel switching and the continuity of communication services.

[0028] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0029] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0030] Figure 1A schematic flowchart illustrating a signal processing method according to an exemplary embodiment of the present disclosure is shown; Figure 2 A schematic diagram of a three-modular-redundant majority voting output logic structure in a specific embodiment of this disclosure is shown; Figure 3 A schematic diagram of the output signal hierarchical protection timing in a specific embodiment of this disclosure is shown; Figure 4 A block diagram of the logic-hardened internal structure of a complex programmable logic device according to a specific embodiment of the present disclosure is shown; Figure 5 A block diagram of a signal processing apparatus according to an exemplary embodiment of the present disclosure is shown; Figure 6 A schematic diagram of the structure of a computer system suitable for implementing the embodiments of the present disclosure is shown. Detailed Implementation

[0031] To enable those skilled in the art to better understand the technical solutions of this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings.

[0032] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein.

[0033] The following exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this disclosure more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a full understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more of the specific details omitted, or other methods, components, apparatus, steps, etc., can be employed. In other instances, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0034] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0035] In some related embodiments, when a bit transition occurs in the CPLD's internal channel selection register, the software-layer recovery scheme has the following inherent limitations: 1. Delayed fault detection: BIT jumps are usually only passively discovered after access anomalies occur at the business layer. The lack of a proactive write-after-read verification mechanism leads to a long fault detection time. 2. Ineffective register rewriting recovery: After discovering the fault, only attempt is made to rewrite the CPLD register, but the I2C communication link itself may have been interfered with after the BIT transition, and the rewrite operation cannot actually be successfully delivered; even if it is delivered, if the communication link itself is in an abnormal state due to the transition, the rewrite operation cannot repair the transition state. 3. Manual power-off intervention is required: It cannot be automatically restored through software means. The entire board of equipment must be powered off and restarted, which seriously affects the availability and operation and maintenance efficiency of the equipment in unattended data center scenarios.

[0036] To address the aforementioned issues, this exemplary implementation first provides a signal processing method applicable to complex programmable logic devices. (Reference) Figure 1 As shown, the above signal processing method may include the following steps: Step S110. Obtain the channel number from the original channel selection signal, encode the channel number, and convert the channel number into the corresponding Gray code channel value.

[0037] Step S120. Write the Gray code channel value into the channel selection register, wherein the channel selection register contains multiple independent triggers, and the number of triggers is odd.

[0038] Step S130. Sample the Gray code channel values ​​through each trigger, and obtain the target Gray code channel value based on the Gray code sampled values ​​output by each trigger.

[0039] Step S140. Decode the target Gray code channel value and convert it into the corresponding target channel selection signal to determine the signal output channel.

[0040] In the signal processing method of the exemplary implementation of this disclosure, on the one hand, by adopting Gray code encoding conversion, it is ensured that only one bit changes each time during multi-bit switching, which can eliminate transient combination hazards during multi-bit switching; on the other hand, by using odd-numbered trigger sampling and majority voting mechanism, multiple independent triggers store the same channel control value, and the final channel selection signal is output through majority voting logic, which can shield single bit jumps in real time, exponentially reducing the probability of failure. It is applicable to channel selection registers with arbitrary width, and the protection delay is only the propagation time of combinational logic (nanosecond level), which is far superior to the millisecond-level response of software detection schemes, realizing real-time source protection; furthermore, no external hardware modification is required, multiplexing services are not interrupted, and no software intervention is required, which fundamentally improves the reliability of the multiplexing system in the noise interference environment, and ensures the accuracy of signal channel switching and the continuity of communication services.

[0041] The steps described above in this example implementation will now be explained in more detail.

[0042] In step S110, the channel number is obtained from the original channel selection signal and encoded to convert the channel number into the corresponding Gray code channel value.

[0043] In this example implementation, a complex programmable logic device (CLP) is an integrated circuit that contains programmable logic blocks and programmable interconnect resources, enabling it to implement complex digital logic functions. The initial channel selection signal is an input from an external system or master controller, used to indicate the desired selection of a specific data channel. This signal typically carries unique identification information for the target channel. The channel number is the numerical identifier of the specific channel contained in the initial channel selection signal.

[0044] In this example implementation, the channel number can be converted into the corresponding Gray code channel value. The Gray code channel value is the numerical value obtained by encoding the channel number using Gray code. A characteristic of Gray code is that only one bit changes between any two adjacent values, which helps reduce transient errors caused by simultaneous changes in multiple bits during signal transmission or sampling.

[0045] For example, for a 3-bit, 8-channel system, the Gray code encoding table is shown in Table 1:

[0046] Table 1

[0047] As shown in Table 1, only one bit changes each time the channel switches, and only one bit needs to be updated in the subsequent triggers each time, eliminating the transient hazard of multiple bits flipping at the same time.

[0048] In step S120, the Gray code channel value is written into the channel selection register, which contains multiple independent triggers, and the number of triggers is odd.

[0049] In this example implementation, the channel selection register is a storage unit within the complex programmable logic device used to store Gray code channel values. This register consists of multiple independent flip-flops. Flip-flops are basic storage units in digital circuits, capable of storing one bit of binary information. The number of flip-flops is set to an odd number to support subsequent majority decision logic.

[0050] In this example implementation, the flip-flops can be distributed across different logic cell regions of a complex programmable logic device.

[0051] Different logic unit regions refer to logic resource blocks that are physically isolated from each other or far apart within a complex programmable logic device (CPLD). In terms of physical layout, the three flip-flops can be distributed as much as possible in different logic unit regions of the CPLD to reduce the probability of local noise affecting multiple flip-flops simultaneously. This is an important guarantee for the validity of majority voting, thereby improving the reliability and stability of the entire system.

[0052] In step S130, the Gray code channel value is sampled by each trigger, and the target Gray code channel value is obtained based on the Gray code sampled value output by each trigger.

[0053] In this example implementation, the Gray code sample value is the value output by each flip-flop after sampling the Gray code channel value. Since flip-flops may be affected by noise, their output sample values ​​may differ from the actual written Gray code channel value. The target Gray code channel value is the correct Gray code value obtained by majority voting on the Gray code sample values ​​output by each flip-flop; this value eliminates bit transitions caused by noise.

[0054] In this example implementation, the value corresponding to each bit in the Gray code sampled values ​​output by each trigger can be obtained; the value that appears most frequently among the values ​​corresponding to the bit is determined as the target value of the bit, and the target Gray code channel value is obtained based on the target value of each bit.

[0055] Specifically, for each bit of the Gray code channel value, the system obtains the sampling result of that bit from each independent trigger. This step can be achieved by reading the output states of all triggers in parallel, or by reading the output of each trigger sequentially using a multiplexer. Its purpose is to provide the necessary data foundation for subsequent majority voting, ensuring that the decision for each bit is based on multiple independent observations. Subsequently, a majority voting mechanism can be used to determine the final value of a single bit from multiple sampled values. For example, if a bit is sampled as "0, 0, 1" in three triggers, then "0" appears twice and "1" appears once, so the target value for that bit is determined to be "0". Finally, after determining the target value for each bit of the Gray code channel value through majority voting, these independently determined bits are combined to form the complete target Gray code channel value. By integrating the reliable determination results of all bits, a more stable and accurate Gray code channel value is generated overall, providing reliable input for subsequent decoding and channel selection.

[0056] For example, TMR (Triple Modular Redundancy) technology can be applied to the CPLDI2C multiplexed channel selection register to mask single bit transitions in real time using majority voting logic.

[0057] like Figure 2 The diagram shown is a schematic of a three-modular redundancy majority voting output logic structure in a specific embodiment of this disclosure. The three flip-flops, reg_a, reg_b, and reg_c, are sampled independently on the same clock edge, and all three output the same value during normal operation. This indicates that a bit transition has occurred in the trigger; voted[i] indicates the correct value output by majority vote; err_flag=1 indicates that a transition has been detected (optional monitoring); Gray code ensures safe switching.

[0058] The majority voting logic (implemented independently for each bit) is: voted[i] = (reg_a[i] AND reg_b[i]) OR (reg_b[i] AND reg_c[i]) OR (reg_a[i] AND reg_c[i]). Possible bit transitions are shown in Table 2.

[0059] Table 2

[0060] As can be seen from Table 2, when the bit transitions in a single trigger, the majority vote always outputs the correct value, and the bit transition is masked in real time.

[0061] Assuming the transition probability of a single trigger bit is P, then triple modal redundancy reduces the output error probability to the order of 3P²-2P³, which can be considered to be on the order of P³ in typical noisy environments, thus achieving an exponential reduction in the failure probability.

[0062] In this example implementation, by performing a majority vote on each bit—that is, obtaining the value corresponding to each bit in the Gray code sampled values ​​output by each trigger, and selecting the value that appears most frequently as the target value for that bit—the accuracy and robustness of the target Gray code channel value determination can be significantly improved. This method utilizes the redundancy information provided by an odd number of triggers; even if a few triggers erroneously sample, it will not affect the final bit determination result, thereby ensuring the stability and reliability of the target Gray code channel value and providing a solid foundation for the accurate determination of subsequent signal output channels.

[0063] The majority voting is purely combinational logic. When the outputs of the three flip-flops undergo voting, due to the different delays of each signal path, there may be race conditions on the output path, producing glitches with a width of less than one clock cycle, i.e., a brief erroneous level transition at the output. Therefore, glitches can be eliminated by sampling at the clock edge using two-stage registers.

[0064] In this example implementation, after obtaining the target Gray code channel value, the target Gray code channel value can be input into the first-level register. The first-level register performs glitch filtering on each bit of the target Gray code channel value to obtain the first-level filtered target Gray code channel value.

[0065] The first-stage register can be structured as a D flip-flop (Data Flip-Flop). A D flip-flop is a sequential logic element in digital circuits. Its core function is to "capture" the data at the input (D) and pass it to the output (Q) when the clock edge arrives, maintaining the output unchanged at other times. Glitching refers to eliminating brief, unexpected pulses or level transitions in digital signals using specific circuits or algorithms.

[0066] In this example implementation, the value of each bit in the target Gray code channel value can be sampled at the rising edge of the clock by delaying the first-level register by one clock cycle, and the value of the bit sampled at the rising edge of the clock is used as the value of the bit after the first-level filtering.

[0067] Upon receiving the target Gray code channel value, the first-level synchronization register does not immediately capture its value. Instead, it waits for a complete clock cycle and samples the data only when the rising edge of the next clock arrives. The principle behind the first-level register's glitches filtering is that it samples the input only momentarily at the rising edge of the clock and latches the sampled value at the output. Glitches, whose width is insufficient for a full clock cycle, cannot be sampled and are thus naturally filtered out.

[0068] While glitches can occur at combinational logic outputs, their duration is very short (much shorter than a clock cycle), and their occurrence is random, not necessarily near the rising edge of the clock. Even if a glitch happens to appear near the clock edge, the flip-flop will only sample an erroneous value if the setup / hold time window is met—and since the glitch width is usually much smaller than the setup time requirement, it is highly unlikely to be correctly sampled by the flip-flop. Therefore, when sampling at the rising edge of the clock, the flip-flop "sees" a stable valid level, not a brief glitch in the middle, and the glitch is naturally filtered out.

[0069] The above technical solution effectively avoids sampling transient noise or glitches during periods of signal instability or near clock edges, thereby significantly improving the stability of each bit in the target Gray code channel value, ensuring the signal quality of subsequent processing, and enhancing the reliability and accuracy of the entire channel selection signal.

[0070] In this example implementation, the target Gray code channel value after the first-stage filtering can also be input into the second-stage register, and the second-stage register can be used to perform signal stabilization processing on each bit of the target Gray code channel value to obtain the target Gray code channel value after the second-stage filtering.

[0071] The target Gray code channel value after the first-stage filtering refers to the Gray code channel value that has had some glitches removed after processing by the first-stage synchronization register. The second-stage synchronization register is a hardware component used for further synchronization and stabilization of the digital signal. It typically has the same structure as the first-stage register, for example, both being D flip-flops driven by the same clock, but their functions differ. The second-stage register is used to further stabilize the signal, ensuring that the output signal's setup and hold times meet the requirements of downstream logic.

[0072] In this example implementation, a clock cycle delay can be achieved by using a second-level register to sample the value of each bit in the target Gray code channel value after the first-level filtering at the rising edge of the clock, and the value of the bit sampled at the rising edge of the clock can be used as the value of the bit after the second-level filtering.

[0073] Although the glitch in the majority voting combinational logic is less than one clock cycle wide, if the glitch happens to occur within the setup / hold time window of the first-stage flip-flop, the first-stage flip-flop may enter a metastable state—the output is neither a stable 0 nor a stable 1, but an uncertain level between the two.

[0074] Metastability can cause the first-stage output to eventually stabilize to the correct value or the incorrect value within the current clock cycle. More importantly, if the downstream logic directly uses this metastable signal, different downstream paths may interpret this "half-high" level as different values ​​(some read 0, some read 1), leading to logic confusion.

[0075] After the first-stage flip-flop enters a metastable state, its output has a very high probability of naturally converging to a stable 0 or 1 within one clock cycle (the metastable convergence time is a probabilistic event; the longer the time, the higher the convergence probability). The second-stage flip-flop samples the output of the first stage on the next rising edge of the clock. By this time, the output of the first stage has already undergone a full clock cycle of convergence time and is almost certainly stable. Therefore, the output of the second stage is a completely stable signal that can safely drive downstream logic.

[0076] By employing the above technical solution, after filtering out glitches in the target Gray code channel value, a mechanism of delaying by one clock cycle and sampling on the rising edge of the clock is further used for signal stabilization, which significantly enhances the signal's anti-interference capability and stability. This two-stage synchronous register cascaded design effectively solves the metastability problem that may remain after the first-stage filtering, avoiding incorrect channel selection due to signal instability. Therefore, it ensures that even in complex programmable logic devices facing high-speed signal switching or noisy environments, the final target Gray code channel value after the second-stage filtering has extremely high reliability, thereby guaranteeing the accuracy of signal output channel selection and the overall stability of the system.

[0077] like Figure 3 The diagram shown is a timing sequence diagram of the output signal level protection in a specific embodiment of this disclosure. The glitch width is less than one clock cycle, disappearing by the time the first-level synchronization register samples; Gray code ensures only a 1-bit change during switching; the total delay is 2 CLK, having no impact on the I2C channel selection function.

[0078] By adding two stages of registers at the output to eliminate glitches caused by combinational logic race conditions, a three-layer mechanism forms a defense-in-depth. The two stages of registers constitute a classic synchronizer structure. The first stage bears the risk of being hit by metastability, while the second stage waits for a convergence window of one clock cycle before sampling, reducing the probability of metastability propagation from P to P² (where P is the probability of metastability at a single stage), which is almost negligible at a 10MHz CPLD clock.

[0079] The two-level synchronization register introduces a two-clock-cycle delay. Taking a 10MHz CPLD operating clock as an example, the delay is 200ns (nanoseconds), which is much smaller than the minimum bit width of 5μs (microseconds) in I2C 100kHz mode and has no impact on the I2C multiplexing function.

[0080] In this example implementation, the initial channel values ​​of the flip-flops in the first-level register, the second-level register, and the channel selection register can also be set to the default Gray code values ​​when the complex programmable logic device is powered on and reset.

[0081] After the CPLD is powered on and reset, all channels are inactive (or channel 0 is selected), and the I2C bus is in a safe idle state. At this time, the three flip-flops and the synchronization register can be synchronously reset to the default Gray code value, such as all 0s, which is the same as the binary code value of 0. This ensures that the initial state is determined upon power-on, avoids uncertain power-on output, and also allows the register reset to naturally output a low level, without the need for additional initialization logic.

[0082] In step S140, the target Gray code channel value is decoded and converted into a corresponding target channel selection signal, so as to determine the signal output channel through the target channel selection signal.

[0083] In this example implementation, the final target Gray code channel value is decoded into a target channel selection signal. The target channel selection signal is a processed and stabilized signal used to ultimately determine the signal output channel. This signal is used to control the I2C multiplexer or other channel selection logic within the complex programmable logic device, thereby determining the final signal output channel. The signal output channel refers to the physical or logical channel for data transmission or processing determined based on the target channel selection signal.

[0084] In this example implementation, it can also be determined whether the Gray code sample values ​​output by each trigger are the same; if the Gray code sample values ​​are different, the error detection flag corresponding to the bit with different values ​​in the Gray code sample value is set as the first flag.

[0085] Specifically, a consistency check can be performed on the Gray code sample values ​​output from multiple independent flip-flops in the channel selection register. Since these flip-flops operate independently, ideally they should output the same Gray code sample value. This step aims to identify any inconsistencies by comparing the Gray code sample values ​​output from all flip-flops pairwise; if any pair is different, it is considered dissimilar. Once an inconsistency is detected, the system further analyzes which bit(s) differ and assigns a specific error flag to these dissimilar bits.

[0086] Taking the Gray code sampled values ​​output by three triggers as an example, the error detection logic is: err_flag[i] = (reg_a[i] XOR reg_b[i]) OR (reg_b[i] XOR reg_c[i]) OR (reg_a[i] XOR reg_c[i]). When all three are consistent, err_flag[i] = 0; when any one of them changes, err_flag[i] = 1.

[0087] The optional error detection flag register enables BIT transition observability. It allows BIT transition events to be monitored and recorded by the master controller, facilitating online fault statistics and analysis, and enabling hardware protection and software monitoring to work together.

[0088] like Figure 4 The diagram shown is a block diagram of the internal structure of a complex programmable logic device (CPLD) with enhanced logic in a specific embodiment of this disclosure. The triple modulo redundancy register group, majority voting, two-level synchronization registers, and Gray code encoding / decoding are all implemented within the CPLD's internal HDL (Hardware Description Language) design layer, requiring no additional GPIO (General Purpose Input / Output) connections, external devices, or PCB (Printed Circuit Board) routing modifications. CLK is the CPLD's operating clock; err_lag is used for monitoring and readback by the main controller. This block diagram mainly consists of the following modules: Gray code encoding unit: Receives the binary channel number sent by the master controller through the I2C bus, converts it into Gray code, and outputs it to the write end of the triple modulo redundant register group; Triple Modular Redundancy Register Set: Composed of three independent flip-flops, reg_a, reg_b, and reg_c, which independently sample Gray code channel values ​​along the same clock edge; Majority voting logic unit: Performs independent majority voting on each bit of the three flip-flops and outputs a fault-tolerant channel selection signal; Two-stage output registers: cascaded at the majority voting output to filter out combinational logic glitches; Gray code decoding unit: decodes the Gray code output from the two-stage registers into a binary channel selection signal to drive the output pin; Error detection flag unit (optional): Sets err_flag when the outputs of the three triggers are inconsistent, so that the master controller can read back for monitoring.

[0089] The complete data flow is as follows: Master I2C write → Gray code encoding → Triple modal redundancy trigger group → Majority voting → Two-level registers → Gray code decoding → Channel selection output pin → Downstream I2C devices.

[0090] The above solution is applicable to all network devices that use CPLD to implement I2C multiplexing, and can be extended to other control register hardening scenarios implemented by CPLD. It can also be used in conjunction with software-layer write-back verification and GPIO reset recovery solutions to build a two-layer protection system.

[0091] It should be noted that although the steps of the method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or a step may be broken down into multiple steps.

[0092] Furthermore, this disclosure also provides a signal processing apparatus applied to a complex programmable logic device. (Reference) Figure 5 As shown, the signal processing device may include a Gray code encoding module 510, a Gray code writing module 520, a trigger sampling module 530, and a Gray code decoding module 540. Wherein: Gray code encoding module 510 is configured to perform the following: obtain the channel number from the original channel selection signal, encode the channel number, and convert the channel number into the corresponding Gray code channel value. Gray code writing module 520 is configured to write Gray code channel values ​​into a channel selection register, wherein the channel selection register contains multiple independent triggers, and the number of triggers is odd. The trigger sampling module 530 is configured to sample the Gray code channel values ​​through each trigger and obtain the target Gray code channel value based on the Gray code sample values ​​output by each trigger. Gray code decoding module 540 is configured to decode the target Gray code channel value, convert the target Gray code channel value into the corresponding target channel selection signal, and determine the signal output channel through the target channel selection signal.

[0093] In some exemplary embodiments of this disclosure, the trigger sampling module 530 may include a bit value acquisition unit and a value occurrence count comparison unit. Wherein: The bit value acquisition unit is configured to acquire the value of each bit in the Gray code sample value output by each trigger; The numerical occurrence comparison unit is configured to determine the value that appears most frequently among the values ​​corresponding to the bit as the target value of the bit, and obtain the target Gray code channel value based on the target values ​​of each bit.

[0094] In some exemplary embodiments of this disclosure, a signal processing apparatus provided by this disclosure may further include a first-stage filtering module, configured to input the target Gray code channel value into a first-stage register, and perform glitch filtering on each bit of the target Gray code channel value through the first-stage register to obtain the first-stage filtered target Gray code channel value.

[0095] In some exemplary embodiments of this disclosure, the first-stage filtering module may include a clock rising edge sampling unit configured to perform sampling of the value of each bit in the target Gray code channel value at the clock rising edge by delaying for one clock cycle through the first-stage register, and to use the value of the bit sampled at the clock rising edge as the value of the bit after first-stage filtering.

[0096] In some exemplary embodiments of this disclosure, a signal processing apparatus provided by this disclosure may further include a second-stage filtering module, configured to input the target Gray code channel value after the first-stage filtering into a second-stage register, and perform signal stabilization processing on each bit of the target Gray code channel value through the second-stage register to obtain the target Gray code channel value after the second-stage filtering.

[0097] In some exemplary embodiments of this disclosure, the second-stage filtering module may include a clock rising edge sampling unit configured to perform a clock cycle delay based on the first-stage register, sample the value of each bit in the target Gray code channel value after the first-stage filtering at the rising edge of the clock through the second-stage register, and use the value of the bit sampled at the rising edge of the clock as the value of the bit after the second-stage filtering.

[0098] In some exemplary embodiments of this disclosure, a signal processing apparatus provided by this disclosure may further include an initial value setting module configured to set the initial channel value of the flip-flops in the first-level register, the second-level register, and the channel selection register to a default Gray code value when the complex programmable logic device is powered on and reset.

[0099] In some exemplary embodiments of this disclosure, the signal processing apparatus provided by this disclosure may further include an error detection module, configured to determine whether the Gray code sample values ​​output by each trigger are the same; if the Gray code sample values ​​are different, then the error detection flag corresponding to the bit with different values ​​in the Gray code sample values ​​is set as a first flag.

[0100] The specific details of each module / unit in the above signal processing device have been described in detail in the corresponding method embodiment section, and will not be repeated here.

[0101] Figure 6 A schematic diagram of the structure of a computer system suitable for implementing the embodiments of the present disclosure is shown.

[0102] It should be noted that, Figure 6 The computer system 600 of the electronic device shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments disclosed herein.

[0103] like Figure 6 As shown, the computer system 600 includes a central processing unit (CPU) 601, which can perform various appropriate actions and processes based on programs stored in read-only memory (ROM) 602 or programs loaded from storage section 608 into random access memory (RAM) 603. The RAM 603 also stores various programs and data required for system operation. The CPU 601, ROM 602, and RAM 603 are interconnected via a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0104] The following components are connected to I / O interface 605: an input section 606 including a keyboard, mouse, etc.; an output section 607 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and speakers, etc.; a storage section 608 including a hard disk, etc.; and a communication section 609 including a network interface card such as a LAN card, modem, etc. The communication section 609 performs communication processing via a network such as the Internet. A drive 610 is also connected to I / O interface 605 as needed. A removable medium 611, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on drive 610 as needed so that computer programs read from it can be installed into storage section 608 as needed.

[0105] In particular, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication section 609, and / or installed from removable medium 611. When the computer program is executed by central processing unit (CPU) 601, it performs various functions defined in the system of this disclosure.

[0106] An exemplary embodiment of this disclosure also provides a computer program product. The computer program product includes a computer program that, when executed by a processor, implements the signal processing method described above.

[0107] In one implementation, the computer program product can be a tangible product containing a computer program, such as a computer-readable storage medium storing the computer program. The readable storage medium can be a storage medium based on electrical, magnetic, optical, electromagnetic, infrared, or other signals, including but not limited to: random access memory (RAM), read-only memory (ROM), magnetic tape, floppy disk, flash memory, hard disk drive (HDD), solid-state drive (SSD), etc. For example, the computer program product can be implemented as a non-volatile storage medium storing a computer program, such as read-only memory, NAND flash memory, etc.

[0108] In one implementation, the computer program product can be an intangible product containing a computer program. For example, the computer program product can be implemented as a virtual digital product, such as an executable file, installation package, or other digital file storing the computer program.

[0109] Computer program code can be written in one or more programming languages. Examples of programming languages ​​include C, Java, and C++. Program code can execute entirely on the user's computing device, partially on the user's computing device, or as a standalone software package. It can also execute partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, such as a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via an internet connection provided by a mobile network operator).

[0110] Computer programs can be carried or transmitted via signals such as electrical, magnetic, optical, electromagnetic, and infrared rays. Electronic devices can convert signals carrying computer programs into digital signals, thereby running the computer programs. When a computer program runs on an electronic device, its code is used to cause the electronic device to execute (more specifically, to be executed by the processor of the electronic device) the method steps of various exemplary embodiments of this disclosure, such as the signal processing methods described above.

[0111] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0112] It should be noted that although several modules for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules described above can be embodied in one module. Conversely, the features and functions of one module described above can be further divided and embodied by multiple modules.

[0113] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein.

[0114] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A signal processing method applied to a complex programmable logic device, characterized in that, include: Obtain the channel number from the original channel selection signal, encode the channel number, and convert the channel number into the corresponding Gray code channel value; The Gray code channel value is written into the channel selection register, wherein the channel selection register contains multiple independent triggers, and the number of triggers is odd. The Gray code channel value is sampled by each of the aforementioned triggers, and the target Gray code channel value is obtained based on the Gray code sampled value output by each of the aforementioned triggers; The target Gray code channel value is decoded and converted into a corresponding target channel selection signal, so as to determine the signal output channel through the target channel selection signal.

2. The signal processing method according to claim 1, characterized in that, The method of obtaining the target Gray code channel value based on the Gray code sampling values ​​output by each of the triggers includes: Obtain the value corresponding to each bit in the Gray code sample value output by each of the triggers; The value that appears most frequently among the values ​​corresponding to the bit is determined as the target value of the bit, and the target Gray code channel value is obtained based on the target values ​​of each bit.

3. The signal processing method according to claim 1, characterized in that, The method further includes: The target Gray code channel value is input into the first-level register, and each bit in the target Gray code channel value is filtered out by the first-level register to obtain the target Gray code channel value after first-level filtering.

4. The signal processing method according to claim 3, characterized in that, The step of performing glitch filtering on each bit of the target Gray code channel value through the first-level register includes: The first-stage register delays the sampling of each bit in the target Gray code channel value by one clock cycle at the rising edge of the clock, and uses the bit value sampled at the rising edge of the clock as the bit value after the first-stage filtering.

5. The signal processing method according to claim 3, characterized in that, The method further includes: The target Gray code channel value after the first-stage filtering is input into the second-stage register. The second-stage register performs signal stabilization processing on each bit of the target Gray code channel value to obtain the target Gray code channel value after the second-stage filtering.

6. The signal processing method according to claim 5, characterized in that, The step of performing signal stabilization processing on each bit of the target Gray code channel value through the second-level register includes: Based on the first-level register, a clock cycle is delayed, and the value of each bit in the target Gray code channel value after the first-level filtering is sampled at the rising edge of the clock through the second-level register, and the value of the bit sampled at the rising edge of the clock is used as the value of the bit after the second-level filtering.

7. The signal processing method according to claim 5, characterized in that, The method further includes: When the complex programmable logic device is powered on and reset, the initial channel values ​​of the flip-flops in the first-level register, the second-level register, and the channel selection register are set to the default Gray code values.

8. The signal processing method according to claim 1, characterized in that, The method further includes: Determine whether the Gray code sample values ​​output by each of the aforementioned triggers are the same; If the Gray code sample values ​​are different, the error detection flag corresponding to the bit with different values ​​in the Gray code sample values ​​is set as the first flag.

9. The signal processing method according to claim 1, characterized in that, Each of the aforementioned flip-flops is distributed in a different logic unit region of the complex programmable logic device.

10. A signal processing apparatus, applied to a complex programmable logic device, characterized in that, include: The Gray code encoding module is configured to retrieve the channel number from the original channel selection signal, encode the channel number, and convert the channel number into the corresponding Gray code channel value. The Gray code writing module is configured to write the Gray code channel value into a channel selection register, wherein the channel selection register contains multiple independent triggers, and the number of triggers is odd. The trigger sampling module is configured to sample the Gray code channel values ​​through each of the triggers respectively, and obtain the target Gray code channel value based on the Gray code sampled values ​​output by each of the triggers; The Gray code decoding module is configured to decode the target Gray code channel value, convert the target Gray code channel value into a corresponding target channel selection signal, and determine the signal output channel through the target channel selection signal.

11. An electronic device, characterized in that, include: processor; Memory used to store the processor's executable instructions; The processor is configured to execute the instructions to implement the signal processing method as described in any one of claims 1 to 9.

12. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the signal processing method as described in any one of claims 1 to 9.

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