A method for adaptive scheduling of BMS daisy chain communication load and related device

Abstract

The application discloses a BMS daisy chain communication load adaptive scheduling method and related equipment. In the method, the actual communication delay and multi-dimensional real-time load parameters of the last period are obtained in time, and a working condition representation vector is constructed through normalization. The vector is matched with a preset rule library to identify a load sudden increase state and determine a scheduling constraint. Within the constraint range, the vector is used to query a pre-trained Q learning strategy table with the minimum communication delay as a target to generate a basic resource allocation scheme including a bandwidth proportion, a collection priority and an upload frequency. Then, proportional integral compensation is performed based on the deviation between the target and the actual delay, and a continuous compensation amount is added to the bandwidth proportion parameter of the basic scheme to generate a final target resource allocation scheme. Finally, the scheduling queue is updated and the configuration parameters are sequentially issued according to the final target resource allocation scheme. The application is used for reducing communication congestion caused by local load sudden increase, reducing the transmission delay of key state data and improving the communication real-time performance.

Description

Technical Field

[0001] This application belongs to the field of intelligent scheduling, and in particular relates to an adaptive scheduling method and related equipment for BMS daisy chain communication load. Background Technology

[0002] The battery management system (BMS) is a core control component of energy storage systems and new energy vehicles. Its internal main control unit and various data acquisition modules are typically connected via a daisy-chain communication method to achieve functions such as voltage acquisition, temperature monitoring, and equalization control. In the traditional fixed-polling scheduling method, the main controller needs to send instructions to each slave controller sequentially according to a preset order, and after each transmission, wait for the signal to be transmitted cascaded up the daisy chain and returned before executing the next action. This scheduling mechanism causes the main controller to be idle while waiting for a response, unable to handle other computational tasks, resulting in a significant consumption of the main control unit's computing resources and a consistently high overall load rate.

[0003] To reduce the communication load on the main control unit, a daisy-chain communication scheduling method based on task decomposition and operating system collaboration has been proposed. This technique breaks down the originally continuous daisy-chain communication tasks into multiple independent subtasks and alternates their execution with other target tasks in the real-time operating system. Specifically, after sending a daisy-chain communication instruction, the main controller no longer blocks and waits. Instead, it uses the operating system's task scheduling mechanism to hand over control of the processor to other tasks that need computation. When the underlying hardware of the daisy chain receives a return signal and triggers an interrupt, the operating system then reawakens the communication task to continue sending subsequent instructions. This approach reduces the main controller's invalid waiting time during communication and improves the processor's resource utilization.

[0004] In high-power DC fast charging applications for new energy vehicles, the temperature and individual cell voltages within the battery pack change rapidly. During implementation, because the task breakdown granularity and execution priority are pre-set and fixed, when the high-voltage acquisition module experiences a sudden surge in local communication data due to frequent overvoltage or overtemperature warnings, the main controller still allocates bus bandwidth according to the predetermined static mechanism. This can easily cause congestion in the communication queue for sudden high-priority acquisition tasks, making it difficult to quickly acquire the necessary communication resources and thus increasing the transmission delay of critical status data. Summary of the Invention

[0005] This application provides an adaptive scheduling method and related equipment for BMS daisy chain communication load, which can reduce communication congestion caused by sudden local load increases, reduce the transmission delay of critical status data, and improve communication real-time performance.

[0006] In the first aspect, this application provides an adaptive scheduling method for BMS daisy-chain communication load, which, in response to a timer interrupt, obtains the actual communication delay of the previous communication cycle and reads the real-time load parameters in the analog front-end registers at each level. The real-time load parameters include the battery cell state change rate, throughput, instruction response delay, frame error ratio, and the depth of the task queue to be executed.

[0007] Real-time load parameters are normalized to construct a working condition representation vector.

[0008] The working condition representation vector is matched with the rule triggering conditions in the preset rule base to identify local load surge states and determine the target rule. The parameter adjustment range corresponding to the target rule is used as the scheduling constraint.

[0009] Within the scheduling constraints, the working condition representation vector is used as the state input. The pre-trained and converged Q-learning strategy table is queried, and the action space consisting of bandwidth ratio, acquisition priority and upload frequency is output to generate a basic resource allocation scheme. The Q-learning strategy table is pre-trained with the goal of minimizing communication latency as the reward. The bandwidth ratio parameter of each state-action pair in the Q-learning strategy table is stored in discrete increments.

[0010] Calculate the delay deviation based on the target communication delay and the actual communication delay;

[0011] Proportional-integral compensation is performed based on delay deviation to obtain a continuous compensation amount for the bandwidth ratio parameter in the basic resource allocation scheme. The continuous compensation amount is a continuously changing amount.

[0012] The continuous compensation amount is superimposed on the bandwidth ratio parameter in the basic resource allocation scheme, while keeping the acquisition priority and upload frequency unchanged, to obtain a target resource allocation scheme that includes the target bandwidth ratio, target acquisition priority, and target upload frequency. The target bandwidth ratio is equal to the sum of the nominal value corresponding to the basic bandwidth ratio level and the continuous compensation amount. That is, continuous incremental adjustment is applied on the basis of discrete scheduling decision, and the target acquisition priority and target upload frequency are the basic acquisition priority and basic upload frequency.

[0013] The local communication scheduling queue is updated according to the target resource allocation scheme, and the communication configuration parameters in the analog front-end registers at each level are updated by issuing configuration frames level by level.

[0014] By adopting the above technical solution, and by acquiring multi-dimensional real-time load parameters and actual communication delays and performing normalization processing, the system can accurately characterize the current communication condition. The condition characterization vector is matched with a preset rule base to determine scheduling constraints, and within these constraints, a pre-trained Q-learning strategy table is used to output a basic resource allocation scheme. This allows the system to perform macro-level scheduling guided by minimizing communication delays while ensuring safety boundaries. Furthermore, proportional-integral compensation is performed based on the deviation between the target and the actual communication delay, and the continuous compensation is superimposed on the bandwidth ratio parameter. This achieves micro-level fine-tuning of the discrete action space, improving the resource allocation flexibility and response speed of the daisy-chain communication system under dynamic load changes, and reducing the overall communication delay under complex and variable conditions.

[0015] In conjunction with some implementations of the first aspect, in some implementations, the operating condition representation vector is matched with the rule triggering conditions in a preset rule base to identify local load surge states and determine target rules. The parameter adjustment range corresponding to the target rule is used as a scheduling constraint, specifically including:

[0016] Calculate the matching degree between the working condition representation vector and the rule triggering conditions of each candidate rule in the preset rule base;

[0017] The candidate rule with the highest matching degree is identified as the target rule;

[0018] When the target rule belongs to the preset real-time priority rule category, the local load surge state is identified based on the target rule.

[0019] Extract the historical execution scores associated with the target rule;

[0020] Calculate the boundary scaling factor based on historical execution scores;

[0021] The target adjustment boundary is obtained by scaling the preset initial adjustment boundary of the target rule using the boundary scaling factor.

[0022] Use the target adjustment boundary as a scheduling constraint.

[0023] By employing the aforementioned technical solution, the system determines the target rule by calculating the matching degree between the working condition representation vector and the candidate rules, enabling accurate identification of local load surges. Historical execution scores associated with the target rule are extracted and a boundary scaling factor is calculated accordingly. This allows the system to dynamically assess the risk level of the current scheduling based on the actual performance of specific rules in past scheduling. The boundary scaling factor is used to scale the preset initial adjustment boundary to obtain the target adjustment boundary, which is then used as a constraint for subsequent scheduling. This ensures that the adjustment range of resource allocation parameters can adaptively shrink or expand based on historical experience, improving the rationality and specificity of scheduling constraint settings and reducing the risk of parameter exceeding limits due to fixed adjustment boundaries.

[0024] In conjunction with some implementation methods of the first aspect, in some implementation methods, within scheduling constraints, using the working condition representation vector as the state input, a pre-trained and converged Q-learning policy table is queried, and the action space consisting of bandwidth ratio, acquisition priority, and upload frequency is output to generate a basic resource allocation scheme, specifically including:

[0025] Map the operating condition representation vector to the current discrete state;

[0026] Based on scheduling constraints, the action space consisting of bandwidth ratio, acquisition priority, and upload frequency is filtered to obtain a safe action subspace.

[0027] In the pre-trained converged Q-learning policy table, query the Q-value of each candidate action in the safe action subspace corresponding to the current discrete state;

[0028] Select the candidate action with the largest Q value as the target action;

[0029] A basic resource allocation scheme is generated based on the bandwidth ratio, collection priority, and upload frequency of the target action.

[0030] By adopting the above technical solution, the system provides standardized state inputs for the Q-learning strategy table by mapping the working condition representation vector to discrete states. The global action space is filtered using pre-determined scheduling constraints to obtain a safe action subspace, ensuring that subsequent strategy queries are performed only within the range of actions that have been safely verified. The Q-values ​​of each candidate action within this safe subspace are queried in the pre-trained and converged Q-learning strategy table, and the action corresponding to the largest Q-value is used as the target action to generate a basic resource allocation scheme. This ensures that the selected strategy meets both the long-term optimization objective of minimizing latency and the current load scheduling constraints, improving the decision-making efficiency of the reinforcement learning algorithm in practical applications and reducing the probability of outputting invalid or high-risk resource allocation schemes.

[0031] In conjunction with some implementations of the first aspect, in some implementations, after updating the local communication scheduling queue according to the target resource allocation scheme and updating the communication configuration parameters in the analog front-end registers at each level by issuing configuration frames step by step, the method further includes:

[0032] Obtain the forwarding queue overflow flag and local clock offset value from each level of the analog front-end register;

[0033] If it is determined that the forwarding queue overflow flag of the first analog front-end in the middle of the daisy chain is set, locate the second analog front-end that is downstream of the first analog front-end and is allocated the target bandwidth ratio.

[0034] The clock drift difference is calculated based on the local clock deviation value of the first analog front-end and the local clock deviation value of the second analog front-end.

[0035] Calculate the inter-frame micro-sleep duration based on clock drift difference;

[0036] Generate a gap injection command that includes the duration of inter-frame micro-sleep;

[0037] The gap injection command is sent to the second analog front end so that the second analog front end inserts an inter-frame micro-sleep duration between consecutively transmitted data frames.

[0038] By adopting the above technical solution and acquiring the overflow flags of the forwarding queues at each level of the simulated front-end, the system can promptly detect the congestion status of intermediate nodes in the daisy chain. Upon confirming an overflow at an intermediate node, the system locates the downstream node allocated the target bandwidth proportion and calculates the clock drift difference based on the local clock deviation between the two nodes. This accurately quantifies the degree of transmit / receive rate mismatch caused by clock asynchrony between upstream and downstream nodes. Based on this clock drift difference, the system calculates the inter-frame micro-sleep duration and generates a gap injection command, which is then sent to downstream nodes. This prompts downstream nodes to insert sleep gaps between continuously transmitted data frames, proactively reducing the instantaneous data transmission rate, improving the data flow matching degree between adjacent nodes, and reducing the forwarding queue overflow rate and data frame loss rate caused by insufficient processing by intermediate nodes.

[0039] In conjunction with some implementations of the first aspect, in some implementations, the inter-frame micro-sleep duration is calculated based on the clock drift difference, specifically including:

[0040] The base sleep duration is determined based on the clock drift difference;

[0041] Scan the downstream communication links of the first simulated front end and count the number of active downstream nodes currently in the data transmission state;

[0042] When the number of active downstream nodes is greater than 1, the aggregation amplification factor is determined based on the number of active downstream nodes, and the aggregation amplification factor is positively correlated with the number of active downstream nodes.

[0043] The inter-frame micro-sleep duration is obtained by amplifying and adjusting the basic sleep duration using the convergence amplification factor.

[0044] When the number of active downstream nodes is equal to 1, the basic sleep duration is used as the inter-frame micro-sleep duration.

[0045] By adopting the above technical solution and determining the basic sleep duration based on the clock drift difference, the system establishes a preliminary benchmark for transmit and receive rate matching. Further scanning of the downstream communication links of the first analog front-end in the intermediate stage, and counting the number of active downstream nodes currently transmitting data, allows the system to accurately perceive the concurrent pressure when data from multiple nodes converges to the intermediate node. When the number of active downstream nodes is greater than one, the basic sleep duration is amplified and adjusted using a convergence amplification coefficient positively correlated with the number of active nodes, thereby dynamically extending the sleep interval according to the actual degree of concurrent congestion. When the number of active downstream nodes is equal to one, the basic sleep duration is directly used as the micro-sleep duration, avoiding invalid waiting when there is no concurrent pressure, improving the rationality and targeting of the inter-frame micro-sleep duration setting, and reducing the risk of data congestion caused by insufficient processing capacity of intermediate nodes when multiple nodes are concurrently uploading data.

[0046] In some embodiments, in conjunction with some implementations of the first aspect, after issuing a gap injection command to the second analog front-end to cause the second analog front-end to insert an inter-frame micro-sleep duration between consecutively transmitted data frames, the method further includes:

[0047] Obtain the total number of data frames to be sent by the second simulated front-end in the current scheduling period;

[0048] The product of the total number of data frames to be sent and the inter-frame micro-sleep time is used as the periodic cumulative sleep time.

[0049] Obtain the total duration of the current scheduling cycle, and calculate the available allocation duration of the second simulated front end based on the total duration and the target bandwidth ratio in the target resource allocation scheme;

[0050] Obtain the original transmission time of the total number of data frames to be sent continuously by the second simulated front end;

[0051] The sum of the original transmission time and the periodic cumulative sleep time is used as the total time after compensation.

[0052] If the total time consumed after compensation is greater than the allocated available time, the difference between the total time consumed after compensation and the allocated available time is calculated to obtain the overflow time.

[0053] Calculate the number of target frames that need to be truncated based on the overflow duration and the transmission time of a single frame;

[0054] Low-priority data frames, equal in number to the target frames, are stripped from the pending task queue of the second analog front-end to limit the actual transmission time of the second analog front-end to within the allocated available time.

[0055] By adopting the above technical solution, the cumulative sleep time of the cycle is obtained by multiplying the total number of data frames to be sent by the inter-frame micro-sleep duration, and then adding it to the original transmission time to obtain the compensated total time. The system can accurately evaluate the overall time overhead after injecting the micro-sleep mechanism. The allocated available time of the second simulated front end is calculated by combining the current total scheduling cycle duration with the target bandwidth ratio, setting strict time boundaries for the transmission actions of this node. When the compensated total time is greater than the allocated available time, the overflow time is obtained by calculating the difference between the two, and based on this, the number of target frames to be truncated is calculated in combination with the single frame transmission time. Then, the corresponding number of low-priority data frames are stripped from the task queue to be sent, ensuring that the actual transmission time of the node after increasing the sleep gap is still strictly limited within the allocated quota, improving the execution accuracy of communication resource scheduling within a single cycle, and reducing the risk of scheduling cycle timeout caused by the introduction of the micro-sleep mechanism.

[0056] In conjunction with some implementations of the first aspect, in some implementations, a number of low-priority data frames equal to the number of target frames are stripped from the pending task queue of the second analog front-end, in order to limit the actual transmission time of the second analog front-end to within the allocated available time, specifically including:

[0057] Traverse the queue of tasks to be sent and extract candidate data frames with preset low-priority tags;

[0058] Get the queuing time of the candidate data frame in the task queue to be sent;

[0059] Candidate data frames are sorted in ascending order of queuing time from shortest to longest to obtain candidate stripping sequences;

[0060] Starting from the head of the candidate stripping sequence, extract the same number of candidate data frames as the target frames, and use them as the target stripping frames;

[0061] Remove the target stripping frame from the pending task queue to limit the actual transmission time of the second analog front end to the allocated available time.

[0062] By employing the above technical solution, the system extracts candidate data frames with preset low-priority tags by traversing the task queue to be sent. During truncation operations, the system prioritizes the complete transmission of high-priority critical data. Furthermore, the system obtains the queuing time of these candidate data frames and arranges them in ascending order of queuing time to generate a candidate stripping sequence. This allows the system to accurately distinguish the retention status of different low-priority data frames. Frames equal in number to the target frames are truncated from the head of this sequence and removed as target stripping frames. This ensures that the system prioritizes discarding the most recently generated low-priority data while retaining low-priority data with longer waiting times, improving the rationality of task queue management.

[0063] Furthermore, embodiments of this application provide an adaptive scheduling related device for BMS daisy-chain communication load, the related device comprising a system, a computer-readable storage medium, and a computer program product.

[0064] Secondly, embodiments of this application provide an adaptive scheduling system for BMS daisy-chain communication load. The adaptive scheduling system for BMS daisy-chain communication load includes: one or more processors and a memory; the memory is coupled to one or more processors, and the memory is used to store computer program code, the computer program code including computer instructions, and one or more processors call the computer instructions to cause the system to perform the method described in the first aspect and any possible implementation thereof.

[0065] Thirdly, embodiments of this application provide a computer-readable storage medium including instructions that, when executed on a system, cause the system to perform the method described in the first aspect and any possible implementation thereof.

[0066] Fourthly, embodiments of this application provide a computer program product that, when run on a system, causes the system to execute the method described in any possible implementation of the first aspect.

[0067] One or more technical solutions provided in the embodiments of this application have at least the following technical effects or advantages:

[0068] 1. This application provides an adaptive scheduling method for BMS daisy-chain communication load. By acquiring multi-dimensional real-time load parameters and actual communication delays and performing normalization processing, the system can accurately characterize the current communication conditions. The condition characterization vector is matched with a preset rule base to determine scheduling constraints. Within these constraints, a pre-trained Q-learning strategy table is used to output a basic resource allocation scheme, enabling the system to perform macro-level scheduling guided by minimizing communication delays while ensuring safety boundaries. Furthermore, proportional-integral compensation is performed based on the deviation between the target and the actual communication delay, and the continuous compensation amount is superimposed on the bandwidth proportional parameter. This achieves micro-level fine-tuning of the discrete action space, improving the resource allocation flexibility and response speed of the daisy-chain communication system under dynamic load changes, and reducing the overall communication delay under complex and variable conditions.

[0069] 2. This application provides an adaptive scheduling method for BMS daisy-chain communication load. By acquiring the overflow flag of the forwarding queue at each level of the simulated front end, the system can promptly detect the congestion status of intermediate nodes in the daisy chain. When overflow is confirmed at an intermediate node, the downstream node allocated the target bandwidth ratio is located, and the clock drift difference is calculated based on the local clock deviation between the two nodes. This accurately quantifies the degree of mismatch in transmit and receive rates caused by clock asynchrony between upstream and downstream nodes. Based on this clock drift difference, the inter-frame micro-sleep duration is calculated, and a gap injection command is generated and sent to the downstream node. This prompts the downstream node to insert a sleep gap between continuously transmitted data frames, actively reducing the instantaneous data transmission rate, improving the data flow matching degree between adjacent nodes, and reducing the forwarding queue overflow rate and data frame loss rate caused by the intermediate node's inability to process the data.

[0070] 3. This application provides an adaptive scheduling method for BMS daisy-chain communication load. The cumulative sleep time within a period is obtained by multiplying the total number of data frames to be sent by the inter-frame micro-sleep duration, and then added to the original transmission time to obtain the compensated total time. The system can accurately assess the overall time overhead after injecting the micro-sleep mechanism. The allocated available time for the second simulated front-end is calculated by combining the current total scheduling period duration with the target bandwidth ratio, setting strict time boundaries for the node's transmission actions. If the compensated total time exceeds the allocated available time, the overflow time is obtained by calculating the difference between the two. Based on this, the number of target frames to be truncated is calculated in conjunction with the single-frame transmission time. Then, a corresponding number of low-priority data frames are removed from the task queue to be sent, ensuring that the actual transmission time of the node is still strictly limited within the allocated quota after increasing the sleep gap. This improves the execution accuracy of communication resource scheduling within a single period and reduces the risk of scheduling period timeout caused by the introduction of the micro-sleep mechanism. Attached Figure Description

[0071] Figure 1This is a flowchart illustrating an adaptive scheduling method for BMS daisy chain communication load in an embodiment of this application.

[0072] Figure 2 This is another flowchart illustrating an adaptive scheduling method for BMS daisy-chain communication load in an embodiment of this application.

[0073] Figure 3 This is another flowchart illustrating an adaptive scheduling method for BMS daisy-chain communication load in an embodiment of this application.

[0074] Figure 4 This is a schematic diagram of the physical device structure of an adaptive scheduling system for BMS daisy-chain communication load provided in an embodiment of this application. Detailed Implementation

[0075] The terminology used in the following embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. As used in the specification and appended claims of this application, the singular expressions “a,” “an,” “the,” “the,” “the,” and “this” are intended to include the plural expressions as well, unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this application refers to any or all possible combinations including one or more of the listed items.

[0076] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as implying or suggesting relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature, and in the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more.

[0077] The following example is used in conjunction with Figure 1 An adaptive scheduling method for BMS daisy-chain communication load is described in an embodiment of this application:

[0078] Please see Figure 1 This is a flowchart illustrating an adaptive scheduling method for BMS daisy chain communication load in an embodiment of this application.

[0079] S101. In response to a timer interrupt, obtain the actual communication delay of the previous communication cycle and read the real-time load parameters in each level of the analog front-end register.

[0080] The system responds to timer interrupts, obtains the actual communication delay of the previous communication cycle, and reads the real-time load parameters in the analog front-end registers at each level. The real-time load parameters include the battery cell state change rate, throughput, instruction response delay, frame error ratio, and the depth of the task queue to be executed.

[0081] Timer interruption refers to a system interruption mechanism triggered when a hardware or software timer reaches a preset time period. The previous communication cycle refers to the preceding complete data transmission and reception period immediately adjacent to the current scheduling moment on the timeline. Actual communication latency refers to the real physical time elapsed from when a data frame is sent from the sender to when the receiver returns a response. The analog front-end register can be any internal storage unit of the battery sampling chip or the configuration cache of the data acquisition terminal. Real-time load parameters are multi-dimensional dynamic indicators reflecting the current network communication pressure and task backlog, specifically including the battery cell state change rate, throughput, command response latency, frame error ratio, and the depth of the pending task queue. The battery cell state change rate can be any frequency of voltage changes or the number of abnormal temperature fluctuations. Throughput refers to the amount of data successfully transmitted per unit time. Command response latency refers to the interval from issuing a command to receiving a valid response. The frame error ratio refers to the ratio of corrupted data frames to the total number of transmitted frames. The depth of the pending task queue refers to the number of communication requests in the buffer that have not yet been processed. The system performs this step to accurately grasp the current actual communication status and load distribution of the daisy chain. This provides a comprehensive and objective real-time data foundation for subsequent scheduling decisions, improves the system's ability to detect network congestion and abnormal fluctuations, and reduces the risk of communication failures caused by blind resource allocation.

[0082] This can be achieved by triggering an interrupt service routine using a hardware timer. When the hardware timer overflows and generates an interrupt signal, the system automatically suspends the currently executing non-real-time background task, saves the context, and enters a dedicated interrupt handler function. In the interrupt handler function, the system reads the send and receive timestamps of the previous communication cycle recorded in the underlying communication controller and calculates the difference between them to obtain the actual communication delay. Subsequently, the system sends a specific formatted register batch read instruction to each level of the daisy-chain analog front-end via the serial peripheral interface. Upon receiving the instruction, the hardware logic of each level of the analog front-end packages the real-time statistics of battery cell voltage and temperature fluctuation counts, total number of data transmitted and received bytes, instruction response time records, error frame counter values, and task buffer occupancy from its internal registers into an acknowledgment frame and returns it. The system receives these acknowledgment frames, parses out the battery cell state fluctuation rate, throughput, instruction acknowledgment delay, frame error ratio, and task queue depth, and stores them in a designated data structure in local memory for subsequent algorithm calls.

[0083] Alternatively, this can be achieved using a direct memory access controller (DMC) in conjunction with an operating system timer. The system is configured with a high-precision software timer from the real-time operating system. When the timer's set period arrives, a dedicated data acquisition thread, currently in a blocked state, is awakened. This thread is configured with the DMC's transfer descriptor, enabling it to automatically transfer the actual communication delay data from the communication peripheral's data receive register of the previous communication cycle to a designated memory area. Next, the system constructs a broadcast data frame containing a request to read real-time load parameters and sends it to the daisy-chain network via the underlying driver. Each level of the analog front-end automatically responds to the broadcast data frame, transmitting the corresponding battery cell state change rate, throughput, instruction response latency, frame error rate, and task queue depth back through the daisy chain. The DMC then intervenes again, writing the complete data stream directly into a pre-allocated memory buffer. The system then performs cyclic redundancy checks and unpacking operations on the data in the buffer to extract the required real-time load parameters.

[0084] S102. Normalize the real-time load parameters to construct a working condition representation vector.

[0085] Normalization can be achieved through unlimited maximum and minimum value linear scaling, mean-variance standardization, or other data transformation methods to eliminate dimensional differences. The load condition representation vector can be an unlimited array of one-dimensional floating-point numbers containing multi-dimensional features or a state matrix. This step is performed to eliminate dimensional and order-of-magnitude differences between different real-time load parameters caused by their different physical meanings. This allows parameters to be compared and calculated on the same scale, improving the stability and accuracy of subsequent rule matching and reinforcement learning model state inputs, and reducing the probability of model output deviations due to excessively large parameter values.

[0086] Normalization can be achieved using a maximum-minimum scaling algorithm. The system pre-stores the historical maximum and minimum values ​​of various real-time load parameters in non-volatile memory during historical operation. After obtaining the real-time load parameters for the current cycle, the system sequentially iterates through the battery cell state change rate, throughput, command response latency, frame error ratio, and task queue depth, subtracting the corresponding historical minimum value from the current value of each parameter, and then dividing the difference by the difference between the historical maximum and the historical minimum. Through this linear transformation operation, the system uniformly maps all parameter values ​​to a continuous interval between zero and one. After processing, the system concatenates these mapped values ​​sequentially according to a predetermined feature dimension order to form a fixed-length one-dimensional array. This array serves as the constructed operating condition representation vector and is stored in the system's global state variables.

[0087] Normalization can also be achieved using a mean-variance standardization algorithm combined with a sliding window. The system maintains a fixed-length sliding data window in memory to store historical records of real-time load parameters from the most recent communication cycles. When new real-time load parameters arrive, the system adds them to the sliding window and removes the oldest set of data. Then, it calculates the current arithmetic mean and standard deviation of each parameter within the window. Next, the system subtracts the corresponding arithmetic mean from each acquired real-time load parameter and divides it by the corresponding standard deviation to obtain feature values ​​that conform to a standard normal distribution. To prevent extreme outliers from affecting subsequent calculations, the system also truncates the standardized values, forcibly limiting them to preset upper and lower limits. Finally, the system combines these processed feature values ​​into a multi-dimensional vector structure according to a specific dimensional order, thereby constructing a condition representation vector that accurately reflects the fluctuations in the current communication operating conditions.

[0088] S103. Match the working condition representation vector with the rule triggering conditions in the preset rule base to identify the local load surge state and determine the target rule, and use the parameter adjustment range corresponding to the target rule as the scheduling constraint.

[0089] The system matches the operating condition representation vector with the rule triggering conditions in the preset rule base to identify local load surge states and determine the target rule. The parameter adjustment range corresponding to the target rule is used as a scheduling constraint. Specifically, this includes: calculating the matching degree between the operating condition representation vector and the rule triggering conditions of each candidate rule in the preset rule base; determining the candidate rule with the highest matching degree as the target rule; when the target rule belongs to the preset real-time priority rule category, identifying the local load surge state based on the target rule; extracting the historical execution score associated with the target rule; calculating the boundary scaling factor based on the historical execution score; scaling the preset initial adjustment boundary of the target rule using the boundary scaling factor to obtain the target adjustment boundary; and using the target adjustment boundary as a scheduling constraint.

[0090] The preset rule base can be an unlimited lookup table, decision tree, or expert system rule set. Rule triggering conditions refer to the characteristic thresholds or logical combinations that must be met to activate a rule. Local load surge refers to a non-stationary operating condition where some nodes in the network experience a sudden surge in data volume due to a sudden event. Target rule refers to a specific rule selected after matching to guide the current scheduling. Parameter adjustment range can be an unlimited upper and lower limit of bandwidth allocation ratio or a priority adjustment range. Scheduling constraints refer to boundary conditions that restrict the space of subsequent actions. Matching degree refers to the similarity between the operating condition representation vector and the rule triggering condition. Candidate rules refer to all alternative rules in the preset rule base that participate in matching. The preset real-time priority rule category refers to a set of rules specifically set for urgent real-time tasks. Historical execution score refers to a quantitative evaluation of the degree to which a rule has improved system performance after being applied in the past. Boundary scaling factor refers to the product factor used to adjust the width of the preset initial adjustment boundary. The preset initial adjustment boundary originates from the physical limits of the system hardware or the factory default setting. The target adjustment boundary refers to the parameter limit range finally determined after scaling processing. The system performs this step to quickly identify extreme load spikes and impose safety restrictions before using complex models for scheduling. This ensures the system's basic communication capabilities and security under harsh operating conditions, improves the reliability of resource allocation, and reduces the risk of communication breakdowns caused by erroneous actions from purely data-driven models under unseen extreme conditions.

[0091] This refinement technique can be implemented based on cosine similarity calculation and linear mapping. The system traverses all candidate rules in the preset rule base and extracts the rule triggering condition vector corresponding to each candidate rule. The system uses the ratio formula of vector dot product and modulus product to calculate the cosine similarity between the working condition representation vector and each rule triggering condition vector, and uses it as the matching degree. The system sorts all matching degrees in descending order and selects the candidate rule with the largest cosine similarity value as the target rule. Subsequently, the system checks the attribute label of the target rule. If the label indicates that it belongs to the preset real-time priority rule category, the system sets the status register to determine and identify a local load surge state. Next, the system reads the communication latency improvement rate of the target rule after several past triggers from the preset rule base and uses it as the historical execution score. The system uses a monotonically increasing linear mapping function to map the historical execution score to a boundary scaling factor between 0.5 and 1. The system reads the preset initial adjustment boundary of the target rule, multiplies its upper and lower limits by the boundary scaling factor respectively to obtain the narrowed target adjustment boundary, and writes it into the scheduling constraint structure.

[0092] This refinement technique can also be implemented based on Euclidean distance metric and fuzzy logic inference. The system performs multi-dimensional spatial distance calculation between the working condition representation vector and the rule triggering conditions of each candidate rule in the preset rule base, calculates the Euclidean distance between the two, and uses the reciprocal of the Euclidean distance as the matching degree. The system compares all matching degree values ​​and determines the candidate rule with the largest reciprocal as the target rule. The system parses the category field of the target rule. If it matches the preset real-time priority rule category identifier, the system determines that the current network is in a state of local load surge. The system then queries the local database to obtain the reduction in frame error rate during the historical application of the target rule as a historical execution score. The system inputs this historical execution score into a pre-designed fuzzy inference engine. After fuzzification, fuzzy rule matching, and defuzzification processes, it outputs a smooth boundary scaling factor. The system uses this boundary scaling factor to proportionally compress the width of the preset initial adjustment boundary set by the target rule, obtains new upper and lower limits as the target adjustment boundary, and finally uses the target adjustment boundary as the scheduling constraint for subsequent reinforcement learning algorithms.

[0093] S104. Within the scheduling constraints, using the working condition representation vector as the state input, query the pre-trained converged Q-learning strategy table, output the action space consisting of bandwidth ratio, acquisition priority and upload frequency, and generate a basic resource allocation scheme.

[0094] Within scheduling constraints, the system takes the working condition representation vector as the state input, queries a pre-trained and converged Q-learning strategy table, and outputs an action space consisting of bandwidth ratio, acquisition priority, and upload frequency. This generates a basic resource allocation scheme. The Q-learning strategy table is pre-trained with the goal of minimizing communication latency. Specifically, it maps the working condition representation vector to the current discrete state. The action space consisting of bandwidth ratio, acquisition priority, and upload frequency is filtered according to scheduling constraints to obtain a safe action subspace. In the pre-trained and converged Q-learning strategy table, the Q-value of each candidate action in the safe action subspace corresponding to the current discrete state is queried. The candidate action with the largest Q-value is selected as the target action. Based on the bandwidth ratio, acquisition priority, and upload frequency included in the target action, a basic resource allocation scheme is generated.

[0095] State input refers to the current environmental characteristics passed to the decision model. The Q-learning strategy table can be an unrestricted state-action value matrix or a multi-dimensional mapping array. Bandwidth ratio refers to the proportion of transmission channel capacity allocated to different types of data. Acquisition priority refers to the order in which nodes at each level acquire bus usage rights. Upload frequency refers to the number of times a node actively reports data per unit time. Action space refers to the set of all possible scheduling parameter combinations. Basic resource allocation scheme refers to the macro-scheduling strategy initially output by the model. Current discrete state refers to the classification label obtained after quantizing the continuous working condition representation vector. Global action space refers to all parameter combinations without any constraint filtering. Safe action subspace refers to the set of legal combinations remaining after removing actions that violate scheduling constraints. Q-value refers to the expected long-term reward obtained by taking a specific action in a specific state. Candidate action refers to alternative parameter combinations within the safe action subspace. Target action refers to the optimal parameter combination with the maximum Q-value. The system performs this step to find the optimal macro-resource allocation in the current state using artificial intelligence algorithms, while ensuring safety boundaries. This allows the system to adaptively respond to dynamic load changes, improves the scientific and forward-looking nature of global resource allocation, and reduces overall communication latency. The Q-learning strategy table is able to achieve the corresponding function because it records the long-term expected reward that can be obtained by taking a specific action in a specific state through continuous trial and error in a complex environment. This allows the system to greedily select the optimal action that minimizes communication latency by looking up the table.

[0096] This refinement technique can be implemented using grid quantization and lookup table algorithms. First, the system uses a pre-defined grid partitioning algorithm to quantize each dimension of the continuous working condition representation vector with a fixed step size, mapping it to a multi-dimensional integer index, which represents the current discrete state. Next, based on the target adjustment boundary obtained in the previous steps as a scheduling constraint, the system traverses and checks the global action space containing all possible combinations of bandwidth ratios, acquisition priorities, and upload frequencies. The system eliminates all action combinations that exceed the target adjustment boundary limits, retaining the remaining action combinations to form a safe action subspace. Subsequently, the system uses the integer index of the current discrete state as the row address to address the pre-trained and converged Q-learning strategy table stored in flash memory, reading the Q-values ​​of each candidate action within the safe action subspace. The system finds the largest Q-value through comparison operations and identifies its corresponding candidate action as the target action. Finally, the system parses the encoding of the target action, extracting the specific bandwidth ratio, acquisition priority, and upload frequency values, and encapsulates them into a basic resource allocation scheme.

[0097] This refinement technique can also be implemented using clustering mapping and mask filtering mechanisms. The system inputs the working condition representation vector into a pre-trained K-means clustering model, calculates its distance to each cluster center, and assigns it to the nearest cluster. The cluster number is used as the current discrete state. The system generates a Boolean mask matrix with the same dimension as the global action space based on scheduling constraints. Actions that meet the constraints are set to true, and those that don't are set to false. The system uses this mask matrix to filter the global action space and extract the safe action subspace. The system uses the current discrete state number as a key and performs a fast lookup in a pre-trained, converged Q-learning strategy table based on a hash table to obtain a list of Q-values ​​for all available actions in that state. Combining the mask matrix, the system performs a maximum value operation only on the Q-values ​​corresponding to the safe action subspace, and selects the candidate action associated with the maximum Q-value as the target action. Based on the bandwidth ratio, acquisition priority, and upload frequency parameters defined in the target action, the system instantiates a data object for the basic resource allocation scheme.

[0098] S105. Calculate the delay deviation based on the target communication delay and the actual communication delay.

[0099] The target communication delay can be an unlimited system design expectation delay or an ideal delay benchmark dynamically generated based on the current operating mode. Delay deviation refers to the difference between the actual measured communication time and the expected ideal time. The target communication delay originates from the system's factory specifications or performance indicators issued by upper-level applications. This step is performed to quantify the gap between the current actual communication performance and the ideal state. This provides a precise error signal for subsequent closed-loop feedback control, improves the targeting of micro-adjustments, and reduces the blindness of system resource allocation.

[0100] This can be achieved through simple algebraic subtraction. The system reads a pre-set target communication delay constant from the configuration parameter area. This value represents the ideal communication time the system expects to achieve under the current network topology. Simultaneously, the system retrieves the actual communication delay of the previous communication cycle obtained in the initial steps from memory. Using the microprocessor's arithmetic logic unit, the system subtracts the target communication delay from the actual communication delay. If the actual communication delay is greater than the target communication delay, the resulting delay deviation is positive, indicating congestion or lag in current communication; if the actual communication delay is less than the target communication delay, the resulting delay deviation is negative, indicating smooth current communication and potential resource availability. The system stores the calculated signed delay deviation value in a dedicated error register for direct reading and use by subsequent compensation algorithms.

[0101] Alternatively, this can be achieved through difference calculation after moving average filtering. To avoid interference from accidental fluctuations in single communication delays, the system maintains a historical queue in memory containing the actual communication delays of the most recent communication cycles. The system first calculates the arithmetic mean of all actual communication delays in this historical queue, using this as the smoothed actual communication delay. Based on the current system operating mode, the system dynamically retrieves the corresponding target communication delay from a predefined lookup table. Next, the system performs a difference calculation between the smoothed actual communication delay and the dynamically retrieved target communication delay to obtain the delay deviation. The system performs dead-zone processing on the calculated delay deviation; that is, if the absolute value of the delay deviation is less than a very small tolerance threshold, the delay deviation is forcibly set to zero to prevent unnecessary frequent adjustments near the target value. Finally, the system outputs the processed delay deviation.

[0102] S106. Perform proportional-integral compensation based on delay deviation to obtain the continuous compensation amount for the bandwidth ratio parameter in the basic resource allocation scheme.

[0103] Proportional-integral (PI) compensation can be any classic PI control algorithm or an improved PI algorithm with anti-integral saturation. The continuous compensation quantity refers to the fine-tuning parameter with continuous numerical characteristics in the output. The bandwidth ratio parameter refers to the specific value used to control data flow allocation in the basic resource allocation scheme. The system performs this step to compensate for the steady-state error caused by the discrete actions output by the Q-learning strategy table. This achieves smooth and fine-tuning of the bandwidth ratio, improving the system's ability to eliminate communication delay deviations and reducing the risk of severe oscillations in communication delay around the target value.

[0104] This can be achieved using a positional proportional-integral (PI) control algorithm. The system pre-sets the proportional gain and integral gain coefficients in the control parameter library. The system reads the delay deviation calculated in the preceding steps, first multiplying it by the proportional gain coefficient to obtain the proportional control term. Simultaneously, the system maintains an error accumulation variable in memory, accumulating the current delay deviation into this variable, and then multiplying the accumulated total error by the integral gain coefficient to obtain the integral control term. To prevent integral saturation, the system limits the error accumulation variable, restricting its maximum and minimum values. Next, the system algebraically adds the proportional and integral control terms to calculate the total control output value. This control output value is stored in a floating-point variable as a continuous compensation for the bandwidth proportional parameter in the basic resource allocation scheme, for subsequent superposition operations.

[0105] Alternatively, an incremental proportional-integral (PI) control algorithm can be used. The system records the historical delay deviation from the last calculation in memory. Upon obtaining the current delay deviation, the system calculates the difference between the current and historical delay deviations. The system multiplies the current delay deviation by a preset integral coefficient to obtain the integral increment; it then multiplies the difference in delay deviations by a preset proportional coefficient to obtain the proportional increment. The system adds the integral and proportional increments to obtain the compensation increment for this calculation. The system maintains a current continuous compensation variable in memory, accumulating the calculated compensation increments to this variable to update the latest continuous compensation value. This incremental algorithm does not require accumulating all historical errors, has a smaller computational load, and does not cause significant control abrupt changes during abnormal system restarts. After calculation, the system outputs the continuous compensation value for fine-tuning of the bandwidth proportional parameter.

[0106] S107. The continuous compensation amount is superimposed on the bandwidth ratio parameter in the basic resource allocation scheme, while keeping the collection priority and upload frequency unchanged, to obtain a target resource allocation scheme that includes the target bandwidth ratio, target collection priority and target upload frequency.

[0107] The target bandwidth ratio refers to the final bandwidth allocation value determined after fine-tuning and compensation. The target acquisition priority refers to the final confirmed node acquisition order used for data transmission. The target upload frequency refers to the final confirmed data reporting frequency used for transmission. The target resource allocation scheme refers to the final execution strategy that integrates macroscopic discrete scheduling and microscopic continuous compensation. The system executes this step to effectively combine continuous fine-tuning with discrete macroscopic schemes. This improves the resolution and accuracy of bandwidth allocation while maintaining stable priority and frequency, and reduces system instability caused by simultaneous continuous control of multiple variables.

[0108] This can be achieved using floating-point addition and boundary clamping logic. The system extracts the discrete bandwidth ratio parameter output by the reinforcement learning model from the basic resource allocation scheme and reads the continuous compensation amount calculated in the previous step from memory. Using the processor's floating-point unit, the system directly adds the discrete bandwidth ratio parameter to the continuous compensation amount to obtain the preliminary target bandwidth ratio. Since the bandwidth ratio has strict physical meaning, the system then performs boundary clamping processing on the preliminary target bandwidth ratio, forcibly limiting it to the effective range of zero to 100%. After processing, the system directly copies the acquisition priority and upload frequency values ​​from the basic resource allocation scheme, using them as the target acquisition priority and target upload frequency, respectively. Finally, the system encapsulates these three processed and copied parameters into a new structure, forming the final target resource allocation scheme.

[0109] This can also be achieved using fixed-point conversion and parameter synthesis mechanisms. To accommodate microcontrollers lacking floating-point units, the system first converts the bandwidth ratio parameter and continuous compensation amount in the basic resource allocation scheme into high-precision fixed-point representations. The system executes a fixed-point addition instruction to combine the two, obtaining the target bandwidth ratio in fixed-point form. The system checks for overflow during the addition process; if overflow occurs, it saturates and limits the value to the maximum allowed fixed-point value. Subsequently, the system reverses the conversion back to a percentage format recognizable by the system. The system keeps the memory address pointers of the acquisition priority and upload frequency data blocks in the basic resource allocation scheme unchanged and directly links them to a new configuration object as the target acquisition priority and target upload frequency. The system also writes the converted target bandwidth ratio into this configuration object, thus synthesizing a complete target resource allocation scheme, ready for deployment.

[0110] S108. Update the local communication scheduling queue according to the target resource allocation scheme, and update the communication configuration parameters in the analog front-end registers at each level by issuing configuration frames level by level.

[0111] The local communication scheduling queue can be an unrestricted task execution linked list or a priority queue. The configuration frame can be an unrestricted data packet containing control instructions or a management message. Communication configuration parameters refer to the control words actually written to hardware registers to change communication behavior. The system performs this step to translate the calculated software scheduling policy into actual communication behavior at the hardware level. This ensures that all nodes on the daisy chain can synchronously update and execute the latest resource allocation policy, improving the execution efficiency of the scheduling scheme and reducing the probability of communication conflicts between master and slave nodes due to configuration asynchrony.

[0112] This can be achieved by updating the operating system's message queue and the underlying serial peripheral interface communication driver. First, the system recalculates the execution order and trigger cycle of each task to be sent in the local communication scheduling queue based on the target acquisition priority and target upload frequency in the target resource allocation scheme, and updates the local task queue using the operating system's queue management interface. Next, following the daisy-chain communication protocol, the system packages the target bandwidth ratio, target acquisition priority, and target upload frequency into a configuration frame of a specific format, and calculates a cyclic redundancy check (CRC) code to append to the frame end. The system then calls the underlying serial peripheral interface communication driver to send the configuration frame to the directly connected first-level analog front-end. The first-level analog front-end receives and parses the configuration frame, updates the communication configuration parameters in its internal registers, and then uses a hardware forwarding mechanism to pass the configuration frame through to the second-level analog front-end, and so on, achieving hierarchical distribution and updating.

[0113] This can also be achieved by reconstructing the polling schedule and direct memory access linked list transmission. The system parses the target resource allocation scheme and, based on the target upload frequency and target acquisition priority, reconstructs a global communication polling schedule in memory. This schedule defines the time slot allocation for each node in its local communication scheduling queue. The system then constructs a broadcast configuration frame containing complete communication configuration parameters and stores it in a pre-allocated contiguous memory space. The system configures the direct memory access controller in linked list mode, using the address of this contiguous memory space as the source address and the transmit data register of the communication peripheral as the destination address. After transmission is initiated, the direct memory access controller automatically pushes the configuration frame data continuously onto the daisy-chain bus. Upon detecting the broadcast configuration frame, the communication interface hardware at each level of the analog front-end synchronously captures the data within the frame and automatically writes parameters such as the target bandwidth ratio into the corresponding control registers using a hardware state machine, completing the configuration update for the entire link.

[0114] In the above embodiments, by acquiring multi-dimensional real-time load parameters and actual communication delays and performing normalization processing, the system can accurately characterize the current communication condition. The condition characterization vector is matched with a preset rule base to determine scheduling constraints, and within these constraints, a pre-trained Q-learning strategy table is used to output a basic resource allocation scheme. This allows the system to perform macro-level scheduling guided by minimizing communication delays while ensuring safety boundaries. Furthermore, proportional-integral compensation is performed based on the deviation between the target and the actual communication delay, and the continuous compensation amount is superimposed on the bandwidth ratio parameter. This achieves micro-level fine-tuning of the discrete action space, improving the resource allocation flexibility and response speed of the daisy-chain communication system under dynamic load changes, and reducing the overall communication delay under complex and variable conditions.

[0115] In the above embodiments, although adaptive allocation of global communication resources and macroscopic bandwidth adjustment are achieved through reinforcement learning and proportional-integral compensation, in actual daisy-chain communication, the asynchronous hardware clocks of nodes at each level may still cause instantaneous data congestion at local intermediate nodes. To further address this microscopic transmit / receive rate mismatch problem and prevent data frame loss due to insufficient processing by intermediate nodes, this application provides another adaptive scheduling method for BMS daisy-chain communication load, based on the above resource allocation scheme. The following is a combination of... Figure 2 Another adaptive scheduling method for BMS daisy-chain communication load in the embodiments of this application is described:

[0116] Please see Figure 2 This is another flowchart illustrating an adaptive scheduling method for BMS daisy chain communication load in an embodiment of this application.

[0117] S201. Obtain the forwarding queue overflow flag and local clock offset value in each level of analog front-end register;

[0118] The forwarding queue overflow flag can be a specific bit in an unrestricted hardware status register or a software buffer full indicator variable. The local clock offset value can be an unrestricted amount of crystal oscillator frequency drift or a relative offset of the timer count value. The system performs this step to monitor the micro-congestion status and clock synchronization of each underlying node in real time. This provides the underlying hardware basis for identifying local data accumulation and transmit / receive rate mismatch, improves the system's perception accuracy of micro-communication anomalies, and reduces the risk of large-scale data loss due to blind waiting.

[0119] This can be achieved through periodic broadcast polling and status frame parsing. The system master control unit sends broadcast data frames containing status query commands to the daisy-chain network according to a preset diagnostic cycle. Upon receiving the query command, each analog front-end at each level reads the overflow flag status of its own communication controller through internal hardware logic and calls its local clock management unit to obtain the current local clock deviation value. Each node packages this status data into a standard format response status frame and transmits it back to the system master control unit sequentially. After receiving all response status frames, the system master control unit extracts the corresponding flag bit and deviation value for each node through unpacking and verification operations, and updates it to the node status table in its local memory.

[0120] Alternatively, reporting can be achieved through a dedicated diagnostic channel driven by hardware interrupts. During the initialization phase, the system configures a low-bandwidth diagnostic channel for the daisy-chain network, independent of the main data stream. When the hardware monitoring circuit inside any analog front-end detects that its data buffer occupancy has reached its limit, triggering the physical setting of the forwarding queue overflow flag, or when its internal phase-locked loop detects that the local clock deviation exceeds the safety threshold, the node will immediately generate a high-priority hardware interrupt signal. The interrupt service routine of this node will proactively encapsulate the current flag status and deviation value into a miniature diagnostic message and send it asynchronously to the system master control unit through the dedicated diagnostic channel. By listening to this channel, the system master control unit can obtain the real-time status data of the abnormal node with extremely low latency.

[0121] S202. If it is determined that the forwarding queue overflow flag of the first analog front-end in the middle of the daisy chain is set, locate the second analog front-end that is downstream of the first analog front-end and is allocated the target bandwidth ratio.

[0122] The first simulated front-end refers to an intermediate data forwarding node in a daisy-chain topology, located between the master and end nodes, and currently experiencing data congestion. The second simulated front-end refers to a source node in the physical or logical connection, located after the congested node, and currently transmitting large amounts of data according to its allocated bandwidth. Setting a bit refers to the action of modifying a specific binary bit in a register to a valid state. A daisy-chain intermediate stage refers to a relay position in the network topology that needs to both transmit its own data and forward downstream data. The system performs this step to quickly pinpoint the data source causing the congestion upon detection. This clarifies the target of subsequent micro-adjustments, improves the targeting of intervention measures, and reduces interference with other normal communication nodes in the network.

[0123] This can be achieved through topology graph traversal based on node identities. The system maintains a static topology graph in memory that reflects the current physical connection order of the daisy chain. This graph records the identities of all nodes and their upstream and downstream connections. When the system detects that the forwarding queue overflow flag of a first simulated front-end is set, it extracts the identity of that node. Starting from this identity, the system performs a depth-first traversal in the static topology graph in the opposite direction of the data flow, scanning all downstream nodes. During the traversal, the system checks the current resource allocation parameters of each downstream node, searching for nodes allocated the target bandwidth percentage. Once a match is found, the system locks the identity of that node and identifies it as the second simulated front-end requiring rate adjustment.

[0124] Alternatively, this can be achieved through a reverse lookup using a dynamic routing table based on data flow direction. During operation, the system continuously records and updates a dynamic routing table. This table not only contains the physical connection order of nodes but also records the current data transmission rate and bandwidth usage of each node. When congestion is confirmed at the first simulated front-end, the system reads the header information of the data frame currently being processed by that node and extracts the source node address field. The system uses this source node address to perform a reverse lookup in the dynamic routing table to confirm whether the source node is downstream of the first simulated front-end. Subsequently, the system checks the bandwidth configuration status associated with the source node in the dynamic routing table. If it is currently executing a transmission task containing a target bandwidth ratio, the system identifies it as the second simulated front-end and extracts its network address for subsequent command issuance.

[0125] S203. Calculate the clock drift difference based on the local clock deviation value of the first analog front-end and the local clock deviation value of the second analog front-end.

[0126] Clock drift difference refers to the quantified value of the relative timing error generated by the local clocks of two different nodes within the same physical time period. The system performs this step to accurately assess the degree of mismatch in transmit and receive rates between upstream and downstream nodes due to differences in hardware crystal oscillators. This provides an accurate mathematical basis for subsequent calculations of the sleep time that needs to be compensated, improving the scientific rigor and accuracy of micro-rate adjustment and reducing communication link instability caused by over- or under-adjustment.

[0127] This can be achieved through direct algebraic subtraction of the absolute deviation values. The system reads the local clock deviation values ​​reported by the first and second analog front-ends from the node status table in memory. Both deviation values ​​are signed values ​​calculated based on the global reference clock of the system master node. The system uses the arithmetic logic unit of the central processing unit to directly subtract the local clock deviation value of the first analog front-end from the local clock deviation value of the second analog front-end. The system takes the absolute value of the subtraction result to eliminate directional interference caused by the sign, and uses this absolute value as the difference in relative clock drift between the two, storing it in a dedicated high-precision floating-point register for subsequent use by the sleep duration calculation module.

[0128] Alternatively, this can be achieved through moving average filtering and differential calculation of historical deviation data. To eliminate potential random noise interference during a single clock deviation sampling process, the system maintains a fixed-length historical deviation data queue for both the first and second analog front-ends. The system first calculates the arithmetic mean of all local clock deviation values ​​in these two queues, obtaining two smoothed expected local clock deviation values. Next, the system calculates the difference between these two expected values. To further improve accuracy, the system inputs this difference into a preset Kalman filter model for state estimation and noise filtering. The smooth and stable difference signal output after filter processing is identified by the system as the final clock drift difference and passed to the next stage of the calculation process.

[0129] S204. Calculate the inter-frame micro-sleep duration based on clock drift difference;

[0130] The system calculates the inter-frame micro-sleep duration based on the clock drift difference, specifically including: determining the basic sleep duration based on the clock drift difference; scanning the downstream communication links of the first analog front-end and counting the number of active downstream nodes currently in data transmission state; when the number of active downstream nodes is greater than 1, determining the convergence amplification factor based on the number of active downstream nodes, which is positively correlated with the number of active downstream nodes; using the convergence amplification factor to amplify and adjust the basic sleep duration to obtain the inter-frame micro-sleep duration; when the number of active downstream nodes is equal to 1, using the basic sleep duration as the inter-frame micro-sleep duration.

[0131] Inter-frame micro-sleep duration refers to the short pause time in microseconds or milliseconds that is forcibly inserted between two consecutively transmitted data packets. Base sleep duration refers to the initial pause baseline value calculated only considering the clock difference between the two nodes. Number of active downstream nodes refers to the total number of nodes currently transmitting data to the bus. Convergence amplification factor refers to the product factor used to compensate for the superimposed congestion effect caused by multiple data streams simultaneously converging into intermediate nodes. The system performs this step to comprehensively consider the hardware clock differences between nodes and the multi-data convergence effect caused by the network topology, dynamically calculating the most suitable transmission gap. This ensures that the transmission rate of downstream nodes perfectly matches the processing capacity of intermediate nodes, improving the smoothness of data flow and reducing the probability of buffer overflow in intermediate nodes.

[0132] This refinement technique can be implemented using a linear mapping and scaling algorithm. The system first inputs the calculated clock drift difference into a preset linear mapping function, multiplies it by a fixed time conversion constant, and calculates the base sleep duration. Next, the system reads the status register of the underlying communication controller, scans all physical links downstream of the first analog front-end, and counts the number of active downstream nodes with the transmit enable bit currently high. When the number of active downstream nodes is greater than one, the system subtracts one from this number, multiplies it by a preset congestion penalty ratio, and adds the base value of one to calculate a linearly increasing convergence amplification factor. The system uses a multiplier to multiply the base sleep duration by this convergence amplification factor to obtain the final inter-frame micro-sleep duration. If the number of active downstream nodes is equal to one, the system skips the amplification calculation and directly assigns the value of the base sleep duration to the inter-frame micro-sleep duration.

[0133] This refined technical solution can also be implemented using a lookup table method and an exponential compensation algorithm. The system pre-programs a lookup table mapping clock drift to sleep time into non-volatile memory. Using the clock drift difference as an index, the system performs interpolation addressing in the lookup table to obtain the corresponding basic sleep duration. Subsequently, the system sends a specific link listening command to the first analog front-end. The first analog front-end uses a hardware listening mechanism to count the number of downstream nodes transmitting carrier signals and sends this number back to the system. When the number of active downstream nodes is greater than one, the system calculates a non-linearly growing convergence amplification factor using the natural constant as the base and the number of active downstream nodes as the exponent through an exponential function. The system multiplies the basic sleep duration by this exponential convergence amplification factor to obtain the amplified and adjusted inter-frame micro-sleep duration. When the number of active downstream nodes is equal to one, the system does not perform exponential calculations and directly outputs the basic sleep duration obtained from the lookup table as the inter-frame micro-sleep duration.

[0134] S205. Generate a gap injection command that includes the duration of inter-frame micro-sleep;

[0135] The gap injection instruction can be an unrestricted control frame containing a specific opcode or a configuration message with a timestamp parameter. The system performs this step to convert the calculated abstract time value into a standard communication protocol format that the underlying hardware can recognize and execute. This ensures that the micro-adjustment intent can be accurately parsed by the target node, improving the success rate of system scheduling instruction execution and reducing communication anomalies caused by instruction format incompatibility.

[0136] This can be achieved by constructing a standard protocol control frame. The system allocates a contiguous buffer in memory for assembling the gap injection instruction. First, the system writes a specific control frame start symbol and opcode, as defined by the daisy-chain communication protocol, to the header of the buffer. This opcode is specifically used to instruct the receiver to modify the inter-frame transmission interval. Next, the system performs byte order conversion on the inter-frame micro-sleep duration calculated in the previous steps, converting it from the system host byte order to network byte order, and fills it into the data payload field of the instruction. Subsequently, the system uses a cyclic redundancy check (CRC) algorithm to perform polynomial calculations on the data in the entire buffer, generating a checksum which is appended to the end of the instruction. Finally, the system adds a frame end symbol to the end of the instruction, completing the entire gap injection instruction generation process.

[0137] This can also be achieved by modifying the extended header field of existing data frames. To save communication bandwidth, the system does not generate separate control frames, but instead utilizes the extended header mechanism reserved in the daisy-chain protocol. When preparing to send a regular configuration or acknowledgment data frame to the second analog front-end, the system sets the extended header enable flag of that data frame to active. The system performs bit-width compression on the calculated inter-frame micro-sleep duration, encodes it into a short-byte fine-tuning parameter, and embeds it at a specific offset address in the extended header of that data frame. The system updates the total length field of the data frame and recalculates the overall checksum, including the extended header. In this way, the system implicitly carries the gap injection instruction within the regular communication data, ready to be sent along with the data stream.

[0138] S206. Send the gap injection command to the second analog front end so that the second analog front end inserts an inter-frame micro-sleep duration between continuously transmitted data frames.

[0139] A data frame is a standard data packet containing actual business data or control information transmitted in a network. Insertion refers to the operation of forcibly adding an idle waiting period between normally continuous transmission actions. The system performs this step to actually apply the generated adjustment instructions to the target source node, forcing it to change its original high-speed continuous transmission behavior. This physically limits the burst of instantaneous data, improves the throughput stability of the entire daisy-chain network when facing sudden large traffic surges, and reduces the risk of global communication paralysis caused by local congestion.

[0140] This can be achieved by directly sending the high-priority data channel and intercepting it with a hardware timer. The system master control unit places the generated gap injection instruction into its local high-priority transmission queue, ensuring that it can preempt the current bus usage right and be sent first. This instruction is transmitted step by step along the daisy-chain physical link until it reaches the second analog front-end. After parsing the instruction, the communication interface hardware of the second analog front-end extracts the inter-frame micro-sleep duration. Before preparing to send the next data frame, the low-level driver of the second analog front-end will actively configure and start an internal high-precision hardware timer, and the timer's overflow time is set to the inter-frame micro-sleep duration. During the timer's operation, the hardware transmission logic is forcibly suspended and in a micro-sleep state until the timer overflows and generates an interrupt, at which point the hardware transmission logic is awakened and continues to send the next data frame.

[0141] This can also be achieved through out-of-band control bus transmission and a direct memory access controller (DMC) pause mechanism. In a daisy-chain system with a dual-bus architecture, the system master control unit sends gap injection commands directly to the second analog front-end via a dedicated out-of-band control bus for management and diagnostics, thus avoiding conflicts with congested data on the main data channel. Upon receiving the command, the out-of-band communication controller of the second analog front-end transmits the inter-frame micro-sleep duration parameter to the DMC of the main data channel. After completing the memory transfer and transmission of the current data frame, the DMC automatically triggers an internal delay wait state based on this parameter. During this wait state, the DMC pauses reading new data frames from memory, the bus remains idle, and the DMC automatically resumes operation after the delay wait state ends, thus achieving the purpose of inserting micro-sleep durations between consecutive data frames.

[0142] In the above embodiments, by acquiring the forwarding queue overflow flags of each level of the simulated front-end, the system can promptly detect the congestion status of intermediate nodes in the daisy chain. Upon confirming an overflow at an intermediate node, the system locates the downstream node allocated the target bandwidth proportion and calculates the clock drift difference based on their local clock deviation values. This accurately quantifies the degree of transmit / receive rate mismatch caused by clock asynchrony between upstream and downstream nodes. Based on this clock drift difference, the system calculates the inter-frame micro-sleep duration and generates a gap injection command, which is then sent to downstream nodes. This prompts downstream nodes to insert sleep gaps between continuously transmitted data frames, proactively reducing the instantaneous data transmission rate, improving the data flow matching degree between adjacent nodes, and reducing the forwarding queue overflow rate and data frame loss rate caused by insufficient processing by intermediate nodes.

[0143] In the above embodiments, injecting inter-frame micro-sleep time into the target node effectively alleviates the queue overflow and congestion problems of intermediate nodes. However, the introduction of sleep gaps inevitably increases the overall transmission time of the current node within a single scheduling cycle. To prevent the original periodic scheduling constraints (i.e., the available time allocated in the first embodiment) from being broken due to excessively long accumulated sleep time, thereby causing communication cycle timeouts, this application further provides another adaptive scheduling method for BMS daisy-chain communication load. The following is combined with... Figure 3 This application describes yet another adaptive scheduling method for BMS daisy chain communication load in its embodiments:

[0144] Please see Figure 3 This is another flowchart illustrating an adaptive scheduling method for BMS daisy-chain communication load in an embodiment of this application.

[0145] S301. Obtain the total number of data frames to be sent by the second analog front-end in the current scheduling period;

[0146] The current scheduling period can be an unlimited fixed time window or a dynamically allocated polling interval. The total number of data frames to be sent can be an unlimited number of data packets queued in the buffer or the total number of service messages to be generated. The system performs this step to accurately determine the communication load baseline of the source node within the current period, thereby providing the most basic data support for subsequent time cost assessment. This clarifies the original sending needs of the node before intervention, improves the accuracy of subsequent time assessment, and reduces resource allocation errors caused by missing basic data.

[0147] This can be achieved by reading the counter register of the hardware transmit queue. The system master control unit sends a specific register read instruction to the second analog front-end via the underlying serial communication bus. This instruction points to the transmit queue status register area in the communication controller inside the second analog front-end. Upon receiving the instruction, the hardware logic of the second analog front-end directly reads the count value of the currently valid data block in its hardware first-in-first-out buffer. This count value is automatically maintained by the hardware, incrementing by one each time a new data frame enters the queue and decrementing by one after successful transmission. The second analog front-end packages the accurate count value into an acknowledgment frame and returns it to the system master control unit. The system master control unit parses the acknowledgment frame, extracts the count value, and uses it as the total number of data frames to be transmitted by the second analog front-end in the current scheduling cycle, storing it in the node status structure in local memory for later use.

[0148] Alternatively, this can be achieved through task list traversal using a software protocol stack. In scenarios where the second simulated front-end uses a software protocol stack to manage communication tasks, the system's main control unit sends a status query message, triggering a software interrupt in the second simulated front-end. In the interrupt service routine, the microprocessor of the second simulated front-end obtains the head pointer of the current task list to be sent. Subsequently, the microprocessor uses a local accumulator variable to traverse each task node in the list, starting from the head pointer, until it encounters a null pointer representing the end of the list. During the traversal, the accumulator variable is incremented by one each time a node representing a valid data frame is passed. After the traversal is complete, the second simulated front-end uses the final value of the accumulator variable as the total number of data frames to be sent and sends it to the system through a dedicated status reporting channel. Upon receiving the data, the system updates the global scheduling variable library.

[0149] S302. The product of the total number of data frames to be sent and the inter-frame micro-sleep time is used as the periodic cumulative sleep time.

[0150] The cumulative sleep time over a period can be the sum of all additional pause times within a single period or the overall increase in latency. The system performs this step to quantify the additional time overhead incurred throughout the scheduling cycle after the introduction of the micro-sleep mechanism. This integrates the small gaps scattered between data frames into a macroscopic time evaluation metric, improving the completeness of the time consumption model and reducing the risk of periodic timeouts due to ignoring the cumulative effect of sleep gaps.

[0151] This can be achieved directly using the microprocessor's hardware multiplier. The system reads the total number of data frames to be sent obtained from the previous steps and the calculated inter-frame micro-sleep duration from a specified memory address. To ensure calculation accuracy, the system converts the total number of data frames to be sent into a high-precision unsigned integer format and the inter-frame micro-sleep duration into a numerical format of the same precision. Subsequently, the system sends these two operands to the arithmetic logic unit of the central processing unit and calls the hardware multiplication instruction to perform the multiplication operation. During the operation, the system hardware automatically checks whether the multiplication result has overflowed. If there is no overflow, the calculated product is directly output, and the system stores this product as the periodic accumulated sleep time in a dedicated global time overhead register.

[0152] Alternatively, software-level accumulation loop logic can be used. In some low-cost microcontrollers lacking high-performance hardware multipliers, the system uses a software loop instead of direct multiplication. The system initializes an accumulation variable with an initial value of zero in memory to store the cycle-accumulated sleep time. Then, the system constructs a decreasing loop structure using the total number of data frames to be sent as the loop control variable. In each loop iteration, the system adds the value of the inter-frame micro-sleep time to the accumulation variable and decrements the loop control variable by one. When the loop control variable decrements to zero, the loop ends, and the value stored in the accumulation variable is the equivalent product of the total number of data frames to be sent and the inter-frame micro-sleep time. The system extracts the value of the accumulation variable, formally confirms it as the cycle-accumulated sleep time, and writes it into the system's scheduling parameter table.

[0153] S303. Obtain the total duration of the current scheduling cycle, and calculate the available duration of the second simulated front end based on the total duration and the target bandwidth ratio in the target resource allocation scheme.

[0154] The total duration can be either a system-defined macro-cycle time for communication or a dynamically calculated maximum allowed communication window. The allocated available duration can be either an unlimited upper limit on the bus time authorized for a node or the theoretical maximum transmission time. The system performs this step to set a strict time boundary for the transmission actions of a specific node within the current cycle, based on the macro-level resource allocation strategy. This transforms the abstract concept of bandwidth ratio into a concrete time constraint, improving the rigor of cycle management and reducing the probability of a single node over-occupying the bus, causing communication disruptions for other nodes.

[0155] This can be achieved by reading the system configuration table and combining it with floating-point multiplication. The system first accesses the global system configuration table stored in non-volatile memory and reads the current system-set total communication scheduling cycle duration constant. Next, the system retrieves the target resource allocation scheme generated in the first embodiment from memory and extracts the target bandwidth ratio allocated to the second analog front-end. The system calls the microprocessor's floating-point unit to convert the total duration into a floating-point number and multiplies it by the floating-point value of the target bandwidth ratio. To accommodate the integer counting characteristics of the underlying hardware timer, the system performs a floor operation on the result of the multiplication, discarding the decimal part, and uses the resulting integer value as the allocated available duration for the second analog front-end, storing it in the node's dedicated time quota register.

[0156] This can also be achieved through timer interrupt cycle parameters and fixed-point scaling. The system reads the value of the auto-reload register of the hardware timer responsible for triggering the current scheduling cycle. This value represents the number of clock ticks corresponding to the total duration of the current scheduling cycle. The system obtains the numerator and denominator values ​​of the target bandwidth ratio and uses high-precision fixed-point arithmetic logic. First, it multiplies the total duration of clock ticks by the numerator of the target bandwidth ratio. After the multiplication, the system divides the resulting large integer result by the denominator of the target bandwidth ratio. Through this fixed-point scaling calculation of multiplication followed by division, the system avoids the additional overhead of floating-point operations. The calculated quotient is the number of clock ticks allowed for the second analog front-end, which the system uses as the allocated available time and updates to the local scheduling constraint variable library.

[0157] S304. Obtain the original transmission time of the total number of data frames to be sent continuously by the second analog front end;

[0158] The raw transmission time can be the theoretical time required to send all data under ideal, sleep-free conditions, or the pure data transmission time calculated based on the current baud rate. The system performs this step to assess the pure physical time required to send all data under ideal conditions without any intervention. This provides a baseline reference value for calculating the final total time overhead, improving the accuracy of the overall time assessment and reducing calculation bias caused by ignoring the length of the data itself.

[0159] This can be calculated based on the theoretical formulas for communication baud rate and total data volume. The system first reads the byte length of all data frames in the second analog front-end's transmit queue, sums these byte lengths, multiplies them by the number of bits per byte, and adds the fixed overhead bits (frame header, frame trailer, and parity bits) specified by the communication protocol to calculate the total number of bits to be transmitted. Next, the system reads the currently set communication baud rate from the configuration register of the underlying communication controller. The system uses division to divide the total number of bits to be transmitted by the communication baud rate, obtaining the pure data transmission time. Subsequently, the system adds a preset physical layer transceiver fixed delay constant, and stores the final sum as the raw transmission time for the second analog front-end to continuously transmit the total number of data frames to be transmitted, in memory for later use.

[0160] Alternatively, estimation can be achieved through lookup and interpolation based on historical transmission records. The system maintains a dynamically updated historical transmission time mapping table in memory, which records the actual pure transmission time corresponding to different numbers of data frames over several past periods. Once the total number of data frames to be transmitted is obtained, the system uses this as an index to search the historical transmission time mapping table. If a matching record exists in the table, the system directly extracts the corresponding historical time as the original transmission time. If no matching record exists, the system finds the two historical records closest to the current frame number, uses a linear interpolation algorithm, and calculates the estimated time corresponding to the total number of data frames to be transmitted based on the frame number and time at these two records. This estimated time is then output as the original transmission time to the calculation module.

[0161] S305. The sum of the original transmission time and the periodic cumulative sleep time is used as the total time after compensation.

[0162] The total time after compensation can be unlimited, including the actual expected time occupied by pure data transmission and all sleep intervals, or the combined time overhead. The system performs this step to obtain the true expected time occupied after the micro-sleep mechanism is superimposed. This comprehensively reflects the actual bus resources required by the node in the current cycle, improves the reliability of scheduling evaluation, and reduces the risk of scheduling failure and network crashes due to underestimating the actual time.

[0163] This can be achieved by directly summing the values ​​using the addition instruction of the arithmetic logic unit (ALU). After completing the preliminary time calculations, the system loads the original transfer time value stored at a specific memory address into the first general-purpose data register of the CPU. Simultaneously, the system loads the cumulative sleep time value stored at another memory address into the second general-purpose data register. The system then calls the CPU's ALU to execute an unsigned integer addition instruction, directly adding the values ​​in these two registers. After the addition is complete, the system checks the carry flag in the status register to ensure no data overflow has occurred. The calculated sum is then written into a third general-purpose register, which is used as the compensated total time for subsequent comparison logic.

[0164] Alternatively, this can be achieved by merging variables in memory using a timestamp accumulator. The system defines an unsigned long integer variable with sufficient bit width in the global data area specifically for storing the final time overhead. The system first calls the memory read function to obtain the original transmission time value and assigns it to this unsigned long integer variable. Next, the system calls the memory read function again to obtain the cumulative sleep time value. Using a software-level compound assignment addition operator, the system adds the read cumulative sleep time value to the unsigned long integer variable. Through this memory variable merging operation, the system performs the superposition of the two time consumption indicators at the software level. The final value stored in this variable serves as the compensated total time and is passed to the next step's judgment module.

[0165] S306. If the total time consumed after compensation is greater than the allocated available time, calculate the difference between the total time consumed after compensation and the allocated available time to obtain the overflow time.

[0166] Overflow duration can be any unauthorized time exceeding the specified time window or the amount of time that needs to be reduced. The system performs this step to precisely quantify the specific time exceeding the allocated limit when the total time consumption is confirmed to be excessive. This provides a direct mathematical basis for subsequent data frame truncation operations, improving the accuracy of the truncation operation and reducing the risk of disrupting normal communication due to indiscriminate data discarding.

[0167] This can be achieved by combining a hardware comparator with a subtraction circuit. The system sends the compensated total time, calculated in the preprocessing steps, to the non-inverting input of the hardware comparator, and the allocated available time to the inverting input. The comparator compares these two values ​​in real time. When the value at the non-inverting input is greater than the value at the inverting input, the comparator outputs a high-level signal. This high-level signal triggers the subsequent hardware subtraction circuit. In the enabled state, the subtraction circuit automatically subtracts the allocated available time from the compensated total time and outputs the difference through the data bus. The system captures this difference and stores it as an overflow duration in a dedicated overflow status register for later reading by the subsequent frame rate conversion module.

[0168] This can also be achieved using software conditional statements and difference calculation functions. In the main control flow of the scheduling algorithm, the system incorporates conditional branching logic. The system first reads the total time elapsed after compensation and the allocated available time from memory, and compares their values ​​using a greater-than relational operator. If the conditional statement is true, meaning the total time elapsed after compensation is indeed greater than the allocated available time, the system enters the corresponding processing branch and calls the pre-written difference calculation function. This function performs a simple algebraic subtraction, subtracting the allocated available time from the total time elapsed after compensation, and returns the result. The system assigns this return result to a global variable named "overflow time". If the conditional statement is false, the system skips the difference calculation branch and forcibly clears the "overflow time" variable to zero, indicating that no time reduction is needed for the current cycle.

[0169] S307. Calculate the number of target frames that need to be truncated based on the overflow duration and the transmission time of a single frame.

[0170] The transmission time for a single frame can be an unlimited fixed time or average time required to send a standard data packet. The target frame count can be an unlimited number of data packets to be removed from the transmission queue or a stripping metric. The system performs this step to convert the abstract time overflow into a specific number of data frames to be removed. This bridges the gap between time constraints and packet management, improving the operability of the truncation strategy and reducing the complexity of actual queue management.

[0171] This can be achieved using a division operation logic with rounding up. The system first reads the preset single-frame transmission time constant from the configuration library. This constant represents the average time required to send a standard-length data frame under the current network environment. The system uses the overflow time calculated in the previous step as the dividend and the single-frame transmission time as the divisor, and sends them to the division unit of the microprocessor. The system performs the division operation to obtain a quotient and a remainder. To ensure that the excluded data frames completely cover the overflow time, the system adds rounding up logic at the software level: if the remainder generated by the division operation is greater than zero, the system increments the quotient by one; if the remainder is equal to zero, the quotient remains unchanged. Finally, the rounded value is determined by the system as the number of target frames to be truncated and stored in a dedicated control variable.

[0172] Alternatively, a loop-based subtraction and counter accumulation logic can be used. In the absence of a hardware divider, the system initializes a rejection counter with an initial value of zero in memory. The system loads the overflow duration into a temporary working variable. Then, the system enters a conditional loop structure, where the loop continues only if the value of the working variable is greater than zero. In each loop iteration, the system subtracts the single-frame transmission time from the working variable and simultaneously increments the rejection counter. Through continuous loop subtraction, the value of the working variable gradually decreases until it is less than or equal to zero, at which point the loop terminates. At this point, the accumulated value in the rejection counter represents the minimum number of data frames required to cover the overflow duration. The system extracts the final value of the rejection counter, uses it as the target frame count, and passes it to the subsequent queue stripping module.

[0173] S308. Remove low-priority data frames equal to the number of target frames from the pending task queue of the second analog front-end, so as to limit the actual transmission time of the second analog front-end to within the allocated available time.

[0174] The system extracts a number of low-priority data frames equal to the number of target frames from the task queue to be sent in the second analog front-end, so as to limit the actual transmission time of the second analog front-end to within the allocated available time. Specifically, this includes: traversing the task queue to be sent and extracting candidate data frames with preset low-priority tags; obtaining the queuing waiting time of the candidate data frames in the task queue to be sent; sorting the candidate data frames in ascending order according to the queuing waiting time from shortest to longest to obtain a candidate extraction sequence; starting from the head of the candidate extraction sequence, extracting a number of candidate data frames equal to the number of target frames as the target extraction frames; and removing the target extraction frames from the task queue to be sent, so as to limit the actual transmission time of the second analog front-end to within the allocated available time.

[0175] The task queue to be sent can be an unrestricted first-in-first-out buffer or a priority-based linked list structure. The preset low-priority label can be an unrestricted non-real-time data identifier or a normal status reporting marker. Candidate data frames can be unrestricted alternative data packets that meet the initial screening criteria. The queuing time can be an unrestricted time for data frames to reside in the buffer or the difference between the generated timestamp and the current time. The candidate stripping sequence can be an unrestricted list of data packets to be deleted, sorted according to specific rules. The target stripping frame can be an unrestricted data packet that is ultimately selected for deletion. The actual transmission time can be an unrestricted bus time occupied after truncation. The system performs this step to prioritize the retention of important data with long waiting times and discard less important and newly generated data, while meeting strict time constraints. This ensures the continuity of core business operations, improves the retention rate of high-value data, and reduces the negative impact of data loss on overall system performance.

[0176] This refined technical solution can be implemented based on doubly linked list operations and the bubble sort algorithm. The system traverses the queue of tasks to be sent, composed of a doubly linked list, reads the priority field from the data structure of each node, and extracts nodes with preset low-priority labels as candidate data frames. The system reads the generation timestamps of these candidate data frames, subtracts the generation timestamps from the current system time, and calculates their respective queuing wait times. Next, the system stores pointers to these candidate data frames in a temporary array and uses the bubble sort algorithm, with the queuing wait time as the comparison key, to sort the pointers in the array in ascending order, generating a candidate stripping sequence with queuing wait times from shortest to longest. Subsequently, starting from the head of this sequence, the system extracts the same number of node pointers as the number of target frames through a loop operation; these pointers point to the target stripped frames. Finally, the system uses the node deletion logic of the doubly linked list to modify the pointers of the nodes before and after the target stripped frame, physically disconnecting them from the queue of tasks to be sent and releasing the corresponding memory, thereby limiting the actual transmission time to within the allocated available time.

[0177] This refined technical solution can also be implemented based on array index mapping and the quicksort algorithm. In the task queue to be sent, implemented using a circular array, the system uses bitmasking operations to scan the control words of all valid elements, filtering out array indices that match preset low-priority labels, and using the corresponding elements as candidate data frames. The system calls the operating system's tick timer interface to obtain the tick count when each candidate data frame is enqueued, and calculates the queuing waiting time by subtracting it from the current tick count. The system constructs a mapping structure array containing indices and waiting times, and uses the quicksort algorithm to sort this structure array in ascending order according to the waiting time, obtaining a candidate stripping sequence. Based on the number of target frames, the system extracts a corresponding number of structure elements from the head of the sorted sequence, extracting their corresponding array indices; the data frames pointed to by these indices are the target stripping frames. The system performs a logical removal operation by invalidating the valid flags at these index positions in the circular array, ensuring that the actual transmission time of the second analog front-end is strictly limited within the allocated available time.

[0178] In the above embodiments, the cumulative sleep time of the cycle is obtained by multiplying the total number of data frames to be sent by the inter-frame micro-sleep duration, and then added to the original transmission time to obtain the compensated total time. The system can accurately evaluate the overall time overhead after injecting the micro-sleep mechanism. The allocated available time of the second simulated front end is calculated by combining the current total scheduling cycle duration with the target bandwidth ratio, setting a strict time boundary for the transmission action of this node. When the compensated total time is greater than the allocated available time, the overflow time is obtained by calculating the difference between the two, and based on this, the number of target frames to be truncated is calculated in combination with the single frame transmission time. Then, the corresponding number of low-priority data frames are stripped from the task queue to be sent, ensuring that the actual transmission time of the node after increasing the sleep gap can still be strictly limited within the allocated quota, improving the execution accuracy of communication resource scheduling within a single cycle, and reducing the risk of scheduling cycle timeout caused by the introduction of the micro-sleep mechanism.

[0179] The system in the embodiments of this invention is described below from the perspective of hardware processing. Please refer to [link / reference needed]. Figure 4 This is a schematic diagram of the physical device structure of an adaptive scheduling system for BMS daisy-chain communication load provided in an embodiment of this application.

[0180] It should be noted that, Figure 4 The structure of the system shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of the present invention.

[0181] like Figure 4 As shown, the system includes a Central Processing Unit (CPU) 401, which can perform various appropriate actions and processes based on a program stored in Read-Only Memory (ROM) 402 or a program loaded from storage portion 408 into Random Access Memory (RAM) 403, such as executing the methods described in the above embodiments. The RAM 403 also stores various programs and data required for system operation. The CPU 401, ROM 402, and RAM 403 are interconnected via a bus 404. An Input / Output (I / O) interface 405 is also connected to the bus 404.

[0182] The following components are connected to I / O interface 405: input section 406 including a camera, infrared sensor, etc.; output section 407 including a liquid crystal display (LCD) and speakers, etc.; storage section 408 including a hard disk, etc.; and communication section 409 including a network interface card such as a LAN (Local Area Network) card and a modem, etc. Communication section 409 performs communication processing via a network such as the Internet. Drive 410 is also connected to I / O interface 405 as needed. Removable media 411, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., are installed on drive 410 as needed so that computer programs read from it can be installed into storage section 408 as needed.

[0183] In particular, according to embodiments of the present invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of the present invention include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing computer programs for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication section 409, and / or installed from removable medium 411. When the computer program is executed by central processing unit (CPU) 401, it performs the various functions defined in the present invention.

[0184] It should be noted that the computer-readable medium shown in the embodiments of the present invention can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, optical fiber, portable compact disc read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In the present invention, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In the present invention, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, wherein a computer-readable computer program is carried. The transmitted data signal can take many forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof.

[0185] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. Each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0186] In another aspect, the present invention also provides a computer-readable storage medium, which may be included in the system described in the above embodiments; or it may exist independently and not assembled into the system. The storage medium carries one or more computer programs that, when executed by a processor of a system, cause the system to implement the methods provided in the above embodiments.

[0187] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

[0188] As used in the above embodiments, depending on the context, the term "when..." can be interpreted as "if...", "after...", "in response to determining...", or "in response to detecting...". Similarly, depending on the context, the phrase "when determining..." or "if (the stated condition or event) is interpreted as "if determining...", "in response to determining...", "when (the stated condition or event) is detected", or "in response to detecting (the stated condition or event)".

[0189] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive), etc.

[0190] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. This program can be stored in a computer-readable storage medium, and when executed, it can include the processes described in the above method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as ROM or random access memory (RAM), magnetic disks, or optical disks.

Claims

1. An adaptive scheduling method for BMS daisy-chain communication load, characterized in that, include: In response to a timer interrupt, the actual communication delay of the previous communication cycle is obtained, and the real-time load parameters in the analog front-end registers at each level are read. The real-time load parameters include the battery cell state change rate, throughput, instruction response delay, frame error ratio, and queue depth of tasks to be executed. The real-time load parameters are normalized to construct a working condition representation vector. The operating condition representation vector is matched with the rule triggering conditions in the preset rule base to identify local load surge states and determine target rules. The parameter adjustment range corresponding to the target rule is used as a scheduling constraint. Within the scheduling constraints, the working condition representation vector is used as the state input. The pre-trained and converged Q-learning strategy table is queried, and the action space consisting of bandwidth ratio, acquisition priority and upload frequency is output to generate a basic resource allocation scheme. The Q-learning strategy table is pre-trained with the goal of minimizing communication latency as the reward. Calculate the delay deviation based on the target communication delay and the actual communication delay; Proportional-integral compensation is performed based on the delay deviation to obtain a continuous compensation amount for the bandwidth ratio parameter in the basic resource allocation scheme. The continuous compensation amount is superimposed on the bandwidth ratio parameter in the basic resource allocation scheme, while keeping the acquisition priority and upload frequency unchanged, to obtain a target resource allocation scheme that includes the target bandwidth ratio, the target acquisition priority, and the target upload frequency. The local communication scheduling queue is updated according to the target resource allocation scheme, and the communication configuration parameters in the analog front-end registers at each level are updated by issuing configuration frames level by level.

2. The method according to claim 1, characterized in that, The step of matching the operating condition representation vector with the rule triggering conditions in the preset rule base to identify local load surge states and determine target rules, and using the parameter adjustment range corresponding to the target rules as scheduling constraints, specifically includes: Calculate the matching degree between the working condition representation vector and the rule triggering conditions of each candidate rule in the preset rule base; The candidate rule with the highest matching degree is determined as the target rule; When the target rule belongs to the preset real-time priority rule category, the local load surge state is identified according to the target rule. Extract the historical execution scores associated with the target rule; Calculate the boundary scaling factor based on the historical execution score; The target adjustment boundary is obtained by scaling the preset initial adjustment boundary of the target rule using the boundary scaling factor. The target adjustment boundary is used as a scheduling constraint.

3. The method according to claim 1, characterized in that, Within the scheduling constraints, using the working condition representation vector as the state input, a pre-trained and converged Q-learning strategy table is queried, and an action space consisting of bandwidth ratio, acquisition priority, and upload frequency is output to generate a basic resource allocation scheme, specifically including: Map the operating condition representation vector to the current discrete state; The action space consisting of the bandwidth ratio, the acquisition priority, and the upload frequency is filtered according to the scheduling constraints to obtain a safe action subspace. In the pre-trained and converged Q-learning policy table, query the Q-value of each candidate action in the safety action subspace corresponding to the current discrete state; The candidate action with the largest Q value is selected as the target action. A basic resource allocation scheme is generated based on the bandwidth ratio, acquisition priority, and upload frequency included in the target action.

4. The method according to claim 1, characterized in that, After updating the local communication scheduling queue according to the target resource allocation scheme and updating the communication configuration parameters in the analog front-end registers at each level by issuing configuration frames step by step, the method further includes: Obtain the forwarding queue overflow flag and local clock offset value from the analog front-end registers at each level; If it is determined that the forwarding queue overflow flag of the first analog front-end in the middle of the daisy chain is set, locate the second analog front-end that is downstream of the first analog front-end and is allocated the target bandwidth ratio. The clock drift difference is calculated based on the local clock deviation value of the first analog front-end and the local clock deviation value of the second analog front-end. Calculate the inter-frame micro-sleep duration based on the clock drift difference; Generate a gap injection command that includes the inter-frame micro-sleep duration; The gap injection command is sent to the second analog front end so that the second analog front end inserts the inter-frame micro-sleep duration between continuously transmitted data frames.

5. The method according to claim 4, characterized in that, The calculation of inter-frame micro-sleep duration based on the clock drift difference specifically includes: The base sleep duration is determined based on the clock drift difference. Scan the downstream communication links of the first simulated front end and count the number of active downstream nodes currently in the data transmission state; When the number of active downstream nodes is greater than 1, the convergence amplification factor is determined based on the number of active downstream nodes, and the convergence amplification factor is positively correlated with the number of active downstream nodes. The basic sleep duration is amplified and adjusted using the convergence amplification factor to obtain the inter-frame micro-sleep duration; When the number of active downstream nodes is equal to 1, the basic sleep duration is used as the inter-frame micro-sleep duration.

6. The method according to claim 4, characterized in that, After issuing the gap injection command to the second analog front-end to cause the second analog front-end to insert the inter-frame micro-sleep duration between consecutively transmitted data frames, the method further includes: Obtain the total number of data frames to be sent by the second simulated front-end in the current scheduling period; The product of the total number of data frames to be sent and the inter-frame micro-sleep time is used as the periodic cumulative sleep time. Obtain the total duration of the current scheduling cycle, and calculate the available allocation duration of the second simulated front end based on the total duration and the target bandwidth ratio in the target resource allocation scheme; Obtain the original transmission time of the total number of data frames to be sent continuously by the second simulated front end; The sum of the original transmission time and the cumulative sleep time of the period is used as the total time after compensation. If the total time consumed after compensation is greater than the allocated available time, the difference between the total time consumed after compensation and the allocated available time is calculated to obtain the overflow time. Calculate the number of target frames that need to be truncated based on the overflow duration and the transmission time of a single frame; Low-priority data frames, equal in number to the target frames, are stripped from the pending task queue of the second simulated front end to limit the actual transmission time of the second simulated front end to the allocated available time.

7. The method according to claim 6, characterized in that, The step of stripping low-priority data frames, equal in number to the target frames, from the pending task queue of the second simulated front-end to limit the actual transmission time of the second simulated front-end within the allocated available time period specifically includes: Traverse the queue of tasks to be sent and extract candidate data frames with preset low-priority tags; Obtain the queuing time of the candidate data frame in the queue of tasks to be sent; The candidate data frames are sorted in ascending order according to the queuing waiting time from shortest to longest to obtain a candidate stripping sequence; Starting from the head of the candidate stripping sequence, extract the same number of candidate data frames as the target frames, and use them as the target stripping frames; The target stripping frame is removed from the task queue to limit the actual transmission time of the second simulated front end to the allocated available time.

8. An adaptive scheduling system for BMS daisy-chain communication load, characterized in that, The system includes: One or more processors and a memory; the memory is coupled to the one or more processors, the memory being used to store computer program code, the computer program code including computer instructions, the one or more processors invoking the computer instructions to cause the system to perform the method as described in any one of claims 1-7.

9. A computer-readable storage medium comprising instructions, characterized in that, When the instructions are executed on the system, the system performs the method as described in any one of claims 1-7.

10. A computer program product, characterized in that, When the computer program product is run on the system, the system performs the method as described in any one of claims 1-7.

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