A switch function verification method, device and equipment and a readable storage medium

Abstract

The application discloses a switch function verification method, device and equipment and a readable storage medium, and comprises the following steps: obtaining message processing flow information of a switch to be verified; determining required processing stage modules from preset multiple processing stage modules according to the message processing flow; connecting the processing stage modules in sequence to obtain a data processing link through a general data bus according to a message processing sequence; connecting each processing stage module to a table item information pool to obtain a table item query and modification link through a general query bus; connecting each processing stage module to a statistical information pool to obtain a statistical record link through a general statistical bus; and constructing a reference model suitable for the switch to be verified based on the three links, wherein the three buses are independent of each other and bear a message data stream, a table item query stream and a statistical record stream respectively. The application improves the efficiency and reliability of switch function verification.

Description

Technical Field

[0001] This application relates to the field of chip verification technology, and in particular to a method, apparatus, device and readable storage medium for verifying the function of a switch. Background Technology

[0002] As switch chips become increasingly complex, simulation verification based on the Universal Verification Methodology (UVM) has become an indispensable step before chip tape-out. The verification process requires building a reference model to provide expected outputs and comparing them with the actual outputs of the Design Under Test (DUT). However, current switch reference models lack a unified architectural standard. Functions such as packet parsing, table lookup, modification, and forwarding are typically coupled as functions or tasks within the processing flow of a single component. This intertwining of data flow and function calls results in poor scalability and maintainability of the reference model. Adding new functions or adjusting the processing order often necessitates redesigning the processing flow. Furthermore, when verifying different switch models, there is a lack of reusability, requiring the reference model to be built from scratch.

[0003] In summary, how to effectively address the problems of poor scalability and maintainability of the reference models used in current switch function verification methods, as well as the lack of a reuse basis, is an urgent issue that needs to be resolved by those skilled in the art. Summary of the Invention

[0004] The purpose of this application is to provide a method for verifying the function of a switch, which improves the efficiency and reliability of the verification. Another purpose of this application is to provide a device, equipment, and computer-readable storage medium for verifying the function of a switch.

[0005] To solve the above-mentioned technical problems, this application provides the following technical solution: A method for verifying the functionality of a switch, comprising: Obtain the packet processing flow information of the switch to be verified; According to the message processing flow, the required processing stage module is determined from a plurality of preset processing stage modules; wherein, each processing stage module is an independent processing unit corresponding to different functional points of the switch, and the plurality of processing stage modules include at least a message receiving module, a message parsing module, a message modification module, a switching module, and a message sending module; According to the message processing order of the switch, the determined processing stage modules are sequentially connected in series through a general data bus to obtain a data processing link; wherein, the general data bus is implemented based on the transaction-level modeling interface of the general verification methodology and is used to transfer message transaction objects between adjacent processing stage modules; Each processing stage module is connected to the table entry information pool through a general query bus to obtain the table entry query modification link; wherein, the general query bus is implemented based on the transaction-level modeling interface of the general verification methodology and is used to transfer table entry query transaction objects between each processing stage module and the table entry information pool. Each processing stage module is connected to the statistical information pool through a general statistical bus to obtain a statistical record link; wherein, the general statistical bus is implemented based on the transaction-level modeling interface of the general verification methodology and is used to transfer statistical transaction objects between each processing stage module and the statistical information pool. Based on the data processing link, the table entry query and modification link, and the statistical record link, a reference model adapted to the switch to be verified is constructed; wherein, the general data bus, general query bus, and general statistical bus in the reference model are independent of each other, and respectively carry the message data stream, the table entry query stream, and the statistical record stream; The function of the switch to be verified is performed based on the reference model.

[0006] In one specific embodiment of this application, it further includes: Each processing stage module is configured with a unified data input interface and a data output interface; wherein, each processing stage module receives message transaction objects through the data input interface and outputs message transaction objects through the data output interface, and the processing stage modules do not call each other's internal processing functions. When adjusting the functional configuration of the reference model, processing stage modules are added, deleted, or rearranged in the data processing link to adjust the message processing flow, without modifying the internal implementation of existing processing stage modules.

[0007] In one specific embodiment of this application, it further includes: The table entry information pool stores Layer 2 Ethernet physical address entries and / or Layer 3 routing entries; Each processing stage module is configured to send a table entry query transaction object carrying the table entry type, query keyword, and table entry operation type to the table entry information pool through the general query bus, so as to perform query operations and / or modification operations on the table entry information pool.

[0008] In one specific embodiment of this application, it further includes: The statistical information pool stores the processing records generated by each processing stage module during message processing. Each processing stage module is configured to send a statistical transaction object carrying a message identifier and processing action information to the statistical information pool through the general statistical bus; wherein, the processing action information includes one or more of message modification information, message discard information, and message forwarding information.

[0009] In one specific embodiment of this application, the determined processing stage modules are sequentially connected in series via a universal data bus, including: A transaction-level modeling first-in-first-out queue is set up between adjacent processing stage modules; wherein, the upstream and downstream connection ends of the transaction-level modeling first-in-first-out queue both adopt the transaction-level modeling interface of the general verification methodology. The message transaction object carrying Ethernet message model and message processing attribute information is transmitted through the general data bus; wherein, the message processing attribute information includes message tagging information required in the switch processing model.

[0010] In one specific embodiment of this application, it further includes: Based on the functional requirements of the switch to be verified, determine the number and order of the processing stage modules; When the functional requirements of the switch to be verified include packet dropping processing and / or custom processing logic, the dropping processing module and / or optional extended processing module are added to the data processing link.

[0011] In one specific embodiment of this application, it further includes: During the simulation verification operation phase, the test input message is input to the first processing stage module of the data processing link. The corresponding switch function processing is executed sequentially by each processing stage module, and the reference message result is output at the end processing stage module. The reference message result is sent to the scoring board for consistency comparison with the message result output by the switch under test.

[0012] A switch function verification device, comprising: The message processing flow information acquisition unit is used to acquire message processing flow information of the switch to be verified. The processing stage module determination unit is used to determine the required processing stage module from a plurality of preset processing stage modules according to the message processing flow; wherein each processing stage module is an independent processing unit corresponding to different functional points of the switch, and the plurality of processing stage modules include at least a message receiving module, a message parsing module, a message modification module, a switching module, and a message sending module; The data processing link acquisition unit is used to sequentially connect the determined processing stage modules through a general data bus according to the packet processing order of the switch to obtain the data processing link; wherein, the general data bus is implemented based on the transaction-level modeling interface of the general verification methodology and is used to transfer packet transaction objects between adjacent processing stage modules. The table entry query modification link acquisition unit is used to connect each processing stage module to the table entry information pool through a general query bus to obtain the table entry query modification link; wherein, the general query bus is implemented based on the transaction-level modeling interface of the general verification methodology and is used to transfer table entry query transaction objects between each processing stage module and the table entry information pool. The statistical record link acquisition unit is used to connect each processing stage module to the statistical information pool through a general statistical bus to obtain the statistical record link; wherein, the general statistical bus is implemented based on the transaction-level modeling interface of the general verification methodology and is used to transfer statistical transaction objects between each processing stage module and the statistical information pool. The reference model construction unit is used to construct a reference model adapted to the switch to be verified based on the data processing link, the table entry query and modification link, and the statistical record link; wherein, the general data bus, general query bus, and general statistical bus in the reference model are independent of each other and respectively carry the message data stream, the table entry query stream, and the statistical record stream.

[0013] A switch function verification device, comprising: Memory, used to store computer programs; A processor is used to implement the steps of the switch function verification method as described above when executing the computer program.

[0014] A computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the switch function verification method described above.

[0015] The switch function verification method provided in this application includes: obtaining message processing flow information of the switch to be verified; determining the required processing stage modules from a set of multiple pre-set processing stage modules according to the message processing flow; wherein each processing stage module is an independent processing unit corresponding to different functional points of the switch, and the multiple processing stage modules include at least a message receiving module, a message parsing module, a message modification module, a switching module, and a message sending module; sequentially connecting the determined processing stage modules in series through a general data bus according to the message processing order of the switch to obtain a data processing link; wherein the general data bus is implemented based on the transaction-level modeling interface of the general verification methodology and is used to transfer message transaction objects between adjacent processing stage modules; and connecting each processing stage module to a table entry information pool through a general query bus to obtain table entries. The system comprises three stages: a query / modification link, a general query bus (implemented based on a transaction-level modeling interface of a general verification methodology) for transmitting table query transaction objects between each processing stage module and the table entry information pool, a general statistics bus connecting each processing stage module to the statistics information pool to form a statistical record link, and a reference model adapted to the switch to be verified based on the data processing link, the table query / modification link, and the statistical record link. The general data bus, general query bus, and general statistics bus in the reference model are independent, carrying message data streams, table query streams, and statistical record streams, respectively. Functional verification of the switch to be verified is performed based on the reference model.

[0016] As can be seen from the above technical solution, by determining the required modules from the pre-set processing stage modules according to the message processing flow of the switch to be verified and sequentially connecting them to form a data processing link, each processing stage module serves as an independent processing unit corresponding to different functional points. It carries the message data stream, table query stream, and statistical record stream respectively through a general data bus, a general query bus, and a general statistics bus. The three buses are independent of each other and are all implemented based on the transaction-level modeling interface of the general verification methodology. Therefore, it can solve the technical problems of poor scalability and maintainability of the reference model and lack of reusability. It achieves the technical effect of allowing processing stage modules to be added, deleted, and their order adjusted independently without affecting the internal implementation of existing modules, decoupling the three types of data streams to improve the scalability and maintainability of the reference model, and quickly building an adapted reference model by selecting and combining processing stage modules in different switch verification scenarios, thereby improving the efficiency and reliability of switch functional verification.

[0017] Accordingly, this application also provides a switch function verification device, equipment, and computer-readable storage medium corresponding to the above-mentioned switch function verification method, which have the above-mentioned technical effects, and will not be described in detail here. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 An overall architecture diagram of a switch function verification environment; Figure 2 This is a flowchart of a reference model for switch functionality in related technologies. Figure 3 This is a flowchart illustrating the implementation of a switch function verification method in this application. Figure 4 This is a diagram showing the serial architecture of a switch function verification processing stage module in an embodiment of this application. Figure 5 This is a structural block diagram of a general data bus connection in an embodiment of this application; Figure 6 This is a structural block diagram of a message transaction object in an embodiment of this application; Figure 7 This is a diagram of a northbound table entry query architecture in an embodiment of this application; Figure 8 This is a structural block diagram of a general query bus in an embodiment of this application; Figure 9 This is a diagram of a general query bus transaction object structure in an embodiment of this application; Figure 10 This is a diagram of a southbound statistical record architecture in an embodiment of this application; Figure 11 This is a block diagram of a general statistical bus in an embodiment of this application; Figure 12 This is a structural block diagram of a general statistical bus transaction object in an embodiment of this application; Figure 13 This is a structural block diagram of a switch function verification device according to an embodiment of this application; Figure 14 This is a structural block diagram of a switch function verification device according to an embodiment of this application; Figure 15 This is a schematic diagram of the specific structure of a switch function verification device provided in an embodiment of this application. Detailed Implementation

[0020] See Figure 1 , Figure 1This is an overall architecture diagram of a switch functional verification environment. The environment mainly includes a driver, a reference model, a design under test (DUT), a monitor, and a scoring board. The driver simultaneously applies stimulus messages to both the reference model and the DUT. The reference model and the DUT each output their processing results. The monitor collects the DUT's output and sends it to the scoring board, which then performs a consistency comparison between the reference model's output and the DUT's output.

[0021] See Figure 2 , Figure 2 This is a flowchart illustrating the processing flow of a switch function reference model in related technologies. In these technologies, reference models are typically built based on components from general verification methodologies, and the data processing flow is organized in the order of acquisition, processing, and writing during simulation. The processing stage functions as one or more functions or tasks to implement the switch's functions, including packet parsing, packet modification, table lookup and forwarding, etc. The more complex the functions, the more bloated and chaotic the entire processing flow becomes; adding new functions or changing the processing order can easily lead to a redesign of the processing section.

[0022] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0023] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0024] See Figure 3 , Figure 3 This is a flowchart illustrating an implementation method for verifying switch functionality according to an embodiment of this application. The method may include the following steps: S301: Obtain message processing flow information of the switch to be verified.

[0025] Obtain the packet processing flow information of the switch to be verified. The switch to be verified refers to the switch chip design that needs functional verification, i.e., the design under test. The packet processing flow information characterizes the various functional stages and their sequence during packet processing by the switch to be verified. The data processing flow of a typical switch can be abstracted into the following general steps: packet reception, packet parsing, table lookup and forwarding decision, packet modification, switching scheduling, and packet transmission. Different models and specifications of switches may have different packet processing flows; for example, some switches may include a packet dropping process, while others may include custom extended processing logic. Obtaining the packet processing flow information of the switch to be verified provides a basis for subsequently determining the required processing stage modules from the pre-defined processing stage modules.

[0026] S302: Based on the message processing flow, determine the required processing stage module from among the multiple preset processing stage modules.

[0027] Each processing stage module is an independent processing unit corresponding to different functional points of the switch. Multiple processing stage modules include at least a message receiving module, a message parsing module, a message modification module, a switching module, and a message sending module.

[0028] The system has multiple pre-configured processing stage modules, each corresponding to a functional point of the switch and serving as an independent processing unit. These pre-configured processing stage modules include at least a message receiving module, a message parsing module, a message modification module, a switching module, and a message sending module. Specifically, the message receiving module corresponds to the switch's message receiving function and is used to receive input messages; the message parsing module corresponds to the switch's message parsing function and is used to parse messages to extract header information; the message modification module corresponds to the switch's message modification function and is used to modify message content; the switching module corresponds to the switch's switching scheduling function and is used to determine the message forwarding port based on a lookup table; and the message sending module corresponds to the switch's message sending function and is used to send the processed message to the target port.

[0029] Based on the acquired message processing flow information, the required processing stage modules for the switch to be verified are determined from a set of pre-defined processing stage modules. For example, if the message processing flow of the switch to be verified is message reception, message parsing, message modification, switching, and message sending, then the required processing stage modules are determined to be the message reception module, message parsing module, message modification module, switching module, and message sending module.

[0030] S303: According to the message processing order of the switch, the determined processing stage modules are connected in series through the general data bus to obtain the data processing link.

[0031] The general data bus is implemented based on the transaction-level modeling interface of the general verification methodology and is used to pass message transaction objects between adjacent processing stage modules.

[0032] See Figure 4 , Figure 4 This is a schematic diagram of a serialized architecture for a switch function verification processing stage module in an embodiment of this application. Following the switch's message processing order, the determined processing stage modules are sequentially connected in series via a general-purpose data bus to form a data processing link. The general-purpose data bus is implemented based on a transaction-level modeling interface of a general verification methodology and is used to transmit message transaction objects between adjacent processing stage modules. A message transaction object is a data packet transmitted on the general-purpose data bus, carrying message data and processing attribute information.

[0033] The implementation of a general-purpose data bus is not limited to transaction-level modeling with a first-in-first-out (FIFO) buffer; it can also be implemented using the direct port connection method or the mailbox method found in general verification methodologies. When using transaction-level modeling with a FIFO buffer, adjacent processing stage modules buffer and pass message transaction objects through the FIFO buffer. When using the direct port connection method, the output port of the upstream processing stage module is directly connected to the input port of the downstream processing stage module. All of these implementations are within the standard framework of the general verification methodologies and do not introduce any non-standard dependencies.

[0034] S304: Connect each processing stage module to the table entry information pool through the general query bus to obtain the table entry query and modification link.

[0035] The general query bus is implemented based on the transaction-level modeling interface of the general verification methodology, and is used to transfer table query transaction objects between modules in each processing stage and the table entry information pool.

[0036] See Figure 7 , Figure 7 This is a diagram illustrating a northbound table entry query architecture in an embodiment of this application. A table entry information pool is constructed, and each processing stage module is connected to the table entry information pool via a universal query bus, forming a table entry query and modification link. The table entry information pool is a resource pool used to centrally store table entry information shared during the processing of the switch reference model. The universal query bus is implemented based on a transaction-level modeling interface of a universal verification methodology, used to transfer table entry query transaction objects between each processing stage module and the table entry information pool. The connection interface between each processing stage module and the table entry information pool is consistent, and any processing stage module can perform query and modification operations on the table entry information pool through the universal query bus.

[0037] S305: Connect each processing stage module to the statistical information pool through a general statistical bus to obtain a statistical record link.

[0038] The general statistical bus is implemented based on the transaction-level modeling interface of the general verification methodology, and is used to transfer statistical transaction objects between modules in each processing stage and the statistical information pool.

[0039] See Figure 10 , Figure 10 This is a southbound statistical recording architecture diagram according to an embodiment of this application. A statistical information pool is constructed, and each processing stage module is connected to the statistical information pool through a general statistical bus to form a statistical recording link. The statistical information pool is an information pool used to centrally store the processing records generated by each processing stage module during message processing. The general statistical bus is implemented based on a transaction-level modeling interface of a general verification methodology and is used to transfer statistical transaction objects between each processing stage module and the statistical information pool. The connection interface between each processing stage module and the statistical information pool is consistent, and any processing stage module can send statistical transaction objects to the statistical information pool through the general statistical bus to record processing actions.

[0040] S306: Based on the data processing link, the table entry query and modification link, and the statistical record link, a reference model adapted to the switch to be verified is constructed.

[0041] In the reference model, the general data bus, general query bus, and general statistics bus are independent of each other, carrying message data streams, table query streams, and statistical record streams, respectively.

[0042] Based on the established data processing link, table entry query and modification link, and statistical record link, a reference model adapted to the switch to be verified is constructed. In this reference model, the general data bus, general query bus, and general statistical bus are independent of each other, carrying the message data stream, table entry query stream, and statistical record stream respectively, achieving complete decoupling of the three dimensions of data flow, table entry query, and statistical record.

[0043] S307: Perform functional verification of the switch to be verified based on the reference model.

[0044] After constructing a reference model adapted to the switch under test, the reference model is deployed in the switch functional verification environment to perform functional verification on the switch. Test input packets can be simultaneously input to both the reference model and the switch under test. The reference model processes the packets according to the correct switch processing logic and outputs reference packet results. The switch under test processes the packets and outputs actual packet results. The reference packet results and actual packet results are compared for consistency. If they match, the switch under test is deemed to be functionally correct; if they do not match, the switch under test is deemed to have a functional defect.

[0045] As can be seen from the above technical solution, by determining the required modules from the pre-set processing stage modules according to the message processing flow of the switch to be verified and sequentially connecting them to form a data processing link, each processing stage module serves as an independent processing unit corresponding to different functional points. It carries the message data stream, table query stream, and statistical record stream respectively through a general data bus, a general query bus, and a general statistics bus. The three buses are independent of each other and are all implemented based on the transaction-level modeling interface of the general verification methodology. Therefore, it can solve the technical problems of poor scalability and maintainability of the reference model and lack of reusability. It achieves the technical effect of allowing processing stage modules to be added, deleted, and their order adjusted independently without affecting the internal implementation of existing modules, decoupling the three types of data streams to improve the scalability and maintainability of the reference model, and quickly building an adapted reference model by selecting and combining processing stage modules in different switch verification scenarios, thereby improving the efficiency and reliability of switch functional verification.

[0046] It should be noted that, based on the above embodiments, this application also provides corresponding improvement solutions. In subsequent embodiments, steps that are the same as or corresponding to those in the above embodiments can be referred to each other, and the corresponding beneficial effects can also be referred to each other. These improvements will not be elaborated upon in the following improved embodiments.

[0047] In one specific embodiment of this application, the method may include the following steps: Step 1: Configure a unified data input interface and data output interface for each processing stage module; wherein, each processing stage module receives message transaction objects through the data input interface and outputs message transaction objects through the data output interface, and the processing stage modules do not call each other's internal processing functions. Step 2: When adjusting the functional configuration of the reference model, add, delete, or rearrange the processing stage modules in the data processing link to adjust the message processing flow, without modifying the internal implementation of the existing processing stage modules.

[0048] For ease of description, the two steps above can be combined for explanation.

[0049] Each processing stage module is configured with a unified data input interface and a unified data output interface. Each processing stage module receives message transaction objects through the unified data input interface and outputs message transaction objects through the unified data output interface. Because each processing stage module uses a unified input and output interface and does not call each other's internal processing functions, when it is necessary to adjust the functional configuration of the reference model, processing stage modules can be added, deleted, or rearranged directly in the data processing chain to complete the adjustment of the message processing flow without modifying the internal implementation of the existing processing stage modules.

[0050] Data transfer between modules in different processing stages can also be achieved through their own independent interfaces instead of a unified interface. However, this increases the coupling between modules, and adjustments may require synchronous modification of the interface definitions.

[0051] By configuring unified data input and output interfaces for each processing stage module, the modules do not need to call each other's internal processing functions, thus achieving plug-and-play characteristics. Modules can be combined, added, deleted, or their order adjusted arbitrarily without modifying the internal implementation of existing modules. This allows the reference model to adapt to the verification requirements of different switch design codes, significantly improving the reusability and scalability of the reference model.

[0052] In one specific embodiment of this application, the method may include the following steps: Step 1: Store Layer 2 Ethernet physical address entries and / or Layer 3 routing entries in the entry information pool; Step 2: Configure each processing stage module to send a table entry query transaction object carrying the table entry type, query keyword, and table entry operation type to the table entry information pool through the general query bus, so as to perform query operations and / or modification operations on the table entry information pool.

[0053] For ease of description, the two steps above can be combined for explanation.

[0054] See Figure 8 , Figure 8 This is a structural block diagram of a general query bus in an embodiment of this application. See also... Figure 9 , Figure 9 This is a structural diagram of a general query bus transaction object in an embodiment of this application. The table entry information pool stores table entry information shared during the switch reference model processing. This table entry information includes Layer 2 Ethernet physical address entries and / or Layer 3 routing table entries. Layer 2 Ethernet physical address entries record the mapping between Media Access Control addresses and ports, while Layer 3 routing table entries record the mapping between Internet Protocol addresses and next hops.

[0055] Each processing stage module is configured to send table query transaction objects to the table entry information pool via a general query bus. Each table query transaction object carries the table entry type, query keyword, and table entry operation type. The table entry type indicates the category of the table entry to be queried or modified, such as a Layer 2 Ethernet physical address table entry or a Layer 3 routing table entry; the query keyword is used to locate the target table entry within the corresponding table entry category, such as a Media Access Control address or an Internet Protocol address; and the table entry operation type indicates the operation to be performed, such as a query operation or a modification operation. Each processing stage module performs query and / or modification operations on the table entry information pool by sending table query transaction objects carrying the above information.

[0056] By centrally storing shared entries in an entry information pool, each processing stage module can access them through a unified interface via a general query bus, shielding the underlying implementation details and achieving complete decoupling of the entry query flow and message data flow. This eliminates the need for each processing stage module to maintain its own copy of the entries, reducing the coupling between modules.

[0057] In one specific embodiment of this application, the method may include the following steps: Step 1: Store the processing records generated by each processing stage module during message processing in the statistics information pool; Step 2: Configure each processing stage module to send statistical transaction objects carrying message identifiers and processing action information to the statistical information pool through the general statistical bus; wherein, the processing action information includes one or more of message modification information, message discard information, and message forwarding information.

[0058] For ease of description, the two steps above can be combined for explanation.

[0059] See Figure 11 , Figure 11 This is a block diagram of a general statistical bus in an embodiment of this application. See also... Figure 12 , Figure 12 This is a structural block diagram of a general statistical bus transaction object in an embodiment of this application. The processing records generated by each processing stage module during message processing are stored in the statistical information pool. Each processing stage module is configured to send a statistical transaction object to the statistical information pool via the general statistical bus. The statistical transaction object carries a message identifier and processing action information. The message identifier is used to uniquely identify the processed message, and the processing action information records the processing actions performed by the processing stage module on the message. The processing action information includes one or more of the following: message modification information, message discard information, and message forwarding information.

[0060] By centrally storing the processing records of each processing stage module in a statistical information pool, and recording processing actions through a unified interface via a general statistical bus, the statistical record stream and the message data stream are completely decoupled, making the recording of processing actions and the processing of message data independent of each other, which facilitates subsequent traceability and analysis of the processing process.

[0061] In one specific embodiment of this application, connecting the determined processing stage modules sequentially in series via a universal data bus may include the following steps: Step 1: Set up a transaction-level modeling FIFO queue between adjacent processing stage modules; wherein, the upstream and downstream connections of the transaction-level modeling FIFO queue both adopt the transaction-level modeling interface of the general verification methodology; Step 2: Transmit the message transaction object carrying the Ethernet message model and message processing attribute information through the general data bus; wherein, the message processing attribute information includes the message tagging information required in the switch processing model.

[0062] For ease of description, the two steps above can be combined for explanation.

[0063] See Figure 5 , Figure 5 This is a structural block diagram of a general data bus connection according to an embodiment of this application. See also... Figure 6 , Figure 6 This is a structural block diagram of a message transaction object in an embodiment of this application. A transaction-level modeling FIFO buffer is set up between adjacent processing stage modules to realize a universal data bus. Both the upstream and downstream connections of the transaction-level modeling FIFO buffer adopt the transaction-level modeling interface of a universal verification methodology, used for queuing and transferring message transaction objects between different processing stage modules.

[0064] Message transaction objects transmitted via the general-purpose data bus carry Ethernet message models and message processing attribute information. The Ethernet message model is the data model of a standard Ethernet message, and the message processing attribute information is message marking information needed in the switch's processing model, including but not limited to message ingress port, message priority, and VLAN identifier. The content of the message transaction object can be customized according to actual needs and is not limited to the fields mentioned above.

[0065] By setting up a transaction-level modeling first-in-first-out cache between adjacent processing stage modules, and utilizing the native transaction-level modeling interface of the general verification methodology to achieve standardized communication between processing stage modules, the data flow and processing flow are clear, each module can be maintained independently, and it is very convenient to extend the reference model.

[0066] In one specific embodiment of this application, the method may further include the following steps: Step 1: Determine the number and order of processing modules based on the functional requirements of the switch to be verified; Step 2: When the functional requirements of the switch to be verified include packet dropping processing and / or custom processing logic, add the dropping processing module and / or optional extended processing module to the data processing link.

[0067] For ease of description, the two steps above can be combined for explanation.

[0068] Based on the functional requirements of the switch to be verified, the number and order of the processing stage modules are determined. The pre-configured processing stage modules also include a drop processing module and optional extended processing modules. The drop processing module corresponds to the switch's packet drop function and is used to drop packets that do not need to be forwarded according to preset rules. The optional extended processing module is used to add custom processing logic based on the functional requirements of the switch to be verified.

[0069] When the functional requirements of the switch to be verified include packet dropping and / or custom processing logic, a drop processing module and / or optional extended processing modules are added to the data processing link. The number and order of processing stage modules are determined based on the functional requirements of the switch to be verified to achieve maximum flexibility in the processing model. For example, if the switch to be verified does not require packet dropping functionality, the drop processing module can be removed from the data processing link; if the switch to be verified includes special multicast replication functionality, an optional extended processing module for multicast replication can be added to the data processing link.

[0070] By flexibly determining the number and order of processing stage modules according to the functional requirements of the switch to be verified, and adding drop processing modules and optional extended processing modules to the data processing link when needed, the reference model can adapt to the functional differences of different switches, thus improving the adaptability and flexibility of the reference model.

[0071] In one specific embodiment of this application, the method may further include the following steps: Step 1: During the simulation verification run phase, the test input message is input to the first processing stage module of the data processing link. The corresponding switch function is executed sequentially by each processing stage module, and the reference message result is output at the end processing stage module. Step 2: Send the reference message results to the scoring board for consistency comparison with the message results output by the switch under test.

[0072] For ease of description, the two steps above can be combined for explanation.

[0073] During the simulation verification phase, the test input packets are fed into the first processing stage module of the data processing link. Each processing stage module then sequentially executes the corresponding switch function. For example, the packet receiving module receives the test packets, the packet parsing module parses the packets, the packet modification module modifies the packet content, the switching module determines the forwarding port based on the lookup table result, the packet sending module outputs the processed packets, and the final processing stage module outputs the reference packet result.

[0074] The reference message result is sent to the scoring board, which simultaneously receives the message result output by the switch under test. The reference message result is compared with the message result output by the switch under test to verify whether the function of the switch under test is correct.

[0075] By inputting test input messages into the data processing link during the simulation verification operation phase, each processing module sequentially executes the corresponding switch function processing and outputs reference message results at the end. The reference message results are then sent to the scoring board for consistency comparison with the output of the switch under test, thus realizing automated verification of switch functions and improving the accuracy and efficiency of verification.

[0076] It should be noted that the embodiments in this application are entirely built upon standard components of the general verification methodology, without introducing any non-standard dependencies. The general verification methodology is an industry-standard chip verification methodology developed by a standardization organization. Built upon a system verification language, it provides a complete verification framework and base class library, including core components such as component classes, transaction-level modeling interfaces, and phase mechanisms. The processing phase module, general data bus, general query bus, general statistics bus, table entry information pool, and statistics information pool in this application are all implemented based on the general verification methodology standard framework.

[0077] It should also be noted that the embodiments of this application are implemented through system verification language encoding, and simulation software needs to be called to run them during implementation. In the simulation software, each processing stage module is instantiated as a general verification methodology component. The general data bus, general query bus, and general statistics bus are connected through transaction-level modeling ports and first-in-first-out queues. The table entry information pool and the statistics information pool are encapsulated in the form of components, providing a unified query and record interface.

[0078] It should also be noted that the division of processing stage modules in this embodiment is based on the abstraction of a general processing flow of a switch. The data processing flow of a typical switch can be abstracted into the following general steps: packet reception, packet parsing, table lookup and forwarding decision, packet modification, switching scheduling, and packet transmission. The division of processing stage modules in this application is based on the above general process abstraction, while also retaining scalability. Through optional expansion of processing modules and adjustment of the order of processing stage modules, the number and order of each processing stage module can be flexibly adjusted according to the design of the specific switch.

[0079] Corresponding to the above method embodiments, this application also provides a switch function verification device, and the switch function verification device described below can be referred to in correspondence with the switch function verification method described above.

[0080] See Figure 13 , Figure 13 This is a structural block diagram of a switch function verification device according to an embodiment of this application. The device may include: The message processing flow information acquisition unit 11 is used to acquire the message processing flow information of the switch to be verified. The processing stage module determination unit 12 is used to determine the required processing stage module from a plurality of preset processing stage modules according to the message processing flow; wherein each processing stage module is an independent processing unit corresponding to different functional points of the switch, and the plurality of processing stage modules include at least a message receiving module, a message parsing module, a message modification module, a switching module and a message sending module. The data processing link acquisition unit 13 is used to connect the determined processing stage modules sequentially through a general data bus according to the message processing order of the switch to obtain the data processing link; wherein, the general data bus is implemented based on the transaction-level modeling interface of the general verification methodology and is used to transfer message transaction objects between adjacent processing stage modules. The table entry query modification link acquisition unit 14 is used to connect each processing stage module to the table entry information pool through the general query bus to obtain the table entry query modification link; wherein, the general query bus is implemented based on the transaction-level modeling interface of the general verification methodology and is used to transfer table entry query transaction objects between each processing stage module and the table entry information pool. The statistical record link acquisition unit 15 is used to connect each processing stage module to the statistical information pool through a general statistical bus to obtain the statistical record link; wherein, the general statistical bus is implemented based on the transaction-level modeling interface of the general verification methodology and is used to transfer statistical transaction objects between each processing stage module and the statistical information pool. The reference model construction unit 16 is used to construct a reference model adapted to the switch to be verified based on the data processing link, the table entry query modification link, and the statistical record link. The general data bus, general query bus, and general statistical bus in the reference model are independent of each other and carry the message data stream, the table entry query stream, and the statistical record stream, respectively.

[0081] As can be seen from the above technical solution, by determining the required modules from the pre-set processing stage modules according to the message processing flow of the switch to be verified and sequentially connecting them to form a data processing link, each processing stage module serves as an independent processing unit corresponding to different functional points. It carries the message data stream, table query stream, and statistical record stream respectively through a general data bus, a general query bus, and a general statistics bus. The three buses are independent of each other and are all implemented based on the transaction-level modeling interface of the general verification methodology. Therefore, it can solve the technical problems of poor scalability and maintainability of the reference model and lack of reusability. It achieves the technical effect of allowing processing stage modules to be added, deleted, and their order adjusted independently without affecting the internal implementation of existing modules, decoupling the three types of data streams to improve the scalability and maintainability of the reference model, and quickly building an adapted reference model by selecting and combining processing stage modules in different switch verification scenarios, thereby improving the efficiency and reliability of switch functional verification.

[0082] In one specific embodiment of this application, the device may further include: The interface configuration unit is used to configure a unified data input interface and data output interface for each processing stage module. Each processing stage module receives message transaction objects through the data input interface and outputs message transaction objects through the data output interface. The processing stage modules do not call each other's internal processing functions. The message processing flow adjustment unit is used to add, delete, or rearrange processing stage modules in the data processing link to adjust the message processing flow when adjusting the functional configuration of the reference model, without modifying the internal implementation of the existing processing stage modules.

[0083] In one specific embodiment of this application, the device may further include: The table entry storage unit is used to store Layer 2 Ethernet physical address entries and / or Layer 3 routing entries in the table entry information pool; The table entry information pool query and modification unit is used to configure each processing stage module to send a table entry query transaction object carrying the table entry type, query keyword, and table entry operation type to the table entry information pool through the general query bus, so as to perform query operations and / or modification operations on the table entry information pool.

[0084] In one specific embodiment of this application, the device may further include: The processing record storage unit is used to store the processing records generated by each processing stage module during message processing in the statistical information pool; The statistical transaction object sending unit is used to configure each processing stage module to send statistical transaction objects carrying message identifiers and processing action information to the statistical information pool through the general statistical bus; wherein, the processing action information includes one or more of message modification information, message discard information, and message forwarding information.

[0085] In one specific embodiment of this application, the data processing link acquisition unit 13 may include: The queue setting subunit is used to set up transaction-level modeling first-in-first-out queues between adjacent processing stage modules; wherein, the upstream and downstream connection ends of the transaction-level modeling first-in-first-out queues both adopt the transaction-level modeling interface of the general verification methodology; The message transaction object transmission subunit is used to transmit message transaction objects carrying Ethernet message model and message processing attribute information through the general data bus; wherein, the message processing attribute information includes message tagging information required in the switch processing model.

[0086] In one specific embodiment of this application, the device may further include: The quantity and order determination unit is used to determine the quantity and order of processing stage modules based on the functional requirements of the switch to be verified. The module addition unit is used to add a packet dropping module and / or optional extended processing module to the data processing link when the functional requirements of the switch to be verified include packet dropping processing and / or custom processing logic.

[0087] In one specific embodiment of this application, the device may further include: The reference message result output unit is used to input the test input message into the first processing stage module of the data processing link during the simulation verification run phase. The corresponding switch function processing is executed sequentially by each processing stage module, and the reference message result is output in the terminal processing stage module. The consistency comparison unit is used to send the reference message result to the scoring board for consistency comparison with the message result output by the switch under test.

[0088] For the method embodiments described above, see [link to relevant documentation]. Figure 14 , Figure 14 This is a schematic diagram of the switch function verification device provided in this application. The device may include: Memory 332 is used to store computer programs; The processor 322 is used to implement the steps of the switch function verification method in the above method embodiment when executing a computer program.

[0089] For details, please refer to Figure 15 , Figure 15This is a schematic diagram illustrating the specific structure of a switch function verification device provided in this embodiment. The switch function verification device can vary significantly due to different configurations or performance. It may include a processor (central processing unit, CPU) 322 (e.g., one or more processors) and a memory 332. The memory 332 stores one or more computer programs 342 or data 344. The memory 332 can be temporary or persistent storage. The program stored in the memory 332 may include one or more modules (not shown in the diagram), each module may include a series of instruction operations on the data processing device. Furthermore, the processor 322 may be configured to communicate with the memory 332 and execute the series of instruction operations stored in the memory 332 on the switch function verification device 301.

[0090] The switch function verification device 301 may also include one or more power supplies 326, one or more wired or wireless network interfaces 350, one or more input / output interfaces 358, and / or one or more operating systems 341.

[0091] The steps in the switch function verification method described above can be implemented by the structure of the switch function verification device.

[0092] Corresponding to the above method embodiments, this application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, can perform the following steps: The process involves: acquiring the message processing flow information of the switch to be verified; determining the required processing stage modules from a set of pre-defined processing stage modules based on the message processing flow; wherein each processing stage module is an independent processing unit corresponding to different functional points of the switch, and the multiple processing stage modules include at least a message receiving module, a message parsing module, a message modification module, a switching module, and a message sending module; sequentially connecting the determined processing stage modules in series via a general-purpose data bus according to the switch's message processing order to obtain a data processing link; wherein the general-purpose data bus is implemented based on the transaction-level modeling interface of the general verification methodology and is used to transfer message transaction objects between adjacent processing stage modules; and connecting each processing stage module to the table entry information pool via a general-purpose query bus to obtain the table entry query and modification link. A general query bus is implemented based on a transaction-level modeling interface of a general verification methodology. It is used to transfer table query transaction objects between each processing stage module and the table entry information pool. A general statistical bus connects each processing stage module to the statistical information pool, forming a statistical record link. The general statistical bus, also based on a transaction-level modeling interface of a general verification methodology, is used to transfer statistical transaction objects between each processing stage module and the statistical information pool. Based on the data processing link, table entry query modification link, and statistical record link, a reference model adapted to the switch to be verified is constructed. In this reference model, the general data bus, general query bus, and general statistical bus are independent, carrying the message data stream, table entry query stream, and statistical record stream, respectively. Functional verification of the switch to be verified is performed based on the reference model.

[0093] The computer-readable storage medium may include various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0094] For a description of the computer-readable storage medium provided in this application, please refer to the above method embodiments; further details will not be repeated here.

[0095] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatuses, devices, and computer-readable storage media disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple; relevant parts can be referred to the method section.

[0096] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core ideas of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of this application.

Claims

1. A method for verifying the function of a switch, characterized in that, include: Obtain the packet processing flow information of the switch to be verified; Based on the message processing flow information, the required processing stage module is determined from a plurality of preset processing stage modules; wherein, each processing stage module is an independent processing unit corresponding to different functional points of the switch, and the plurality of processing stage modules include at least a message receiving module, a message parsing module, a message modification module, a switching module, and a message sending module; According to the message processing order of the switch, the determined processing stage modules are sequentially connected in series through a general data bus to obtain a data processing link; wherein, the general data bus is implemented based on the transaction-level modeling interface of the general verification methodology and is used to transfer message transaction objects between adjacent processing stage modules; Each processing stage module is connected to the table entry information pool through a general query bus to obtain the table entry query modification link; wherein, the general query bus is implemented based on the transaction-level modeling interface of the general verification methodology and is used to transfer table entry query transaction objects between each processing stage module and the table entry information pool. Each processing stage module is connected to the statistical information pool through a general statistical bus to obtain a statistical record link; wherein, the general statistical bus is implemented based on the transaction-level modeling interface of the general verification methodology and is used to transfer statistical transaction objects between each processing stage module and the statistical information pool. Based on the data processing link, the table entry query and modification link, and the statistical record link, a reference model adapted to the switch to be verified is constructed; wherein, the general data bus, general query bus, and general statistical bus in the reference model are independent of each other, and respectively carry the message data stream, the table entry query stream, and the statistical record stream; The function of the switch to be verified is performed based on the reference model.

2. The switch function verification method according to claim 1, characterized in that, Also includes: Each processing stage module is configured with a unified data input interface and a data output interface; wherein, each processing stage module receives message transaction objects through the data input interface and outputs message transaction objects through the data output interface, and the processing stage modules do not call each other's internal processing functions. When adjusting the functional configuration of the reference model, processing stage modules are added, deleted, or rearranged in the data processing link to adjust the message processing flow, without modifying the internal implementation of existing processing stage modules.

3. The switch function verification method according to claim 1, characterized in that, Also includes: The table entry information pool stores Layer 2 Ethernet physical address entries and / or Layer 3 routing entries; Each processing stage module is configured to send a table entry query transaction object carrying the table entry type, query keyword, and table entry operation type to the table entry information pool through the general query bus, so as to perform query operations and / or modification operations on the table entry information pool.

4. The switch function verification method according to claim 1, characterized in that, Also includes: The statistical information pool stores the processing records generated by each processing stage module during message processing. Each processing stage module is configured to send a statistical transaction object carrying a message identifier and processing action information to the statistical information pool through the general statistical bus; wherein, the processing action information includes one or more of message modification information, message discard information, and message forwarding information.

5. The switch function verification method according to claim 1, characterized in that, The defined processing stage modules are sequentially connected in series via a universal data bus, including: A transaction-level modeling first-in-first-out queue is set up between adjacent processing stage modules; wherein, the upstream and downstream connection ends of the transaction-level modeling first-in-first-out queue both adopt the transaction-level modeling interface of the general verification methodology. The message transaction object carrying Ethernet message model and message processing attribute information is transmitted through the general data bus; wherein, the message processing attribute information includes message tagging information required in the switch processing model.

6. The switch function verification method according to claim 1, characterized in that, Also includes: Based on the functional requirements of the switch to be verified, determine the number and order of the processing stage modules; When the functional requirements of the switch to be verified include packet dropping processing and / or custom processing logic, the dropping processing module and / or optional extended processing module are added to the data processing link.

7. The switch function verification method according to any one of claims 1 to 6, characterized in that, Also includes: During the simulation verification operation phase, the test input message is input to the first processing stage module of the data processing link. The corresponding switch function processing is executed sequentially by each processing stage module, and the reference message result is output at the end processing stage module. The reference message result is sent to the scoring board for consistency comparison with the message result output by the switch under test.

8. A device for verifying the function of a switch, characterized in that, include: The message processing flow information acquisition unit is used to acquire message processing flow information of the switch to be verified. The processing stage module determination unit is used to determine the required processing stage module from a plurality of preset processing stage modules according to the message processing flow; wherein each processing stage module is an independent processing unit corresponding to different functional points of the switch, and the plurality of processing stage modules include at least a message receiving module, a message parsing module, a message modification module, a switching module, and a message sending module; The data processing link acquisition unit is used to sequentially connect the determined processing stage modules through a general data bus according to the packet processing order of the switch to obtain the data processing link; wherein, the general data bus is implemented based on the transaction-level modeling interface of the general verification methodology and is used to transfer packet transaction objects between adjacent processing stage modules. The table entry query modification link acquisition unit is used to connect each processing stage module to the table entry information pool through a general query bus to obtain the table entry query modification link; wherein, the general query bus is implemented based on the transaction-level modeling interface of the general verification methodology and is used to transfer table entry query transaction objects between each processing stage module and the table entry information pool. The statistical record link acquisition unit is used to connect each processing stage module to the statistical information pool through a general statistical bus to obtain the statistical record link; wherein, the general statistical bus is implemented based on the transaction-level modeling interface of the general verification methodology and is used to transfer statistical transaction objects between each processing stage module and the statistical information pool. The reference model construction unit is used to construct a reference model adapted to the switch to be verified based on the data processing link, the table entry query and modification link, and the statistical record link; wherein, the general data bus, general query bus, and general statistical bus in the reference model are independent of each other and respectively carry the message data stream, the table entry query stream, and the statistical record stream.

9. A switch function verification device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the switch function verification method as described in any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the switch function verification method as described in any one of claims 1 to 7.

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