FPGA-oriented configurable fixed-point precision selection and chaos maintenance detection method and device

Abstract

The application discloses a configurable fixed-point precision selection and chaos maintenance detection method and device for FPGA, and belongs to the field of communication technology; the method comprises the following steps: constructing a fixed-point number configuration candidate set containing different decimal bit widths; respectively performing comprehensive verification on each format, obtaining FPGA hardware resource consumption data and exporting a fixed-point chaos sequence to calculate a Lyapunov exponent spectrum; arranging the fixed-point number formats in ascending order of decimal bit width, and determining whether the system chaos state condition is satisfied; on this basis, the maximum Lyapunov exponent gain of adjacent bit widths is calculated, the gain is compared with a preset threshold value, it is determined whether the precision improvement enters a platform period to confirm the chaos maintenance constraint; finally, in the format satisfying the constraint, the format with the smallest resource consumption is selected as a target configuration and deployed to the FPGA; the application solves the problem of non-monotonic change of resources when converting a floating point to a fixed point, and realizes lossless migration of chaos system characteristics under the premise of effectively controlling the consumption of underlying hardware resources.

Description

Technical Field

[0001] This invention belongs to the field of communication technology, specifically relating to a configurable fixed-point precision selection and chaos-preserving detection method and apparatus for FPGA. Background Technology

[0002] With the continuous development of emerging technologies such as 6G, AI, IoT, and cloud computing, the number of network users and network traffic are surging. Under this trend, the transmission rate, security, and real-time performance of communication systems have become particularly important. However, current research mostly focuses on using offline digital signal processing to improve transmission capacity and spectral efficiency, neglecting real-time performance, a key characteristic that enables the engineering application of optical communication technology. To achieve ultra-high-speed signal transmission, real-time optical communication is attracting increasing attention.

[0003] With breakthroughs in semiconductor technology and the ever-growing demand for real-time communication, Field-Programmable Gate Arrays (FPGAs), with their advantages of hardware programmability, high parallel processing capabilities, and flexibility, have become the preferred hardware platform for realizing real-time optical interconnect systems in recent years. Although FPGAs provide robust hardware support for real-time optical interconnect systems, ensuring the security of real-time information transmission remains a crucial issue. Researchers have explored upper-layer and physical-layer encryption technologies in optical networks. Compared to the numerous problems faced by upper-layer encryption technologies, such as complex key management, vulnerability to quantum attacks, and high resource consumption, physical-layer encryption, geared towards fiber optic transmission channels, can fundamentally guarantee the security of the communication system. Among these, chaotic encryption technology, with its high initial value sensitivity and large key space, provides a guarantee for secure information transmission. However, computational complexity and hardware resource consumption have become bottlenecks limiting the security of real-time optical interconnect systems. Therefore, a method that can balance hardware resource consumption and the characteristics of chaotic systems, outputting the minimum resource target configuration while maintaining the non-degradation of chaotic characteristics, is urgently needed.

[0004] Most current research focuses on offline simulation of chaotic systems. In engineering implementation, MATLAB is often used for floating-point simulation to verify the characteristics of chaotic systems, while FPGA implementations typically use fixed-point implementations to reduce resource overhead and improve speed. However, migrating chaotic systems from MATLAB floating-point implementations to FPGA fixed-point implementations presents several contradictions and difficulties. When using fixed-point representations, different bit widths or decimal places can lead to numerical errors in discrete systems, potentially causing chaotic degradation, periodic trajectories, and compromising the security of information transmission. Furthermore, different fixed-point bit widths can trigger the mapping and migration of multipliers between different resources in synthesis tools, resulting in non-monotonic changes in resource overhead, making it difficult to choose the fixed-point format empirically. Finally, there is a lack of a quantifiable joint decision-making mechanism. Existing designs often only verify chaotic characteristics in MATLAB or only observe FPGA resource usage, lacking a closed-loop method to constrain resource optimization with chaotic standard indicators, leading to either resource waste or unreliable chaotic performance. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the present invention aims to provide a configurable fixed-point accuracy selection and chaos-preserving detection method and apparatus for FPGAs, thereby solving the problems in the prior art.

[0006] The objective of this invention can be achieved through the following technical solutions: A configurable fixed-point accuracy selection and chaos-preserving detection method for FPGAs includes the following steps: Construct a candidate set of fixed-point number configurations for a chaotic system, wherein the candidate set of fixed-point number configurations includes fixed-point number formats with different decimal widths; The chaotic system is comprehensively verified using each fixed-point number format in the candidate set of fixed-point number configurations, the hardware resource consumption data of the FPGA under the corresponding fixed-point number format is obtained, and the fixed-point chaotic sequence is exported. The derived fixed-point chaotic sequence is calculated to obtain the corresponding Lyapunov exponent spectrum; Arrange the fixed-point number formats in the candidate set of fixed-point number configurations in ascending order of decimal width, and determine whether the Lyapunov exponent spectrum satisfies the preset system chaotic state condition; when the system chaotic state condition is satisfied, calculate the maximum Lyapunov exponent gain corresponding to the fixed-point number formats with adjacent decimal widths; based on the comparison result of the maximum Lyapunov exponent gain and the preset gain threshold, determine whether the accuracy improvement has entered a plateau period, and determine the fixed-point number formats in the plateau period as satisfying the chaos preservation constraint; Among all fixed-point number formats that satisfy the chaos preservation constraint, the fixed-point number format with the smallest hardware resource consumption data value is selected as the target configuration, and the chaotic system is deployed to the FPGA with the target configuration.

[0007] Furthermore, before constructing the candidate set of fixed-point configurations for the chaotic system, the process also includes: using the Euler algorithm to perform calculations and parameter discretization on the continuous four-dimensional hyperchaotic Lüszcz system equations in the time domain according to a preset sampling interval, thereby generating a discrete chaotic system model.

[0008] Furthermore, the process of obtaining the Lyapunov index spectrum includes: Perform a numerical fixed-point scaling operation on the fixed-point chaotic sequence; The data of the fixed-point chaotic sequence at the front end of the preset iteration step size is truncated to remove the transient sequence; For the stable fixed-point chaotic sequence after stripping the transient sequence, the Lyapunov exponents of the system state variables are calculated dimension by dimension to generate the Lyapunov exponent spectrum containing the system's maximum Lyapunov exponent.

[0009] Furthermore, the process of determining whether the improvement in accuracy has reached a plateau includes: Among the fixed-point number formats with adjacent decimal places, the format with the lower decimal place width is designated as the first fixed-point number format, and the format with the higher decimal place width is designated as the second fixed-point number format. Extract the system's maximum Lyapunov exponent corresponding to the first fixed-point number format and the second fixed-point number format, and calculate the difference between the two as the maximum Lyapunov exponent gain. Compare whether the maximum Lyapunov exponential gain is greater than the preset gain threshold; If the maximum Lyapunov exponential gain is less than or equal to the preset gain threshold, it is determined that the precision gain of the current fractional bit width improvement has entered the plateau period, and the first fixed-point number format is determined to satisfy the chaos preservation constraint.

[0010] Furthermore, the hardware resource consumption data includes: the consumption of lookup tables, triggers, and digital signal processing units; The process of selecting the fixed-point format with the lowest hardware resource consumption data value as the target configuration includes: Obtain the number of digital signal processing units consumed for each fixed-point format in the comprehensive verification; Among all fixed-point formats that satisfy the chaos-preserving constraint, the fixed-point format with the least number of digital signal processing units is selected and locked as the target configuration.

[0011] Furthermore, after deploying the chaotic system to the FPGA in the target configuration, the method further includes: The target configuration decimal places are written to the FPGA through a customized fixed-point format configuration register bus, and multiple fixed-point chaotic sequences are output according to the iterative clock cycle. The multi-channel fixed-point chaotic sequence output by the FPGA during continuous operation is fed back to the collaborative verification platform to detect the Lyapunov exponent spectrum state of the sequence; If the Lyapunov exponent spectrum calculation result based on the collaborative verification platform does not meet the preset conditions for a hyperchaotic state or exhibits periodic degradation characteristics, a chaotic state abnormality alarm flag is triggered and written to the FPGA via the fixed-point format configuration register bus.

[0012] Furthermore, the preset conditions for the hyperchaotic state include: at least two Lyapunov exponents in the Lyapunov exponent spectrum are greater than zero, and the sum of all Lyapunov exponents is less than zero.

[0013] Furthermore, the detection method also includes: performing a reset operation on the initial value of the chaotic system based on the written chaotic hold-state abnormal alarm flag signal, or switching the currently used fixed-point number format by overwriting the data written to the fixed-point format configuration register.

[0014] A configurable fixed-point precision selection and chaos-preserving detection device for FPGAs performs the above-described method, including: Candidate configuration construction unit: Constructs a fixed-point number configuration candidate set for a chaotic system, wherein the fixed-point number configuration candidate set includes fixed-point number formats with different decimal widths; Resource and sequence acquisition unit: The chaotic system is comprehensively verified by using each fixed-point number format in the candidate set of fixed-point number configurations, the hardware resource consumption data of the FPGA under the corresponding fixed-point number format is obtained, and the fixed-point chaotic sequence is exported. Exponential spectrum calculation unit: Calculates the derived fixed-point chaotic sequence to obtain the corresponding Lyapunov exponential spectrum; Constraint determination unit: Arranges each fixed-point number format in the candidate set of fixed-point number configurations in ascending order of decimal width, and determines whether the Lyapunov exponent spectrum satisfies the preset system chaotic state condition; when the system chaotic state condition is satisfied, calculates the maximum Lyapunov exponent gain corresponding to the fixed-point number formats with adjacent decimal widths; based on the comparison result of the maximum Lyapunov exponent gain and the preset gain threshold, determines whether the accuracy improvement has entered a plateau period, and determines the fixed-point number formats in the plateau period as satisfying the chaos preservation constraint; Screening and Deployment Unit: Among all fixed-point number formats that satisfy the chaos preservation constraints, select the fixed-point number format with the smallest hardware resource consumption data value as the target configuration, and deploy the chaotic system to the FPGA with the target configuration.

[0015] An electronic device includes: a processor, a memory, a communication interface, and a communication bus, wherein the processor, the memory, and the communication interface communicate with each other through the communication bus; The memory is used to store at least one executable instruction that causes the processor to perform the operation described above for the FPGA-oriented configurable fixed-point precision selection and chaos-preserving detection method.

[0016] The beneficial effects of this invention are: 1. This invention constructs a candidate set of fixed-point number configurations containing different decimal bit widths, and synthesizes each combination on an FPGA to obtain the actual resource usage. Then, from the candidate set that satisfies chaotic constraints, the fixed-point number format with the minimum hardware resource (such as DSP) consumption is selected as the target configuration. Based on the above-mentioned quantitative joint evaluation closed loop, it can effectively avoid the waste of hardware resources caused by blindly increasing the decimal bit width based on experience. Under the premise of ensuring encryption security performance, it provides a reliable resource optimization path for the engineering implementation of the system on the resource-constrained FPGA platform.

[0017] 2. This invention, after deriving the fixed-point chaotic sequence to be evaluated, introduces Lyapunov exponent spectrum calculation and sets a criterion for profit increase or decrease: whether the accuracy improvement has entered a plateau period is determined based on whether the maximum Lyapunov exponent gain exceeds a preset threshold, thus serving as a constraint for maintaining chaos. By introducing rigorous nonlinear dynamic mathematical constraints, this invention replaces the rough judgment method based solely on phase diagram observation in traditional engineering, objectively ensuring that the discretized fixed-point system maintains a relatively optimal chaotic or hyperchaotic state, thereby guaranteeing the complexity of the key sequence and its secure transmission capability. 3. This invention employs the Euler algorithm, which has relatively low computational complexity, to discretize the differential equations of the four-dimensional hyperchaotic Lüszcz system in the time domain, generating a discrete model that is easy to deploy on an FPGA. The discretization scheme based on the Euler algorithm reduces the scale of the system's computational logic layers and underlying operation modules. This enables the high-dimensional hyperchaotic system to be solved and generated smoothly in real time on the FPGA hardware platform, meeting the actual needs of the engineering implementation of real-time optical communication technology.

[0018] 4. The chaotic IP core system of the present invention is designed with a chaotic state flag and an anomaly alarm interface. Based on the detected conditions such as the Lyapunov exponent criterion not being met or the sequence entering a periodic trend, the flag bit is triggered to output. This enables the host computer or control logic to promptly execute operations to reset the initial value or dynamically switch the fixed-point configuration according to the alarm signal, thereby effectively improving the stability and fault tolerance of the physical layer security encryption module under complex working environments and long-term operating conditions. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a flowchart of the configurable fixed-point precision selection and chaos-preserving detection method for FPGA of the present invention; Figure 2 This is the phase diagram of the four-dimensional hyperchaotic Lützen system of the present invention; Figure 3 This is the Lyapunov index spectrum under different fixed-point configurations of the present invention. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] Example 1 like Figure 1 As shown, a configurable fixed-point accuracy selection and chaos-preserving detection method for FPGAs mainly includes: simulation results in MATLAB and observations of FPGA resource usage after synthesis in Vivado software. First, a set of fixed-point configurations is constructed. Then, a chaotic sequence is synthesized in Vivado software, and resource usage is observed. The exported chaotic sequence is used to calculate the Lyapunov exponent spectrum in MATLAB. The scheme with the minimum resource configuration under the Lyapunov exponent constraint is output for deployment on the FPGA.

[0023] Specifically, the method includes the following steps: S1, Construct a candidate set of fixed-point number configurations for a chaotic system, wherein the candidate set of fixed-point number configurations includes fixed-point number formats with different decimal places; In the engineering closed loop of achieving configurable fixed-point accuracy and resource reuse, the candidate fixed-point configuration is represented as: And construct a candidate set of fixed-point number configurations. In this embodiment, fixed-point number formats with different decimal widths are adopted, such as Q... 12.16 Q 12.20 And Q 12.24 These are three different fixed-point number formats.

[0024] Chaos is a complex dynamic behavior arising from deterministic nonlinear systems, characterized by its sensitivity to initial conditions and uncertainty in long-term behavior. Although the trajectory of a chaotic system is deterministic—that is, it can be described by deterministic differential equations—its internal motion in phase space is highly disordered and aperiodic. Therefore, chaotic systems are widely used in the field of encryption.

[0025] In this embodiment, a four-dimensional hyperchaotic Lüshi system is used, which can simultaneously generate four sets of chaotic sequences for encryption during information transmission. To deploy the chaotic system on an FPGA, the chaotic system must first be discretized and then solved in real time on the FPGA.

[0026] First, the four-dimensional hyperchaotic Lübsch system is discretized. The four-dimensional hyperchaotic Lübsch system is defined by the following equations: (1) In equation (1), This is a state parameter. These are the three constants of the Lü's chaotic system. These are control parameters. Here, The values ​​are 36, 3, 20, and 1.2 respectively. And the initial values ​​are... Set to (12, 12, 33, 124). In order to generate chaotic sequences in real time on the FPGA, it is necessary to discretize equation (1) in the time domain. Common discretization methods include Runge-Kutta algorithm and Euler algorithm. Since Euler algorithm has low computational complexity and is easy to deploy on FPGA, in order to reduce the consumption of hardware resources, Euler algorithm is used to discretize the equation of the four-dimensional hyperchaotic Lüszcz system in this patent. The discretization of the chaotic system by Euler algorithm is implemented by the following formula: (2) In this formula, Indicates the sampling interval, here Taking 0.001, substituting equation (2) into equation (1), the discretized four-dimensional hyperchaotic Lübeckian system is obtained as follows: (3) like Figure 2 The diagram shown is a phase diagram of a four-dimensional hyperchaotic Lützen system model. Figure 2 (a) in the figure is the phase diagram of the four-dimensional hyperchaotic Lübeckian system generated by MATLAB simulation; Figure 2 (b) shows the phase diagram of the four-dimensional hyperchaotic Lübeckian system generated without using FPGA. Figure 2 In the phase diagram shown, the chaotic system is implemented on the FPGA using Q... 12.20 The fixed-point number format. (By...) Figure 2 It can be seen that both the simulated and FPGA-generated chaotic system phase diagrams exhibit complex chaotic trajectories, reflecting the inherent complexity of chaotic systems. Even if an attacker knows the algorithm structure and control parameters but not the system's key, due to the sensitivity of chaotic systems to initial conditions, a tiny change in the initial conditions will result in a completely different chaotic sequence, effectively ensuring the security of information transmission.

[0027] S2, the chaotic system is comprehensively verified using each fixed-point number format in the candidate set of fixed-point number configurations, the hardware resource consumption data of the FPGA under the corresponding fixed-point number format is obtained, and the fixed-point chaotic sequence is exported. For the constructed fixed-point configuration set, each combination was synthesized using tools such as Vivado, and chaotic sequences were exported to observe the FPGA resource usage. Specifically, the acquired data included the consumption of lookup tables (LUTs), flip-flops (FFs), and digital signal processing units (DSPs) in the corresponding fixed-point format, and the non-monotonic resource changes caused by mapping migration in the synthesis tool were observed.

[0028] In FPGAs, hardware resources are extremely valuable; therefore, minimizing FPGA hardware resource consumption is crucial. Table 1 shows the different approaches taken using Q... 12.16 Q 12.20 And Q 12.24 Hardware resource consumption under three different fixed-point number formats.

[0029] Table 1 Hardware resource consumption under three different fixed-point number formats In the FPGA, the number of available lookup tables (LUTs) is 341,280, the number of available flip-flops (FFs) is 682,560, and the number of available DSPs is 3,528. Table 1 shows that as the number of decimal places increases, the implementation of the multiplier by the synthesis tool undergoes mapping migration between different resources, resulting in a non-monotonic change in resource usage. Therefore, it is difficult to choose the fixed-point format based solely on experience. In this embodiment, since the number of available DSPs is the smallest and resources are relatively scarce, the goal is to minimize the number of DSPs used. In the above analysis of the Lyapunov exponent, Q...12.16 In the fixed-point scheme, chaotic systems are in a chaotic state, while in the other two fixed-point schemes, they are in a hyperchaotic state. Therefore, when the requirements for the chaotic properties of a chaotic system are not so high, Q can be chosen. 12.16 This fixed-point format reduces the number of DSPs used, further reducing hardware resource consumption. In scenarios with high security requirements, such as military communications, where a chaotic system needs to be in a hyperchaotic state, Q can be selected. 12.20 The fixed-point format, because compared to Q... 12.24 For fixed-point number formats, increasing the precision of decimal places does not significantly improve chaotic properties, while choosing Q... 12.20 Fixed-point format requires less DSP usage, which can reduce hardware resource consumption.

[0030] S3, Calculate the derived fixed-point chaotic sequence to obtain the corresponding Lyapunov exponent spectrum; The exported hardware fixed-point chaotic sequence is transferred to a host computer (such as a MATLAB verification platform). Fixed-point scaling and discarding of transient data are then performed on the chaotic sequence. Since the FPGA output is in fixed-point format, it needs to be converted to floating-point numbers. Fixed-point scaling is implemented based on the following formula: in, It is a double-precision floating-point value. For fixed-point integer values, The decimal width corresponds to the format. After scaling, the first 500 iteration steps of the sequence are truncated to remove the transient sequence and ensure that the system enters a stable chaotic attractor state.

[0031] Subsequently, for the transient-free sequence, an algorithm combining local Jacobian matrix estimation based on nearest-neighbor points in phase space and QR decomposition is used to solve the Lyapunov exponent spectrum. This process does not rely on the continuous differentiability of the system's differential equations. Specifically, the KD-tree algorithm is used to search for and obtain the nearest-neighbor set in the truncated multidimensional phase space sequence; the local Jacobian matrix of the state evolution is fitted using the least squares method, and QR decomposition orthogonalization operations are performed successively; finally, the Lyapunov exponent of the chaotic system is solved by accumulating the logarithmic values ​​of the diagonal elements of the orthogonal upper triangular matrix, generating Lyapunov exponent spectra under different fixed-point configurations for subsequent analysis.

[0032] The Lyapunov exponent is a crucial indicator for determining whether the chaotic properties of a chaotic system have degraded. In this embodiment, Q is used respectively. 12.16 Q 12.20 And Q 12.24 The Lyapunov exponents of chaotic sequences derived under three different fixed-point number schemes were solved, and the following were generated: Figure 3 The Lyapunov index spectrum is shown below; Figure 3 In the diagram, (a), (b), and (c) represent Q respectively. 12.16 Q 12.20 And Q 12.24 Lyapunov exponent spectrum under fixed-point configuration.

[0033] Table 2 shows Q 12.16 Q 12.20 And Q 12.24 The convergence values ​​of the Lyapunov exponent under three different fixed-point number schemes after stabilization.

[0034] Table 2. Lyapunov exponential convergence values ​​under three different fixed-point number schemes. S4, arrange the fixed-point number formats in the candidate set of fixed-point number configurations in ascending order of decimal width, and determine whether the Lyapunov exponent spectrum satisfies the preset system chaotic state condition; when the system chaotic state condition is satisfied, calculate the maximum Lyapunov exponent gain corresponding to the fixed-point number formats with adjacent decimal widths; based on the comparison result of the maximum Lyapunov exponent gain and the preset gain threshold, determine whether the accuracy improvement has entered a plateau period, and determine the fixed-point number formats in the plateau period as satisfying the chaos preservation constraint; By observing different fixed-point number formats (such as those based on precision Q), 12.16 To Q 12.24 (Observation) to determine the chaotic state of the system. For example, determining it based on the Lyapunov exponent, using Q... 12.20 and Q 12.24 When formatting, because ,and The system meets the conditions for being in a hyperchaotic state; while using Q... 12.16 hour The system is in a chaotic state and its characteristics have already significantly degraded. Based on the system state analysis, the maximum Lyapunov exponent of the chaotic system is extracted, and the results are calculated for different bit-width fixed-point number formats (e.g., the fixed-point number format changes from Q...). 12.16 Change to Q 12.20 , or by Q 12.20 Change to Q 12.24 ), the specific difference (i.e. gain) in the increase of the maximum Lyapunov exponent.

[0035] Define chaos preservation constraints and introduce a profit increase / decrease criterion mechanism; specifically, set a gain determination threshold (e.g.) When the gain of the maximum Lyapunov exponent exceeds this threshold, the improvement in chaotic properties is considered significant; if the increase in gain does not exceed the threshold after the accuracy is improved, the improvement is considered insignificant, and the accuracy gain enters a plateau. The preceding sequence (e.g., Q) corresponds to this plateau. 12.20 This means that the format is deemed to meet the chaos-preserving constraint.

[0036] In this embodiment, observation Figure 3 As can be seen from Table 2, the fixed-point number format uses Q 12.20 as well as Q12.24 When formatting, ,and ,and and At this point, the chaotic system is in a hyperchaotic state, indicating that when the chaotic system is deployed on an FPGA using Euler's algorithm, it also exhibits the same chaotic characteristics. However, when using Q in a fixed-point format... 12.16 When formatting, you can observe this from Table 1. ,and At this point, the chaotic system is not in a hyperchaotic state but in a chaotic state. Compared to using Q... 12.20 and Q 12.24 For fixed-point formats, Q is used. 12.16 The chaotic properties are significantly degraded in fixed-point formats. A threshold is also set as follows: = When the gain of the maximum Lyapunov exponent exceeds this threshold, the chaotic properties are considered to have improved significantly; otherwise, it is considered to have entered a plateau phase. The maximum Lyapunov exponent of the chaotic system can be observed in Table 2. When the fixed-point number format is Q 12.16 Change to Q 12.20 At this point, the increase in the largest Lyapunov exponent exceeds the threshold, and the chaotic characteristics of the chaotic system become significantly more stable. However, when the fixed-point scheme uses Q... 12.24 At that time, compared to Q 12.20 The increase in the maximum Lyapunov exponent did not exceed the threshold, indicating that the improvement in chaotic properties was not particularly significant at this point.

[0037] To ensure the method's universal applicability and high reproducibility for fixed-point deployment of arbitrary dynamical chaotic systems, the construction of the candidate set follows strict quantitative derivation mathematical constraints.

[0038] First, a high-precision full-time dynamics simulation of the target chaotic system is performed using a double-precision floating-point architecture, capturing the maximum absolute value of the state variables in all dimensions of the system along the entire convergent attractor orbit. To ensure that fixed-point numbers do not overflow when performing large-scale continuous multiplication and addition operations internally in the hardware, this method establishes the sum of the widths of the sign bit and the integer bits. The general derivation equation: in, For the floor function, adding 1 reserves one bit for the sign bit of a signed number. The reserved safety margin bit width for the underlying hardware dynamic range (taken as an integer from 1 to 4).

[0039] Fixed integer bits After that, the decimal places width Within the range defined by hardware and dynamics boundaries Within, with a preset minimum resolution step size Perform a one-dimensional linear space scan. The lower bound of the interval is... The failure precision required to maintain the minimum chaotic characteristics of a chaotic system is determined by the upper limit of the interval. The maximum signed bit width of the input multiplier built into a single DSP hard core in the target hardware platform is uniquely limited.

[0040] This method employs a closed-loop automatic collision mechanism between "multi-dimensional hardware resource vectors" and "nonlinear dynamic indicators" supported by an automated master control script. The specific execution flow is as follows: The main control script determines the decimal width based on the current iteration. The script automatically modifies FPGA project parameters and calls hardware synthesis tools for background compilation. After compilation, the script accurately parses the generated resource utilization report, seamlessly extracting the resource consumption quantities of LUTs, FFs, and DSPs, and encapsulating them into a three-dimensional hardware resource consumption vector. Simultaneously, the collaborative verification platform receives the fixed-point sequence exported from the FPGA simulation, restores it to floating-point numbers using a fixed-point scaling formula, and automatically removes unstable transient data from the front end. Then, it calculates the system's maximum Lyapunov exponent for the current sequence. And the exponential gain compared to the previous bit width. .

[0041] The main control script will receive each time The data is summarized and automatically filtered twice: 1. Fixed-point number formats that do not meet the chaos condition are directly removed. 2. Among the qualified configurations, those that, although the decimal width is increased, have a minimal maximum Lyapunov exponent gain (less than...). The configuration range of ), which means that the chaotic system has entered a "plateau period".

[0042] S5. Among all fixed-point number formats that satisfy the chaos preservation constraint, select the fixed-point number format with the smallest hardware resource consumption data value as the target configuration, and deploy the chaotic system to the FPGA with the target configuration.

[0043] Based on the comprehensive characteristic assessment and hardware consumption results, among the candidate set that meets the chaos-preserving constraint, the joint optimization objective is to minimize the use of limited hardware resources (e.g., the number of DSPs used). The final output is the solution that satisfies the requirements under the Lyapunov exponent constraint and minimizes DSP resource configuration (e.g., Q). 12.20 This is used as the target configuration for the final implementation deployment of the FPGA.

[0044] Furthermore, the configurable fixed-point precision selection and chaos-preserving detection method for FPGAs described in this invention is applicable to scenarios requiring the generation of highly complex chaotic sequences or keystreams with controllable hardware overhead, such as lightweight encryption and scrambling for image / voice / data links, physical layer secure communication, random number / pseudo-random sequence generation, and FPGA-side reconfigurable security modules. This chaotic system can be integrated into the FPGA system as an independent "IP core" and work collaboratively with the host computer MATLAB verification platform to achieve a closed-loop process of "offline evaluation—online deployment."

[0045] The chaotic IP core runs in real-time at an extremely high clock frequency within the FPGA, outputting a key stream sequence. The FPGA is equipped with a data buffer module that, during continuous operation, extracts a fixed-length real-time fixed-point key stream sequence at preset time intervals, stores it in a FIFO, and periodically transmits it back to the host computer's backend monitoring system via a high-speed data interface. The host computer then calculates the Lyapunov metric to confirm whether the chaotic system has degraded. If the condition is not met, the host computer immediately triggers and writes a chaotic hold-state abnormality alarm flag to the FPGA's underlying control register via a customized fixed-point format configuration register bus. Upon detecting this alarm flag, the FPGA's control logic immediately triggers a reset logic to reset the chaotic system's initial value, or dynamically switches to a higher-precision fixed-point number format from the candidate set by overwriting the data written to the register, thereby forcing the system off its periodic trajectory and re-entering a safe, highly complex chaotic attractor state.

[0046] In terms of interfaces, the chaotic system provides an initialization interface at the input end to write the initial state. The system provides control parameters and a fixed-point format configuration register to select the number of decimal places. This configuration can be written via a custom register bus. The output terminal outputs four state variables or their selected segments as a key stream according to the iteration clock cycle, which can be exported via a FIFO or logic analysis interface for Vivado simulation or online testing. For ease of engineering application, the invention also provides a chaotic state flag and anomaly alarm interface. When the Lyapunov exponent criterion is not met or the sequence enters a periodic / degenerate trend, the flag is triggered, facilitating system reset of initial values ​​or switching of fixed-point configuration.

[0047] Example 2 This embodiment proposes a configurable fixed-point accuracy selection and chaos-preserving detection device for FPGAs, including: Candidate configuration construction unit: Constructs a fixed-point number configuration candidate set for a chaotic system, wherein the fixed-point number configuration candidate set includes fixed-point number formats with different decimal widths; Resource and sequence acquisition unit: The chaotic system is comprehensively verified by using each fixed-point number format in the candidate set of fixed-point number configurations, the hardware resource consumption data of the FPGA under the corresponding fixed-point number format is obtained, and the fixed-point chaotic sequence is exported. Exponential spectrum calculation unit: Calculates the derived fixed-point chaotic sequence to obtain the corresponding Lyapunov exponential spectrum; Constraint determination unit: Arranges each fixed-point number format in the candidate set of fixed-point number configurations in ascending order of decimal width, and determines whether the Lyapunov exponent spectrum satisfies the preset system chaotic state condition; when the system chaotic state condition is satisfied, calculates the maximum Lyapunov exponent gain corresponding to the fixed-point number formats with adjacent decimal widths; based on the comparison result of the maximum Lyapunov exponent gain and the preset gain threshold, determines whether the accuracy improvement has entered a plateau period, and determines the fixed-point number formats in the plateau period as satisfying the chaos preservation constraint; Screening and Deployment Unit: Among all fixed-point number formats that satisfy the chaos preservation constraints, select the fixed-point number format with the smallest hardware resource consumption data value as the target configuration, and deploy the chaotic system to the FPGA with the target configuration.

[0048] The methods of the present invention can be implemented in hardware, firmware, or as software or computer code that can be stored in a recording medium (such as a CD-ROM, RAM, floppy disk, hard disk, or magneto-optical disk), or as computer code originally stored on a remote recording medium or a non-transitory machine-readable medium and subsequently stored on a local recording medium, downloaded via a network. Thus, the methods described herein can be processed by software stored on a recording medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware (such as an ASIC or FPGA). It is understood that the computer, processor, microprocessor controller, or programmable hardware includes storage components (e.g., RAM, ROM, flash memory, etc.) capable of storing or receiving software or computer code that, when accessed and executed by the computer, processor, or hardware, implements the methods described herein. Furthermore, when a general-purpose computer accesses the code used to implement the methods shown herein, the execution of the code transforms the general-purpose computer into a dedicated computer for performing the methods shown herein.

[0049] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claimed invention.

Claims

1. A configurable fixed-point accuracy selection and chaos-preserving detection method for FPGAs, characterized in that, Includes the following steps: Construct a candidate set of fixed-point number configurations for a chaotic system, wherein the candidate set of fixed-point number configurations includes fixed-point number formats with different decimal widths; The chaotic system is comprehensively verified using each fixed-point number format in the candidate set of fixed-point number configurations, the hardware resource consumption data of the FPGA under the corresponding fixed-point number format is obtained, and the fixed-point chaotic sequence is exported. The derived fixed-point chaotic sequence is calculated to obtain the corresponding Lyapunov exponent spectrum; Arrange the fixed-point number formats in the candidate set of fixed-point number configurations in ascending order of decimal width, and determine whether the Lyapunov exponent spectrum satisfies the preset system chaotic state condition; when the system chaotic state condition is satisfied, calculate the maximum Lyapunov exponent gain corresponding to the fixed-point number formats with adjacent decimal widths; based on the comparison result of the maximum Lyapunov exponent gain and the preset gain threshold, determine whether the accuracy improvement has entered a plateau period, and determine the fixed-point number formats in the plateau period as satisfying the chaos preservation constraint; Among all fixed-point number formats that satisfy the chaos preservation constraint, the fixed-point number format with the smallest hardware resource consumption data value is selected as the target configuration, and the chaotic system is deployed to the FPGA with the target configuration.

2. The configurable fixed-point accuracy selection and chaos-preserving detection method for FPGAs according to claim 1, characterized in that, Before constructing the candidate set of fixed-point configurations for the chaotic system, the process also includes: using the Euler algorithm to calculate and discretize the parameters of the continuous four-dimensional hyperchaotic Lüszcz system equations in the time domain according to a preset sampling interval, thereby generating a discrete chaotic system model.

3. The configurable fixed-point accuracy selection and chaos-preserving detection method for FPGAs according to claim 1, characterized in that, The process of obtaining the Lyapunov index spectrum includes: Perform a numerical fixed-point scaling operation on the fixed-point chaotic sequence; The data of the fixed-point chaotic sequence at the front end of the preset iteration step size is truncated to remove the transient sequence; For the stable fixed-point chaotic sequence after stripping the transient sequence, the Lyapunov exponents of the system state variables are calculated dimension by dimension to generate the Lyapunov exponent spectrum containing the system's maximum Lyapunov exponent.

4. The configurable fixed-point accuracy selection and chaos-preserving detection method for FPGAs according to claim 1, characterized in that, The process of determining whether the improvement in accuracy has reached a plateau includes: Among the fixed-point number formats with adjacent decimal places, the format with the lower decimal place width is designated as the first fixed-point number format, and the format with the higher decimal place width is designated as the second fixed-point number format. Extract the system's maximum Lyapunov exponent corresponding to the first fixed-point number format and the second fixed-point number format, and calculate the difference between the two as the maximum Lyapunov exponent gain. Compare whether the maximum Lyapunov exponential gain is greater than the preset gain threshold; If the maximum Lyapunov exponential gain is less than or equal to the preset gain threshold, it is determined that the precision gain of the current fractional bit width improvement has entered the plateau period, and the first fixed-point number format is determined to satisfy the chaos preservation constraint.

5. The configurable fixed-point accuracy selection and chaos-preserving detection method for FPGA according to claim 1, characterized in that, The hardware resource consumption data includes: the consumption of lookup tables, triggers, and digital signal processing units; The process of selecting the fixed-point format with the lowest hardware resource consumption data value as the target configuration includes: Obtain the number of digital signal processing units consumed for each fixed-point format in the comprehensive verification; Among all fixed-point formats that satisfy the chaos-preserving constraint, the fixed-point format with the least number of digital signal processing units is selected and locked as the target configuration.

6. The configurable fixed-point precision selection and chaos-preserving detection method for FPGA according to claim 1, characterized in that, After deploying the chaotic system to the FPGA in the target configuration, the method further includes: The target configuration decimal places are written to the FPGA through a customized fixed-point format configuration register bus, and multiple fixed-point chaotic sequences are output according to the iterative clock cycle. The multi-channel fixed-point chaotic sequence output by the FPGA during continuous operation is fed back to the collaborative verification platform to detect the Lyapunov exponent spectrum state of the sequence; If the Lyapunov exponent spectrum calculation result based on the collaborative verification platform does not meet the preset conditions for a hyperchaotic state or exhibits periodic degradation characteristics, a chaotic state abnormality alarm flag is triggered and written to the FPGA via the fixed-point format configuration register bus.

7. The configurable fixed-point accuracy selection and chaos-preserving detection method for FPGA according to claim 6, characterized in that, The preset conditions for the hyperchaotic state include: at least two Lyapunov exponents in the Lyapunov exponent spectrum are greater than zero, and the sum of all Lyapunov exponents is less than zero.

8. The configurable fixed-point precision selection and chaos-preserving detection method for FPGA according to claim 6, characterized in that, The detection method further includes: performing a reset of the initial value of the chaotic system based on the written chaotic hold-state abnormal alarm flag signal, or switching the currently used fixed-point number format by overwriting the data written to the fixed-point format configuration register.

9. A configurable fixed-point precision selection and chaos-preserving detection device for FPGAs, comprising performing the method according to any one of claims 1-8, including: Candidate configuration construction unit: Constructs a fixed-point number configuration candidate set for a chaotic system, wherein the fixed-point number configuration candidate set includes fixed-point number formats with different decimal widths; Resource and sequence acquisition unit: The chaotic system is comprehensively verified by using each fixed-point number format in the candidate set of fixed-point number configurations, the hardware resource consumption data of the FPGA under the corresponding fixed-point number format is obtained, and the fixed-point chaotic sequence is exported. Exponential spectrum calculation unit: Calculates the derived fixed-point chaotic sequence to obtain the corresponding Lyapunov exponential spectrum; Constraint determination unit: Arranges each fixed-point number format in the candidate set of fixed-point number configurations in ascending order of decimal width, and determines whether the Lyapunov exponent spectrum satisfies the preset system chaotic state condition; when the system chaotic state condition is satisfied, calculates the maximum Lyapunov exponent gain corresponding to the fixed-point number formats with adjacent decimal widths; based on the comparison result of the maximum Lyapunov exponent gain and the preset gain threshold, determines whether the accuracy improvement has entered a plateau period, and determines the fixed-point number formats in the plateau period as satisfying the chaos preservation constraint; Screening and Deployment Unit: Among all fixed-point number formats that satisfy the chaos preservation constraints, select the fixed-point number format with the smallest hardware resource consumption data value as the target configuration, and deploy the chaotic system to the FPGA with the target configuration.

10. An electronic device, characterized in that, include: The processor, memory, communication interface, and communication bus are provided, wherein the processor, memory, and communication interface communicate with each other via the communication bus. The memory is used to store at least one executable instruction that causes the processor to perform the operation corresponding to the configurable fixed-point precision selection and chaos-preserving detection method for FPGA as described in any one of claims 1-8.

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