Fast charging protocol test system, method and electronic device

Abstract

Embodiments of the present application relate to the technical field of chip testing, and specifically relate to a fast charging protocol testing system and method and electronic equipment. A fast charging protocol testing system includes a test platform, a main control module, and a fast charging protocol control module. The test platform is configured to place a chip under test and initiate a start test signal. The main control module is configured to generate a test instruction in response to the start test signal. The fast charging protocol control module is configured to obtain and parse the test instruction to obtain parsed information, configure a level threshold based on the parsed information, perform protocol communication testing on the chip under test based on the level threshold, obtain identity information and a test state identifier, and transmit the test state identifier and the identity information to the main control module to cause the main control module to obtain a test result in response to the test state identifier and an identity result in response to the identity information. Embodiments of the present application shorten the cycle of testing UFCS protocol application communication processes, thereby shortening the cycle of product mass production testing development.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, and in particular to a fast charging protocol testing system, method and electronic device. Background Technology

[0002] With the development of UFCS (Universal Fast Charging Specification) fast charging protocol technology, more and more charging and discharging devices such as mobile phones, vehicles, and power banks are compatible with the UFCS fast charging protocol. These devices achieve fast charging by applying UFCS fast charging power supply chips. In this context, the reliability of UFCS fast charging power supply chip applications is particularly important.

[0003] Typically, UFCS fast charging power supply chips undergo analog and digital testing via FT (Final Test) before leaving the factory. However, conventional UFCS protocol testing solutions are developed using ATE (Automatic Test Equipment), which only covers the test protocol-related analog circuits and digital scans, failing to fully test the UFCS protocol application communication process. Furthermore, developing and testing the UFCS protocol application communication process using ATE is time-consuming, impacting the product mass production testing development cycle. Summary of the Invention

[0004] One objective of this application is to provide a fast charging protocol testing system, method, and electronic device to improve the technical problem that the long cycle of testing the communication process of the UFCS protocol application in related technologies affects the cycle of product mass production testing and development.

[0005] This application provides a fast charging protocol testing system, comprising: a test platform configured to place a chip under test (DUT) and initiate a start test signal; a main control module electrically connected to the test platform and configured to generate a test command in response to the start test signal; and a fast charging protocol control module electrically connected to the main control module and configured to acquire and parse the test command to obtain parsed information, configure a level threshold based on the parsed information, perform protocol communication testing on the DUT based on the level threshold to obtain identity information and a test status identifier, and transmit the test status identifier and the identity information to the main control module, so that the main control module obtains a test result in response to the test status identifier and obtains an identity result in response to the identity information.

[0006] Optionally, in a first implementation of the first aspect of this application, the fast charging protocol control module is configured to perform protocol communication testing on the chip under test based on the level threshold to obtain identity information and test status identifier, including: performing fast charging protocol identification on the chip under test based on the level threshold to obtain a protocol identification signal; obtaining identity information based on the protocol identification signal and the level threshold; and obtaining a test status identifier based on the identity information and the level threshold.

[0007] Optionally, in a second implementation of the first aspect of this application, the fast charging protocol control module is configured to perform fast charging protocol identification on the chip under test based on the level threshold to obtain a protocol identification signal, including: performing handshake detection on the chip under test to obtain a handshake status signal, the handshake status signal including a handshake success signal; and performing fast charging protocol identification in response to the handshake status signal being a handshake success signal to obtain a protocol identification signal.

[0008] Optionally, in the third implementation of the first aspect of this application, the fast charging protocol control module is configured to perform fast charging protocol identification and obtain a protocol identification signal in response to a handshake status signal that is a handshake success signal. This includes: in response to a handshake status signal that is a handshake success signal, sending a probe identification message to the chip under test based on a preset standard threshold, so that the chip under test sends a first response confirmation message based on the probe identification message. The probe identification message is used to detect whether the chip under test can parse the fast charging protocol, and the first response confirmation message is used to characterize that the chip under test supports parsing the fast charging protocol; receiving the first response confirmation message based on a preset standard threshold, performing fast charging protocol identification, and obtaining a protocol identification signal.

[0009] Optionally, in the fourth implementation of the first aspect of this application, the level threshold includes a minimum input threshold and a minimum output threshold. The fast charging protocol control module is configured to obtain identity information based on the protocol identification signal and the level threshold, including: sending an information acquisition request to the chip under test based on the minimum input threshold, so that the chip under test replies with a second response confirmation message and device information based on the information acquisition request; and receiving the second response confirmation message and the device information based on the minimum output threshold, wherein the device information includes identity information.

[0010] Optionally, in the fifth implementation of the first aspect of this application, the level threshold includes a maximum input threshold and a maximum output threshold. The fast charging protocol control module is configured to obtain a test status identifier based on the identity information and the level threshold, including: sending an output capability acquisition request to the chip under test based on the maximum input threshold, so that the chip under test replies with a third response confirmation message and an output capability message based on the output capability acquisition request; and receiving the third response confirmation message and the output capability message based on the maximum output threshold, wherein the output capability message includes the test status identifier.

[0011] Optionally, in the sixth implementation of the first aspect of this application, the chip under test includes multiple signal channels, and the fast charging protocol test system further includes: a multi-channel signal switching module, which is electrically connected to the chip under test and the main control module respectively, and is configured to switch the target signal channel of the chip under test to the next signal channel in response to a first control signal sent by the main control module.

[0012] Optionally, in the seventh implementation of the first aspect of this application, the fast charging protocol testing system further includes: a power supply module configured to supply power to the fast charging protocol testing system; and a power switch module electrically connected to the main control module and the fast charging protocol control module, configured to turn on or off the power supply module in response to a second control signal from the main control module.

[0013] A second aspect of this application provides a fast charging protocol testing method, applied to the fast charging protocol testing system described above. The fast charging protocol testing method includes: placing a chip under test (DUT) in a test platform to initiate a start test signal, wherein the DUT includes multiple signal channels; generating a test instruction in response to the start test signal; acquiring and parsing the test instruction to obtain parsed information; configuring a level threshold based on the parsed information; performing a protocol communication test on the DUT based on the level threshold to obtain identity information and a test status identifier; and transmitting the test status identifier and the identity information to a main control module, so that the main control module obtains a test result in response to the test status identifier and an identity result in response to the identity information.

[0014] A third aspect of this application provides an electronic device including a memory and a processor, the memory being connected to the processor, the processor being configured to execute one or more computer programs stored in the memory, wherein when the processor executes the one or more computer programs, the electronic device implements the fast charging protocol testing method described above.

[0015] The embodiments of this application achieve the following technical effects: These embodiments solve the problem that traditional ATE product testing only covers analog circuits and digital SCAN, failing to fully test the UFCS protocol application communication process. The fast charging protocol control module in this application executes the entire UFCS protocol communication interaction based on configured level thresholds, comprehensively detecting protocol business processes such as handshake communication and device identity reading, effectively detecting latent defects in protocol interactions, and improving the reliability of UFCS fast charging power chip products. This application relies on a dedicated fast charging protocol control module to carry out protocol parsing and interaction logic, eliminating the need for complex customized development for ATE devices, shortening the testing cycle of the UFCS protocol application communication process, and significantly shortening the development cycle of mass production product testing solutions, accelerating product mass production deployment. Employing a dual-dimensional verification mechanism of test status identification and identity information, the main control module separately completes communication link qualification judgment and device identity compliance verification, distinguishing between hardware path failures and firmware ID burning anomalies, reducing missed detections and misjudgments caused by a single judgment standard, and improving the accuracy of test results. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application; Figure 2 A schematic diagram of a fast charging protocol testing system provided in this application embodiment; Figure 3 A schematic diagram of a fast charging protocol testing system provided in another embodiment of this application; Figure 4 A schematic diagram of a fast charging protocol testing system provided in another embodiment of this application; Figure 5 A flowchart illustrating a fast charging protocol testing method provided in an embodiment of this application; Figure 6 This is a schematic diagram of the structure of an electronic device provided in another embodiment of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0019] It should be noted that, unless there is a conflict, the various features in the embodiments of this application can be combined with each other, all of which are within the protection scope of this application. Furthermore, although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than the module division in the device or the order in the flowchart. Moreover, the terms "first," "second," and "third" used in this application do not limit the data or execution order, but only distinguish identical or similar items with essentially the same function and effect.

[0020] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items.

[0021] Please see Figure 1 This application provides an electronic device 100, including a fast charging protocol testing system 11. The electronic device 100 is an automatic testing fixture for finished fast charging chips or a portable fast charging protocol tester, integrating the fast charging protocol testing system 11. The electronic device 100 is used for finished product testing of UFCS (Universal Fast Charging Specification) power chips and verification of protocol functions of R&D samples. It can completely execute the UFCS full protocol communication process testing, and simultaneously complete communication link status verification and device identity information verification. It makes up for the shortcomings of traditional ATE equipment, which cannot fully cover UFCS protocol application interaction and has a long development cycle. It realizes efficient screening of fast charging chip protocol-related defective products. ATE (Automatic Test Equipment) is the quality inspection center of chip mass production. Under the unified control of a computer, it performs high-speed and automatic digital + analog + mixed signal testing on packaged chips (DUT), determines good and bad products and sorts them. It is the core hardware of FT (Final Test). The UFCS protocol relies on USB D+ / D- (DPDM) differential lines to complete serial port protocol communication.

[0022] Please see Figure 2 This application also provides a fast charging protocol testing system 11, which includes a testing platform 111, a main control module 112, and a fast charging protocol control module 113.

[0023] Test platform 111 is configured to place chip under test 114 and initiate a test start signal. Test platform 111 is a channel resource of ATE equipment, initiating a test start signal and receiving test success and test failure flags. Test platform 111 communicates with chip under test 114 and controls chip under test 114 to perform UFCS protocol testing.

[0024] The main control module 112 is electrically connected to the test platform 111 and is configured to generate test commands in response to a start test signal. The main control module 112 sends test commands and protocol identification information to the fast charging protocol control module 113 via IIC communication. It performs protocol tests on high, typical, and low communication I / O level thresholds as required, and determines the UFCS protocol ID of the chip under test 114 during the handshake process. Furthermore, the main control module 112 also acts as a firmware upgrade intermediary, switching the firmware required for the test to the fast charging protocol control module 113 at any time to adapt to the complexity of test firmware under different applications and better optimize costs as needed. After the test is completed, the main control module 112 feeds back the test success or failure result to the test platform 111 via I / O. IIC (Inter-Integrated Circuit) is a low-speed communication bus between the main control module 112 and the fast charging protocol control module 113. It is used to transmit control commands, configuration parameters, and test data back between the two. It is the communication channel for the system to send control parameters and upload test data. IO (Input / Output) refers to the hardware input / output pins of the fast charging protocol control module 113 used for DPDM differential signal transmission and reception, which are divided into transmit IO (TX) and receive IO (RX).

[0025] The fast charging protocol control module 113 is electrically connected to the main control module 112 and is configured to acquire and parse test commands to obtain parsed information, configure a level threshold based on the parsed information, perform protocol communication tests on the chip under test 114 based on the level threshold, obtain identity information and test status identifier, and transmit the test status identifier and identity information to the main control module 112 so that the main control module 112 obtains the test result in response to the test status identifier and obtains the identity result in response to the identity information.

[0026] In some embodiments, the fast charging protocol control module 113 includes an IP2723T chip, which receives test commands issued by the main control module 112 and parses the parsed information, including level threshold values ​​and test process parameters. It dynamically configures multiple IO level threshold values, simulates the UFCS power supply to complete the entire protocol communication process including Ping handshake, device information reading, and output capability interaction, collects the identity information and test status identifier of the chip under test 114, and sends the identity information and test status identifier back to the main control module 112. The level threshold values ​​are the high and low voltage judgment criteria for DPDM differential communication specified by the UFCS protocol, divided into Source standard threshold, minimum input threshold, minimum output threshold, maximum input threshold, and maximum output threshold, used to control the amplitude of the output waveform and identify the logic level of the received message. Protocol communication testing refers to the fast charging protocol control module 113 sequentially executing the entire message interaction process based on different level threshold values, including Ping message sending, ACK response identification, and device identity and power parameter acquisition. The test status identifier refers to the communication link judgment signal output by the fast charging protocol control module 113, which is divided into a test pass identifier and a test failure identifier. It is used to characterize whether the UFCS handshake and message transmission and reception communication between the chip under test 114 and the fast charging protocol control module 113 are normal. The identity information refers to the device identification data uploaded by the chip under test 114 through the UFCS protocol. Its core includes parameters such as the unique UFCS device ID, manufacturer code, and protocol version, used to verify whether the chip firmware is correctly and compliantly burned. The test result refers to the communication link judgment conclusion generated by the main control module 112 based on the test status identifier, used to distinguish hardware communication failures such as DPDM hardware disconnection and protocol stack failure. The identity result refers to the verification conclusion obtained by the main control module 112 after comparing the received actual identity information with the internally pre-stored standard baseline ID, used to determine whether the ID of the chip under test 114 is burned incorrectly or missing.

[0027] The chip under test 114 is placed on the test platform 111, and the test platform 111 is operated to initiate a test start signal. The main control module 112 receives the test start signal, generates a test instruction carrying multiple level threshold parameters, a standard reference ID, and a test process timing, and sends it to the fast charging protocol control module 113. The fast charging protocol control module 113 receives and parses the test instruction, extracts various level threshold configuration parameters, and completes the voltage judgment threshold configuration of the internal TX transmission path and RX reception path. The fast charging protocol control module 113 switches the level thresholds in stages to perform a complete UFCS protocol communication test. After the protocol communication test is completed, the fast charging protocol control module 113 uploads the test status identifier and the measured identity information of the chip under test 114 to the main control module 112. The main control module 112 executes a dual verification logic: it determines whether the communication link is intact based on the test status identifier and generates a test result; it compares the measured identity information with the locally stored standard protocol ID to determine whether the ID is compliant and generates an identity result; the two results are combined to obtain the comprehensive quality inspection conclusion of the chip under test 114.

[0028] This application addresses the problem that traditional ATE (Automatic Test Equipment) product testing only covers analog circuits and digital SCAN, failing to fully test the UFCS protocol application communication process. This application's embodiment utilizes a fast charging protocol control module 113, based on configured level thresholds, to completely execute the entire UFCS protocol communication interaction. This comprehensively detects protocol business processes such as handshake communication and device identity reading, effectively detecting latent defects in protocol interactions and improving the reliability of UFCS fast charging power chip products upon delivery. This application's embodiment relies on a dedicated fast charging protocol control module 113 to handle protocol parsing and interaction logic, eliminating the need for complex customized development for ATE equipment. This shortens the testing cycle for the UFCS protocol application communication process and significantly reduces the development cycle of mass production product testing solutions, accelerating product mass production deployment. Employing a dual-dimensional verification mechanism of test status identification and identity information, the main control module 112 separately completes communication link qualification judgment and device identity compliance verification. This distinguishes between hardware path failures and firmware ID burning anomalies, reducing missed detections and misjudgments caused by a single judgment standard and improving the accuracy of test results. This application embodiment dynamically switches multiple level thresholds through the fast charging protocol control module 113 to fully simulate three real working conditions: UFCS power supply standard, low voltage boundary, and high voltage boundary. It can detect hidden defects that ATE cannot identify, such as DPDM driver abnormality, protocol stack failure, and ID burning error, thus ensuring the reliability of the fast charging chip at the factory.

[0029] In some embodiments, the fast charging protocol control module 113 is configured to perform protocol communication testing on the chip under test 114 based on a level threshold to obtain identity information and test status identifier, including: performing fast charging protocol identification on the chip under test 114 based on a level threshold to obtain a protocol identification signal, obtaining identity information based on the protocol identification signal and the level threshold, and obtaining a test status identifier based on the identity information and the level threshold.

[0030] The protocol identification signal is the judgment signal output by the fast charging protocol control module 113 after simulating the UFCS power supply and completing the Ping handshake detection. It is used to characterize whether the handshake interaction was successful and is a pre-entry signal for entering the identity information reading process. The protocol identification signal has two states: protocol identification success and protocol identification failure. Fast charging protocol identification relies on the level threshold to perform the handshake detection process of Ping message sending and ACK response identification, completing the pre-check of the compatibility between the communication link of the chip under test 114 and the UFCS protocol. Ping message sending refers to the fast charging protocol control module 113 simulating the UFCS power supply, loading the standard input level threshold, and outputting a Ping probe message to the DPDM differential channel of the chip under test 114 through TX IO, which is used to actively detect the communication path and protocol support capabilities of the chip under test 114. ACK response identification refers to the chip under test 114 receiving the Ping message and outputting an ACK response message after verifying that it is correct.

[0031] This application's embodiments do not rely solely on a single handshake result to determine the overall quality. Instead, it uses a three-layer linkage mechanism—handshake identification, identity information acquisition, and full-level message interaction—to generate the final test status identifier, forming a multi-level verification mechanism. This prevents products from being released that are normal in one aspect but fail in other communication levels, thus improving chip reliability before shipment. The protocol communication test is broken down into three logical layers: protocol identification, identity acquisition, and status determination. Each step is independently associated with a corresponding level threshold. When replacing different models of the UFCS chip under test, only the corresponding level threshold needs to be modified; there is no need to reconstruct the entire test process, making the fast charging protocol test system 11 more versatile.

[0032] In some embodiments, the fast charging protocol control module 113 is configured to perform fast charging protocol identification on the chip under test 114 based on a level threshold to obtain a protocol identification signal, including: performing handshake detection on the chip under test 114 to obtain a handshake status signal, the handshake status signal including a handshake success signal, and performing fast charging protocol identification in response to the handshake status signal being a handshake success signal to obtain a protocol identification signal.

[0033] Handshake detection refers to the process by which the fast charging protocol control module 113 simulates the UFCS power supply and performs a complete set of interactive detection actions, including sending Ping messages and recognizing ACK responses, using standard thresholds. This is used to verify the DPDM communication path and the basic UFCS protocol capabilities of the chip under test 114. The handshake status signal is the judgment signal output after the handshake detection is completed, divided into a handshake success signal and a handshake failure signal; it is used to characterize whether the Ping-ACK interaction is completed normally. The handshake success signal is the signal generated by the fast charging protocol control module 113 when it recognizes a compliant ACK response message within the timing window, indicating that the DPDM path is intact and the chip under test 114 can parse the UFCS Ping message.

[0034] The fast charging protocol control module 113 loads the standard input and output level thresholds of the power supply side and initiates handshake detection: TX IO sends a Ping message, and RX IO continuously samples the feedback level of the chip under test 114, identifying the ACK response within a specified timeout window. A handshake status signal is generated based on the ACK response identification result. Successfully captured a compliant ACK and output a handshake success signal; If no valid ACK is detected, a handshake failure signal is output, and the entire protocol process is terminated directly.

[0035] The fast charging protocol control module 113 detects the handshake status signal. Only when the signal is a successful handshake signal will the subsequent fast charging protocol identification process be started and a protocol identification signal be generated. If the signal is a failed handshake signal, the protocol identification and identity information collection steps will be skipped, and a failed test status identifier will be generated and uploaded to the main control module 112 directly.

[0036] This application's embodiment sets handshake detection as the first-level pre-inspection. Severe defects such as open circuits in hardware and missing protocol stacks directly output handshake failure signals, eliminating the need for subsequent protocol identification and high / low voltage boundary tests. This significantly reduces the testing time for a single chip and optimizes the production line's testing cycle. Separating the basic Ping handshake and complete protocol identification into two levels of judgment can distinguish between two types of faults: handshake failure corresponds to DPDM hardware path damage or lack of UFCS protocol; protocol identification failure corresponds to low-voltage level decoding and abnormal message interaction. This facilitates rapid fault location on the production line and reduces the difficulty of chip retrospective analysis. The complete protocol identification process is only initiated after the communication link and basic protocol functions meet the standards, avoiding repeated invalid operations such as multi-level switching and message transmission / reception by the hardware-failed chip, reducing module resource consumption, and extending equipment lifespan.

[0037] In some embodiments, the fast charging protocol control module 113 is configured to perform fast charging protocol identification in response to a handshake success signal, and obtain a protocol identification signal. This includes: in response to a handshake success signal, sending a probe identification message to the chip under test 114 based on a preset standard threshold, so that the chip under test 114 sends a first response confirmation message based on the probe identification message. The probe identification message is used to detect whether the chip under test 114 can parse the fast charging protocol, and the first response confirmation message is used to characterize that the chip under test 114 supports parsing the fast charging protocol. The module receives the first response confirmation message based on the preset standard threshold, performs fast charging protocol identification, and obtains the protocol identification signal.

[0038] The standard threshold refers to the standard input level threshold and standard output level threshold of the UFCS power supply terminal. These standard thresholds are dedicated level parameters for the handshake phase, used to constrain the output waveform of the detection and identification message and to determine the level reference for the received acknowledgment message. The standard input level threshold is the level reference for the transmit IO of the fast charging protocol control module 113 TX, corresponding to a high level of 3.3V and a low level of 0V. It is used to control the amplitude of the differential waveform of the transmitted message, simulating the transmission of detection messages under normal operating conditions of a real adapter. The standard output level threshold is the voltage judgment threshold for the receive IO of the fast charging protocol control module 113 RX, used to transmit the first acknowledgment message (ACK message) from the chip under test during the handshake phase, corresponding to a high level of 3.3V and a low level of 0V.

[0039] The detection and identification message refers to the Ping message, which is actively sent by the fast charging protocol control module 113 simulating the power supply end. It is used to detect whether the chip under test 114 has the ability to parse the UFCS protocol. The first response confirmation message refers to the ACK message in the handshake phase. The first response confirmation message is the response message fed back by the chip under test 114 after it has completely parsed the detection and identification message and verified that it is correct. It means that the chip under test 114 can normally recognize the UFCS protocol message.

[0040] The fast charging protocol control module 113 first completes the handshake detection and outputs a handshake status signal; only when a successful handshake signal is detected will this stage of the detection and identification process be initiated. The fast charging protocol control module 113 retrieves a preset standard threshold to configure its own TX IO, generates a detection and identification message according to the standard 3.3V high level and 0V low level encoding, and sends it to the DPDM differential channel of the chip under test 114. The chip under test 114 acquires the differential signal and verifies the frame header and CRC checksum of the detection and identification message; if all verifications pass, it indicates that the chip under test 114 can parse the UFCS protocol and outputs a first response confirmation message based on the same set of standard levels; if the message is distorted, the level is offset, or the verification fails, no response message is output.

[0041] The fast charging protocol control module 113 acquires the feedback level of the chip under test 114 by matching a preset standard threshold through RX IO, and determines whether a compliant first response confirmation message exists within a preset response timing window. If a valid first response confirmation message is successfully identified, the basic UFCS protocol parsing function of the chip under test 114 is determined to be normal, and a valid protocol identification signal is output; if no response is identified, the protocol identification is determined to have failed, an failure signal is generated, and the subsequent identity information and output capability testing process is terminated.

[0042] Only chips under test (DUTs) 114 with intact DPDM hardware pathways and fault-free basic communication will enter the detection and identification process. Chips that fail to handshake will have their testing terminated immediately, eliminating the need for message transmission and reception operations, thus shortening the testing time for a single chip and improving production line efficiency. Through one-to-one message exchange, the system specifically detects whether the DUT 114 is equipped with a usable UFCS protocol parser, identifying functional defects that traditional ATE digital / analog tests cannot cover, such as missing protocol firmware or disabled protocol functions, thereby improving chip reliability. The same standard level threshold is used for both probe message transmission and response message reception, and the output waveform amplitude is matched to the reception judgment threshold, reducing missed response identification and misinterpretation caused by circuit noise and minute level drift, thus improving the accuracy of fast charging protocol identification. Faults can be divided into two categories: no successful handshake signal (damaged DPDM hardware pathway) and successful handshake but no first response confirmation message (normal hardware but abnormal protocol stack). This allows staff to quickly locate the root cause of the failure, reducing the cost of chip retesting and fault analysis. The detection and identification messages and the first response confirmation messages follow the unified UFCS standard timing and level specifications. When replacing different specifications of the chip under test 114, only the threshold parameters need to be fine-tuned, without the need to reconstruct the protocol identification logic, making the system more versatile.

[0043] In some embodiments, the level threshold includes a minimum input threshold and a minimum output threshold. The fast charging protocol control module 113 is configured to obtain identity information based on the protocol identification signal and the level threshold, including: sending an information acquisition request to the chip under test 114 based on the minimum input threshold, so that the chip under test 114 replies with a second response confirmation message and device information based on the information acquisition request; and receiving the second response confirmation message and device information based on the minimum output threshold. The device information includes identity information.

[0044] The minimum input threshold refers to the low-voltage boundary reception level standard specified by the UFCS protocol. It is the voltage amplitude reference used by the fast charging protocol control module 113 TX IO when sending messages, corresponding to a high level of 1.4V and a low level of 0V. It is used to simulate low-voltage extreme conditions such as adapter light load and line voltage drop. The minimum output threshold refers to the low-voltage boundary transmission level standard specified by the UFCS protocol. It is the voltage judgment threshold for the fast charging protocol control module 113 RX IO to identify the feedback signal of the chip under test 114, corresponding to a high level of 2.56V and a low level of 0V. It is used to distinguish logic 0 and logic 1 under low-voltage conditions. The information acquisition request refers to the query message sent by the fast charging protocol control module 113 after successful protocol recognition. It is used to request the chip under test 114 to report its own device parameters and is an instruction message for reading identity information. The second response confirmation message refers to the response frame fed back by the chip under test 114 after completely parsing the information acquisition request message. It indicates that the message reception and parsing under low voltage is normal and informs the test module that device information can be transmitted. Device information refers to the complete set of parameter data packets uploaded by the chip under test 114 according to the UFCS protocol. The data packet contains information such as the manufacturer code, chip unique ID, and protocol version. Identity information refers to the core identification field in the device information data packet, which is the unique identification ID of the chip under test 114 and is used by the main control module 112 to verify whether the firmware burning is correct and compliant.

[0045] The fast charging protocol control module 113 only switches the level setting and uses the minimum input threshold and minimum output threshold to execute the device information reading process after receiving a valid protocol recognition signal; if protocol recognition fails, this step is skipped. The fast charging protocol control module 113 uses the minimum input threshold to configure the TX IO, outputting a differential waveform of 1.4V high and 0V low, and sends an information request message to the chip under test 114. The chip under test 114 parses the request message under low voltage, completing the frame header and CRC check. The fast charging protocol control module 113 switches the RX IO to the minimum output threshold, continuously acquiring differential signals, first recognizing the second response confirmation message, and then receiving the complete device information after confirming the response is valid. Core identity information is extracted from the parsed device information data packet, cached in the module register, and awaited upload to the main control module 112 via IIC for identity verification.

[0046] This application embodiment uses minimum input threshold and minimum output threshold to reproduce low-voltage operating scenarios, enabling the detection of the message transmission and decoding capabilities of the chip under test (114) when the voltage margin is insufficient. It detects hidden defects that ATE (Automatic Test Equipment) cannot find, such as insufficient IO drive and protocol decoding failure under low voltage, thus improving the completeness of test coverage. The second response confirmation message is identified before reading device information, providing double confirmation that low-voltage message parsing is normal. This prevents erroneous acquisition of device information due to low-voltage level drift and waveform distortion, ensuring accurate and reliable identity information acquisition. The standard threshold only completes handshake identification, while the minimum output threshold separately verifies the identity reading function. This distinguishes between two types of faults: a normal handshake at the standard threshold but no response / device information at the minimum output threshold, accurately locating low-voltage communication performance defects in the chip and facilitating production line defect analysis. Device information includes multiple parameters; the identity information is separately extracted and uploaded. The main controller can directly compare it with the standard ID, quickly completing firmware flashing compliance determination and simplifying the main controller's verification logic.

[0047] In some embodiments, the level threshold includes a maximum input threshold and a maximum output threshold. The fast charging protocol control module 113 is configured to obtain a test status identifier based on the identity information and the level threshold, including: sending a request to acquire output capability to the chip under test 114 based on the maximum input threshold, so that the chip under test 114 replies with a third response confirmation message and an output capability message based on the request to acquire output capability, and receiving the third response confirmation message and the output capability message based on the maximum output threshold. The output capability message includes the test status identifier.

[0048] The maximum input threshold refers to the high-voltage boundary reception level standard specified by the UFCS protocol, used to configure the fast charging protocol control module 113 TX IO to output a differential message waveform with a high voltage of 3.85V and a low voltage of 0.99V, simulating the adapter's high-voltage heavy-load extreme communication conditions. The maximum output threshold refers to the high-voltage boundary transmission level standard specified by the UFCS protocol, used to configure the fast charging protocol control module 113 RX IO, using a high voltage of 3.6V and a low voltage of 0.5V as logic level distinction thresholds to complete message sampling and parsing under high-voltage conditions. The "Obtain Output Capability Request" refers to the power query message sent by the fast charging protocol control module 113 after reading the identity information, used to request the chip under test 114 to report parameters such as the fast charging voltage, current, and power level it supports. The third response confirmation message refers to the response frame output by the chip under test 114 after parsing the "Obtain Output Capability Request" under high-voltage conditions and verifying its accuracy, indicating that message recognition is normal under high-voltage conditions and it is ready to upload power parameters. The output capability message refers to the power parameter data packet fed back by the chip under test 114, which includes all fast charging capability parameters such as supported voltage range, current limit value, and maximum power.

[0049] After successfully acquiring valid identity information, the fast charging protocol control module 113 switches to the maximum input threshold and maximum output threshold to initiate the high-voltage boundary condition test. If identity information acquisition fails, a failure test status flag is directly generated, skipping this high-voltage interaction process. The fast charging protocol control module 113 configures TX IO to the maximum input threshold, outputs a high-voltage differential waveform, and sends an output capability request message to the chip under test 114. The chip under test 114 completes message frame header and CRC verification under high-voltage conditions. If the verification passes, it sequentially outputs a third response confirmation message and a complete output capability message. If there is high-voltage level offset, waveform distortion, or decoding abnormality, no valid message feedback is provided. The fast charging protocol control module 113 configures RX IO to the maximum output threshold, samples the differential signal within a preset timing window, first identifies the third response confirmation message, and after confirming that the high-voltage communication path is normal, it completely receives and parses the output capability message.

[0050] The system integrates all interaction results across three levels of operating conditions: standard threshold Ping handshake, minimum threshold device information reading, and maximum threshold output capability interaction. A unified test status identifier is generated based on the completeness of the output capability message parsing. Failure is indicated by message loss, level mismatch, or verification error at any stage. Success is indicated by all three stages of normal interaction. Subsequently, the identity information and test status identifier are uploaded to the main control module 112 via IIC. High-voltage interaction simultaneously verifies high-voltage communication capabilities and the integrity of the chip power configuration firmware. Hardware path, protocol decoding, ID burning, and power parameter detection are completed synchronously within the same process, improving the overall testing efficiency of a single chip and shortening the production line testing cycle.

[0051] Please see Figure 3 In some embodiments, the chip under test 114 includes multiple signal channels, and the fast charging protocol test system 11 further includes a multi-channel signal switching module 115, which is electrically connected to the chip under test 114 and the main control module 112 respectively, and is configured to switch the target signal channel of the chip under test 114 to the next signal channel in response to the first control signal sent by the main control module 112.

[0052] Multiple signal channels refer to the multiple independent DPDM differential communication channels mounted on the chip under test (DUT) 114. Each signal channel corresponds to a fast charging output port, and each channel is independent of the others, all capable of executing complete UFCS protocol communication. The multi-channel signal switching module 115 is a channel selection hardware unit controlled by the main control module 112. It integrates a multi-channel analog switch array and is responsible for time-division multiplexing the DPDM communication links between different signal channels of the DUT 114 and the fast charging protocol control module 113. The first control signal refers to the channel switching control command output by the main control module 112, which is used to notify the multi-channel signal switching module 115 to perform channel switching. The target signal channel refers to the signal channel of the DUT 114 that is currently connected to the fast charging protocol control module 113 and is performing UFCS protocol testing.

[0053] The multi-channel signal switching module 115 selects the first signal channel of the chip under test 114 as the target signal channel. The target signal channel establishes a DPDM communication link with the fast charging protocol control module 113, completing a full set of protocol tests including standard level handshake, low-voltage identity reading, and high-voltage output capability. After all test procedures for the current target signal channel are completed, the main control module 112 generates a first control signal and sends it to the multi-channel signal switching module 115. The multi-channel signal switching module 115 receives the first control signal, disconnects the current target signal channel from the fast charging protocol control module 113, and switches to the next signal channel connected to the chip under test 114, updating the next channel as the new target signal channel. After the switching is completed, the fast charging protocol control module 113 repeats the complete UFCS protocol communication test on the new target signal channel; the main control module 112 continues to send the first control signal to switch in a loop until all signal channels of the chip under test 114 have been tested. The internal analog switch of the multi-channel signal switching module 115 has isolation characteristics. During the switching process, the old channel is disconnected to avoid crosstalk between multiple DPDM signals and prevent signal interference between channels from causing test misjudgment.

[0054] After all channels have been tested, the main control module 112 returns a test success or failure flag to the test platform 111. A low level indicates the default state and a BUSY flag, a continuous high level indicates success, and a 1kHz 50% duty cycle signal indicates failure. A single fast-charging protocol control module 113 supports fully automated testing of multiple channels, saving hardware costs by eliminating the need for a separate IP2723T protocol control hardware for each signal channel of the chip under test 114. The multi-channel signal switching module 115 time-division multiplexes the same protocol test unit, significantly reducing the number of core chips and peripheral circuits, and lowering the hardware investment in mass production testing equipment. The main control module 112 automatically sends the first control signal to complete channel switching, requiring no manual intervention to switch DPDM signal lines. This enables fully automated batch testing of multi-port fast-charging chips, shortening the overall testing time for a single chip and optimizing production line cycle time. When switching between multiple signal channels, the multi-channel switching module 115 disconnects the signal link of the previous channel, isolating the differential levels of different signal channels. This prevents interference between DP / DM signals caused by multiple channels being powered on simultaneously, avoiding misjudgments such as handshake failure and message parsing errors, and ensuring accurate and reliable test results for each channel. The number of cycles of the first control signal issued by the main control module can be flexibly adjusted according to the number of signal channels of the chip under test (114). It is compatible with UFCS fast charging chips with different port specifications, such as 2-channel, 3-channel, and 4-channel, allowing one testing system to adapt to multiple product models and expand the applicable scenarios of the equipment. The channel switching action is uniformly scheduled by the main control module 112, which can record the identity information and test status identifier of each signal channel. If a channel fails the test, the corresponding faulty port can be accurately located, facilitating port-by-port fault analysis of defective chips on the production line.

[0055] Please see Figure 4 In some embodiments, the fast charging protocol testing system 11 further includes a power supply module 116 and a power switch module 117. The power supply module 116 is configured to supply power to the fast charging protocol testing system 11, and the power switch module 117 is electrically connected to the main control module 112 and the fast charging protocol control module 113 respectively, and is configured to turn on or off the power supply module 116 in response to a second control signal from the main control module 112.

[0056] Power supply module 116 is the power supply unit for the entire fast charging protocol test system 11. It outputs a stable DC operating voltage to provide power to all hardware units, including the main control module 112, fast charging protocol control module 113, and multi-signal switching module 115. Power supply module 116 outputs a low-voltage +3.3V power supply to the VCC of fast charging protocol control module 113. Power switch module 117 is a controlled on / off circuit unit connected in series between the power supply module 116 and the power supply circuit of fast charging protocol control module 113. It receives level / command type second control signals from the main control module 112 to enable controllable power-on and power-off of fast charging protocol control module 113. The second control signal refers to the power on / off control command output by the main control module 112, which controls the power switch module 117 to perform power-on or power-off operations. The power switch module 117 is implemented using a MOS combination switching circuit or a relay. In the UFCS protocol test, the main control module 112 controls the power supply to and from the fast charging protocol control module 113 by controlling the CH.

[0057] The power supply module 116 continuously outputs a stable voltage to power the main control module 112 and the multi-channel signal switching module 115, ensuring that the main control module is always in a schedulable state. When it is necessary to start the UFCS protocol test of the chip under test 114, the main control module 112 generates a second control signal of the conduction type and sends it to the power switch module 117; after receiving the signal, the power switch module 117 conducts the circuit, and the power supply module 116 supplies power to the fast charging protocol control module 113. The fast charging protocol control module 113 starts and sequentially performs a full set of protocol tests, including channel switching, Ping handshake, reading identity information, and detecting output capability. When a single signal channel test is completed, all channel tests are completed, or an abnormal fault is detected, the main control module 112 outputs a second control signal of the disconnect type; the power switch module 117 responds to the signal and cuts off the power supply circuit of the fast charging protocol control module 113, and the fast charging protocol control module 113 is powered off and stops working. If a fault such as DPDM short circuit or abnormal level occurs during the test, the main controller can immediately send a second control signal to quickly cut off the power supply of the fast charging protocol control module 113 to avoid damage to the fast charging protocol control module 113 and the chip under test 114 due to overcurrent or overvoltage.

[0058] The fast charging protocol control module 113 is powered only during the testing phase, and its power is cut off during idle and channel switching phases to reduce unnecessary power consumption. This is suitable for long-term continuous operation of the production line and saves equipment power. When faults such as communication short circuits or abnormal levels occur, the main control module 112 can quickly shut off the power supply to the fast charging protocol control module 113 through the second control signal, promptly cutting off the abnormal power supply circuit and preventing overcurrent from burning out the fast charging protocol control module 113 and the chip under test 114, thereby reducing equipment wear and product scrap rate. After a single-channel test is completed, the fast charging protocol control module 113 can be restarted by power-off, clearing the residual register level parameters of the previous channel, avoiding interference from the level threshold and message buffer of the previous channel to the test of the next channel, eliminating cross-contamination of test data between channels, and improving the accuracy of multi-channel testing.

[0059] Please see Figure 5 This application embodiment also provides a fast charging protocol testing method, applied to the fast charging protocol testing system 11 as described above. The fast charging protocol testing method includes the following steps S101 to S106: S101. Place the chip under test 114 in the test platform 111 so that the test platform 111 initiates a start test signal. The chip under test 114 includes multiple signal channels. S102. In response to the start test signal, generate test instructions; S103. Obtain and parse the test command to get the parsed information; S104. Configure the level threshold based on the parsed information; S105. Perform protocol communication test on the chip under test 114 based on the level threshold to obtain identity information and test status identifier; S106. Transmit the test status identifier and identity information to the main control module 112, so that the main control module 112 obtains the test result in response to the test status identifier and obtains the identity result in response to the identity information.

[0060] A chip under test (DUT) 114 with multiple DPDM signal channels is fixed on a test platform 111. The multiple signal channels of the DUT 114 are connected to a multi-signal switching module 115. Upon sensing the arrival of the DUT 114, the test platform 111 automatically generates and sends a start test signal to the main control module 112, initiating the entire test process. The main control module 112 receives the start test signal, retrieves locally pre-stored UFCS standard thresholds, ID, and channel switching timing parameters, and integrates and encapsulates them into a complete test instruction. Simultaneously, the main control module 112 can issue a second control signal as needed to turn on the power switch module 117, powering on the fast charging protocol control module 113. The main control module 112 sends the test instruction to the fast charging protocol control module 113 via the IIC bus. The fast charging protocol control module 113 reads the instruction data packet, performs data verification, decodes it, and extracts various level thresholds, test process timing, and other parsing information. The fast charging protocol control module 113 writes the standard, minimum, and maximum input / output thresholds from the parsed information into the corresponding registers of TX IO and RX IO, completing the initialization of the voltage judgment benchmark for the transmission and reception paths, and preparing the hardware configuration for the phased protocol interaction. It loads the standard level thresholds, executes Ping message sending and ACK recognition, completes the fast charging protocol handshake detection, and generates a protocol identification signal; if the handshake fails, it directly generates a failure test status identifier and skips subsequent steps; if the handshake succeeds, it switches the minimum input and minimum output thresholds, sends an information acquisition request, receives a second response confirmation message and device information, and extracts identity information from the device information; after successfully acquiring identity information, it switches the maximum input and maximum output thresholds, sends an output capability query request, and receives a third response confirmation message and output capability message; it integrates all message transmission and verification results from the three stages of standard threshold handshake, low-voltage threshold identity reading, and high-voltage threshold power interaction to uniformly generate a test status identifier.

[0061] If the current channel test is completed, the main controller sends the first control signal to control the multi-channel signal switching module 115 to switch to the next signal channel, repeating steps S104 to S105 until all signal channels of the chip under test 114 have been tested.

[0062] The fast charging protocol control module 113 uploads the current channel's identity information and test status identifier to the main control module 112 via IIC. The main control module 112 performs dual verification: it generates test results based on the test status identifier to determine if there are hardware or protocol faults in the UFCS communication link; it compares the measured identity information with the local standard ID to generate an identity result and determine if the chip firmware is correctly burned. The main control module stores the test results and identity results corresponding to each signal channel and summarizes them to obtain the overall quality inspection conclusion of the chip under test 114. After all channels have been tested, the main control module sends a second control signal to cut off the power supply to the fast charging protocol control module 113, completing the single chip complete testing process.

[0063] This application embodiment automates the entire process from chip under test (DUT) 114 loading and triggering the test, instruction generation, protocol interaction to result determination. Multiple channels are automatically polled and switched, eliminating the need for manual wiring and level parameter configuration. This significantly reduces the testing time for a single multi-channel fast charging chip and is suitable for large-scale FT (Fixed-Time) finished product testing scenarios in factories. All level thresholds and test parameters are uniformly encapsulated in the test instructions. Replacing different models of the UFCS DUT 114 only requires modifying the pre-stored threshold parameters in the main controller; no modification to the overall test method is needed. One set of test logic adapts to multiple fast charging chip specifications. It should be noted that in the above embodiments, there is no necessarily a certain order between the steps. Those skilled in the art can understand from the description of the embodiments of this application that the above steps may have different execution orders in different embodiments, that is, they may be executed in parallel or in turn, etc.

[0064] Please see Figure 6 The electronic device 100 includes one or more processors 12 and a memory 13. The memory 13 is connected to one or more processors 12, for example, via a bus.

[0065] Processor 12 is configured to support the electronic device 100 in performing the corresponding functions in the methods described in the above method embodiments. Processor 12 may be a central processing unit (CPU), a network processor (NP), a hardware chip, or any combination thereof. The aforementioned hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The aforementioned PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0066] Memory 13 is used to store program code, etc. Memory 13 may include volatile memory (VM), such as random access memory (RAM); memory 13 may also include non-volatile memory (NVM), such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid-state drive (SSD); memory 13 may also include combinations of the above types of memory 13.

[0067] The memory 13 can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules corresponding to the fast charging protocol testing method in the embodiments of this application. The processor 12 executes the fast charging protocol testing method by running the non-volatile software programs, instructions, and modules stored in the memory 13, thereby implementing the fast charging protocol testing method provided in the above method embodiments.

[0068] The memory 13 may include a program storage area and a data storage area, wherein the program storage area may store the operating system and application programs required for at least one function. In some embodiments, the memory 13 may optionally include a memory 13 remotely located relative to the processor 12. Examples of the aforementioned networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0069] One or more modules are stored in memory 13. When executed by one or more processors 12, they execute the fast charging protocol testing method in any of the above method embodiments. For example, they execute the method steps described in the above method embodiments to realize the functions of the modules described in the above device embodiments.

[0070] This application also provides a computer-readable storage medium storing a computer program, the computer program including program instructions, which, when executed by an electronic device 100, cause the electronic device 100 to perform the method as described in the foregoing embodiments.

[0071] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0072] The above-disclosed embodiments are merely preferred embodiments of this application and should not be construed as limiting the scope of this application. Therefore, any equivalent variations made in accordance with the claims of this application shall still fall within the scope of this application.

Claims

1. A fast charging protocol testing system, characterized in that, include: The test platform is configured to place the chip under test and initiate a test start signal; The main control module, electrically connected to the test platform, is configured to generate test commands in response to the start test signal; The fast charging protocol control module, electrically connected to the main control module, is configured to acquire and parse the test command to obtain parsed information, configure a level threshold based on the parsed information, perform protocol communication test on the chip under test based on the level threshold, obtain identity information and test status identifier, and transmit the test status identifier and the identity information to the main control module so that the main control module obtains the test result in response to the test status identifier and obtains the identity result in response to the identity information.

2. The fast charging protocol testing system according to claim 1, characterized in that, The fast charging protocol control module is configured to perform protocol communication tests on the chip under test based on the level threshold, and obtain identity information and test status identifiers, including: Based on the stated level threshold, fast charging protocol identification is performed on the chip under test to obtain a protocol identification signal; Based on the protocol identification signal and the level threshold, identity information is obtained; Based on the identity information and the level threshold, a test status identifier is obtained.

3. The fast charging protocol testing system according to claim 2, characterized in that, The fast charging protocol control module is configured to perform fast charging protocol identification on the chip under test based on the level threshold, and obtain a protocol identification signal, including: A handshake detection is performed on the chip under test to obtain a handshake status signal, which includes a handshake success signal. In response to the handshake status signal being a successful handshake, fast charging protocol identification is performed to obtain the protocol identification signal.

4. The fast charging protocol testing system according to claim 3, characterized in that, The fast charging protocol control module is configured to perform fast charging protocol identification in response to a handshake success signal, and obtain a protocol identification signal, including: In response to a handshake status signal indicating a successful handshake, a probe and identification message is sent to the chip under test based on a preset standard threshold, so that the chip under test sends a first response confirmation message based on the probe and identification message. The probe and identification message is used to detect whether the chip under test can parse the fast charging protocol, and the first response confirmation message is used to characterize that the chip under test supports parsing the fast charging protocol. The first response confirmation message is received based on a preset standard threshold, and fast charging protocol identification is performed to obtain a protocol identification signal.

5. The fast charging protocol testing system according to claim 2, characterized in that, The level threshold includes a minimum input threshold and a minimum output threshold. The fast charging protocol control module is configured to obtain identity information based on the protocol identification signal and the level threshold, including: Based on the minimum input threshold, a request to obtain information is sent to the chip under test, so that the chip under test replies with a second response confirmation message and device information based on the request to obtain information. The second response confirmation message and the device information, including identity information, are received based on the minimum output threshold.

6. The fast charging protocol testing system according to claim 2, characterized in that, The level threshold includes a maximum input threshold and a maximum output threshold. The fast charging protocol control module is configured to obtain a test status identifier based on the identity information and the level threshold, including: Based on the maximum input threshold, a request to acquire output capability is sent to the chip under test, so that the chip under test replies with a third response confirmation message and an output capability message based on the request to acquire output capability. The third response confirmation message and the output capability message are received based on the maximum output threshold, wherein the output capability message includes a test status identifier.

7. The fast charging protocol testing system according to any one of claims 1 to 6, characterized in that, The chip under test includes multiple signal channels, and the fast charging protocol testing system also includes: The multi-channel signal switching module is electrically connected to both the chip under test and the main control module, and is configured to switch the target signal channel of the chip under test to the next signal channel in response to a first control signal sent by the main control module.

8. The fast charging protocol testing system according to claim 7, characterized in that, The fast charging protocol testing system also includes: The power supply module is configured to supply power to the fast charging protocol test system; The power switch module is electrically connected to both the main control module and the fast charging protocol control module, and is configured to turn the power supply module on or off in response to a second control signal from the main control module.

9. A fast charging protocol testing method, characterized in that, The fast charging protocol testing method, applied to the fast charging protocol testing system as described in any one of claims 1 to 8, comprises: The chip under test is placed in the test platform so that the test platform initiates a test start signal. The chip under test includes multiple signal channels. In response to the start test signal, a test command is generated; The test command is acquired and parsed to obtain parsed information; Configure the level threshold based on the parsed information; Based on the level threshold, a protocol communication test is performed on the chip under test to obtain identity information and test status identifier; The test status identifier and the identity information are transmitted to the main control module, so that the main control module obtains the test result in response to the test status identifier and obtains the identity result in response to the identity information.

10. An electronic device, characterized in that, Includes the fast charging protocol testing system as described in any one of claims 1 to 8.

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