Communication detection circuit, chip and electronic device

Abstract

A communication detection circuit, chip and electronic device belong to the technical field of electronic circuit, including pull-up circuit and two detection units connected to the first node, the detection unit includes capacitor assembly, amplifier circuit and first switch circuit; the communication polarity signal after AC coupling of the capacitor assembly is output to the amplifier circuit in another detection unit, so that the amplifier circuit in another detection unit amplifies the communication polarity signal after AC coupling to output the first amplified signal to the amplifier circuit in the detection unit; the amplifier in the detection unit amplifies the first amplified signal to output the second amplified signal; the first switch circuit outputs a trigger signal through the first node in response to the second amplified signal being greater than the first preset value; therefore, the static power consumption of the communication detection circuit is reduced, and the layout area is reduced.

Description

Technical Field

[0001] This application belongs to the field of electronic circuit technology, and in particular relates to a communication detection circuit, chip and electronic device. Background Technology

[0002] In modern battery management systems (BMS), especially those used in high-voltage electric vehicles and grid-scale energy storage systems, BMS integrated circuits must maintain extremely high energy efficiency while managing complex battery packs. To minimize long-term standby power consumption, these integrated circuits often operate in sleep or shutdown mode, but must also remain "always on standby" to be immediately woken up when they detect signal activity on communication lines such as the controller area network (CAN) bus or daisy-chain protocol.

[0003] Related communication detection circuits typically employ constant bias differential comparators, Schmitt trigger buffers, or topologies that first pass through a resistor attenuation network before being connected to an active amplifier stage. While these traditional architectures can provide high sensitivity and accurate timing for signal detection, they suffer from a fundamental contradiction: a trade-off between power consumption and interference immunity.

[0004] Specifically, the relevant communication detection circuits require continuous biasing, resulting in high static current and continuous "parasitic power consumption," which can deplete the battery during long-term storage. These key defects restrict the operating efficiency of ultra-low power systems.

[0005] From an integration perspective, the technology of using AC coupling capacitors to block DC offset requires a large chip area to withstand the full voltage swing, which significantly increases the cost of the die and the complexity of manufacturing.

[0006] Therefore, the related communication detection circuits have high static power consumption and large chip layout area. Summary of the Invention

[0007] The purpose of this application is to provide a communication detection circuit, chip, and electronic device, which aims to solve the problems of high static power consumption and large chip layout area in related communication detection circuits.

[0008] This application provides a communication detection circuit for outputting a trigger signal based on an incoming communication signal; the communication detection circuit includes a pull-up circuit connected to a first node and two detection units. The pull-up circuit is configured to pull up the voltage of the first node; The detection unit includes: A capacitor assembly is configured to AC couple the communication polarity signal and output the AC-coupled communication polarity signal to an amplification circuit in another detection unit, so that the amplification circuit in the other detection unit amplifies the AC-coupled communication polarity signal to output a first amplified signal to its own amplification circuit in the detection unit. The connection between the amplification circuit in the detection unit itself and the capacitor assembly and the amplification circuit in another detection unit is configured to amplify the first amplified signal to output a second amplified signal; A first switching circuit is connected to the amplifier circuit and is configured to output a trigger signal via a first node in response to the second amplified signal being greater than a first preset value. The communication signal includes two communication polarity signals; the two communication polarity signals have opposite or the same polarity.

[0009] In one embodiment, it further includes: A Schmitt trigger, connected to the first switching circuit, is configured to perform waveform shaping on the trigger signal to output the waveform-shaped trigger signal.

[0010] In one embodiment, the Schmitt trigger includes an inverter, a first PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a first capacitor; The source of the first PMOS transistor, the substrate of the first PMOS transistor, and the power supply terminal of the inverter are all connected to the first power supply. The gate of the first PMOS transistor, the gate of the first NMOS transistor, and the first terminal of the first capacitor are connected and together form the input terminal of the Schmitt trigger, which is connected to the two detection units to receive the trigger signal; The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor and the input terminal of the inverter. The source of the first NMOS transistor is connected to the drain of the second NMOS transistor, the gate of the second NMOS transistor, and the drain of the third NMOS transistor. The substrates of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the second terminal of the first capacitor C1, the source of the second NMOS transistor, and the source of the third NMOS transistor N3 are all connected to the power supply ground. The output terminal of the inverter U1 and the gate of the third NMOS transistor N3 are connected and together form the output terminal of the Schmitt trigger to output the waveform-shaped trigger signal.

[0011] In one embodiment, the detection unit further includes; The second switching circuit, connected to the capacitor assembly, is configured to output the trigger signal in response to the communication polarity signal being greater than a second preset value.

[0012] In one embodiment, the detection unit further includes; The first clamping circuit is connected to the capacitor assembly and is configured to clamp the voltage difference between the communication polarity signal and the power supply ground, so as to output the clamped communication polarity signal. The capacitor assembly is specifically configured to perform AC coupling on the clamped communication polarity signal.

[0013] In one embodiment, the detection unit further includes; The second clamping circuit, connected to the capacitor assembly, is configured to clamp the voltage difference between the communication polarity signal and the voltage of the first node, so as to output the clamped communication polarity signal. The capacitor assembly is specifically configured to perform AC coupling on the clamped communication polarity signal.

[0014] In one embodiment, the second clamping circuit includes a second PMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor; The source of the second PMOS transistor forms the input terminal of the second clamping circuit and is connected to the first node to receive the voltage of the first node. The gate of the second PMOS transistor is connected to the drain of the second PMOS transistor, the gate of the fourth NMOS transistor is connected to the drain of the fourth NMOS transistor, the source of the fourth NMOS transistor is connected to the drain of the fifth NMOS transistor, and the gate of the fifth NMOS transistor is connected to the power supply ground. The substrate of the fourth NMOS transistor, the substrate of the fifth NMOS transistor, and the source of the fifth NMOS transistor constitute the input and output terminals of the second clamping circuit, which are connected to the capacitor assembly to receive the communication polarity signal and output the clamped communication polarity signal.

[0015] In one embodiment, the amplifier circuit includes a sixth NMOS transistor and a first resistor; The drain of the sixth NMOS transistor and the first end of the first resistor are connected to form the output terminal of the amplifier circuit, which is connected to the amplifier circuit, the capacitor assembly and the first switch circuit in another detection unit to output the second amplified signal of the detection unit itself and the first amplified signal of the other detection unit. The gate of the sixth NMOS transistor forms the input terminal of the amplifier circuit and is connected to the amplifier circuit in another detection unit to receive the first amplified signal of the detection unit itself and the communication polarity signal after AC coupling of the other detection unit. The substrate of the sixth NMOS transistor, the source of the sixth NMOS transistor, and the second terminal of the first resistor are all connected to the power supply ground.

[0016] This invention also provides a chip, which includes the communication detection circuit described above.

[0017] This invention also provides an electronic device, which includes the communication detection circuit described above.

[0018] The beneficial effects of this invention compared to the prior art are as follows: Since the communication detection circuit includes a pull-up circuit connected to the first node and two detection units, the capacitor component performs AC coupling on the communication polarity signal and outputs the AC-coupled communication polarity signal to the amplification circuit in the other detection unit. This allows the amplification circuit in the other detection unit to amplify the AC-coupled communication polarity signal and output a first amplified signal to its own detection unit's amplification circuit. The amplification circuit in its own detection unit amplifies the first amplified signal to output a second amplified signal, causing the first switching circuit to respond when the second amplified signal exceeds a first preset value, and then output a trigger signal through the first node. Therefore, there is no need to configure a bias circuit, the circuit is no longer continuously biased, and the static current is reduced. Furthermore, the two amplification circuits are interleaved, improving the amplification factor. This allows the two amplification circuits to achieve high gain and ensure high accuracy in communication signal detection, while simplifying the hardware configuration and reducing the chip layout area. Attached Figure Description

[0019] To more clearly illustrate the technical inventions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of a communication detection circuit provided in an embodiment of this application; Figure 2 A schematic diagram of another structure of the communication detection circuit provided in one embodiment of this application; Figure 3 A schematic diagram of another structure of the communication detection circuit provided in one embodiment of this application; Figure 4 A schematic diagram of another structure of the communication detection circuit provided in one embodiment of this application; Figure 5 A schematic diagram of another structure of the communication detection circuit provided in one embodiment of this application; Figure 6 This is a partial example circuit schematic diagram of a communication detection circuit provided in an embodiment of this application. Detailed Implementation

[0021] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0022] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0023] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0024] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0025] Figure 1 A schematic diagram of the communication detection circuit provided in a preferred embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and are described in detail below: The aforementioned communication detection circuit is used to output a trigger signal based on the incoming communication signal; the communication detection circuit includes a pull-up circuit 03 connected to the first node A and two detection units (01, 02).

[0026] Pull-up circuit 03 is configured to pull up the voltage of the first node A.

[0027] The detection unit includes a capacitor assembly 10, an amplifier circuit 20, and a first switching circuit 30.

[0028] The capacitor component 10 is configured to AC couple the communication polarity signal and output the AC-coupled communication polarity signal to the amplification circuit 20 in another detection unit, so that the amplification circuit 20 in the other detection unit amplifies the AC-coupled communication polarity signal and outputs a first amplified signal to the amplification circuit 20 in its own detection unit.

[0029] The connection between the amplification circuit 20 in the self-detection unit, the capacitor assembly 10, and the amplification circuit 20 in another detection unit is configured to amplify the first amplified signal to output a second amplified signal.

[0030] The first switching circuit 30 is connected to the amplifier circuit 20 and is configured to output a trigger signal through the first node A in response to the second amplified signal being greater than the first preset value.

[0031] The communication signal includes two communication polarity signals; the two communication polarity signals have opposite polarities.

[0032] It should be noted that the two communication polarity signals can be the positive input signal VINP and the negative input signal VINN, respectively.

[0033] Through the above technical solution, since the communication detection circuit includes a pull-up circuit 03 connected to the first node A and two detection units, the capacitor component 10 performs AC coupling on the communication polarity signal and outputs the AC-coupled communication polarity signal to the amplification circuit 20 in the other detection unit. This allows the amplification circuit 20 in the other detection unit to amplify the AC-coupled communication polarity signal and output a first amplified signal to the amplification circuit 20 in its own detection unit. The amplification circuit 20 in its own detection unit amplifies the first amplified signal and outputs a second amplified signal, causing the first switching circuit 30 to respond to the second amplified signal being greater than a first preset value and outputting a trigger signal through the first node A. Therefore, there is no need to configure a bias circuit, the circuit is no longer continuously biased, and the static current is reduced. Furthermore, the two amplification circuits 20 are interleaved, which improves the amplification factor. This allows the two amplification circuits 20 to achieve high gain and ensure high accuracy in communication signal detection, while simplifying the hardware configuration and reducing the chip layout area.

[0034] like Figure 2 As shown, the communication detection circuit also includes a Schmitt trigger 04.

[0035] Schmitt trigger 04 is connected to the first switching circuit 30 and is configured to perform waveform shaping on the trigger signal to output the waveform-shaped trigger signal.

[0036] The above technical solution shapes the waveform of the trigger signal, thereby improving the anti-interference capability and stability of the communication detection circuit.

[0037] like Figure 3 As shown, the detection unit also includes a second switching circuit 40.

[0038] The second switching circuit 40 is connected to the capacitor assembly 10 and is configured to output a trigger signal in response to a communication polarity signal being greater than a second preset value.

[0039] Through the above technical solution, when the communication polarity signal is greater than the second preset value, the second switching circuit 40 is controlled to output a trigger signal, which adapts to the large signal communication polarity signal and expands the application scenarios of the communication detection circuit.

[0040] like Figure 4 As shown, the detection unit also includes a first clamping circuit 50.

[0041] The first clamping circuit 50 is connected to the capacitor assembly 10 and is configured to clamp the voltage difference between the communication polarity signal and the power supply ground so as to output the clamped communication polarity signal. The capacitor assembly 10 is specifically configured to perform AC coupling on the clamped communication polarity signal.

[0042] The related communication detection circuits usually do not have sufficient high voltage withstand capability and cannot withstand the typical high-frequency AC common-mode stress under harsh automotive conditions. Large voltage transients may cause dielectric breakdown or latch-up effects in standard complementary metal oxide semiconductor (CMOS) gate circuits.

[0043] The above technical solution clamps the voltage difference between the communication polarity signal and the power supply ground, making the upper limit amplitude of the clamped communication polarity signal controllable, reducing the possibility of component breakdown or latch-up in the downstream circuit, and improving the reliability of the communication detection circuit.

[0044] like Figure 5 As shown, the detection unit also includes a second clamping circuit 60.

[0045] The second clamping circuit 60 is connected to the capacitor assembly 10 and is configured to clamp the voltage difference between the communication polarity signal and the voltage of the first node A, so as to output the clamped communication polarity signal. The capacitor assembly 10 is specifically configured to perform AC coupling on the clamped communication polarity signal.

[0046] The above technical solution clamps the voltage difference between the communication polarity signal and the voltage of the first node A, making the lower limit amplitude of the clamped communication polarity signal controllable, reducing the possibility of component breakdown or latch-up in the lower stage circuit, and improving the reliability of the communication detection circuit.

[0047] Figure 6 The illustration shows a partial example circuit structure of a communication detection circuit provided in an embodiment of the present invention. For ease of explanation, only the parts related to the embodiment of the present invention are shown, and are described in detail below: The Schmitt trigger 04 includes an inverter U1, a first P-channel metal oxide semiconductor (PMOS) transistor P1, a first N-channel metal oxide semiconductor (NMOS) transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, and a first capacitor C1.

[0048] The source of the first PMOS transistor P1, the substrate of the first PMOS transistor P1, and the power supply terminal of the inverter U1 are all connected to the first power supply VCC; the gate of the first PMOS transistor P1, the gate of the first NMOS transistor N1, and the first terminal of the first capacitor C1 are connected and together form the input terminal of the Schmitt trigger 04, which is connected to two detection units to receive the trigger signal; the drain of the first PMOS transistor P1 is connected to the drain of the first NMOS transistor N1 and the input terminal of the inverter U1, and the source of the first NMOS transistor N1 is connected to the second NMOS transistor U1. The drain of N2, the gate of N2, and the drain of N3 are connected. The substrates of N1, N2, and N3, the second terminal of the first capacitor C1, the source of N2, and the source of N3 are all connected to the power supply ground. The output of inverter U1 and the gate of N3 are connected and together form the output of Schmitt trigger 04 to output the waveform-shaped trigger signal.

[0049] The second clamping circuit 60 includes a second PMOS transistor P2, a fourth NMOS transistor N4, and a fifth NMOS transistor N5.

[0050] The source of the second PMOS transistor P2 forms the input terminal of the second clamping circuit 60 and is connected to the first node A to receive the voltage of the first node A. The gate of the second PMOS transistor P2 is connected to the drain of the second PMOS transistor P2, the gate of the fourth NMOS transistor N4, and the drain of the fourth NMOS transistor N4. The source of the fourth NMOS transistor N4 is connected to the drain of the fifth NMOS transistor N5, and the gate of the fifth NMOS transistor N5 is connected to the power supply ground. The substrate of the fourth NMOS transistor N4, the substrate of the fifth NMOS transistor N5, and the source of the fifth NMOS transistor N5 form the input and output terminals of the second clamping circuit 60 and are connected to the capacitor assembly 10 to receive the communication polarity signal and output the clamped communication polarity signal.

[0051] The amplifier circuit 20 includes a sixth NMOS transistor N6 and a first resistor R1.

[0052] The drain of the sixth NMOS transistor N6 and the first end of the first resistor R1 are connected and together form the output terminal of the amplifier circuit 20, which is connected to the amplifier circuit 20, capacitor assembly 10 and first switching circuit 30 in another detection unit to output the second amplified signal of its own detection unit and the first amplified signal of the other detection unit; the gate of the sixth NMOS transistor N6 forms the input terminal of the amplifier circuit 20, which is connected to the amplifier circuit 20 in another detection unit to receive the first amplified signal of its own detection unit and the communication polarity signal after AC coupling of the other detection unit; the substrate of the sixth NMOS transistor N6, the source of the sixth NMOS transistor N6 and the second end of the first resistor R1 are connected to the power supply ground.

[0053] The first switching circuit 30 includes a seventh NMOS transistor N7; the gate of the seventh NMOS transistor N7 forms the input terminal of the first switching circuit 30, and is connected to the capacitor assembly 10 and the amplifier circuit 20 to receive the second amplified voltage; the drain of the seventh NMOS transistor N7 forms the output terminal of the first switching circuit 30, and is connected to another detection unit and the pull-up circuit 03 to output a trigger signal; the source and substrate of the seventh NMOS transistor N7 are connected to the power supply ground.

[0054] The second switching circuit 40 includes an eighth NMOS transistor N8; the gate of the eighth NMOS transistor N8 forms the input terminal of the second switching circuit 40 and is connected to the capacitor component 10 to receive a communication polarity signal; the drain of the eighth NMOS transistor N8 forms the output terminal of the second switching circuit 40 and is connected to another detection unit and the pull-up circuit 03 to output a trigger signal; the source and substrate of the eighth NMOS transistor N8 are connected to the power supply ground.

[0055] The first clamping circuit 50 includes a ninth NMOS transistor N9, a tenth NMOS transistor N10, an eleventh NMOS transistor N11, a twelfth NMOS transistor N12, a thirteenth NMOS transistor N13, and a second resistor R2.

[0056] The first end of the second resistor R2 forms the input terminal of the first clamping circuit 50 to receive the communication polarity signal; the second end of the second resistor R2, the drain of the ninth NMOS transistor N9, the gate of the ninth NMOS transistor N9, the substrate of the ninth NMOS transistor N9, and the source of the twelfth NMOS transistor N12 are connected to form the output terminal of the first clamping circuit 50 to output the clamped communication polarity signal; the source of the ninth NMOS transistor N9 is connected to the drain and gate of the tenth NMOS transistor N10, and the source of the tenth NMOS transistor N10 is connected to the... The gate of the eleventh NMOS transistor N11 is connected to the drain of the eleventh NMOS transistor N11. The gate of the twelfth NMOS transistor N12 is connected to the drain of the twelfth NMOS transistor N12, the substrate of the twelfth NMOS transistor N12, the source of the thirteenth NMOS transistor N13, and the substrate of the thirteenth NMOS transistor N13. The substrate of the tenth NMOS transistor N10, the substrate of the eleventh NMOS transistor N11, the source of the eleventh NMOS transistor N11, the gate of the thirteenth NMOS transistor N13, and the drain of the thirteenth NMOS transistor N13 are all connected to the power supply ground.

[0057] The pull-up circuit 03 includes a third resistor R3; the first end of the third resistor R3 is connected to the first power supply VCC, and the first end of the third resistor R3 is connected to the first node A.

[0058] The capacitor assembly 10 includes a second capacitor C2; the first end of the second capacitor C2 constitutes the input terminal of the capacitor assembly 10 to receive a communication polarity signal; the first end of the second capacitor C2 constitutes the output terminal of the capacitor assembly 10 to output the AC-coupled communication polarity signal.

[0059] The following is based on the working principle. Figure 6 Further explanation is provided below: The communication detection circuit includes two detection units (detection unit 01 on the left and detection unit 02 on the right).

[0060] When a communication polarity signal is connected to the detection unit 01 on the left, in each circuit module of the detection unit 01 on the left, the second resistor R2 limits the current of the communication polarity signal. Since the gate and drain of the ninth NMOS transistor N9 to the eleventh NMOS transistor N11 are connected in series, the ninth NMOS transistor N9 to the eleventh NMOS transistor N11 clamps the voltage difference between the current-limited communication polarity signal and the power supply ground (i.e., makes the current-limited communication polarity signal less than 3 times the threshold voltage of the NMOS transistor). The gate and drain of the twelfth NMOS transistor N12 to the thirteenth NMOS transistor N13 are connected in series, and clamp the voltage difference between the current-limited communication polarity signal and the power supply ground (i.e., makes the current-limited communication polarity signal less than 2 times the threshold voltage of the NMOS transistor). Similarly, the second PMOS transistor P2, the fourth NMOS transistor N4, and the fifth NMOS transistor N5 clamp the voltage difference between the communication polarity signal clamped by the first clamping circuit 50 and the voltage of the first node A, and input the clamped communication polarity signal to the first terminal of the second capacitor C2. The second capacitor C2 performs AC coupling on the clamped communication polarity signal, and the AC-coupled communication polarity signal is output to the gate of the sixth NMOS transistor N6 in the detection unit 02 on the right.

[0061] Then, in the amplification circuit 20 of the right-side detection unit 02, the sixth NMOS transistor N6 amplifies the clamped communication polarity signal to output a first amplified signal to the gate of the sixth NMOS transistor N6 in the amplification circuit 20 of the left-side detection unit 01. The amplification factor of the sixth NMOS transistor N6 in the right-side detection unit 02 is g. mN62 ·R1 2， g mN62 R12 is the transconductance of the sixth NMOS transistor N6 in the detection unit 02 on the right, and R12 is the resistance value of the first resistor R1 in the detection unit 02 on the right.

[0062] Next, in the detection unit 01 on the left, the sixth NMOS transistor N6 of the amplifier circuit 20 amplifies the first amplified signal to output a second amplified signal to the gate of the seventh NMOS transistor N7 of the first switching circuit 30 in the detection unit 01 on the left. The amplification factor of the sixth NMOS transistor N6 in the detection unit 01 on the left is g. mN61 ·R1 1， g mN61R11 represents the transconductance of the sixth NMOS transistor N6 in the left detection unit 01, and R11 represents the resistance of the first resistor R1 in the left detection unit 02. In the left detection unit 01, the seventh NMOS transistor N7 of the first switching circuit 30 responds to the second amplified signal exceeding the first preset value, turning on and outputting a trigger signal (low level) to the gates of the first PMOS transistor P1 and the first NMOS transistor N1 via the first node A. It can be understood that the sixth NMOS transistor N6 in the left detection unit 01 and the sixth NMOS transistor N6 in the right detection unit 02 are both operating in the amplification region at this time, while the seventh NMOS transistor N7 of the first switching transistor in the left detection unit 01 is operating in the saturation region. When the communication polarity signal continues to increase, the eighth NMOS transistor N8 in the left detection unit 01 turns on, thereby outputting a trigger signal (low level) to the gates of the first PMOS transistor P1 and the first NMOS transistor N1.

[0063] It should be noted that the situation where the detection unit 01 on the right is connected to a communication polarity signal is similar to the situation where the detection unit 01 on the left is connected to a communication polarity signal, and will not be described again here.

[0064] Finally, the low-level trigger signal controls the first PMOS transistor P1 to turn on and the first NMOS transistor N1 to turn off, thereby outputting a high-level first digital signal to the input of inverter U1. Inverter U1 outputs a waveform-shaped trigger signal (low level). It is worth emphasizing that when the output of inverter U1 is high (stopping the output of the waveform-shaped trigger signal), the third NMOS transistor N3 turns on, causing the second NMOS transistor N2 to stop boosting the voltage to ground, thereby reducing the voltage triggered by the falling edge of Schmitt trigger 04. Similarly, when the output of inverter U1 is low (outputting the waveform-shaped trigger signal), the third NMOS transistor N3 turns off, causing the second NMOS transistor N2 to boost the voltage to ground, thereby increasing the voltage triggered by the rising edge of Schmitt trigger 04; thus realizing the hysteresis characteristic of Schmitt trigger 04.

[0065] In this application, by connecting the substrate of the NMOS transistor to a low potential and the substrate of the PMOS transistor to a high potential, the possibility of leakage current in the NMOS transistor and PMOS transistor is reduced.

[0066] This invention also provides a chip that includes the communication detection circuit described above.

[0067] This invention also provides an electronic device that includes the communication detection circuit described above.

[0068] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0069] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A communication detection circuit, characterized in that, It is used to output a trigger signal based on the received communication signal; the communication detection circuit includes a pull-up circuit connected to the first node and two detection units. The pull-up circuit is configured to pull up the voltage of the first node; The detection unit includes: A capacitor assembly is configured to AC couple the communication polarity signal and output the AC-coupled communication polarity signal to an amplification circuit in another detection unit, so that the amplification circuit in the other detection unit amplifies the AC-coupled communication polarity signal to output a first amplified signal to its own amplification circuit in the detection unit. The connection between the amplification circuit in the detection unit itself and the capacitor assembly and the amplification circuit in another detection unit is configured to amplify the first amplified signal to output a second amplified signal; A first switching circuit is connected to the amplifier circuit and is configured to output a trigger signal via a first node in response to the second amplified signal being greater than a first preset value. The communication signal includes two communication polarity signals; the two communication polarity signals have opposite or the same polarity.

2. The communication detection circuit as described in claim 1, characterized in that, Also includes: A Schmitt trigger, connected to the first switching circuit, is configured to perform waveform shaping on the trigger signal to output the waveform-shaped trigger signal.

3. The communication detection circuit as described in claim 2, characterized in that, The Schmitt trigger includes an inverter, a first PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a first capacitor; The source of the first PMOS transistor, the substrate of the first PMOS transistor, and the power supply terminal of the inverter are all connected to the first power supply. The gate of the first PMOS transistor, the gate of the first NMOS transistor, and the first terminal of the first capacitor are connected and together form the input terminal of the Schmitt trigger, which is connected to the two detection units to receive the trigger signal; The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor and the input terminal of the inverter. The source of the first NMOS transistor is connected to the drain of the second NMOS transistor, the gate of the second NMOS transistor, and the drain of the third NMOS transistor. The substrates of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the second terminal of the first capacitor C1, the source of the second NMOS transistor, and the source of the third NMOS transistor N3 are all connected to the power supply ground. The output terminal of the inverter U1 and the gate of the third NMOS transistor N3 are connected and together form the output terminal of the Schmitt trigger to output the waveform-shaped trigger signal.

4. The communication detection circuit as described in claim 1, characterized in that, The detection unit further includes; The second switching circuit, connected to the capacitor assembly, is configured to output the trigger signal in response to the communication polarity signal being greater than a second preset value.

5. The communication detection circuit as described in claim 1, characterized in that, The detection unit further includes; The first clamping circuit is connected to the capacitor assembly and is configured to clamp the voltage difference between the communication polarity signal and the power supply ground, so as to output the clamped communication polarity signal. The capacitor assembly is specifically configured to perform AC coupling on the clamped communication polarity signal.

6. The communication detection circuit as described in claim 1, characterized in that, The detection unit further includes; The second clamping circuit, connected to the capacitor assembly, is configured to clamp the voltage difference between the communication polarity signal and the voltage of the first node, so as to output the clamped communication polarity signal. The capacitor assembly is specifically configured to perform AC coupling on the clamped communication polarity signal.

7. The communication detection circuit as described in claim 6, characterized in that, The second clamping circuit includes a second PMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor; The source of the second PMOS transistor forms the input terminal of the second clamping circuit and is connected to the first node to receive the voltage of the first node. The gate of the second PMOS transistor is connected to the drain of the second PMOS transistor, the gate of the fourth NMOS transistor is connected to the drain of the fourth NMOS transistor, the source of the fourth NMOS transistor is connected to the drain of the fifth NMOS transistor, and the gate of the fifth NMOS transistor is connected to the power supply ground. The substrate of the fourth NMOS transistor, the substrate of the fifth NMOS transistor, and the source of the fifth NMOS transistor constitute the input and output terminals of the second clamping circuit, which are connected to the capacitor assembly to receive the communication polarity signal and output the clamped communication polarity signal.

8. The communication detection circuit as described in any one of claims 1 to 7, characterized in that, The amplifier circuit includes a sixth NMOS transistor and a first resistor; The drain of the sixth NMOS transistor and the first end of the first resistor are connected to form the output terminal of the amplifier circuit, which is connected to the amplifier circuit, the capacitor assembly and the first switch circuit in another detection unit to output the second amplified signal of the detection unit itself and the first amplified signal of the other detection unit. The gate of the sixth NMOS transistor forms the input terminal of the amplifier circuit and is connected to the amplifier circuit in another detection unit to receive the first amplified signal of the detection unit itself and the communication polarity signal after AC coupling of the other detection unit. The substrate of the sixth NMOS transistor, the source of the sixth NMOS transistor, and the second terminal of the first resistor are all connected to the power supply ground.

9. A chip, characterized in that, The chip includes the communication detection circuit as described in any one of claims 1 to 8.

10. An electronic device, characterized in that, The electronic device includes a communication detection circuit as described in any one of claims 1 to 8.

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