Descriptor cache state management method, cache management unit, network card chip and network device

Abstract

The application relates to a descriptor cache state management method, a cache management unit, a network card chip and network equipment. The method comprises the following steps: in response to an access request of a receiving queue descriptor initiated by a network card chip; the receiving queue identifier and position information of the receiving queue descriptor to be accessed are carried in the access request; according to the receiving queue identifier and the position information, it is determined whether a target cache line corresponding to the receiving queue descriptor exists in a descriptor cache, and a determination result is obtained; the descriptor cache is a cache area in the network card chip, and a plurality of cache lines are stored in the cache area; and according to the determination result, the state information of the descriptor cache is updated. By using the method, the bus overhead generated by frequent reading of the host memory can be greatly reduced, the data interaction delay is reduced, and the memory management resources are saved.

Description

Technical Field

[0001] This application relates to the field of network interface card (NIC) cache management technology, and in particular to a descriptor cache state management method, cache management unit, NIC chip, and network device. Background Technology

[0002] With the popularization of virtualization technology and the continuous upgrading of network bandwidth, the size of network card queues has expanded significantly. The massive number of receive queue descriptors cannot all be stored in the static storage of the network card. Descriptor caching is usually used to achieve high-speed reading of receive queue descriptors.

[0003] In related technologies, network transmission often adopts a push mode, where the receiving end specifies a receive queue descriptor. This descriptor contains the host's storage address to store packets sent by the sending end, thus completing the reception of those packets. In this mode, to cooperate with the receiving end's Network Interface Controller (NIC) chip in receiving packets from the sending end, the receiving host needs to pre-allocate a storage area for the receive queue descriptor in its main memory. The NIC chip reads the receive queue descriptor from the host's main memory, stores it in its internal receive queue descriptor buffer, and then modifies the state of the corresponding buffer to manage the receive queue descriptor buffer's state.

[0004] However, the aforementioned state management method for the receive queue descriptor cache suffers from a significant increase in memory management resource consumption. Summary of the Invention

[0005] Therefore, it is necessary to provide a descriptor cache state management method, cache management unit, network card chip, and network device that can reduce memory management resource consumption to address the above-mentioned technical problems.

[0006] Firstly, this application provides a method for managing the state of a descriptor cache, including:

[0007] In response to an access request for the receive queue descriptor initiated by the network interface card (NIC) chip; the access request carries the receive queue identifier and location information of the receive queue descriptor to be accessed;

[0008] Based on the receive queue identifier and location information, determine whether there is a target cache line corresponding to the receive queue descriptor in the descriptor cache, and obtain the determination result; the descriptor cache is a cache area in the network card chip that stores multiple cache lines;

[0009] Based on the determined result, update the state information of the descriptor cache.

[0010] In one embodiment, determining whether a target cache line corresponding to a receive queue descriptor exists in the descriptor cache based on the receive queue identifier and location information includes:

[0011] Based on the location information, determine the target cache group where the access request is located in the descriptor cache;

[0012] The target cache line containing the access request is determined based on the receive queue identifier, location information, and cache line labels of each cache line in the target cache group.

[0013] In one embodiment, determining the target cache group where the access request resides in the descriptor cache based on the location information includes:

[0014] Obtain the mapping relationship between bit values ​​in location information and cache groups;

[0015] Based on the value of the middle bit of the location information and the mapping relationship, the target cache group where the access request is located is determined.

[0016] In one embodiment, determining the target cache group where the access request resides in the descriptor cache based on the location information includes:

[0017] The location information is hashed to obtain the target cache group index corresponding to the location information;

[0018] Determine the target cache group where the access request belongs based on the target cache group index.

[0019] In one embodiment, updating the state information of the descriptor cache based on the determination result includes:

[0020] If it is determined that the target cache line exists in the descriptor cache, update the status information of the target cache line;

[0021] If the result indicates that the target cache line does not exist in the descriptor cache, a new target cache line is determined from the descriptor cache, and the status information of the new target cache line is updated.

[0022] In one embodiment, determining a new target cache line from the descriptor cache includes:

[0023] If an invalid cache line exists in the descriptor cache, the invalid cache line will be used as the new target cache line.

[0024] If no invalid cache line exists in the descriptor cache, then a valid and free cache line in the descriptor cache will be used as the new target cache line.

[0025] In one embodiment, the aforementioned status information includes: the number of request prefetches for the cache line, and the status information for updating the target cache line includes:

[0026] Retrieve the access type of the descriptor access request; the access type includes descriptor prefetch type and descriptor read type;

[0027] If the access type is a descriptor prefetch type and the network interface card (NIC) chip successfully initiates a prefetch request, the original request prefetch count of the target cache line is incremented by 1, which is used as the current request prefetch count.

[0028] If the access type is a descriptor read type, and the descriptor to be accessed is read from the target cache line, the original request prefetch count of the target cache line is reduced by 1 to obtain the current request prefetch count.

[0029] In one embodiment, the aforementioned state information further includes: cache line status. In the case of an invalid and locked cache line, after subtracting 1 from the original request prefetch count of the target cache line to obtain the current request prefetch count, the method further includes:

[0030] If the number of request prefetches for the target cache line is 0, then the cache line status of the target cache line is set to invalid.

[0031] In one embodiment, the aforementioned state information further includes: cache line status. Before incrementing the original request prefetch count of the target cache line by a value of 1, the method further includes:

[0032] If the traversal pointer of the receiving circular queue corresponding to the target cache line reaches the end of the target cache line, then update the cache line status of the target cache line to invalid.

[0033] If the traversal pointer of the circular queue has not reached the end of the target cache line, then update the cache line status of the target cache line to the valid state.

[0034] In one embodiment, the aforementioned state information includes: cache line status, cache line label, and request prefetch count; the aforementioned state information for updating the new target cache line includes:

[0035] Update the cache line status of the new target cache line to valid;

[0036] Set the cache line label for the new target cache line based on the receive queue identifier and position information;

[0037] The number of original request prefetches for the new target cache line is increased by 1, and this number is determined as the number of new request prefetches for the new target cache line.

[0038] Secondly, this application also provides a cache management unit, including programmable logic circuits and / or program instructions, which implement the steps of the method in the first aspect above when the cache management unit is running.

[0039] Thirdly, this application also provides a network interface card (NIC) chip, including the cache management unit as described in the second aspect above.

[0040] Fourthly, this application also provides a network device, including a network interface card (NIC) chip as described in the third aspect above.

[0041] The aforementioned descriptor cache state management method, cache management unit, network interface card (NIC) chip, and network device, after the NIC chip initiates an RQE access request, combines the receive queue identifier and descriptor memory location information to jointly determine whether a corresponding target cache line exists in the descriptor cache, and updates the descriptor cache state based on the determination result. In other words, this application only needs to locate and update the state of the corresponding target cache line to complete descriptor cache management. In contrast, existing solutions require the host to allocate and maintain a cache area separately based on the size of a single RQE, and the size of a single RQE is much smaller than the cache line, resulting in a large number of redundant memory accesses. Therefore, this solution can significantly reduce the bus overhead caused by frequent reads of host memory, reduce data interaction latency, and save memory management resources. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 This is an application environment diagram of a state management method for descriptor caching in one embodiment;

[0044] Figure 2 This is an application environment diagram of the state management method for descriptor caching in another embodiment;

[0045] Figure 3 This is a flowchart illustrating a state management method for a descriptor cache in one embodiment;

[0046] Figure 4 This is a flowchart illustrating the state management method for descriptor caching in another embodiment;

[0047] Figure 5 This is a flowchart illustrating the state management method for descriptor caching in another embodiment;

[0048] Figure 6 This is a flowchart illustrating the state management method for descriptor caching in another embodiment;

[0049] Figure 7 This is a flowchart illustrating the state management method for descriptor caching in another embodiment;

[0050] Figure 8 This is a flowchart illustrating the state management method for descriptor caching in another embodiment;

[0051] Figure 9 This is a flowchart illustrating the state management method for descriptor caching in another embodiment;

[0052] Figure 10 This is a flowchart illustrating the state management method for descriptor caching in another embodiment;

[0053] Figure 11 This is a flowchart illustrating the state management method for descriptor caching in another embodiment;

[0054] Figure 12 This is a flowchart illustrating the state management method for descriptor caching in another embodiment;

[0055] Figure 13 This is a flowchart illustrating the state management method for descriptor caching in another embodiment. Detailed Implementation

[0056] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0057] With the popularization of virtualization technology and the continuous upgrading of network bandwidth, the size of network card queues has expanded significantly. The massive number of receive queue descriptors cannot all be stored in the static storage of the network card. Descriptor caching is usually used to achieve high-speed reading of receive queue descriptors.

[0058] In related technologies, network transmission often adopts the Push mode, where the receiving end specifies a receive queue descriptor. This descriptor contains the host's storage address to store packets sent by the sending end, thus completing the reception of the packets sent by the sending end. For example, see [link to example]. Figure 1This diagram illustrates a typical data flow diagram of packet transmission and reception in a Network Interface Controller (NIC). The host connects to a switch via the NIC's network interface, using fiber optic or copper wires. Multiple switches form a larger network. The host's CPU and memory connect to the NIC via a host interface (e.g., a PCIe interface). The host's CPU can run multiple Virtual Machines (VMs), managed by a Virtual Machine Manager (VMM) which controls VM operation, resource allocation, and permission management. The host operating system and VMs allocate send queues (SQ) and receive queues (RQ) in memory and populate send queue entries (SQE) and receive queue entries (RQE) accordingly. These descriptors contain data pointers pointing to the descriptor caches in memory awaiting transmission or reception. During operation, the client on the remote host sends a Send command to the local host. The local host's receive queue (RQ) stores the packet indicated by the Send command into memory based on the data pointer of RQE in the descriptor cache.

[0059] In this operating mode, to cooperate with the network interface controller (NIC) chip at the receiving end to receive packets sent by the sending end, the receiving host needs to pre-allocate a storage area for receive queue descriptors in its main memory. The NIC chip reads the receive queue descriptors from the host's main memory, stores them in the chip's internal receive queue descriptor buffer, and then modifies the state of the corresponding buffer to achieve state management of the receive queue descriptor buffer.

[0060] However, the aforementioned state management method for the receive queue descriptor cache suffers from a significant increase in memory management resource consumption. Therefore, this paper proposes a state management method for the descriptor cache to address this problem.

[0061] The application environment of the descriptor cache state management method provided in this application will be described below. For the descriptor cache state management method provided in the embodiments of this application, please refer to... Figure 2 It can be applied to the cache management unit 20, which is set on the network card chip 01 and is used to manage the receive queue descriptor cache 10. It includes programmable logic circuits and / or program instructions. When the cache management unit is running, it implements the steps of the methods described in the following embodiments.

[0062] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0063] In one embodiment, a descriptor cache state management method is provided. The following description uses the application of this method to the cache management unit 20 as an example. Figure 3 As shown, it includes the following steps:

[0064] S201, responding to an access request for the receive queue descriptor initiated by the network interface card chip; the access request carries the receive queue identifier and location information of the receive queue descriptor to be accessed.

[0065] Among them, the network interface chip is a network interface control hardware set on the receiving end to communicate with the sending end. The sending end of the remote host NIC can send packets to the local host NIC, triggering the receiving end of the local NIC to initiate an access request for the receive queue descriptor, so that the network interface chip can initiate an access request for the receive queue descriptor to the cache management unit.

[0066] The access request for the receive queue descriptor refers to the request to retrieve the descriptor in advance from the descriptor cache. The access request for the receive queue descriptor carries the receive queue identifier and location information of the receive queue descriptor to be accessed. The receive queue identifier is the queue number of the receive queue to which the receive queue descriptor to be accessed is located, and the location information is the index position information of the receive queue to which the receive queue descriptor to be accessed is located. It should be noted that the receive queue to which the receive queue descriptor to be accessed is located, as well as its specific location in the receive queue, can be determined based on the receive queue identifier and the location information.

[0067] In this embodiment, when the network interface card (NIC) chip initiates an access request for the receive queue descriptor, the cache management unit can respond to the access request for the receive queue descriptor initiated by the NIC chip, and determine the specific location information of the receive queue descriptor to be accessed in the access request based on the receive queue identifier and location information of the receive queue descriptor to be accessed carried in the access request.

[0068] S202. Based on the receive queue identifier and location information, determine whether there is a target cache line corresponding to the receive queue descriptor in the descriptor cache, and obtain the determination result; the descriptor cache is a cache area in the network card chip that stores multiple cache lines.

[0069] The descriptor buffer stores receive queue descriptors and is a buffer area within the network interface card (NIC) chip containing multiple buffer lines. Each buffer line includes storage space for multiple descriptors. The descriptor buffer can be set-associative in 8-way or 16-way configurations to reduce buffer line collisions. Typically, each buffer line is 128 bytes. Since the descriptor size can be 16 bytes or 32 bytes, each line can store 4 or 8 descriptors.

[0070] In this embodiment, after obtaining the identifier and location information of the receiving queue descriptor to be accessed, the receiving queue to be accessed can be determined based on the receiving queue identifier. Then, based on the location information, it can be determined whether there is a target cache line corresponding to the receiving queue descriptor in the receiving queue.

[0071] Optionally, the cache management unit can extract the middle bits of the location information to obtain the cache group index, generate a matching tag by combining it with the identifier of the receiving queue to complete the tag comparison within the corresponding cache group, thereby determining whether there is a target cache line corresponding to the receiving queue descriptor under the receiving queue.

[0072] S203. Based on the determined result, update the status information of the descriptor cache.

[0073] The determination results include whether the target cache line corresponding to the receive queue descriptor exists in the descriptor cache, and whether the target cache line corresponding to the receive queue descriptor does not exist in the descriptor cache.

[0074] In this embodiment, if the result indicates that a target cache line corresponding to a receive queue descriptor exists in the descriptor cache, the status of the target cache line can be modified according to the access type of the access request to update the status information of the descriptor cache. If the result indicates that a target cache line corresponding to a receive queue descriptor does not exist in the descriptor cache, a new target cache line can be determined from the descriptor cache, and the status of the new target cache line can be modified to update the status information of the descriptor cache.

[0075] In this embodiment, after the network interface card (NIC) chip initiates an RQE access request, it combines the receive queue identifier and descriptor memory location information to determine whether a corresponding target cache line exists in the descriptor cache, and updates the descriptor cache state based on the determination result. In other words, this application only needs to locate and update the state of the corresponding target cache line to complete the descriptor cache management. In contrast, existing solutions require the host to allocate and maintain the state of a cache area separately based on the size of a single RQE. Since the size of a single RQE is much smaller than the cache line, a large number of redundant memory accesses will be generated. Therefore, this solution can significantly reduce the bus overhead caused by frequent readings of host memory, reduce data interaction latency, and save memory management resources.

[0076] In one exemplary embodiment, in the above Figure 3 Based on the illustrated embodiment, a specific implementation method for determining whether a target cache line corresponding to a receive queue descriptor exists in the descriptor cache can be described. See [link to relevant documentation]. Figure 4 The aforementioned S202 includes:

[0077] S301. Based on the location information, determine the target cache group where the access request is located in the descriptor cache.

[0078] In this embodiment, any bit in the location information can be selected, and the number on the selected bit can be used as the target cache group index. Then, the target cache group where the access request is located can be determined in the descriptor cache according to the target cache group index.

[0079] Optionally, two more specific implementations for determining the target cache group where an access request resides in the descriptor cache are provided below.

[0080] In one exemplary embodiment, see Figure 5 The aforementioned S301 includes:

[0081] S3011. Obtain the mapping relationship between bit values ​​in the location information and the cache group.

[0082] The location information includes multiple different bits, and the value of each bit has a certain mapping relationship with different cache groups, that is, the mapping relationship between the bit values ​​in the location information and the cache groups.

[0083] In this embodiment, when determining the target cache group where the access request is located, it is necessary to first obtain the mapping relationship between the value corresponding to the bit in the location information and the cache group from the mapping relationship library.

[0084] For example, location information 0101, decimal number 5, indicates that the cache group index value is 5. Therefore, location information 0101 is mapped to cache group index value 5. Similarly, location information 0110, decimal number 6, indicates that the cache group index value is 6. Therefore, location information 0110 is mapped to cache group index value 6, and so on, thus obtaining the above mapping relationship.

[0085] S3012. Determine the target cache group where the access request is located based on the value and mapping relationship of the middle bit of the location information.

[0086] The location information can be divided into high bits, middle bits, and low bits. The high bits serve as tag verification bits, the low bits serve as offset bits within the cache line, and the middle bits can determine the target cache group where the access request is located.

[0087] In this embodiment, after obtaining the location information, the target cache group where the access request is located can be determined based on the value of the middle bit of the location information and the mapping relationship.

[0088] Continuing with the previous example, the two middle bits 10 in location information 0101 are used as the cache group index value. Since the decimal number corresponding to 10 is 2, the mapping relationship is: the correspondence between the two middle bits 10 in location information 0101 and the cache group index value 2, thereby determining the target cache group 2 where the access request is located.

[0089] It should be noted that the location information includes a total of eight bits. Therefore, the first two bits are determined to be high bits, the middle two bits are determined to be middle bits, and the last two bits are determined to be low bits. The specific determination of which bits are high bits, low bits, and middle bits can be determined according to the situation, and this embodiment does not impose any restrictions here.

[0090] Optionally, the access request carries the location information corresponding to the descriptor of the receiving queue to be accessed. The cache management unit in the network card chip extracts the middle preset bit segment of the location information as the cache group index, and directly addresses the corresponding cache group in the descriptor cache according to the cache group index, thereby determining the target cache group corresponding to the current access request.

[0091] In another exemplary embodiment, see Figure 6 The aforementioned S301 includes:

[0092] S3013. Perform a hash operation on the location information to obtain the target cache group index corresponding to the location information.

[0093] In this embodiment, another method for determining the target cache group where the access request is located is also provided, namely, performing a hash operation on the location information to obtain the target cache group index corresponding to the location information.

[0094] S3014. Determine the target cache group where the access request is located based on the target cache group index.

[0095] In this embodiment, after obtaining the target cache group index, the target cache group where the access request is located in the descriptor cache can be located according to the target cache group index.

[0096] S302. Determine the target cache line where the access request is located based on the receiving queue identifier, location information, and cache line labels of each cache line in the target cache group.

[0097] In this embodiment, the target cache group includes multiple cache lines, each cache line corresponding to its own cache line label. A waiting label can be constructed based on the high-order bits of the receiving queue identifier and the position information. Then, the waiting label is compared with the cache line labels of each cache line in the target cache group to determine whether there is a target cache line in the target cache group where the access request is located.

[0098] Optionally, if there is a tag in the cache line label of each cache line in the target cache group that matches the pending tag, then the cache line corresponding to the matching tag is determined as the target cache line where the access request is located. If there is no tag in the cache line label of each cache line in the target cache group that matches the pending tag, then it means that there is no target cache line in the target cache group corresponding to the access request, and a new target cache line needs to be determined in other ways.

[0099] In this embodiment, a mapping relationship between location information bit values ​​and cache groups is pre-established. By extracting the value of the middle bit of the location information and combining it with this mapping relationship, the target cache group is quickly located without traversing the entire storage area of ​​the descriptor cache, significantly reducing the cache group addressing time. Then, the target cache line is identified by jointly comparing the receive queue identifier, location information and cache line labels of each cache line in the target cache group. By using a segmented address bit hierarchical retrieval method, the cache group is first locked, and then the cache line labels are verified. Hierarchical filtering reduces invalid label comparison operations and avoids cache mismatches between RQEs of different receive queues and different memory addresses. The overall hierarchical addressing logic reduces the internal retrieval operation overhead of the network card chip, improves the RQE cache hit query speed, reduces bus interaction of repeated access to host memory, effectively reduces packet processing latency, and improves the overall throughput performance of the network card for sending and receiving packets.

[0100] In one exemplary embodiment, in the above Figure 3 Based on this, a specific implementation method for updating the state information of the descriptor cache according to the determined result can also be described, see [link to relevant documentation]. Figure 7 The aforementioned S203 includes:

[0101] S401. If it is determined that the target cache line exists in the descriptor cache, update the status information of the target cache line.

[0102] The target cache line's status information includes cache line status, cache line label, and request prefetch count. The cache line status (V) includes valid and invalid states. Valid state (V=1) means that the cache line is valid and its cache line label can participate in address matching. Invalid state (V=0) means that the cache line is invalid and its cache line label will be ignored during address matching.

[0103] Among them, the cache line label can uniquely identify the cache line. As described in the above embodiment, when performing cache line matching, a waiting label is formed based on the receiving queue identifier and location information of the receiving queue descriptor to be accessed carried in the access request. The waiting label is then matched with the cache line labels of multiple cache lines in the descriptor cache to determine the target cache line corresponding to the receiving queue descriptor from the descriptor cache.

[0104] The Request Prefetch Count (LCNT) refers to the number of requests accessing the target cache line, i.e., the number of times a packet initiates a descriptor prefetch but has not yet been written back to the host from the receiving end. When the network interface card (NIC) chip initiates a descriptor prefetch to the target cache line, the LCNT count of the target cache line increases by 1. When the NIC chip reads a descriptor from the target cache and writes it back to the host, the LCNT count of the target cache line decreases by 1. In addition, multiple packets may initiate prefetches to the target cache line at the same time. Therefore, the LCNT count of the target cache line can also indicate the locking status of the target cache line. If the LCNT count of the target cache line is greater than 0, it means that a packet needs to read a descriptor from the target cache line, and this target cache line cannot be evicted.

[0105] Generally, the status of a cache line is represented by a combination of status information and the number of request prefetches. The status of a cache line includes the following four types:

[0106] V=0, LCNT=0: This indicates that the cache line is invalid, the cache line label does not participate in address matching, and no packet uses this cache line;

[0107] V=1, LCNT>0: This indicates that the cache line is valid and locked and cannot be evicted. The cache line label can participate in address matching. The packet initiates descriptor prefetching, but the descriptor has not yet been read and written back to the host.

[0108] V=1, LCNT=0: This indicates that the cache line is valid but not locked and can be evicted. The cache line label can participate in address matching. The packet initiates descriptor prefetching and has already read the descriptor and written it back to the host.

[0109] V=0, LCNT>0: This indicates that the cache line is invalid but the lock cannot be removed, the cache line label cannot participate in address matching, the packet initiates descriptor prefetching, but the descriptor has not yet been read and written back to the host.

[0110] In this embodiment, if the result indicates that the target cache line exists in the descriptor cache, the status information of the target cache line can be updated.

[0111] It should be noted that, if the result indicates that the target cache line exists in the descriptor cache, the status information includes: the number of request prefetches for the cache line, such as... Figure 8 As shown, the above S401 includes:

[0112] S4011. Obtain the access type of the descriptor access request; the access type includes descriptor prefetch type and descriptor read type.

[0113] In this embodiment, the prefetch request for the receive queue descriptor carries an access type, which includes a descriptor prefetch type and a descriptor read type.

[0114] Optionally, the descriptor prefetch type refers to the network card chip initiating descriptor prefetching to the target cache line. That is, when processing network packets, the network card and other hardware initiate a memory loading request in advance to load the target cache line containing the packet descriptors from main memory into the network card cache. When the descriptor is actually read to parse the data packet, the cache is hit directly without waiting for slow memory access, which greatly reduces the latency of network packet transmission and reception.

[0115] Optionally, the descriptor read type refers to the network card chip reading the descriptor from the target cache and writing it back to the host. That is, the network card hardware directly reads the descriptor that records the data packet information in the target cache line and reads the data from the host according to the descriptor.

[0116] S4012. If the access type is a descriptor prefetch type and the network card chip successfully initiates a prefetch request, then the original request prefetch count of the target cache line is increased by 1, which is used as the current request prefetch count.

[0117] In this embodiment, when the network card chip issues a prefetch request, the corresponding target cache line in the descriptor cache will have an additional pre-prepared descriptor. At this time, the request prefetch count of the target cache line needs to be incremented by 1.

[0118] S4013. If the access type is descriptor read type, and the descriptor to be accessed is read from the target cache line, the original request prefetch count of the target cache line is reduced by 1 to obtain the current request prefetch count.

[0119] In this embodiment, when the access request belongs to the descriptor read type, and the receive queue descriptor to be accessed has been read from the corresponding target cache line, the prefetch count originally recorded in the target cache line is decremented by one to obtain the current prefetch count corresponding to this request.

[0120] In this embodiment, by distinguishing between two access types—descriptor prefetching and descriptor reading—the prefetch count of the target cache line is incremented by one when a prefetch request is initiated and decremented by one after the descriptor is read and consumed. This allows for accurate real-time statistics of the amount of unconsumed prefetch requests in the cache line, accurately characterizing the cache line prefetch load. This provides a reliable quantitative basis for NIC chip cache scheduling and prefetch traffic management. It not only shortens descriptor reading latency and improves packet reception and processing efficiency by relying on the prefetch mechanism, but also promptly clears consumed prefetch counts, avoiding problems such as cache overflow and bus resource contention caused by excessive accumulation of prefetch requests. With low hardware overhead from lightweight addition and subtraction operations, it achieves precise management of prefetch behavior throughout its entire lifecycle, effectively reducing hardware access conflicts and packet loss risks, and improving the overall stability and processing performance of the NIC receive queue descriptor access link.

[0121] Furthermore, based on the above S4011-S4013, the cache line status information also includes: cache line status. If the result determines that the target cache line exists in the descriptor cache, and the target cache line is invalid and locked, after executing the above process of subtracting 1 from the original request prefetch count of the target cache line as the current request prefetch count, see [link to relevant documentation]. Figure 9 The above methods also include:

[0122] S4014. If the number of request prefetches for the target cache line is 0, then set the cache line status of the target cache line to invalid.

[0123] In this embodiment, when the target cache behavior is invalid and the cache line is locked, after the pending access receive queue descriptor is read from the target cache line, the original request prefetch count of the target cache line is reduced by 1 to obtain the current request prefetch count. When the current request prefetch count is 0, it indicates that the cache line has been completely released. At this time, the cache line status of the target cache line can be set to invalid.

[0124] In this embodiment, after the target cache line is an invalid locked cache line and the prefetch count is deducted, the prefetch count of the cache line is checked in real time. When the prefetch count is zero, the cache line status is updated to invalid status synchronously. This can accurately match the resource release time when the prefetch request is completely consumed, avoid cache lines without unprocessed prefetch tasks from continuously maintaining a locked state and occupying hardware cache resources for a long time, release cache lines in a timely manner for new descriptor access scheduling, reduce idle waste of cache resources, and improve the utilization rate of network card cache space.

[0125] Furthermore, based on S4011-S4013 above, the cache line status information also includes: cache line status, before increasing the original request prefetch count of the target cache line by 1, see [link to relevant documentation]. Figure 10 The above methods also include:

[0126] S4015. If the traversal pointer of the receiving circular queue corresponding to the target cache line reaches the last position of the target cache line, then update the cache line status of the target cache line to invalid.

[0127] In this embodiment, if the network interface card (NIC) chip successfully initiates a prefetch request, but the traversal pointer of the receive circular queue corresponding to the target cache line reaches the end of the target cache line, the cache line is invalidated, i.e., V=0 is set, but LCNT is incremented by 1. Setting V=0 indicates that this line will not participate in the comparison of subsequent new descriptor prefetches because the descriptors in this cache line have been used up. Although V=0, this cache line can still be read by prefetched packets because when a descriptor prefetch hits, the descriptor cache returns cache line identification information to the prefetch request. When the NIC chip writes the corresponding data packet back to the host memory, this cache line identification information can be used to initiate a descriptor read request to the descriptor cache, so that the descriptor cache returns the corresponding descriptor to the NIC chip.

[0128] S4016. If the traversal pointer of the circular queue has not reached the end of the target cache line, then update the cache line status of the target cache line to the valid state.

[0129] In this embodiment, if the network card chip successfully initiates a prefetch request and the traversal pointer of the receive circular queue corresponding to the target cache line has not reached the last position of the target cache line, the state of the target cache line is kept as valid, and the original request prefetch count of the target cache line is increased by 1 as the current request prefetch count.

[0130] In this embodiment, if the target cache line exists in the descriptor cache, it is further determined whether the traversal pointer of the receive circular queue corresponding to the target cache line has reached the end of the cache line. Differentiated cache line validity bit V and lock count LCNT update rules are set. When the prefetch hits and the pointer reaches the end of the line, V is set to 0 to block the line from participating in new prefetch matching. At the same time, LCNT is incremented by 1 to retain the lock flag, allowing prefetched packets to continue reading the descriptor of the line using the cache line ID to complete the host memory write-back. If the prefetch hits but the end of the line is not reached, V remains valid and LCNT is incremented. For invalid locked cache lines, LCNT is decremented when the packet reads the descriptor and writes it back to the host. After LCNT reaches zero, the cache line is completely released to a pure invalid state. This can isolate cache lines that have exhausted descriptors from receiving new prefetch requests, avoid invalid caches from participating in prefetch matching and causing logical redundancy and resource consumption, and will not interrupt the descriptor reading process of currently initiated prefetched packets, thus balancing the efficiency of new prefetch scheduling and the integrity of existing packet processing.

[0131] S402. If the result indicates that the target cache line does not exist in the descriptor cache, a new target cache line is determined from the descriptor cache, and the status information of the new target cache line is updated.

[0132] In this embodiment, if the result indicates that there is no target cache line in the descriptor cache, a new target cache line can be determined from other cache lines in the descriptor cache, and the status information of the new target cache line can be updated.

[0133] Optionally, a specific implementation for determining a new target cache line from the descriptor cache is provided below; see [link to relevant documentation]. Figure 11 The aforementioned S402 includes:

[0134] S4021. If an invalid cache line exists in the descriptor cache, then the invalid cache line will be used as the new target cache line.

[0135] In this embodiment, if the result indicates that there is no target cache line in the descriptor cache, and there is an invalid cache line in other cache lines in the descriptor cache, then the invalid cache line is used as the new target cache line.

[0136] S4022. If there is no invalid cache line in the descriptor cache, then the valid and free cache line in the descriptor cache shall be used as the new target cache line.

[0137] In this embodiment, if the result indicates that there is no target cache line in the descriptor cache, and there are no invalid cache lines in other cache lines in the descriptor cache, then the valid and free cache line in the descriptor cache is taken as the new target cache line.

[0138] Optionally, after determining a new target cache line from the descriptor cache, it is also necessary to update the status information of the new target cache line. The status information to be updated includes: cache line status, cache line tag, and request prefetch count. A specific implementation method for updating the status information of a new target cache line is provided below; see [link to implementation details]. Figure 12 The aforementioned S402 includes:

[0139] S4023. Update the cache line status of the new target cache line to the valid state.

[0140] S4024. Set the cache line label for the new target cache line based on the receive queue identifier and position information.

[0141] S4025. Increase the original request prefetch count of the new target cache line by 1, and determine it as the new request prefetch count of the new target cache line.

[0142] In this embodiment, after acquiring a new target cache line, the scheme sequentially completes the cache line validity status update, configures a dedicated cache line label based on the receive queue identifier and location information, and increments the prefetch count. This enables the complete and standardized initial configuration of the new cache line access prefetch process. By marking the validity status, the cache line participates in subsequent descriptor prefetch matching. By generating a unique label based on queue and location information, it achieves accurate differentiation and addressing of different cache lines under multiple receive queues. The prefetch count is updated synchronously to record the current cache line's pending prefetch task volume in real time. This provides accurate basic data for subsequent cache line status management, prefetch load statistics, and descriptor read count deduction, ensuring orderly cache line scheduling and quantifiable tracking of prefetch behavior in multi-queue scenarios, and improving the accuracy and scheduling efficiency of network card descriptor access processing.

[0143] In an exemplary embodiment, for scenarios where excessive receive queue descriptor access requests within the same cache group cause cache resource conflicts, resulting in neither cache hits nor available free invalid cache lines, a valid free cache line is selected as the eviction target. The system supports two eviction strategies: random or pseudo-Least Recently Used (LRU). This allows for the rapid release of available cache space to accommodate new descriptor access requests when cache resources are exhausted. The pseudo-LRU strategy prioritizes eviction of cache lines that have not been accessed for a long time, reducing the probability of subsequent cache misses. The random strategy has simple logic and low hardware implementation overhead. Both methods flexibly adapt to the performance requirements of different chips, effectively alleviating cache resource contention conflicts caused by multiple access requests, reducing access latency caused by cache misses, ensuring the continuous and stable execution of the receive queue descriptor access process, and improving the overall throughput of the network card cache.

[0144] In an exemplary embodiment, when the queue is closed, the remaining cache lines in the queue need to be cleared and the state of the cache lines is set to V=0. If there are packets in the cache line that have not been written back to the host, then the cache line needs to wait for all packets to read their descriptors and be written back to the host before LCNT returns to the value of 0.

[0145] In one exemplary embodiment, see Figure 13 A method for managing the state of a descriptor cache is provided, including:

[0146] T1. Responds to the access request for the receive queue descriptor initiated by the network interface card chip; the access request carries the receive queue identifier and location information of the receive queue descriptor to be accessed;

[0147] T2. Based on the location information, determine the target cache group where the access request is located in the descriptor cache; the descriptor cache is a cache area in the network card chip that stores multiple cache lines;

[0148] T3. Based on the receiving queue identifier, location information, and cache line labels of each cache line in the target cache group, determine the target cache line where the access request is located, and obtain the determination result;

[0149] T4. If the result indicates that the target cache line exists in the descriptor cache, obtain the access type of the descriptor access request; the access type includes descriptor prefetch type and descriptor read type.

[0150] T5. If the access type is descriptor prefetch type and the network card chip successfully initiates a prefetch request, then the original request prefetch count of the target cache line is increased by 1, which is used as the current request prefetch count.

[0151] T6. If the access type is descriptor read type, and the descriptor to be accessed is read from the target cache line, subtract 1 from the original request prefetch count of the target cache line to get the current request prefetch count.

[0152] T7. If the result indicates that the target cache line does not exist in the descriptor cache, determine a new target cache line from the descriptor cache and update the cache line status of the new target cache line to the valid state.

[0153] T8. Set the cache line label for the new target cache line based on the receive queue identifier and position information;

[0154] T9. Increase the original request prefetch count for the new target cache line by 1, and determine it as the new request prefetch count for the new target cache line.

[0155] It should be noted that the descriptions of T1-T9 above can be found in the relevant descriptions in the above embodiments, and their effects are similar, so they will not be repeated here.

[0156] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0157] In one exemplary embodiment, a cache management unit is provided, including programmable logic circuitry and / or program instructions, which, when the cache management unit is running, implement the following steps:

[0158] In response to an access request for the receive queue descriptor initiated by the network interface card (NIC) chip; the access request carries the receive queue identifier and location information of the receive queue descriptor to be accessed;

[0159] Based on the receive queue identifier and location information, determine whether the target cache line corresponding to the receive queue descriptor exists in the descriptor cache, and obtain the determination result; the descriptor cache is a cache area in the network card chip that stores multiple cache lines;

[0160] Based on the determined result, update the state information of the descriptor cache.

[0161] In one embodiment, the cache management unit performs the following steps at runtime:

[0162] Based on the location information, determine the target cache group where the access request is located in the descriptor cache;

[0163] The target cache line containing the access request is determined based on the receive queue identifier, location information, and cache line labels of each cache line in the target cache group.

[0164] In one embodiment, the cache management unit performs the following steps at runtime:

[0165] Obtain the mapping relationship between bit values ​​in location information and cache groups;

[0166] Based on the value of the middle bit of the location information and the mapping relationship, the target cache group where the access request is located is determined.

[0167] In one embodiment, the cache management unit performs the following steps at runtime:

[0168] The location information is hashed to obtain the target cache group index corresponding to the location information;

[0169] Determine the target cache group where the access request belongs based on the target cache group index.

[0170] In one embodiment, the cache management unit performs the following steps at runtime:

[0171] If it is determined that the target cache line exists in the descriptor cache, update the status information of the target cache line;

[0172] If the result indicates that the target cache line does not exist in the descriptor cache, a new target cache line is determined from the descriptor cache, and the status information of the new target cache line is updated.

[0173] In one embodiment, the cache management unit performs the following steps at runtime:

[0174] If an invalid cache line exists in the descriptor cache, the invalid cache line will be used as the new target cache line.

[0175] If no invalid cache line exists in the descriptor cache, then a valid and free cache line in the descriptor cache will be used as the new target cache line.

[0176] In one embodiment, the cache management unit performs the following steps at runtime:

[0177] Retrieve the access type of the descriptor access request; the access type includes descriptor prefetch type and descriptor read type;

[0178] If the access type is a descriptor prefetch type and the network interface card (NIC) chip successfully initiates a prefetch request, the original request prefetch count of the target cache line is incremented by 1, which is used as the current request prefetch count.

[0179] If the access type is a descriptor read type, and the descriptor to be accessed is read from the target cache line, the original request prefetch count of the target cache line is reduced by 1 to obtain the current request prefetch count.

[0180] In one embodiment, the cache management unit performs the following steps at runtime:

[0181] If the number of request prefetches for the target cache line is 0, then the cache line status of the target cache line is set to invalid.

[0182] In one embodiment, the cache management unit performs the following steps at runtime:

[0183] If the traversal pointer of the receiving circular queue corresponding to the target cache line reaches the end of the target cache line, then update the cache line status of the target cache line to invalid.

[0184] If the traversal pointer of the circular queue has not reached the end of the target cache line, then update the cache line status of the target cache line to the valid state.

[0185] In one embodiment, the cache management unit performs the following steps at runtime:

[0186] Update the cache line status of the new target cache line to valid;

[0187] Set the cache line label for the new target cache line based on the receive queue identifier and position information;

[0188] The number of original request prefetches for the new target cache line is increased by 1, and this number is determined as the number of new request prefetches for the new target cache line.

[0189] In one embodiment, a network interface card (NIC) chip is provided, including a cache management unit as described in the above embodiment.

[0190] In one embodiment, a network device is provided, including a network interface card (NIC) chip as described in the above embodiments.

[0191] The databases involved in the various embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases.

[0192] In the above embodiments, the functions of each functional unit can be implemented entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions (programs). When the computer program instructions (programs) are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., digital video discs, DVDs), or semiconductor media (e.g., solid-state disks, SSDs), etc.

[0193] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0194] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0195] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for managing the state of a descriptor cache, characterized in that, The method includes: In response to an access request for a receive queue descriptor initiated by the network interface card (NIC) chip; the access request carries the receive queue identifier and location information of the receive queue descriptor to be accessed; Based on the receive queue identifier and the location information, it is determined whether there is a target cache line corresponding to the receive queue descriptor in the descriptor cache, and a determination result is obtained; the descriptor cache is a cache area in the network card chip that stores multiple cache lines; Based on the determination result, update the state information of the descriptor cache.

2. The method according to claim 1, characterized in that, The step of determining whether the target cache line corresponding to the receive queue descriptor exists in the descriptor cache based on the receive queue identifier and the location information includes: Based on the location information, determine the target cache group where the access request is located in the descriptor cache; The target cache line where the access request is located is determined based on the receiving queue identifier, the location information, and the cache line labels of each cache line in the target cache group.

3. The method according to claim 2, characterized in that, The step of determining the target cache group where the access request is located in the descriptor cache based on the location information includes: Obtain the mapping relationship between bit values ​​in location information and cache groups; Based on the value corresponding to the middle bit of the location information and the mapping relationship, the target cache group where the access request is located is determined.

4. The method according to claim 2, characterized in that, The step of determining the target cache group where the access request is located in the descriptor cache based on the location information includes: The location information is hashed to obtain the target cache group index corresponding to the location information; The target cache group where the access request is located is determined based on the target cache group index.

5. The method according to any one of claims 1-4, characterized in that, The step of updating the state information of the descriptor cache based on the determination result includes: If the determination result indicates that the target cache line exists in the descriptor cache, update the status information of the target cache line; If the determination result is that the target cache line does not exist in the descriptor cache, a new target cache line is determined from the descriptor cache, and the status information of the new target cache line is updated.

6. The method according to claim 5, characterized in that, Determining a new target cache line from the descriptor cache includes: If an invalid cache line exists in the descriptor cache, then the invalid cache line is used as the new target cache line; If there are no invalid cache lines in the descriptor cache, then the valid and free cache line in the descriptor cache is used as the new target cache line.

7. The method according to claim 5, characterized in that, The status information includes: the number of request prefetches for the cache line, and the status information for updating the target cache line includes: Obtain the access type of the descriptor access request; the access type includes descriptor prefetch type and descriptor read type; If the access type is the descriptor prefetch type, and the network interface chip successfully initiates a prefetch request, then the original request prefetch count of the target cache line is increased by 1, which is used as the current request prefetch count. If the access type is the descriptor read type, and after the descriptor to be accessed is read from the target cache line, the original request prefetch count of the target cache line is reduced by 1 to obtain the current request prefetch count.

8. The method according to claim 7, characterized in that, The status information further includes: cache line status. In the case that the target cache line is invalid and locked, after subtracting 1 from the original request prefetch count of the target cache line to obtain the current request prefetch count, the method further includes: If the number of request prefetches for the target cache line is 0, then the cache line status of the target cache line is set to invalid.

9. The method according to claim 7, characterized in that, The status information also includes: cache line status. Before incrementing the original request prefetch count of the target cache line by 1, the method further includes: If the traversal pointer of the receiving circular queue corresponding to the target cache line reaches the last position of the target cache line, then the cache line status of the target cache line is updated to invalid. If the traversal pointer of the circular queue has not reached the end of the target cache line, then the cache line status of the target cache line is updated to the valid state.

10. The method according to claim 5, characterized in that, The status information includes: cache line status, cache line label, and request prefetch count. The status information for updating the new target cache line includes: Update the cache line status of the new target cache line to valid; Set a cache line label for the new target cache line based on the receiving queue identifier and the location information; The original request prefetch count for the new target cache line is increased by 1, and this number is determined as the new request prefetch count for the new target cache line.

11. A cache management unit, characterized in that, The cache management unit includes programmable logic circuits and / or program instructions, which, when the cache management unit is running, implement the steps of the method according to any one of claims 1 to 10.

12. A network interface card (NIC) chip, characterized in that, The network interface card chip includes the cache management unit as described in claim 11.

13. A network device, characterized in that, The network device includes the network interface card (NIC) chip as described in claim 12.

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