An SRIO_PCIe protocol conversion system and method suitable for complex data transmission

Abstract

The application provides an SRIO_PCIe protocol conversion system and method suitable for complex data transmission. The system comprises a PCIe to SRIO protocol conversion bridge and an SRIO to PCIe protocol conversion bridge, and can realize high-speed interconnection between a domestic CPU without an SRIO interface and a DSP and other key components of a guide waveform. Meanwhile, the protocol conversion bridge has a certain universality and expansibility, so that in some cases, the protocol conversion bridge based on SRIO can be used to replace PCIe to become the backbone bus inside the chassis or module and control various AXI IP. Overall, SRIO has the advantages of low logical resource consumption, independence from FPGA hard core, low delay, autonomous controllability and the like.

Description

Technical Field

[0001] This invention belongs to the field of communication technology, specifically relating to an SRIO_PCIe protocol conversion system and method suitable for complex data transmission. Background Technology

[0002] With the development of high-performance computing technology, such as Figure 1 As shown, heterogeneous computing architectures (such as DSP+FPGA+CPU combinations) have become the mainstream solution in fields such as radar and communications. Among them: The SRIO bus, with its low latency (nanosecond level), high reliability (supports hardware-level flow control), and flexible topology (point-to-point / switched network), is widely used for real-time data interaction between DSPs and FPGAs. With its high bandwidth and standardized software ecosystem, the PCIe bus has become the preferred choice for communication between FPGAs and host CPUs.

[0003] However, the two differ significantly in protocol stack, address space, and transaction model. In recent years, with the major trend of domestic production, most domestic CPUs do not support the SRIO interface. Therefore, a domestically produced SRIO / PCIe protocol conversion bridge is needed in fields such as communications and radar. Since data interoperability between heterogeneous systems relies on the protocol conversion bridge, its design quality directly affects the overall system performance.

[0004] In terms of FPGA products, domestic manufacturers such as Fudan Microelectronics and Unigroup Guoxin Microelectronics do not yet possess mature and comprehensive self-developed IP libraries and EDA toolchains. Although foreign FPGA manufacturers such as Xilinx and Altera provide PCIe and SRIO IPs, they currently do not offer PCIe / SRIO protocol conversion bridge IPs for use, requiring users to perform customized development according to their needs.

[0005] In terms of ASIC products, Renesas Electronics' Tsi721 (foreign) and Wellchip Microelectronics' PRB0400 (domestic) provide high-performance SRIO / PCIe Converter chips. However, in practical applications, these two chips primarily focus on protocol conversion. For complex business scenarios, such as SRIO simultaneously bridging multiple buses including PCIe / FC ASM / ARINC 818 / Aurora / various low-speed serial networks, multi-channel SRIO-PCIe protocol conversion, protocol conversion under customized constraints of transport layer protocols, and multi-channel QoS design, a general, systematic solution is still lacking. Furthermore, factors such as chip procurement price, supply stability, PCB area constraints, and power consumption limit the chips, making them unsuitable for all project application needs. Summary of the Invention

[0006] The purpose of this invention is to address the problems existing in the prior art by providing an SRIO_PCIe protocol conversion system and method suitable for complex data transmission.

[0007] The technical solution of the present invention: To achieve the above-mentioned objective, according to a first aspect of the present invention, an SRIO_PCIe protocol conversion system suitable for complex data transmission is proposed. The PCIe to SRIO protocol conversion bridge includes: a configuration register group module for receiving control data from the CPU PCIe interface, enabling the CPU to configure and control the protocol conversion bridge through the PCIe interface; a logic transmission interface module for receiving control data from the FPGA, enabling other modules within the FPGA to configure and control the protocol conversion bridge; a response packet buffer module for receiving control data from the protocol conversion bridge's internal automatic reply response packets; a transmission arbitrator module for implementing equal-priority arbitration among the three types of control data from the configuration register group module, the logic transmission interface module, and the response packet buffer module, and outputting a transmission vector to the fragmentation module, achieving zero-latency processing to reduce logic bubbles; and a fragmentation module for processing the transmission vector. The system performs data alignment and splitting to meet SRIO data alignment and protocol length requirements; the transmit control module controls the DMA to move data from the CPU's DDR memory to the FPGA's on-chip cache and generates a transmit completion interrupt signal; the transmit FIFO module includes a transmit data FIFO unit, a transmit control FIFO unit, and a transmit header FIFO unit, which are used to buffer the data / control information / packet header to be transmitted, respectively, to realize data buffering and cross-clock domain processing; the AXIS transmit interface module is used to assemble the packet header and data buffered in the transmit FIFO module into the AXI-Stream format and deliver it to the downstream SRIO MAC IP.

[0008] In one possible embodiment, the SRIO to PCIe protocol conversion bridge includes: an AXIS receive interface module for receiving data from the AXIS interface and splitting it into header / control information / data; a receive FIFO module, including a receive header FIFO unit, a receive control FIFO unit, and a receive data FIFO unit, used to buffer the received header / control information / data respectively, realizing data buffering and cross-clock domain processing; a receive control module for initiating DMA to move data from the FPGA's on-chip cache to the CPU's DDR; a reassembly module for marking the received data packet ID, and when receiving out-of-order packets, generating a receive completion interrupt signal and sending it to the receive arbitrator module only after the entire packet data has been completely received; and a receive arbitrator module for receiving a transmit completion interrupt signal from the transmit control module, used to implement equal-priority arbitration between the transmit completion interrupt signal and the receive completion interrupt signal, generating an MSI interrupt signal, and providing it to the upstream PCIe MAC IP.

[0009] In one possible embodiment, a maintenance packet interface module is also included, which converts the maintenance packet send / receive commands in the configuration register group module into an AXI-lite interface and connects to the downstream SRIO IP to realize SRIO network management functions.

[0010] In one possible embodiment, a status monitoring unit is also included, which collects the status signals of each module inside the protocol conversion bridge and connects them to the configuration register group so that the CPU can read the internal status of the protocol conversion bridge through the PCIe interface.

[0011] The protocol conversion bridge register group includes a set of status monitoring registers containing the following signals: Handshake type for each module (valid / ready / sof / eof, etc.).

[0012] Record the number of handshake taps and back pressure taps over a period of time. These signals can be used to observe which part of the module is experiencing back pressure that prevents data from being written, or to locate the specific module that is malfunctioning when the module is stuck.

[0013] Counters and internal pointers. Most counters are reset to zero after a task or instruction completes and have a maximum expected value. During maintenance and error localization, counters and internal pointers can be used to pinpoint the specific state of a function, aiding in performance testing and troubleshooting.

[0014] The FIFO is empty or full. The FIFO interface's empty / full, half-empty / half-full, and depth records can accurately reflect a lot of information from upstream and downstream data interfaces.

[0015] Bus status signals. Records the current number of outstanding AXI buses, the maximum latency for data read / write response (ar-r, aw-b time), and statistics on the maximum and average data volume over a period of time.

[0016] In one possible embodiment, the DMA function is implemented in the protocol conversion bridge transmission control module, and it implements outstanding transmission, window mapping and byte alignment functions, which enable the software to initiate memory copy functions of arbitrary length from any address, thereby improving communication efficiency.

[0017] DMA transfers data between the FIFO and AXI MemoryMapped interfaces, and is divided into two parts: reading (MemoryMapped2FIFO) and writing (FIFO2MemoryMapped).

[0018] In one possible implementation, the minimum number of outstanding items = command-to-data latency / data transmission time per item.

[0019] The PCIe MAC IP supports up to 8 outstanding capabilities.

[0020] For other commonly used AXI interface IPs, such as AXI Bram, which supports 2 outstanding parameters, and MIG (DDR / QDR controller), which supports 8 outstanding parameters, the protocol conversion bridge uses the number of outstanding parameters as an IP configuration parameter, supporting a maximum of 8 outstanding parameters. This allows for the continuous issuance of up to 8 AXI bus access commands even if Bvalid or Rvalid has not returned a response.

[0021] According to a second aspect of the present invention, an SRIO_PCIe protocol conversion method suitable for complex data transmission is proposed, employing the aforementioned SRIO_PCIe protocol conversion system suitable for complex data transmission, wherein the protocol conversion bridge from PCIe to SRIO includes the following steps: Step 1.1: The CPU writes to the register group module through the PCIe interface to configure the packet type, packet length, source address, destination address and priority to be sent, and writes to the send enable register group module to start sending; Step 1.2: The arbitrator module arbitrates the three types of control data—configuration register group module, logical transmission interface module, and response packet buffer module—with equal priority to generate a transmission vector; Step 1.3: The fragmentation module decomposes unaligned or SRIO maximum packet length transmission vectors into aligned or no more than maximum packet length small packets, assembles the packet header of each small packet, and generates a transmission enable; the transmission enable is a single clock cycle enable signal, which is the start signal of step 1.4 below; Step 1.4: After receiving the transmit enable command from the fragmentation module, the transmit control module starts DMA according to the transmit length and source address information of each small packet, and retrieves the data into the transmit data FIFO of the FPGA. At the same time, it writes the destination ID, packet length and destination address of the transmit vector into the control FIFO, and writes the packet header into the packet header FIFO. When all small packets have been transmitted, a transmit completion interrupt signal is generated. Step 1.5: After the sending FIFO module performs cross-clock domain isolation, the AXI-Stream sending module retrieves the data from the FIFO according to the length information in the control FIFO, assembles it with the packet header in the packet header FIFO, and sends it as an SRIO data packet to the downstream SRIO MAC IP.

[0022] In one possible embodiment, in step 1.3, for transmission vectors exceeding the maximum packet length of SRIO, in order to avoid multiple DMA initiations and thus improve bandwidth utilization, the DMA read command on the PCIe side is sent only once. The protocol conversion bridge collects all the PCIe data and then fragments and sends the data through SRIO.

[0023] In one possible embodiment, in step 1.4, to reduce the time overhead of software alignment, the protocol conversion bridge uses pure logic to align the addresses at both ends. After data is retrieved from the PCIe side, the data is first buffered and shifted in a register. The shifting requires calculating whether to shift left or right and the shift length based on the source and destination addresses. After the data is aligned, it is written into the data buffer FIFO.

[0024] For the SRIO receive-to-PCIe transmit direction in the protocol conversion bridge, byte alignment is implemented by the SRIO peer. This method ensures that the CPUs at both ends of the SRIO link copy data in the PCIe address space with arbitrary alignment.

[0025] For two unaligned SRIO data packets with insufficient bus data width at the beginning and end, the lower three bits of Size and Addr in the packet header need to be encoded according to the SRIO unaligned data mask encoding rules to indicate which byte is actually sent; when receiving SRIO data, the byte strobe signal on the AXI MemoryMapped side is calculated by decoding according to the SRIO unaligned data mask encoding rules.

[0026] In one possible embodiment, in step 1.5, the protocol conversion bridge operates internally under two clock domains: SRIO's log_clk and PCIe's aclk. Control signals and data signals need to be processed across clocks via an asynchronous FIFO.

[0027] In one possible embodiment, step 1.5 further includes the following process: The sending control module counts the time between the start of sending and the receipt of the response packet. If the time exceeds the threshold set in the configuration register, a sending reset is generated to reset the sending logic, thus preventing the sending logic that requires the response packet from becoming dead due to a crash at the peer end of the link.

[0028] In one possible embodiment, the SRIO to PCIe conversion protocol bridge includes the following steps: Step 2.1: The AXI receiving interface module receives the HELLO format SRIO data packets uploaded by the SRIO MAC IP, splits the packet header and data, writes them into the receive packet header FIFO and receive data FIFO respectively, and writes the data length into the receive control FIFO; Step 2.2: After the receive FIFO is isolated across clock domains, the receive control module starts DMA according to the data length in the receive control FIFO and the packet type in the packet header FIFO, and transfers the data in the data FIFO to the CPU's DDR memory; If the packet type in the header FIFO is a data packet without a data payload, such as a Doorbell packet, then a Doorbell interrupt is generated. If the packet type in the header FIFO is a data packet that requires a response packet, then a response header is generated, and the response packet is written to the response packet buffer module.

[0029] Step 2.3: The reassembly module performs group statistics based on the packet ID information in the packet header FIFO. When a complete packet of SRIO data is received, a reception completion interrupt signal is generated. Step 2.4: The receiving arbitration module performs equal-priority arbitration based on the transmission completion interrupt signal generated by the transmitting control module, the doorbell interrupt generated by the receiving control module, and the receiving completion interrupt signal generated by the reassembly module, and delivers the arbitration output signal as the MSI enable signal to the upstream PCIe MAC IP.

[0030] In one possible embodiment, the reassembly module ensures the correct reception of SRIO out-of-order packets and generates a PCIe MSI interrupt signal.

[0031] When receiving SRIO data, the data will be directly written to memory via DMA under the operation of the receive control module. This process will not be detected by the PCIe side software. Therefore, the protocol conversion bridge needs to generate a receive completion interrupt to notify the PCIe device.

[0032] However, when SRIO data passes through the SRIO switching network, the data packets are rearranged due to channel congestion. At this time, the protocol conversion bridge, which acts as a node, will receive out-of-order data packets. Therefore, the reassembly module needs to confirm that all data packets of the transaction have been received before reporting the interruption of reception completion.

[0033] Advantages and beneficial effects of the present invention: 1. The data fragmentation function is implemented using pure logic code, which greatly improves the data sending efficiency.

[0034] 2. The reassembly module ensures the correct reception of out-of-order SRIO data packets and generates a PCIe MSI interrupt signal.

[0035] 3. To ensure compatibility with various hardware architectures, the DMA function is implemented in the protocol conversion bridge IP, and it also features outstanding transfer, window mapping, and byte alignment, enabling the software to initiate memory copy functions of any length from any address, thereby improving communication efficiency.

[0036] 4. A mailbox mechanism has been implemented for SRIO data packets of message type.

[0037] 5. The protocol conversion bridge IP uses Xilinx's XPM macro module, which enables top-down parameterized design. Under different channel widths and rates, it can be used simply by changing the top-level parameters.

[0038] 6. The protocol conversion bridge includes fault recovery functionality.

[0039] 7. In addition to SRIO-PCIe conversion, the protocol conversion bridge can also be extended to SRIO-any AXI interface IP conversion. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. The drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 For heterogeneous computing architecture of integrated signal processing systems; Figure 2 This is a schematic diagram of an SRIO_PCIe protocol conversion system suitable for complex data transmission, according to a preferred embodiment of the present invention. Figure 3 This is a timing diagram of a round-robin arbitrator for a preferred embodiment of the SRIO_PCIe protocol conversion method suitable for complex data transmission according to the present invention; Figure 4 An example of SRIO data alignment for a preferred embodiment of the SRIO_PCIe protocol conversion method suitable for complex data transmission according to the present invention; Figure 5 A schematic diagram of SRIO unaligned data mask encoding rules for an SRIO_PCIe protocol conversion method suitable for complex data transmission, according to a preferred embodiment of the present invention; Figure 6 This is a schematic diagram of an unaligned copy of PCIe space to SRIO space according to a preferred embodiment of the present invention; Figure 7 This is a schematic diagram of the DMA read delay in a preferred embodiment of the present invention; Figure 8 This is a schematic diagram of the DMA write delay in a preferred embodiment of the present invention; Figure 9 This is a diagram illustrating an example of outstanding transmission in a preferred embodiment of the present invention. Figure 10 This is an idle time count-efficiency curve of a preferred embodiment of the present invention; Figure 11 This is a schematic diagram of the maintenance package write timing according to a preferred embodiment of the present invention; Figure 12 This is a schematic diagram of the maintenance package read timing according to a preferred embodiment of the present invention. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0043] The features and illustrative embodiments of various aspects of the present invention will now be described in detail. Numerous specific details are set forth in the following detailed description to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without requiring some of these specific details. The following description of embodiments is merely intended to provide a better understanding of the invention by illustrating examples of the invention. The invention is by no means limited to any specific setups and methods set forth below, but covers any improvements, substitutions, and modifications to structures, methods, and devices without departing from the spirit of the invention. Well-known structures and techniques are not shown in the drawings and the following description to avoid unnecessarily obscuring the invention.

[0044] In the description of this invention, it should be noted that the directions or positional relationships indicated by terms such as "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" are based on the directions or positional relationships shown in the accompanying drawings and are only for the convenience of describing and simplifying the invention, and should not be construed as limiting the invention. Furthermore, the use of ordinal numbers (e.g., "first and second," etc.) is for distinguishing objects and is not limited to this order, and should not be construed as indicating or implying relative importance.

[0045] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly, encompassing both direct connection and indirect connection via an intermediate medium. Those skilled in the art can understand the specific meaning of these terms in this invention based on the specific circumstances.

[0046] It should be noted that, unless otherwise specified, the embodiments of the present invention and the features thereof can be combined with each other, and the various embodiments can be referenced and cited in each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0047] The present invention will be further described in detail below with reference to the embodiments and accompanying drawings, but the embodiments of the present invention are not limited thereto.

[0048] Example 1 like Figure 2 As shown, an SRIO / PCIe protocol conversion system suitable for complex data transmission is presented. The SRIO / PCIe protocol conversion bridge needs to include a control register set, transmit / receive control logic, fragmentation and reassembly logic, an arbiter, a DMA for transferring data between the AXI interface and the FIFO, a parameter-configurable FIFO buffer, and an AXI Stream interface timing module. In this architecture, the upper yellow area represents the PCIe to SRIO data transmission direction, and the lower green area represents the SRIO to PCIe data transmission direction.

[0049] The PCIe to SRIO protocol conversion bridge includes: a configuration register group module for receiving control data from the CPU PCIe interface, enabling the CPU to configure and control the protocol conversion bridge via the PCIe interface; a logic transmit interface module for receiving control data from the FPGA, enabling other modules within the FPGA to configure and control the protocol conversion bridge; a response packet buffer module for receiving control data from the protocol conversion bridge's internal automatic reply response packets; a transmit arbitrator module for implementing equal-priority arbitration among the three types of control data from the configuration register group module, logic transmit interface module, and response packet buffer module, and outputting the transmit vector to the fragmentation module, achieving zero-latency processing to reduce logic bubbles; and a fragmentation module for processing the transmit vector. The system performs data alignment and splitting to meet SRIO data alignment and protocol length requirements; the transmit control module controls the DMA to move data from the CPU's DDR memory to the FPGA's on-chip cache and generates a transmit completion interrupt signal; the transmit FIFO module includes a transmit data FIFO unit, a transmit control FIFO unit, and a transmit header FIFO unit, which are used to buffer the data / control information / packet header to be transmitted, respectively, to realize data buffering and cross-clock domain processing; the AXIS transmit interface module is used to assemble the packet header and data buffered in the transmit FIFO module into the AXI-Stream format and deliver it to the downstream SRIO MACIP.

[0050] The SRIO to PCIe protocol conversion bridge includes: an AXIS receive interface module for receiving data from the AXIS interface and splitting it into header / control information / data; a receive FIFO module, including a receive header FIFO unit, a receive control FIFO unit, and a receive data FIFO unit, used to buffer the received header / control information / data respectively, realizing data buffering and cross-clock domain processing; a receive control module for initiating DMA to move data from the FPGA's on-chip buffer to the CPU's DDR; a reassembly module for marking the received data packet ID, and when receiving out-of-order packets, generating a receive completion interrupt signal and sending it to the receive arbitrator module only after the entire packet data has been completely received; and a receive arbitrator module for receiving the transmit completion interrupt signal from the transmit control module, used to achieve equal priority arbitration between the transmit completion interrupt signal and the receive completion interrupt signal, generating an MSI interrupt signal, and providing it to the upstream PCIe MAC IP.

[0051] The fragmentation module divides the data sent via PCIe into segments according to the SRIO IP requirements. The reassembly module identifies out-of-order packets received by SRIO and generates a receive completion interrupt upon complete data reception.

[0052] In one possible embodiment, a maintenance packet interface module is also included, which converts the maintenance packet send / receive commands in the configuration register group into an AXI-lite interface, connects to the downstream SRIO IP, and implements SRIO network management functions.

[0053] like Figure 11 , 12 As shown, an AXI-Lite master interface is designed in the protocol conversion bridge. The AXI master uses the AXI-Lite master interface to send maintenance packet messages under the control of the configuration register. Sending a maintenance packet requires three signals: HOP_CNT (hop count), destination device ID, and maintenance packet payload. The high 8 bits of the AXI-Lite master interface address are used to transmit the HOP_CNT of the maintenance packet, i.e., the hop count. The data channel (RDATA or WDATA) is used to transmit the maintenance packet payload. The destination device ID is set by writing to the Maintenance Request Information Register at address 0x10000 through the AXI-Lite master interface.

[0054] In one possible embodiment, a status monitoring unit is also included, which collects the status signals of each module inside the protocol conversion bridge and connects them to the configuration register group so that the CPU can read the internal status of the protocol conversion bridge through the PCIe interface.

[0055] like Figure 3As shown, a round-robin arbiter is a strategy that distributes the bus as evenly as possible among different hosts.

[0056] When multiple bits are set in the input vector In_Req, the leftmost bit is forwarded to the output vector Out_Grant first. Then, the next leftmost set bits are processed sequentially, and so on. The Out_Valid handshake signal is set as long as at least one bit in the Out_Grant vector is set, indicating a request. When the user of the Out_Grant vector completes the access operation, they pull the Out_Ready signal high to acknowledge it.

[0057] The data fragmentation function is implemented using pure logic code, which greatly improves data transmission efficiency. Data fragmentation stems from two scenarios. One is to simplify data addressing in the system. SRIO assumes all transactions are aligned to double-word (8-byte) boundaries. If the data being transmitted does not begin or end at a double-word boundary, a special mask is used to indicate which bytes in the current double-word channel contain valid data. Figure 4 The output shows a 48-byte data stream. Because the start and end of the stream are not aligned with the double-word boundary, the protocol conversion bridge needs to split the transaction into three independent SRIO send transactions during transmission.

[0058] For SRIO narrow data packets with two unaligned headers and tails that are insufficient for the bus data width, the lower three bits of Size and Addr in the packet header need to be sorted. Figure 5 The SRIO unaligned data mask encoding rules are used to encode which byte is actually being transmitted. When receiving SRIO data, the byte strobe signal on the AXI MemoryMapped side is calculated according to the following table after decoding.

[0059] When sending SRIO packets, the padding length field in the header needs to be rounded up to the value specified by the protocol. For write-type packets, valid values ​​in the header are 7, 15, 31, 63, 127, and 255; for read-type packets, valid values ​​are 7, 15, 31, 63, 95, 127, 159, 191, 223, and 255. The data payload following the header should still be sent according to its actual length.

[0060] Another situation requiring fragmentation arises from the difference in maximum payload length supported by SRIO and PCIe. SRIO supports a maximum packet length of 256 bytes, while PCIe supports a maximum of 4096 bytes. Therefore, when sending data larger than 256 bytes via SRIO, to avoid initiating DMA multiple times and thus improve bandwidth utilization, the DMA read command on the PCIe side is sent only once. The protocol conversion bridge receives all the data from the PCIe side and then fragments the data for transmission via SRIO.

[0061] The fragmentation function is implemented entirely by logic, so the software does not need to consider the maximum length of data to be sent.

[0062] To reduce the time overhead of software alignment, the protocol translation bridge uses pure logic to align the addresses at both ends, such as... Figure 6 As shown, after data is retrieved from the PCIe side, it is first buffered and shifted in a register. The shifting process requires calculating whether to shift left or right and the shift length based on the source and destination addresses. After data alignment, it is written into the data buffer FIFO. For the SRIO receive-to-PCIe transmit direction in the protocol conversion bridge, byte alignment is implemented by the SRIO peer. This method ensures that the CPUs at both ends of the SRIO link copy data in the PCIe address space with arbitrary alignment.

[0063] The reassembly module ensures the correct reception of out-of-order SRIO packets and generates a PCIe MSI interrupt signal. When receiving SRIO data, the data is directly written to memory via DMA under the operation of the receive control module; this process is not detected by the PCIe software. Therefore, the protocol conversion bridge needs to generate a receive completion interrupt to notify the PCIe device. However, when SRIO data passes through the SRIO switching network, packet reordering may occur due to channel congestion. In this case, the protocol conversion bridge, acting as a node, will receive out-of-order packets. Therefore, the reassembly module needs to confirm that all packets for the transaction have been received before reporting the receive completion interrupt.

[0064] For Nwrite type data, the last packet of the Nwrite transaction is replaced with Nwrite_R. Therefore, upon receiving Nwrite_R, the reassembly module checks whether the TID of the Nwrite transaction has been fully received. When the Nwrite TID has been fully received and the DMA write operation is complete, a receive completion interrupt is generated. Similarly, for Message type data, the reassembly module checks whether msg_seg has been fully received when msg_seg == msg_len. When msg_seg has been fully received and the DMA write operation is complete, a receive completion interrupt is generated.

[0065] To ensure compatibility with various hardware architectures, the DMA function is implemented in the protocol conversion bridge IP, and it also features outstanding transfer, window mapping, and byte alignment, enabling software to initiate memory copy functions of any length from any address, thus improving communication efficiency.

[0066] DMA transfers data between the FIFO and AXI MemoryMapped interfaces, and is divided into two parts: reading (MemoryMapped2FIFO) and writing (FIFO2MemoryMapped).

[0067] The data forwarding efficiency of the protocol conversion bridge is equivalent to the utilization rate of the AXI bus. Therefore, it is necessary to minimize AXI bus bubbles. Taking the AXI Stream side as an example, since the bus data width is fixed at 8 bytes by the official IP, the maximum SRIO packet length is 256 bytes (32 clock cycles), and the packet header occupies 8 bytes (1 clock cycle). The bus utilization rate of AXI Stream when the bus is idle for x clock cycles can be expressed as:

[0068] It can be seen that the bus utilization rate and the number of idle cycles have a hyperbolic function relationship, and the improvement in bus utilization rate becomes increasingly significant as the number of idle cycles decreases. Figure 10 As shown.

[0069] Therefore, in addition to data alignment and window mapping, DMA design also needs to take into account data latency, pipelined processing, and bus bubble reduction.

[0070] In the project, DMA read / write waveforms were captured using a logic analyzer, and the PCIe bus latency between the FPGA and CPU was observed, such as... Figure 7 and Figure 8 As shown. Among them, The latency for the FPGA to read data via AXI PCIe is 864 * 8ns = 6.912us. The latency for writing data to the FPGA via AXI PCIe is 26 * 8ns = 208ns. For the PCIe read -> SRIO write direction in the protocol conversion bridge, since the RTT (round-trip time) of PCIe access is relatively large, it is obviously too inefficient to fetch only one SRIO packet each time DMA is started, given that the maximum packet length of SRIO is only 256 bytes. Therefore, the protocol conversion bridge fetches a maximum of 4096 bytes of data from the PCIe side each time DMA is started. After the data is stored in the FIFO, the SRIO data packet is fragmented and sent one by one according to the output length of the fragmentation module.

[0071] When the data retrieved on the PCIe side exceeds 4096 bytes, or for the SRIO receive -> PCIe transmit direction in the protocol conversion bridge, the PCIe transmission latency will still significantly reduce the AXI bus utilization. Therefore, the AXI side needs to support the AXIOutstanding feature (incomplete transmission) to further improve bus utilization.

[0072] As shown in the diagram above, the Outstanding transmission characteristic of the AXI bus initiates the next command before a transmission transaction is completed, ensuring bubble-free transmission of subsequent data after the initial delay. Essentially, it streamlines command and data processing. However, increasing the number of Outstanding commands leads to increased hardware resource consumption, such as the need for additional buffers to store byte strobes and data alignment information for each command. The diagram also shows a formula for calculating the minimum number of Outstanding commands: Minimum number of outstanding items = Command-to-data latency / Data transmission time per item from Figure 9 In this diagram, the delay from command to data is 15 seconds, and the transmission time for each piece of data is 5 seconds. Therefore, supporting 3 outstanding parameters is sufficient to achieve fully pipelined data transmission. The 4 outstanding parameters in the diagram cannot further improve bandwidth utilization.

[0073] AXI PCIe IP supports up to 8 outstanding capabilities. Other commonly used AXI interface IPs, such as AXIBRAM, support 2 outstanding capabilities, and MIG (DDR / QDR controller) supports 8 outstanding capabilities. Therefore, the protocol conversion bridge uses the number of outstanding capabilities as an IP configuration parameter, supporting a maximum of 8 outstanding capabilities, allowing up to 8 AXI bus access commands to be issued consecutively even if Bvalid or Rvalid has not returned.

[0074] For the PCIe receive -> SRIO transmit direction in the protocol conversion bridge, the DMA module also needs to implement byte alignment. Assume that 56 bytes of data need to be sent from address 2 in the PCIe address space to address 5 in the SRIO address space. To reduce the time overhead of software alignment, the protocol conversion bridge uses pure logic to align the addresses at both ends. After retrieving data from the PCIe side, the data is first buffered and shifted in a register. The shifting requires calculating whether to shift left or right and the shift length based on the source and destination addresses. After data alignment, it is written to the data buffer FIFO. For the SRIO receive to PCIe transmit direction in the protocol conversion bridge, the byte alignment function is implemented by the SRIO peer. This method ensures that the CPUs at both ends of the SRIO link copy data in the PCIe address space with arbitrary alignment.

[0075] For the SRIO receive -> PCIe transmit direction in the protocol conversion bridge, inbound window address mapping is also required to map destination addresses from different SRIO nodes to specific PCIe address spaces. The protocol conversion bridge provides eight sets of registers, each containing an SRIO window address register, a PCIe window address register, and a window size register. When a remote SRIO data packet is received, the protocol conversion bridge first checks whether the SRIO destination address falls within these eight SRIO window address ranges before DMA transfer. If a match is found, DMA is initiated to store the data in the corresponding PCIe window address. If no match is found, the data packet is discarded.

[0076] The protocol conversion bridge includes fault recovery functionality. For the transmit channel (PCIe --> SRIO direction), a transmit completion interruption requires the SRIO peer node to return a response packet. If the peer device goes offline during communication—for example, the SRIO node dynamically goes offline when the radar enters low-power mode or when debugging software functions in the laboratory—or if there is a faulty node in the SRIO network, the data packets sent by the local node will not receive a response. Without handling, the local node will remain in a busy-wait state, causing the local transmit channel to become blocked. For this type of hangup caused by external node anomalies, a timeout recovery mechanism needs to be designed to ensure that the local node can continue to function normally even when the peer node fails.

[0077] In the transmission control module, a counter is designed to start counting whenever an SRIO data packet is sent. If no response packet is received from the link peer within a preset time, the counter is reset to zero, the busy signal is cleared, the transmission logic is restored, and the timeout count register is incremented, allowing the PCIe master to query how many faults have occurred. Furthermore, the protocol conversion bridge also includes a soft reset register, allowing the PCIe master software to actively reset the IP.

[0078] Example 2 A method for SRIO_PCIe protocol conversion suitable for complex data transmission, employing the aforementioned SRIO_PCIe protocol conversion system for complex data transmission, wherein the protocol conversion bridge from PCIe to SRIO includes the following steps: Step 1.1: The CPU writes to the register group module through the PCIe interface to configure the packet type, packet length, source address, destination address and priority to be sent, and writes to the send enable register group module to start sending; Step 1.2: The arbitrator module arbitrates the three types of control data—configuration register group module, logical transmission interface module, and response packet buffer module—with equal priority to generate a transmission vector; Step 1.3: The fragmentation module decomposes unaligned or SRIO maximum packet length transmission vectors into aligned or no more than maximum packet length smaller packets, assembles the header of each smaller packet, and generates a transmission enable; During transmission, an unaligned transmit vector is split into two unaligned transmits at the beginning and end, and an aligned transmit in the middle. For example, Figure 5 shows a 48-byte data stream. Because the beginning and end of the stream are not aligned with the double-word boundary, the general SRIO logic needs to split the transaction into three independent SRIO transmit transactions during transmission.

[0079] Step 1.4: After receiving the transmit enable command from the fragmentation module, the transmit control module starts DMA according to the transmit length and source address information of each small packet, and retrieves the data into the transmit data FIFO on the FPGA. Simultaneously, it writes the destination ID of the transmit vector, the packet length, and the destination address into the control FIFO, and writes the packet header into the packet header FIFO. Once all small packets have been transmitted, a transmit completion interrupt signal is generated; as shown in Figure 6, the heterogeneous computing architecture of the integrated signal processing system. In the IP design, the asynchronous FIFO uses Xilinx's XPM macro, which can parameterize parameters such as the FIFO's bit width and depth, allowing the protocol conversion bridge IP to set parameters in the top-level UI and pass them to each lower-level module.

[0080] Step 1.5: After the sending FIFO module performs cross-clock domain isolation, the AXI-Stream sending module retrieves the data from the FIFO according to the length information in the control FIFO, assembles it with the packet header in the packet header FIFO, and sends it as an SRIO data packet to the downstream SRIO MAC IP module.

[0081] The SRIO to PCIe conversion protocol bridge includes the following steps: Step 2.1: The AXI receiving interface module receives the HELLO format SRIO data packets uploaded by the SRIO MAC IP, splits the packet header and data, writes them into the receive packet header FIFO and receive data FIFO respectively, and writes the data length into the receive control FIFO; Step 2.2: After the receive FIFO is isolated across clock domains, the receive control module starts DMA according to the data length in the receive control FIFO and the packet type in the packet header FIFO, and transfers the data in the data FIFO to the CPU's DDR memory; If the packet type in the header FIFO is a data packet without a data payload, such as a Doorbell packet, then a Doorbell interrupt is generated. If the packet type in the header FIFO is a data packet that requires a response packet, then a response header is generated, and the response packet is written to the response packet buffer module.

[0082] Step 2.3: The reassembly module performs group statistics based on the packet ID information in the packet header FIFO. When a complete packet of SRIO data is received, a reception completion interrupt signal is generated. Step 2.4: The receiving arbitration module performs equal-priority arbitration based on the transmission completion interrupt signal generated by the transmitting control module, the doorbell interrupt generated by the receiving control module, and the receiving completion interrupt signal generated by the reassembly module, and delivers the arbitration output signal as the MSI enable signal to the upstream PCIe MAC IP.

[0083] For SRIO message-type data packets, a mailbox mechanism is implemented. SRIO Message transactions define `msg_len`, `mailbox`, and `letter` fields, supporting a total of 32 mailboxes, each supporting 4 emails, with each email having a maximum length of 4096 bytes. Therefore, an SRIO Message requires a maximum of 32 * 4 * 4096 = 0.5MB of space. Received SRIO Message transactions can be mapped to the PCIe address space based on the `msg_seg`, `mailbox`, and `letter` fields. The protocol translation bridge incorporates a MessageInbound address register, configured by the CPU during initialization via PCIe. Upon receiving a Message, the PCIe (AXI) address space address is calculated based on the various fields within the Message. AXI write address = Message Inbound address register + msg_seg * Message packet length + mailbox * 16384 + letter * 4096 Similarly, when sending a Message, the protocol conversion bridge is designed with a Message Outbound address register. The DMA reads data from the corresponding address according to the mailbox and letter set by the PCIe master, and then sends it via SRIO packet assembly. Since the maximum length of a Message is consistent with the maximum data payload length of PCIe, the DMA reads the entire Message into the data FIFO at once. AXI read address = Message Outbound address register + mailbox * 16384 + letter * 4096 In addition to SRIO-PCIe conversion, the protocol conversion bridge can also be extended to convert SRIO to any AXI interface IP. In summary, the SRIO / PCIe protocol conversion bridge essentially converts the AXI-Stream interface encapsulated with the SRIO protocol into the general AXI-MemoryMapped access via a built-in DMA module. Therefore, besides converting to the PCIe protocol, it can also be used to bridge SRIO with various AXI interface IPs.

[0084] The protocol conversion bridge designed using this invention enables high-speed interconnection between domestically produced CPUs and key components with pass-through waveforms, such as DSPs, even without an SRIO interface. Simultaneously, the protocol conversion bridge possesses a certain degree of versatility and scalability, allowing it to replace PCIe as the main bus within a chassis or module in certain applications, controlling various AXI IPs. Overall, SRIO offers advantages such as low logic resource consumption, independence from FPGA hard cores, low latency, and independent controllability.

[0085] The above detailed embodiments are a description of the present invention. It should not be considered that the specific embodiments of the present invention are limited to these descriptions. For those skilled in the art, several simple deductions and substitutions can be made without departing from the concept of the present invention, and all of these should be considered to fall within the protection scope of the present invention.

Claims

1. An SRIO_PCIe protocol conversion system suitable for complex data transmission, characterized in that, The PCIe to SRIO protocol conversion bridge includes: a configuration register group module for receiving control data from the CPU PCIe interface, enabling the CPU to configure and control the protocol conversion bridge via the PCIe interface; a logic transmit interface module for receiving control data from the FPGA, enabling other modules within the FPGA to configure and control the protocol conversion bridge; a response packet buffer module for receiving control data from the protocol conversion bridge's internal automatic reply response packets; a transmit arbitrator module for implementing equal-priority arbitration among the three types of control data from the configuration register group module, logic transmit interface module, and response packet buffer module, and outputting the transmit vector to the fragmentation module, achieving zero-latency processing to reduce logic bubbles; and a fragmentation module for processing the transmit vector. The system performs data alignment and splitting to meet SRIO data alignment and protocol length requirements; the transmit control module controls the DMA to move data from the CPU's DDR memory to the FPGA's on-chip cache and generates a transmit completion interrupt signal; the transmit FIFO module includes a transmit data FIFO unit, a transmit control FIFO unit, and a transmit header FIFO unit, which are used to buffer the data / control information / packet header to be transmitted, respectively, to realize data buffering and cross-clock domain processing; the AXIS transmit interface module is used to assemble the packet header and data buffered in the transmit FIFO module into the AXI-Stream format and deliver it to the downstream SRIO MAC IP.

2. The SRIO_PCIe protocol conversion system suitable for complex data transmission according to claim 1, characterized in that, The SRIO to PCIe protocol conversion bridge includes: an AXIS receive interface module for receiving data from the AXIS interface and splitting it into header / control information / data; a receive FIFO module, including a receive header FIFO unit, a receive control FIFO unit, and a receive data FIFO unit, used to buffer the received header / control information / data respectively, realizing data buffering and cross-clock domain processing; a receive control module for initiating DMA to move data from the FPGA's on-chip buffer to the CPU's DDR; a reassembly module for marking the received data packet ID, and when receiving out-of-order packets, generating a receive completion interrupt signal and sending it to the receive arbitrator module only after the entire packet data has been completely received; and a receive arbitrator module for receiving the transmit completion interrupt signal from the transmit control module, used to achieve equal priority arbitration between the transmit completion interrupt signal and the receive completion interrupt signal, generating an MSI interrupt signal, and providing it to the upstream PCIe MAC IP.

3. The SRIO_PCIe protocol conversion system suitable for complex data transmission according to claim 1, characterized in that, It also includes a maintenance package interface module, which converts the maintenance package send / receive commands in the configuration register group module into an AXI-lite interface, which is then connected to the downstream SRIO IP to realize SRIO network management functions.

4. The SRIO_PCIe protocol conversion system suitable for complex data transmission according to claim 1, characterized in that, It also includes a status monitoring unit, which collects the status signals of each module inside the protocol conversion bridge and connects them to the configuration register group, so that the CPU can read the internal status of the protocol conversion bridge through the PCIe interface.

5. A method for SRIO_PCIe protocol conversion suitable for complex data transmission, employing the SRIO_PCIe protocol conversion system for complex data transmission as described in any one of claims 1-4, characterized in that, The PCIe to SRIO conversion protocol bridge includes the following steps: Step 1.1: The CPU writes to the register group module through the PCIe interface to configure the packet type, packet length, source address, destination address and priority to be sent, and writes to the send enable register group module to start sending; Step 1.2: The arbitrator module arbitrates the three types of control data—configuration register group module, logical transmission interface module, and response packet buffer module—with equal priority to generate a transmission vector; Step 1.3: The fragmentation module decomposes unaligned or SRIO maximum packet length transmission vectors into aligned or no more than maximum packet length small packets, assembles the packet header of each small packet, and generates a transmission enable; the transmission enable is a single clock cycle enable signal, which is the start signal of step 1.4 below; Step 1.4: After receiving the transmit enable command from the fragmentation module, the transmit control module starts DMA according to the transmit length and source address information of each small packet, and retrieves the data into the transmit data FIFO of the FPGA. At the same time, it writes the destination ID, packet length and destination address of the transmit vector into the control FIFO, and writes the packet header into the packet header FIFO. When all small packets have been transmitted, a transmit completion interrupt signal is generated. Step 1.5: After the sending FIFO module performs cross-clock domain isolation, the AXI-Stream sending module retrieves the data from the FIFO according to the length information in the control FIFO, assembles it with the packet header in the packet header FIFO, and sends it as an SRIO data packet to the downstream SRIO MAC IP.

6. A method for SRIO_PCIe protocol conversion suitable for complex data transmission, employing the SRIO_PCIe protocol conversion system for complex data transmission as described in any one of claims 1-4, characterized in that, Step 2.1: The AXI receiving interface module receives the HELLO format SRIO data packets uploaded by the SRIO MAC IP, splits the packet header and data, writes them into the receive packet header FIFO and receive data FIFO respectively, and writes the data length into the receive control FIFO; Step 2.2: After the receive FIFO is isolated across clock domains, the receive control module starts DMA according to the data length in the receive control FIFO and the packet type in the packet header FIFO, and transfers the data in the data FIFO to the CPU's DDR memory; Step 2.3: The reassembly module performs group statistics based on the packet ID information in the packet header FIFO. When a complete packet of SRIO data is received, a reception completion interrupt signal is generated. Step 2.4: The receiving arbitration module performs equal-priority arbitration based on the transmission completion interrupt signal generated by the transmitting control module, the doorbell interrupt generated by the receiving control module, and the receiving completion interrupt signal generated by the reassembly module, and delivers the arbitration output signal as the MSI enable signal to the upstream PCIe MAC IP.

7. A computer device, characterized in that, The computer device includes a processor and a memory; the memory is used to store a computer program; the processor is used to execute the computer program to implement the method of any one of claims 5-6.

8. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, which, when executed by a processor, implements the method described in any one of claims 5-6.

9. A computer program product, characterized in that, The computer program product stores computer instructions, which, when executed by a processor, implement the method described in any one of claims 5-6.

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