A multi-camera hardware bypass adaptive frame extraction edge acquisition device

Abstract

The application discloses a kind of multi-path camera hardware bypass adaptive frame extraction edge acquisition device, belong to edge computing video security technical field.The device includes multi-path video signal input interface group, hardware frame feature detection circuit, motion change hardware discrimination module, bypass interception switch circuit, key frame cache hardware partition, RK3588 main control unit, time-sharing multi-path scheduling hardware circuit.Video code stream is directly completed frame discrimination, invalid frame interception, key frame screening by hardware bypass circuit before entering main control chip decoding, still frame is directly truncated and discarded by hardware circuit, and key frame is written into exclusive cache block and then sent into main control for AI identification.The application filters more than 85% invalid data by pure hardware front frame extraction, reduces more than 80% equipment cost, does not need computer room deployment, and is suitable for large-scale campus security scene.

Description

Technical Field

[0001] This invention belongs to the fields of edge computing video security, multi-channel video hardware preprocessing, and embedded video acquisition hardware technology. Specifically, it relates to an edge acquisition hardware device that uses a hardware bypass circuit to intercept invalid frames from multiple video channels and adaptive key frame filtering. Background Technology

[0002] Existing intelligent monitoring equipment in schools and communities suffers from serious structural defects: 1. All AI monitoring equipment on the market adopts a full-stream 24-hour complete recording + full-volume decoding architecture, requiring high-end 128-channel GPUs with a single device costing as much as 90,000-100,000 yuan. This extremely high deployment cost makes large-scale deployment impossible in schools and communities, and the AI ​​application scenarios deviate from real market needs. 2. The massive amount of full-stream data and the over 85% invalid still frames result in wasted computing power, high power consumption, severe device overheating, and short hard drive lifespan. 3. Traditional equipment relies on software algorithms for frame extraction, consuming a large amount of main control computing power, leading to AI recognition stuttering, high latency, and high failure rates due to long-term high-load operation. 4. Currently, the industry lacks a purely hardware-based front-end bypass frame extraction physical structure, relying entirely on software processing. This results in high computing power consumption, high cost, poor stability, and a high dependence on imported chips, hindering large-scale adoption. Summary of the Invention

[0003] Purpose of the invention: The purpose of this invention is to overcome the shortcomings of the prior art and provide a multi-camera hardware bypass adaptive frame extraction edge acquisition device. By using an independent hardware bypass pre-frame extraction circuit, the hardware circuit directly completes frame discrimination, invalid frame interception, and key frame screening before the video bitstream enters the main control chip for decoding, thereby achieving hardware-level load reduction and significantly reducing system cost and power consumption.

[0004] Technical Solution: A multi-camera hardware bypass adaptive frame extraction edge acquisition device, comprising: 1. a multi-channel video signal input interface group for parallel access to video streams from multiple cameras; 2. a hardware frame feature detection circuit connected after the multi-channel video signal input interface group for real-time detection of pixel changes in the input video stream; a motion change hardware discrimination module connected after the hardware frame feature detection circuit for determining whether the current frame is a key frame based on the detection result; 3. a bypass interception switch circuit connected after the motion change hardware discrimination module for directly truncating and discarding still frames, preventing them from entering the main control unit; a key frame buffer hardware partition for receiving and storing key frame data filtered by the bypass interception switch circuit; 4. an RK3588 main control unit connected after the key frame buffer hardware partition for AI recognition and storage processing of key frames; and a time-division multiplexing scheduling hardware circuit connected between the multi-channel video signal input interface group and each processing circuit for implementing hardware time-division polling scheduling of multiple video channels.

[0005] Working Principle: The device operates as follows: 1. Multiple camera video streams are fed into the hardware bypass circuit in parallel, bypassing the main control pre-decoding; 2. The hardware frame feature detection circuit compares the pixel changes and dynamic features of the frames in real time; 3. Static frames without change are directly intercepted and discarded by the bypass interception switch circuit, without entering storage or consuming computing power; 4. Keyframes containing human figures, movement, or abnormal changes are directly sent to the keyframe cache hardware partition by the bypass interception switch circuit; 5. The time-division multiplexing hardware circuit realizes hardware time-division polling scheduling of multiple channels, avoiding congestion, frame loss, and stuttering of multiple concurrent video streams; 6. Only a small number of filtered keyframes are sent to the RK3588 main control unit for AI recognition and storage.

[0006] Key hardware innovations: 1. The front-end bypass independent hardware detection link is completely physically separated from the main control unit, forming an independent front-end video processing path; 2. Hardware-level pixel change threshold discrimination circuit: a comparator array and threshold register constitute pure circuit judgment logic, without software computation; 3. Multi-channel parallel hardware time-sharing scheduling timing control circuit: composed of a timing controller and a multiplexer, realizing multi-channel polling switching; 4. Invalid frame hardware fast discarding path: composed of a switching transistor array, still frames are directly grounded and discarded without being written to any memory unit.

[0007] Beneficial effects: 1. Hardware directly filters over 85% of invalid video data, greatly reducing computing power, storage, and power consumption; 2. No need for high-end GPU computing power, completely eliminating reliance on server rooms, reducing equipment costs by over 80%; 3. Frame extraction does not consume main control computing power, resulting in more stable AI recognition and lower latency; 4. Pure hardware processing, millisecond-level response, 24-hour stable operation, and extremely low failure rate; 5. Adaptable to large-scale campus concurrency scenarios with 64-128 channels, and can be mass-produced and widely adopted. Attached Figure Description

[0008] Figure 1 : Overall hardware bypass topology diagram of the present invention; Figure 2 Block diagram of multi-channel hardware frame extraction circuit. Figure 3 Hardware frame filtering timing control flowchart. Detailed Implementation

[0009] As shown in Figure 1, the device of the present invention includes a multi-channel video signal input interface group J1, a hardware frame feature detection circuit U1, a motion change hardware discrimination module U2, a bypass interception switch circuit U3, a keyframe buffer hardware partition M1, an RK3588 main control unit U4, and a time-division multiplexing hardware circuit U5. The multi-channel video signal input interface group J1 uses a standard BNC or RJ45 interface, supporting 4-16 channels of video signal input in parallel. Each signal first enters the time-division multiplexing hardware circuit U5, where a timing controller sequentially selects each channel according to a fixed time slot. The hardware frame feature detection circuit U1 consists of a differential pixel comparator array, which performs pixel-by-pixel differential calculations between the current frame and a reference frame, outputting a pixel change signal. The motion change hardware discrimination module U2 compares the pixel change with a preset threshold; if the change exceeds the threshold, it is determined to be a keyframe; otherwise, it is determined to be a still frame. The bypass interception switch circuit U3 consists of a MOS switch array. Based on the judgment result, it controls the data flow: the switch corresponding to a still frame disconnects the storage path and is directly grounded and discarded; the switch corresponding to a critical frame is turned on and written to the critical frame cache hardware partition M1. The critical frame cache hardware partition M1 uses an independent DDR or SRAM memory chip, physically isolated from the system's main memory. The RK3588 main control unit U4 only triggers an interrupt to read data after the critical frame is ready, avoiding invalid data occupying bus bandwidth.

Claims

1. A multi-channel camera hardware bypass adaptive frame extraction edge acquisition device, characterized in that, include: The system includes a multi-channel video signal input interface group, a hardware frame feature detection circuit, a motion change hardware discrimination module, a bypass interception switch circuit, a key frame buffer hardware partition, an RK3588 main control unit, and a time-division multiplexing hardware circuit. The hardware frame feature detection circuit performs frame difference discrimination before the video stream enters the main control unit, and the bypass interception switch circuit directly discards still frames.

2. The apparatus according to claim 1, characterized in that, The hardware frame feature detection circuit consists of a differential pixel comparator array and a threshold register, which performs pixel-by-pixel differential operations on consecutive frames and outputs the change signal.

3. The apparatus according to claim 1, characterized in that, The bypass interception switch circuit is composed of a MOS switch array. It controls the data flow according to the discrimination result. The switch corresponding to the still frame disconnects the storage path and is grounded and discarded.

4. The apparatus according to claim 1, characterized in that, The time-division multiplexing hardware circuit consists of a timing controller and a multiplexer, which sequentially selects each video channel according to a fixed time slot to avoid congestion of multiple concurrent channels.

5. The apparatus according to claim 1, characterized in that, The keyframe cache hardware partition uses an independent DDR or SRAM storage chip, which is physically isolated from the system's main storage.

6. The apparatus according to claim 1, characterized in that, The RK3588 main control unit only triggers an interrupt to read the data after the keyframe is ready, without performing full-stream pre-decoding.

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