A high-throughput hardware architecture for SVAC SAO

Abstract

The application relates to the field of video coding, and discloses a high-throughput hardware architecture for SVAC SAO, which comprises a statistical collection unit, a parameter decision unit and an offset compensation unit, is designed in aspects such as decoupling of a statistical window and a compensation window, parallel statistical collection of a sliding window, table lookup fixed-point RDO decision, three-way parallel BO candidate search and boundary-aware offset compensation scheduling, and realizes hardware-friendly mapping of the encoding-end statistical collection, parameter decision and offset compensation process on the premise that the SVAC SAO syntax, code stream format and decoding-end compensation process remain unchanged.

Description

Technical Field

[0001] This invention relates to the field of video coding, and more specifically to a high-throughput hardware architecture for SVAC SAO. Background Technology

[0002] SAO (Side Offset Optimization) is a key tool in the SVAC standard loop filter chain, located after the Deblocking Filter (DBF). Its basic function is to apply offset compensation to the reconstructed samples after DBF based on the sample category, thereby reducing systematic reconstruction distortion introduced by quantization and prediction processes and improving the quality of subsequent reference frames. The encoder-side SAO typically includes three stages: statistical collection, parameter decision, and offset compensation. The statistical collection and parameter decision stages require combining the original samples, reconstructed samples, category statistics, and rate-distortion optimization results to determine the optimal SAO parameters.

[0003] SAO includes two types of compensation: Edge Offset (EO) and Band Offset (BO). EO characterizes the local edge structure by comparing the size relationship between the current reconstructed sample and the samples in its directional neighborhood; BO classifies the reconstructed sample based on the band to which its amplitude belongs and applies corresponding offset compensation to the selected band. Figure 2 As shown, unlike the four consecutive band BO selection method in the VVC standard, SVAC SAO supports two band groups, each containing two consecutive bands, and the two groups can be non-consecutive, resulting in 435 valid BO candidate combinations. This mechanism improves adaptability to non-continuous amplitude distributions, but significantly increases the computational burden of candidate traversal, rate estimation, and RD cost comparison at the encoder end.

[0004] Existing SAO hardware implementation methods mainly revolve around improving statistical throughput, reducing RDO complexity, optimizing memory access, and coordinating CTU-level pipelining. For example, some solutions reduce complexity through bitmap statistics, single-stage LCU / CTU processing, coarse range selection, or accumulator bit width reduction; others alleviate parameter decision and boundary dependency issues through hierarchical rate estimation or expanding the processing window. These methods are effective in standard scenarios such as HEVC, VVC, or AVS3, but most still rely on the assumption of BO band continuity, simplified RDO decision models, or approximate boundary processing strategies, making it difficult to directly adapt to the combination of two non-continuous BO bands and the high-throughput hardware pipelining requirements in SVAC.

[0005] In direct hardware mapping, the SAO encoder also faces the following problems: First, the statistical stage may need to access the extended region around the CTB and maintain the spatial alignment between the original sample and the reconstructed sample after DBF, thereby increasing the pressure on the on-chip cache and memory access ports; Second, the CABAC dynamic rate estimation in software RDO involves context state, binarization, and conditional branching, which will form a complex feedback path in hardware implementation; Third, floating-point λ calculation is not conducive to high-frequency fixed-point data paths; Fourth, if the 435 candidates of SVAC BO are traversed serially, it will cause a long parameter decision delay; Fifth, the offset compensation stage also needs to deal with issues such as sample availability at the CTU boundary, delay compensation region, and consistency of parameter sources. Summary of the Invention

[0006] To address the technical problems of existing technologies, such as difficulty in meeting on-chip storage and throughput requirements in high-resolution real-time encoding scenarios, feedback dependencies and complex arithmetic paths, long parameter decision latency, and ensuring consistency between sample space ownership and parameter source, this invention provides a high-throughput hardware architecture for SVAC SAO, with the following technical solution:

[0007] A high-throughput hardware architecture for SVAC SAO includes:

[0008] The statistical collection unit is used to receive the original sample block and the DBF reconstructed sample block, and obtain the Sum and Count statistical results of EO and BO in one CTU-level traversal. The statistical collection unit uses 2×2 sample blocks as the basic processing granularity, and through the register window, it enables four samples to complete EO four-direction classification and BO band classification in the same period. It also uses category-level local merging logic to sum the errors and counts of multiple samples under the same target category in the current period and write them into the corresponding statistical items.

[0009] The parameter decision unit receives the Sum and Count statistics output by the statistical collection unit, caches the SAO parameters of the adjacent CTUs above, and calculates the distortion cost and bitrate cost in OFF, MERGE, and NEW modes respectively. It then compares and outputs the optimal SAO parameters for the current CTU. The parameter decision unit uses fixed-point Lagrange multipliers. The fixed-point cost is calculated using the fixed-point bit rate estimate obtained from the lookup table, and the BO candidates are divided into three subspaces and configured with a three-way parallel traversal architecture for parallel evaluation.

[0010] The offset compensation unit receives the optimal SAO parameters and DBF reconstructed sample blocks output by the parameter decision unit. It is used to either directly output the input sample or determine whether the current sample needs compensation based on the mode selected by the current CTU, and to perform additive compensation and result pruning when the conditions are met. The offset compensation unit first determines the source of valid parameters, generates an EO class or BO band according to the compensation type, selects the corresponding offset value, performs additive compensation and result pruning, and outputs the compensated SAO reconstructed sample and the SAO parameters used for entropy encoding. The offset compensation unit employs a boundary-aware filtering region scheduling strategy, dividing the samples to be compensated into immediate compensation regions and delayed compensation regions.

[0011] Furthermore, the statistical area of ​​the statistical collection unit consists of the current CTB basic area and the left cross-CTB boundary neighborhood. After the DBF is completed in the adjacent CTU processing stage, the right boundary area of ​​the current CTU participates in the statistics as the left extended statistical area of ​​the next CTU; while the original samples in the upper extended area are no longer cached and participate in the statistics.

[0012] Furthermore, the statistical collection unit adopts a parallel statistical data path based on 2×2 sample block reading and register window reuse, as follows: the statistical collection unit reads two new 2×2 sample blocks from the sample RAM each cycle, and together with two 2×2 historical sample blocks cached in the register, forms a sliding window covering four adjacent 2×2 sample blocks, providing directional neighborhoods for the four parallel statistical samples. EO classification is generated by the size relationship between the current sample and the two adjacent samples in the corresponding direction, and the four EO directions share the same window; BO classification is based on the amplitude of the current reconstructed sample and is mapped to one of the 32 bands through shift mapping.

[0013] Furthermore, the category-level local merging logic determines the category index of the four samples in the current period using the target category t as the unit. When the sample category is equal to the target category and the valid flag is true, its error value and count value are selected; otherwise, they are set to zero. The errors and counts of multiple samples under the same target category are summed to form the unique Sum increment and Count increment in the current period, and then written into the corresponding statistical items.

[0014] Furthermore, the parameter decision unit includes Above RAM, Sum RAM, Count RAM, MERGE path, NEW path, optimal mode selection module, and final parameter output module. The Above RAM caches the SAO parameters of the adjacent CTU above and provides parameter reuse information for the MERGE path. The Sum RAM and Count RAM store the residual accumulation value and sample count generated by the statistical collection unit and input them into the NEW path. In the NEW path, the Offset decision unit generates candidate offset values ​​based on the category-level Sum and Count, and the EO decision and BO decision respectively complete the parameter decision and cost evaluation for EO and BO types. The MERGE path and NEW path respectively output the corresponding mode decision results. The optimal mode selection module completes the unified comparison of the three modes: OFF, Merge, and NEW. The final parameter output module outputs the optimal SAO parameters of the current CTU.

[0015] Furthermore, the parameter decision unit decomposes the mode cost, type cost, and offset cost into relatively independent lookup table entries; the mode cost is used to distinguish between OFF, Merge, and NEW; the type cost is used to describe the EO direction index or BO position relationship; the offset cost is determined by the offset value magnitude and sign; for the BO type, the type cost is further indexed by the delta-band position features between the two bands; the lookup table output is the fixed-point code rate estimate; the fixed-point cost calculation formula is:

[0016] ,

[0017] in, The distortion change for each candidate offset value; R represents the fixed-point bit rate estimate obtained from the lookup table.

[0018] Furthermore, in the three-way parallel traversal architecture, each search unit reads the Sum and Count of the corresponding band combination in each cycle, calculates the distortion cost and bitrate cost of the candidate, and inputs the three candidate costs and the historical global optimal cost into a four-input minimum value comparator to update the global optimal BO parameters in each cycle.

[0019] Furthermore, in the boundary-aware filtering region scheduling strategy, the immediate compensation region corresponds to the samples within the current CTU that already have complete classification conditions, and uses the SAO parameters of the current CTU; the delay compensation region corresponds to the boundary samples that were delayed to the current stage because the neighboring samples had not previously met the DBF availability conditions, wherein the spatial affiliation of the top row delay compensation sample belongs to the previous row CTU, and uses the CTU parameters cached in the parameter RAM of the previous row CTU.

[0020] Furthermore, the offset compensation unit adopts a unified data path for EO / BO. The EO path selects directional neighborhood samples from the sliding window, left boundary buffer, upper boundary buffer, or top row buffer according to the directional pattern and completes the size relationship comparison. The BO path maps the current sample amplitude to 32 bands and determines whether the target band group is hit.

[0021] Beneficial effects

[0022] This invention decouples the statistical window from the compensation window, restricting access to raw samples during the statistical phase to the current CTB and the necessary left boundary, thus reducing on-chip storage overhead and cross-CTU data synchronization complexity. It supports parallel classification and statistical accumulation of multiple samples, merging statistical results of hits in the same class or band within the same period through a category-level local merging mechanism, improving statistical throughput and avoiding write conflicts for similar statistical items. By transforming dynamic bitrate estimation and floating-point calculation into a lookup-style fixed-point RDO path, it quickly obtains the bitrate term and combines it with fixed-point λ to complete cost comparison, thereby reducing control complexity and critical path latency. Through a three-way parallel BO candidate search structure, it compresses the SVAC BO candidate search cycle from 435 to 145, reducing parameter decision latency. Without changing the SAO syntax and the decoding compensation process, this invention achieves high-throughput hardware mapping for the statistical, decision-making, and compensation processes. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of a high-throughput hardware architecture for SVAC SAO;

[0024] Figure 2 A diagram illustrating the differences in selection rules between VVC and SVAC BO bands;

[0025] Figure 3 This is a schematic diagram comparing the statistical region of the reference model with the statistical region of this invention;

[0026] Figure 4 A schematic diagram showing the organization of statistical regions at different locations;

[0027] Figure 5 This is a schematic diagram of a parallel statistical data path based on 2×2 sample block reading and register window multiplexing;

[0028] Figure 6 This is a schematic diagram of the category-level local merge logic;

[0029] Figure 7 This is a schematic diagram of RDO optimization based on lookup table-based rate estimation and fixed-point operation;

[0030] Figure 8This is a schematic diagram of the traversal process of a three-way parallel traversal architecture;

[0031] Figure 9 This is a schematic diagram of the organization of filter regions at different locations in a boundary-aware filter region scheduling strategy. Detailed Implementation

[0032] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0033] like Figure 1 As shown, the high-throughput hardware architecture for SVAC SAO of this invention is suitable for loop filtering modules in video encoding chips. This architecture receives raw sample blocks and reconstructed sample blocks after DBF (Database Filtering), and sequentially completes statistical collection, parameter decision-making, and offset compensation in a CTU-level pipelined order, outputting SAO-compensated reconstructed samples and SAO syntax parameters for entropy coding. The overall data stream uses 2×2 sample blocks as the basic processing granularity, where raw samples are only sent to the statistical collection unit for error accumulation, while reconstructed samples after DBF are simultaneously sent to both the statistical collection unit and the offset compensation unit for classification statistics and final compensation.

[0034] The specific architecture is as follows:

[0035] I. Statistical Collection Unit

[0036] The statistical collection unit is used to simultaneously obtain the Sum and Count statistical results of EO and BO in a single CTU-level traversal. For each image component, the EO part contains four orientation types, each orientation type contains five classes; the BO part contains 32 bands, thus each component corresponds to 52 sets of statistical terms. Each set of statistical terms includes a signed error accumulator and an unsigned sample count accumulator, where Sum is used to accumulate the difference between the original samples and the reconstructed samples after DBF, and Count is used to count the number of valid samples that hit the class or band.

[0037] Regarding boundary organization, the statistical region of this invention is as follows: Figure 3 As shown, it consists of the current CTB basic region and the neighboring region across the left CTB boundary. Figure 4 As shown, the right boundary region of the current CTU, after the DBF is completed in the adjacent CTU processing stage, participates in the statistics as the left extended statistical region of the next CTU; while the original samples of the upper extended region are no longer cached or participate in the statistics. This design preserves the contribution of the left boundary samples to parameter decisions, while avoiding caching of the original samples of the upper extended region, thereby reducing on-chip storage and cross-CTU synchronization overhead.

[0038] In parallel classification, such as Figure 5As shown, the statistical unit reads two new 2×2 sample blocks from the sample RAM each cycle, and these, together with two 2×2 historical sample blocks cached in the register, form a sliding window. This window covers four adjacent 2×2 sample blocks, providing directional neighborhoods for the four parallel statistical samples. EO classification is generated based on the magnitude relationship between the current sample and its two adjacent samples in the corresponding direction; the four EO directions share the same window. BO classification is based on the amplitude of the currently reconstructed sample, mapped to one of 32 bands through shifting.

[0039] like Figure 6 As shown, to avoid accumulation conflicts caused by parallel statistics of multiple samples, the category-level local merging logic determines the category index of the four samples in the current period using the target category t as the unit. When the sample category equals the target category and the valid flag is true, its error value and count value are selected; otherwise, they are set to zero. Subsequently, the errors and counts of multiple samples under the same target category are summed separately to form the unique Sum increment and Count increment for the current period, which are then written to the corresponding statistical items. Thus, the statistical RAM does not need to be configured with multiple write ports to support multiple samples hitting the same category in the same period.

[0040] From a hardware resource reuse perspective, 2×2 pixel blocks not only improve data throughput but also significantly reduce the overhead of neighborhood comparison and window organization. If single-pixel point-by-point processing is used, each pixel needs to establish a comparison and classification relationship with its eight neighboring pixels during the statistical and filtering stages, resulting in 4×8=32 neighboring pixel references for four pixels. With unified processing using 2×2 blocks, four pixels share the same 4×4 neighborhood window, and its eight-neighbor union only contains the outer 12 unique neighboring pixels. Therefore, the number of neighboring references is reduced from 32 to 12, a reduction of approximately 62.5%, and the equivalent neighborhood reuse rate is increased by approximately 2.67 times. This reuse relationship allows comparator input selection, window register, and boundary buffer read / write control to all be implemented around a block-level structure, reducing redundant hardware while maintaining the parallel statistical capability of four samples.

[0041] The statistical collection unit and the offset compensation unit further adopt the same granularity of 2×2 pixel block organization. In the statistical stage, this block structure is used to complete the synchronous classification and error accumulation of the original samples and the reconstructed samples after DBF. In the filtering stage, the isomorphic block structure continues to be used to complete EO / BO classification, offset acquisition, and cropping output. Since the two types of units share the same sample block arrangement, sliding window boundary relationship, and row and column address rhythm, the on-chip RAM does not need to configure two separate sets of neighborhood caches for the statistical window and the filtering window. The left boundary, upper boundary, and the sample cache within the current CTU can all be organized according to a unified block interface, thereby further reducing RAM and LUTRAM resource consumption.

[0042] II. Parameter Decision Unit

[0043] The parameter decision unit consists of Above RAM, Sum RAM, Count RAM, MERGE path, NEW path, optimal mode selection module, and final parameter output module. Above RAM caches the SAO parameters of the adjacent CTU above and provides parameter reuse information for the MERGE path. Sum RAM and Count RAM store the accumulated residual values ​​and sample counts generated during the statistical phase and input them into the NEW path. In the NEW path, the Offset decision unit generates candidate offset values ​​based on the category-level Sum and Count, and EOdecision and BO decision complete the parameter decisions and cost evaluations for EO and BO types, respectively. The MERGE path and NEW path output the corresponding mode decision results, and finally, the optimal mode selection module performs a unified comparison of the OFF, Merge, and NEW modes. The final parameter output module outputs the optimal SAO parameters for the current CTU.

[0044] In offset estimation, this invention generates initial candidate offset values ​​based on the category-level average error relationship and uses SVAC to constrain the values ​​of EO categories and BO bands for amplitude limiting. For EO types, "valley" and "half-valley" classes typically use positive offset values, "peak" and "half-peak" classes typically use negative offset values, and flat classes do not participate in compensation; for BO types, each band independently determines candidate offset values ​​based on its Sum and Count. The distortion change of each candidate offset value is as follows:

[0045] ,

[0046] Category-level RD costs are determined by both the distortion term and the bitrate term.

[0047] like Figure 7 As shown, in rate estimation, this invention separates the mode cost, type cost, and offset cost into relatively independent lookup table entries. The mode cost is used to distinguish between OFF, Merge, and NEW; the type cost is used to describe the EO direction index or BO positional relationship; and the offset cost is determined by the offset magnitude and sign. For the BO type, the type cost is further indexed by positional features such as delta-band between the two bands. The lookup table output is a fixed-point rate estimate, which can be compared with fixed-point... It directly participates in RDO calculations.

[0048] exist In fixed-point conversion, floating-point First convert to That is, the Lagrange multipliers are approximated using 2-bit binary fractional precision. The fixed-point cost of the candidate parameters is calculated as follows:

[0049] ,

[0050] Where R represents the fixed-point code rate estimate obtained from the lookup table. Since all candidates are compared at the same scaling scale, the hardware can directly select the minimum cost candidate based on J_Q without having to revert to floating-point form.

[0051] BO decision-making is the main source of complexity in SVAC SAO parameter decision-making. SVAC BO organizes the four bands to be compensated into two band groups, each containing two consecutive bands, and the two groups can be non-consecutive. Under the starting position and delta-band constraints, the number of valid candidates is 435. Directly traversing the data serially using a double loop in the software algorithm would result in a long decision-making delay, such as... Figure 8 As shown, this embodiment divides the 435 BO candidates into three non-overlapping subspaces according to their candidate numbers or positional relationships, and configures three isomorphic search channels. Each search unit reads the Sum and Count of the corresponding band combination in each cycle, calculates the distortion cost and bitrate cost of the candidate, compares it with the current best result of the current channel, and inputs the costs of the three new candidates and the historical global best cost into a four-input minimum comparator to update the global best BO parameters in each cycle. After traversal, the result retained in the register is the global best result among the 435 legal candidates. This structure compresses the search cycle from 435 to 145, while maintaining consistency with the software reference flow in the candidate set, cost calculation method, and priority rules for the same cost.

[0052] III. Offset Compensation Unit

[0053] The offset compensation unit is responsible for applying the optimal SAO parameters output by the parameter decision unit to the DBF to reconstruct the sample. If the current CTU is in OFF mode, the input sample is directly output; if Merge or NEW mode is selected, the offset compensation unit determines whether the current sample needs compensation based on the mode, type, band position, and offset value, and performs additive compensation and result pruning when the conditions are met. Merge and NEW share the same data path in the sample-level compensation stage, with the only difference being the parameter source.

[0054] The offset compensation process includes five steps: parameter selection, sample classification, offset value acquisition, additive compensation, and result pruning. In the parameter selection stage, valid parameter sources are determined based on the current sample location and SAO mode. In the sample classification stage, an EO class or BO band is generated based on the compensation type. In the offset value acquisition stage, the corresponding offset value is selected based on the classification results and parameter information. In the additive compensation stage, the offset value is applied to DBF and the sample is reconstructed. In the result pruning stage, the output sample is ensured to be within the allowable range of the current bit depth.

[0055] like Figure 9As shown, to address the issues of sample availability and parameter source switching at CTU boundaries, this embodiment employs a boundary-aware filtering region scheduling strategy. The samples to be compensated in the current stage are divided into immediate compensation regions and delayed compensation regions. The immediate compensation region corresponds to samples within the current CTU that already meet the complete classification conditions, using the current CTU's SAO parameters; the delayed compensation region corresponds to boundary samples whose processing was postponed to the current stage because neighboring samples had not previously met the DBF availability conditions. Although the top-row delayed compensation samples are compensated in the current CTU stage, their spatial affiliation still belongs to the previous row of CTUs, therefore, the CTU parameters cached in the parameter RAM of the previous row of CTUs are used.

[0056] In the unified EO / BO data pathway, the EO path selects directional neighborhood samples from the sliding window, left boundary buffer, upper boundary buffer, or top row buffer based on the directional pattern and performs a size comparison; the BO path maps the current sample amplitude to 32 bands and determines whether the target band group has been hit. Both paths retain necessary differences at the classification front end while sharing offset value reading, sample addition, and pruning logic, thereby reducing redundant arithmetic resources and maintaining a consistent data rhythm.

[0057] Based on the aforementioned 2×2 pixel block multiplexing, statistical / filtering isomorphic block interface, and lookup table-based fixed-point RDO decision structure, this embodiment verifies the hardware implementation results on an FPGA platform. Based on a Xilinx Kintex UltraScale+ series FPGA, the system design can reach a maximum operating frequency of 300MHz. After resource multiplexing optimization, the main resource consumption is concentrated in three categories: LUTs, registers, and RAM: 16984 CLB LUTs are used; 16967 CLB Registers are used; and 776 LUTRAMs are used. The above results demonstrate that 2×2 block-level window multiplexing and the unified statistical / filtering pixel block structure effectively suppress the resource growth caused by window buffering and repeated comparison logic while improving throughput.

[0058] Regarding the CTU processing cycle, this embodiment calculates the throughput by executing the statistical, decision-making, and filtering stages sequentially: the statistical collection unit requires 1181 cycles / CTU, the parameter decision-making unit requires 700 cycles / CTU, approximately 900 cycles / CTU under complex candidate conditions, and the offset filtering unit requires 1211 cycles / CTU. Therefore, the typical serial cumulative cycle is 1181 + 700 + 1211 = 3092 cycles / CTU; the conservative serial cumulative cycle is 1181 + 900 + 1211 = 3292 cycles / CTU. Based on a resolution of 3840×2160 and a CTU division of 64×64, each frame of 4K video contains 60×34=2040 CTUs, which means each frame has 3092×2040=6307680 cycles. Under complex candidate conditions, it reaches 3292×2040=6715680 cycles. The frame rate = clock frequency / number of cycles per frame, which means that at 300MHz, the frame rates are approximately 4K@47.56fps and 4K@44.67fps respectively.

[0059] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A high-throughput hardware architecture for SVAC SAO, characterized in that, include: The statistical collection unit is used to receive the original sample block and the DBF reconstructed sample block, and obtain the Sum and Count statistical results of EO and BO in one CTU-level traversal. The statistical collection unit uses 2×2 sample blocks as the basic processing granularity, and through the register window, it enables four samples to complete EO four-direction classification and BO band classification in the same period. It also uses category-level local merging logic to sum the errors and counts of multiple samples under the same target category in the current period and write them into the corresponding statistical items. The parameter decision unit receives the Sum and Count statistics output by the statistical collection unit, caches the SAO parameters of the adjacent CTUs above, and calculates the distortion cost and bitrate cost in OFF, MERGE, and NEW modes respectively. It then compares and outputs the optimal SAO parameters for the current CTU. The parameter decision unit uses fixed-point Lagrange multipliers. The fixed-point cost is calculated using the fixed-point bit rate estimate obtained from the lookup table, and the BO candidates are divided into three subspaces and configured with a three-way parallel traversal architecture for parallel evaluation. The offset compensation unit receives the optimal SAO parameters and DBF reconstructed sample blocks output by the parameter decision unit. It is used to either directly output the input sample or determine whether the current sample needs compensation based on the mode selected by the current CTU, and to perform additive compensation and result pruning when the conditions are met. The offset compensation unit first determines the source of valid parameters, generates an EO class or BO band according to the compensation type, selects the corresponding offset value, performs additive compensation and result pruning, and outputs the compensated SAO reconstructed sample and the SAO parameters used for entropy encoding. The offset compensation unit employs a boundary-aware filtering region scheduling strategy, dividing the samples to be compensated into immediate compensation regions and delayed compensation regions.

2. The high-throughput hardware architecture for SVAC SAO as described in claim 1, characterized in that: The statistical area of ​​the statistical collection unit consists of the current CTB basic area and the left cross-CTB boundary neighborhood. After the DBF is completed in the adjacent CTU processing stage, the right boundary area of ​​the current CTU participates in the statistics as the left extended statistical area of ​​the next CTU. The original samples in the extended region above are no longer cached or included in the statistics.

3. The high-throughput hardware architecture for SVAC SAO as described in claim 1, characterized in that: The statistical collection unit adopts a parallel statistical data path based on 2×2 sample block reading and register window reuse, as follows: Each cycle, the statistical collection unit reads two new 2×2 sample blocks from the sample RAM, and together with two 2×2 historical sample blocks cached in the register, they form a sliding window covering four adjacent 2×2 sample blocks, providing directional neighborhoods for the four parallel statistical samples. EO classification is generated by the size relationship between the current sample and the two adjacent samples in the corresponding direction, and the four EO directions share the same window; BO classification is based on the amplitude of the current reconstructed sample and is mapped to one of the 32 bands through shift mapping.

4. The high-throughput hardware architecture for SVAC SAO as described in claim 1, characterized in that: The category-level local merging logic determines the category index of the four samples in the current period using the target category t as the unit. When the sample category is equal to the target category and the valid flag is true, its error value and count value are selected; otherwise, they are set to zero. The errors and counts of multiple samples under the same target category are summed separately to form the unique Sum increment and Count increment for the current period, which are then written into the corresponding statistical items.

5. The high-throughput hardware architecture for SVAC SAO as described in claim 1, characterized in that: The parameter decision unit includes Above RAM, Sum RAM, Count RAM, MERGE path, NEW path, optimal mode selection module, and final parameter output module. Above RAM caches the SAO parameters of adjacent CTUs and provides parameter reuse information for the MERGE path. Sum RAM and Count RAM store the residual accumulation value and sample count generated by the statistical collection unit and input them into the NEW path. In the NEW path, the Offset decision unit generates candidate offset values ​​based on the category-level Sum and Count, and EOdecision and BO decision complete the parameter decision and cost evaluation for EO and BO types, respectively. The MERGE path and NEW path output the corresponding mode decision results. The optimal mode selection module performs a unified comparison of the three modes: OFF, Merge, and NEW. The final parameter output module outputs the optimal SAO parameters for the current CTU.

6. The high-throughput hardware architecture for SVAC SAO as described in claim 1, characterized in that: The parameter decision unit decomposes the mode cost, type cost, and offset cost into relatively independent lookup entries; the mode cost is used to distinguish between OFF, Merge, and NEW; the type cost is used to describe the EO direction index or BO position relationship; the offset cost is determined by the offset value magnitude and sign; for the BO type, the type cost is further indexed by the delta-band position features between the two bands. The lookup table output is the estimated fixed-point bit rate; the fixed-point cost calculation formula is: ， in, The distortion change for each candidate offset value; R represents the fixed-point bit rate estimate obtained from the lookup table.

7. The high-throughput hardware architecture for SVAC SAO as described in claim 1, characterized in that: In the three-way parallel traversal architecture, each search unit reads the Sum and Count of the corresponding band combination in each cycle, calculates the distortion cost and bitrate cost of the candidate, and inputs the three candidate costs and the historical global optimal cost into a four-input minimum value comparator to update the global optimal BO parameters in each cycle.

8. The high-throughput hardware architecture for SVAC SAO as described in claim 1, characterized in that: In the boundary-aware filtering region scheduling strategy, the instant compensation region corresponds to the samples within the current CTU that have complete classification conditions, and uses the SAO parameters of the current CTU; the delay compensation region corresponds to the boundary samples that have been delayed to the current stage because the neighboring samples have not yet met the DBF availability conditions. The spatial affiliation of the top row delay compensation samples belongs to the previous row CTU, and uses the CTU parameters cached in the parameter RAM of the previous row CTU.

9. The high-throughput hardware architecture for SVAC SAO as described in claim 1, characterized in that: The offset compensation unit adopts a unified data path for EO / BO. The EO path selects directional neighborhood samples from the sliding window, left boundary buffer, upper boundary buffer or top row buffer according to the directional pattern and completes the size relationship comparison. The BO path maps the current sample amplitude to 32 bands and determines whether the target band group is hit.

Images