System and method for displaying compressed image data in a display panel

Abstract

A method for compressing image data in a display panel is provided. The method includes grouping a plurality of pixels of the display panel into a plurality of consecutive blocks, and selecting a pixel pattern for a current block from a plurality of pixel patterns. Each block includes an array of pixels having M rows and N columns. Each pixel pattern is assigned an index. Each pixel pattern includes an array of pixels having M rows and N columns, and a portion of the array of pixels of each pixel pattern is compressed. The method further includes obtaining a similarity between the current block and a previous block, and then encoding the current block by a first encoding mode in response to the similarity meeting a preset similarity, or encoding the current block by a second encoding mode in response to the similarity not meeting the preset similarity.

Description

[0001] This application is a divisional application of Chinese patent application number PCT / CN2023 / 138282, which entered the Chinese national phase on December 12, 2025. Background Technology

[0002] This disclosure generally relates to display technology, and more specifically, to a system and method for compressing image data in a display panel.

[0003] Image data needs to be compressed during transmission to improve data transmission efficiency. Higher compression ratios result in higher data transmission efficiency and smaller storage capacity. However, as the compression ratio increases, the performance requirements for display manufacturing also increase. Excessive compression ratios may cause distortion in the decompressed image, resulting in poor image quality displayed on the display panel. Summary of the Invention

[0004] This disclosure generally relates to display technology, and more specifically, to a system and method for compressing image data in a display panel.

[0005] In one example, a method for compressing image data in a display panel having multiple pixels is provided. The method includes: grouping the multiple pixels into multiple consecutive blocks; and selecting a pixel pattern for the current block from multiple pixel patterns. Each block includes a pixel array with M rows and N columns, where M and N are positive integers. Multiple indices are assigned to each of the multiple pixel patterns, each pixel pattern including a pixel array with M rows and N columns, and a portion of the pixels in the pixel array of each pixel pattern are compressed. The method further includes: obtaining a similarity between the current block and a previous block; and then, in response to the similarity between the current block and the previous block meeting a preset similarity, encoding the current block using a first encoding pattern, or in response to the similarity between the current block and the previous block not meeting the preset similarity, encoding the current block using a second encoding pattern. The first encoding pattern includes the index of the pixel pattern assigned to the current block; the second encoding pattern includes the index of the pixel pattern assigned to the current block plus a first amount of content. The bit width of the first encoding pattern is shorter than the bit width of the second encoding pattern.

[0006] In one implementation, selecting a pixel pattern for the current block includes: selecting a first group of pixels and a second group of pixels from the current block based on each of the plurality of pixel patterns; calculating a first average value of the first group of pixels and a second average value of the second group of pixels; and assigning a pixel pattern to the current block in response to a first average value corresponding to the pixel pattern being greater than a minimum average threshold and a second average value corresponding to the pixel pattern being less than a maximum average threshold. The first group of pixels is located at the same positions as uncompressed pixels in the corresponding pixel pattern; the second group of pixels is located at the same positions as compressed pixels in the pixel pattern.

[0007] In one implementation, when more than one pixel mode is assigned to the current block, a pixel mode is selected from the more than one pixel mode by comparing multiple first average values ​​corresponding to the more than one pixel mode, and the pixel mode with the largest first average value is assigned to the current block.

[0008] In one implementation, selecting a pixel pattern for the current block includes: selecting a third group of pixels from the current block based on each of the plurality of pixel patterns; calculating the sum of the third group of pixels for each pixel pattern; and assigning the pixel pattern corresponding to the maximum sum to the current block, wherein the third group of pixels is located at the same position as the uncompressed pixels in that pixel pattern.

[0009] In one implementation, the number of compressed pixels in the pixel array of each pixel pattern is different from that of other pixel patterns, and / or the position of the compressed pixels in the pixel array of each pixel pattern is different from that of other pixel patterns.

[0010] In one implementation, the similarity includes a first difference between the values ​​of a first group of pixels in the current block and the values ​​of a first group of pixels in the previous block. A preset similarity is the maximum value of the first difference, and the similarity is considered to meet the preset similarity if the first difference is less than the maximum value of the first difference.

[0011] In one implementation, the similarity includes a second difference between the value of the i-th pixel in the current block and the value of the i-th pixel in the previous block, where i is a positive integer and M×N ≥ i ≥ 2, and the preset similarity is the maximum value of the second difference; and in response to the second difference being less than the maximum value of the second difference, the similarity meets the preset similarity.

[0012] In one implementation, the similarity includes a third difference obtained by accumulating at least a portion of the second difference from the second pixel to the (M×N)th pixel, the preset similarity is the maximum value of the third difference, and the similarity meets the preset similarity in response to the third difference being less than the maximum value of the third difference.

[0013] In one embodiment, the method further comprises: in response to the similarity between the current block and the previous block not meeting a preset similarity, acquiring the flatness between the current block and the previous block; in response to the flatness between the current block and the previous block meeting a preset flatness, encoding the current block through a third encoding mode, or in response to the flatness between the current block and the previous block not meeting the preset flatness, encoding the current block through a second encoding mode. The third encoding mode comprises the index of the pixel pattern assigned to the current block plus a second amount of content. The second amount of content is smaller than the first amount of content, and the bit width of the third encoding mode is shorter than the bit width of the second encoding mode and longer than the bit width of the first encoding mode.

[0014] In one embodiment, the flatness comprises a first ratio vector obtained by dividing the current block by the absolute value or the average value of the internal vector of the current block. The internal vector is an M-dimensional vector or an N-dimensional vector comprising the first pixel of the current block, the preset flatness comprises the average value of the first ratio vector and the peak value of the first ratio vector, and in response to the average value of the first ratio vector being less than the average value of the first ratio vector and the maximum value of the first ratio vector being less than the peak value of the first ratio vector, the flatness meets the preset flatness.

[0015] In one embodiment, the flatness comprises a second ratio obtained by comparing at least one of the maximum value, the minimum value or the average value of the 2nd to the (M×N)th pixels of the current block with the value of the first pixel of the current block, the preset flatness is a preset range [a, b], where a and b are positive numbers and a<1<b, and in response to the second ratio being within the preset range [a, b], the flatness meets the preset flatness.

[0016] In one embodiment, the method further comprises: acquiring the capacity of a buffer configured to store compressed images; in response to the capacity of the buffer being less than a capacity threshold, encoding the current block through a fourth encoding mode, or in response to the capacity of the buffer being greater than or equal to the capacity threshold, encoding the current block through the second encoding mode. The fourth encoding mode comprises the index of the pixel pattern assigned to the current block plus a third amount of content. The third amount of content is smaller than the first amount of content and larger than the second amount of content, and the bit width of the fourth encoding mode is shorter than the bit width of the second encoding mode and longer than the bit width of the third encoding mode.

[0017] In one embodiment, the capacity of the buffer is updated after each block is compressed based on the bit width of the encoding mode of the current block.

[0018] In one embodiment, before selecting a pixel pattern for each block, the method further comprises: in response to the plurality of pixels comprising three data channels, transforming the data of the plurality of pixels from an RGB color space to a YUV color space or a YCbCr color space.

[0019] In one implementation, the method further includes downsampling the data of the plurality of pixels before selecting a pixel mode for each block.

[0020] In one implementation, the method further includes transforming the data of the plurality of pixels from the time domain to the frequency domain before selecting a pixel mode for each block.

[0021] In one implementation, the method further includes quantizing data of the plurality of pixels in the frequency domain before selecting a pixel mode for each block.

[0022] In another example, a system for display is provided. The system includes a display with a plurality of pixels and a processor. The processor is configured to compress data of the plurality of pixels by grouping the plurality of pixels into a plurality of consecutive blocks and selecting a pixel pattern for the current block from a plurality of pixel patterns. Each block includes a pixel array with M rows and N columns, where M and N are positive integers. A plurality of indices are assigned to each of the plurality of pixel patterns. Each pixel pattern includes a pixel array with M rows and N columns, and a portion of the pixels in the pixel array of each pixel pattern are compressed. The processor is also configured to obtain a similarity between the current block and the previous block; in response to the similarity between the current block and the previous block meeting a preset similarity, the current block is encoded using a first encoding pattern, or in response to the similarity between the current block and the previous block not meeting the preset similarity, the current block is encoded using a second encoding pattern. The first encoding pattern includes the index of the pixel pattern assigned to the current block; the second encoding pattern includes the index of the pixel pattern assigned to the current block plus a first amount of content. The bit width of the first encoding pattern is shorter than the bit width of the second encoding pattern.

[0023] In one implementation, the processor is configured to select a pixel pattern for a current block by: selecting a first group of pixels and a second group of pixels from the current block based on each of the plurality of pixel patterns; calculating a first average value of the first group of pixels and a second average value of the second group of pixels; and assigning a pixel pattern to the current block in response to a first average value corresponding to the pixel pattern being greater than a minimum average threshold and a second average value corresponding to the pixel pattern being less than a maximum average threshold. The first group of pixels is located at the same positions as the uncompressed pixels in the corresponding pixel pattern, and the second group of pixels is located at the same positions as the compressed pixels in the pixel pattern.

[0024] In one implementation, when more than one pixel mode is assigned to the current block, the processor is configured to select a pixel mode for the current block by comparing multiple first average values ​​corresponding to the more than one pixel mode, and assign the pixel mode with the largest first average value to the current block.

[0025] In one implementation, the processor is configured to select a pixel pattern for the current block by: selecting a third group of pixels from the current block based on each of the plurality of pixel patterns; calculating the sum of the third group of pixels for each pixel pattern; and assigning the pixel pattern corresponding to the largest sum to the current block. The third group of pixels is located at the same position as the uncompressed pixels in that pixel pattern.

[0026] In one implementation, the number of compressed pixels in the pixel array of each pixel pattern is different from that of other pixel patterns, and / or the position of the compressed pixels in the pixel array of each pixel pattern is different from that of other pixel patterns.

[0027] In one implementation, the similarity includes a first difference between the values ​​of a first group of pixels in the current block and the values ​​of a first group of pixels in the previous block. A preset similarity is the maximum value of the first difference, and the similarity is considered to meet the preset similarity if the first difference is less than the maximum value of the first difference.

[0028] In one implementation, the similarity includes a second difference between the value of the i-th pixel in the current block and the value of the i-th pixel in the previous block, where i is a positive integer and M×N ≥ i ≥ 2. The preset similarity is the maximum value of the second difference, and the similarity meets the preset similarity in response to the second difference being less than the maximum value of the second difference.

[0029] In one implementation, the similarity includes a third difference obtained by accumulating at least a portion of the second difference from the second pixel to the (M×N)th pixel, the preset similarity is the maximum value of the third difference, and the similarity meets the preset similarity in response to the third difference being less than the maximum value of the third difference.

[0030] In one embodiment, the processor is further configured to: in response to a similarity between the current block and the previous block not meeting a preset similarity, obtain the flatness between the current block and the previous block; in response to the flatness between the current block and the previous block meeting the preset flatness, encode the current block using a third encoding mode, or in response to the flatness between the current block and the previous block not meeting the preset flatness, encode the current block using a second encoding mode. The third encoding mode includes the index of the pixel pattern assigned to the current block plus a second amount of content. The second amount of content is less than a first amount of content, and the bit width of the third encoding mode is shorter than the bit width of the second encoding mode but longer than the bit width of the first encoding mode.

[0031] In one embodiment, the flatness comprises a first ratio vector obtained by dividing a current block by the absolute value or the average value of an inner vector of the current block. The inner vector is an M-dimensional vector or N-dimensional vector comprising a first pixel of the current block, the preset flatness comprises an average value of the first ratio vector and a peak value of the first ratio vector, and in response to the condition that the average value of the first ratio vector is less than the preset average value of the first ratio vector and the maximum value of the first ratio vector is less than the preset peak value of the first ratio vector, the flatness conforms to the preset flatness.

[0032] In one embodiment, the flatness comprises a second ratio obtained by comparing at least one of the maximum value, the minimum value, or the average value of the 2nd to (M×N)th pixels of the current block with the value of the first pixel of the current block, the preset flatness is a preset range [a, b], where a and b are positive numbers and a<1<b, and in response to the second ratio being within the preset range [a, b], the flatness conforms to the preset flatness.

[0033] In one embodiment, the processor is further configured to acquire the capacity of a buffer configured to store compressed images; in response to the capacity of the buffer being less than a capacity threshold, encode the current block through a fourth encoding mode; in response to the capacity of the buffer being greater than or equal to the capacity threshold, encode the current block through a second encoding mode. The fourth encoding mode comprises the index of the pixel pattern assigned to the current block plus a third quantity of content. The third quantity of content is less than the first quantity of content and greater than the second quantity of content, and the bit width of the fourth encoding mode is shorter than the bit width of the second encoding mode and longer than the bit width of the third encoding mode.

[0034] In one embodiment, the capacity of the buffer is updated based on the bit width of the encoding mode of the current block after each block is compressed. Brief Description of the Drawings Figure 1 is a block diagram illustrating an apparatus comprising a display and control logic according to an embodiment.

[0035] Figure 2A-2B illustrates according to various embodiments Figure 1 side views of various examples of the display shown therein.

[0036] Figure 3 illustrates according to an embodiment Figure 1 a plan view of the display comprising a plurality of drivers shown therein.

[0037] Figure 4 shows a flowchart of a method for compressing pixel data in a display panel according to an embodiment.

[0038] Figures 5A-5D illustrates in an embodiment Figure 4 Multiple blocks of different sizes are used to compress pixel data.

[0039] Figure 6 A flowchart is shown for a method for preprocessing pixel data in a display panel according to one embodiment.

[0040] Figure 7 An embodiment is shown. Figure 6 The downsampling process of the method for preprocessing pixel data.

[0041] Figure 8 An embodiment is shown. Figure 6 The quantization process of preprocessing pixel data.

[0042] Figure 9 Multiple pixel patterns with a 4×4 pixel array are shown according to one embodiment.

[0043] Figure 10 A data pattern of compressed pixel data stored in a memory device according to one embodiment is shown.

[0044] Figure 11 A flowchart is shown for a method for decompressing pixel data in a display panel according to one embodiment. Detailed Implementation

[0045] In the following detailed embodiments, numerous specific details are illustrated by way of example to provide a thorough understanding of the relevant disclosure. However, it will be apparent to those skilled in the art that this disclosure may still be practiced even without these specific details. In other instances, well-known methods, steps, systems, components, and / or circuits are described at a higher level without providing details to avoid unnecessarily obscuring various aspects of this disclosure.

[0046] Throughout the specification and claims, certain terms may have nuanced meanings implied or suggested in a specific context beyond their explicitly stated meanings. Similarly, the phrases “in one embodiment” or “in one example” as used herein do not necessarily refer to the same embodiment, nor do the phrases “in another embodiment” or “in another example” necessarily refer to different embodiments. For example, the claimed subject matter includes all or part of the exemplary embodiments.

[0047] Generally, the understanding of a term can be determined at least in part by its usage in a specific context. For example, terms such as “and,” “or,” or “and / or” as used in this article can include a variety of meanings, which depend at least in part on the context in which the term is used. Typically, if “or” is used to relate a list, such as A, B, or C, it is intended to indicate A, B, and C in an inclusive sense, and A, B, or C in an exclusive sense. Furthermore, depending on the context, “one or more” as used in this article can be used to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending on the context, terms such as “a,” “one,” or “the” can also be understood to express singular or plural usage. Moreover, the term “based on” does not necessarily intend to indicate a set of exclusive factors, but can allow for the presence of other factors not explicitly described, which also depends at least in part on the context.

[0048] Image data needs to be compressed during transmission to improve data transmission efficiency. Higher compression ratios result in higher data transmission efficiency and smaller storage capacity. However, as the compression ratio increases, the performance requirements for display manufacturing also increase. Excessive compression ratios may cause distortion in the decompressed image, resulting in poor image quality displayed on the display panel.

[0049] To address the aforementioned problems, this disclosure provides a system and method for calibrating a display. At least one distortion scale parameter is employed to characterize the changes in distance and orientation between distorted pixel data and adjacent pixel data in at least one direction.

[0050] The novel features of this disclosure will be set forth in part in the following description, and in part will be obvious to those skilled in the art upon reading the following description in conjunction with the accompanying drawings, or may be learned by producing or operating the present example. The novel features of this disclosure may be realized and obtained through the practice or use of the methods, means, and combinations described in the following detailed embodiments.

[0051] For ease of description, as used herein, "data," "a piece of data," or similar expressions refer to a set of data (e.g., compensation data or display data) that may include one or more values. In this disclosure, for example, "pixel data" or "a piece of pixel data" refers to any number of values ​​used to compensate for a pixel. Pixel data may include at least one value used to compensate for a subpixel. "A piece of data" and "value" are interchangeable when a piece of data includes a single value. The specific number of values ​​included in a piece of data should not be limited.

[0052] Figure 1A device 100 is shown, including a display 102 and control logic 104. Device 100 can be any suitable device, such as a VR / AR device (e.g., a VR headset), a handheld device (e.g., a non-smartphone or smartphone, tablet, etc.), a wearable device (e.g., glasses, watch, etc.), a car control station, a game console, a television, a laptop, a desktop computer, a netbook, a media center, a set-top box, a Global Positioning System (GPS), an electronic billboard, an electronic sign, a printer, or any other suitable device. In this embodiment, the display 102 is operatively coupled to the control logic 104 and is part of device 100, such as, but not limited to, a head-mounted display, a computer monitor, a television screen, a dashboard, an electronic billboard, or an electronic sign. The display 102 can be an OLED display, a liquid crystal display (LCD), an E-ink display, an electroluminescent display (ELD), a billboard display with LEDs or incandescent lamps, or any other suitable type of display.

[0053] Control logic 104, which may be any suitable hardware, software, firmware, or a combination thereof, is configured to receive display data 106 (e.g., pixel data and compensation data) and generate control signals 108 for driving subpixels on display 102. Control signals 108 are used to control the writing of display data to subpixels and guide the operation of display 102. For example, subpixel rendering algorithms for various subpixel arrangements may be part of or implemented by control logic 104. Control logic 104 may include any other suitable components, such as encoders, decoders, one or more processors, controllers, and storage devices. Control logic 104 may be implemented as a stand-alone integrated circuit (IC) chip, such as an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). Device 100 may also include any other suitable components, such as, but not limited to, tracking devices 110 (e.g., inertial sensors, cameras, eye trackers, GPS, or any other suitable devices for tracking eye movements, facial expressions, head movements, body movements, and gestures) and input devices 112 (e.g., mice, keyboards, remote controls, handwriting devices, microphones, scanners, etc.).

[0054] In this embodiment, device 100 may be a handheld device or a VR / AR device, such as a smartphone, tablet, or VR headset. Device 100 may also include a processor 114 and a memory 116. Processor 114 may be, for example, a graphics processor (e.g., a graphics processing unit (GPU)), an application processor (AP), a general-purpose processor (e.g., an APU, accelerated processing unit; GPGPU, GPU-based general-purpose computing), or any other suitable processor. Memory 116 may be, for example, a discrete frame buffer or a unified memory. Processor 114 is configured to generate display data 106 in a display frame and may temporarily store the display data 106 in memory 116 before sending it to control logic 104. Processor 114 may also generate other data, such as, but not limited to, control instructions 118 or test signals, and provide them directly or via memory 116 to control logic 104. Control logic 104 then receives display data 106 from memory 116 or directly from processor 114. In some embodiments, no control instructions 118 are directly transmitted from processor 114 to control logic 104. In some implementations, compensation data transferred from processor 114 to memory 116 and / or from memory 116 to control logic 104 can be compressed.

[0055] In some embodiments, control logic 104 is part of device 100, processor 114 is part of an external device of device 100, and memory 116 is an external storage device for storing data calculated by processor 114. Data stored by processor 114 can be input to control logic 104 for further processing. In some embodiments, no control instructions 118 are transmitted from processor 114 to control logic 104. For example, device 100 may be a smartphone or tablet, and control logic 104 may be part of device 100. Processor 114 may be part of an external computer different from device 100 / control logic 104. Display data 106 may include any suitable data calculated by processor 114 and transmitted to control logic 104. For example, display data may include compression compensation data. In some embodiments, display data 106 does not include pixel data. Memory 116 may include a flash drive storing compression compensation data processed by processor 114. The memory 116 can be coupled to the control logic 104 to input compression compensation data into the device 100, so that the control logic 104 can decompress the compression compensation data and generate corresponding control signals 108 for the display 102.

[0056] Figure 2AThis is a side view illustrating an example of a display 102 including subpixels 202, 204, 206, and 208. Display 102 can be any suitable type of display, such as an OLED display, an active-matrix OLED (AMOLED) display, or any other suitable display. Display 102 may include a display panel 210 operatively coupled to control logic 104. Figure 2A The example shown illustrates a side-by-side (also known as a side-emitting) OLED color patterning architecture, where the luminescent material of one color is deposited through a metallic shadow mask, while other color areas are blocked by the mask.

[0057] In this embodiment, the display panel 210 includes a light-emitting layer 214 and a driving circuit layer 216. For example... Figure 2A As shown, the light-emitting layer 214 includes a plurality of light-emitting elements (e.g., OLEDs) 218, 220, 222 and 224, corresponding to a plurality of sub-pixels 202, 204, 206 and 208. Figure 2A In this context, A, B, C, and D represent different colored OLEDs, such as, but not limited to, red, green, blue, yellow, cyan, magenta, or white. The light-emitting layer 214 also includes a black array 226 disposed between OLEDs 218, 220, 222, and 224, such as... Figure 2A As shown. The black array 226 serves as the boundary for sub-pixels 202, 204, 206, and 208, blocking light from the outer portions of OLEDs 218, 220, 222, and 224. Each OLED 218, 220, 222, and 224 in the light-emitting layer 214 can emit light with a predetermined color and brightness.

[0058] In this embodiment, the driving circuit layer 216 includes a plurality of pixel circuits 228, 230, 232, and 234, each pixel circuit including one or more thin-film transistors (TFTs) corresponding to OLEDs 218, 220, 222, and 224 of sub-pixels 202, 204, 206, and 208. Pixel circuits 228, 230, 232, and 234 can be individually addressed by control signals 108 from control logic 104 and are configured to drive corresponding sub-pixels 202, 204, 206, and 208 by controlling the emission from the corresponding OLEDs 218, 220, 222, and 224 according to control signals 108. The driving circuit layer 216 may further include one or more drivers (not shown) formed on the same substrate as the pixel circuits 228, 230, 232, and 234. The on-panel drivers may include circuitry for controlling emission, gate scanning, and data writing, as detailed below. Scan lines and data lines are also formed in the driving circuit layer 216 for transmitting scan signals and data signals from the driver to each pixel circuit 228, 230, 232, and 234, respectively. The display panel 210 may include any other suitable components, such as one or more glass substrates, polarizing layers, or touch panels (not shown). In this embodiment, the pixel circuits 228, 230, 232, and 234, along with other components in the driving circuit layer 216, are formed on a low-temperature polycrystalline silicon (LTPS) layer deposited on the glass substrate, and the TFTs in each pixel circuit 228, 230, 232, and 234 are p-type transistors (e.g., PMOS LTPS-TFTs). In some embodiments, the components in the driving circuit layer 216 may be formed on an amorphous silicon (a-Si) layer, and the TFTs in each pixel circuit may be n-type transistors (e.g., NMOS TFTs). In some embodiments, the TFTs in each pixel circuit may be organic TFTs (OTFTs) or indium gallium zinc oxide (IGZO) TFTs.

[0059] like Figure 2AAs shown, each sub-pixel 202, 204, 206, and 208 is formed by at least one OLED 218, 220, 222, and 224 driven by corresponding pixel circuits 228, 230, 232, and 234. Each OLED can be formed by a sandwich structure of an anode, an organic light-emitting layer, and a cathode. Depending on the characteristics of the organic light-emitting layer of the corresponding OLED (e.g., material, structure, etc.), the sub-pixel can exhibit different colors and brightness. In this embodiment, each OLED 218, 220, 222, and 224 is a top-emitting OLED. In some embodiments, the OLEDs can be of different configurations, such as bottom-emitting OLEDs. In one example, a pixel can consist of three adjacent sub-pixels, such as sub-pixels of the three primary colors (red, green, and blue), to present full color. In another example, a pixel can consist of four adjacent sub-pixels, such as sub-pixels of the three primary colors (red, green, and blue) plus a white sub-pixel. In yet another example, a pixel can consist of two adjacent sub-pixels. For example, subpixels A 202 and B 204 can constitute one pixel, and subpixels C 206 and D 208 can constitute another pixel. Here, since display data 106 is typically programmed at the pixel level, two subpixels of each pixel or multiple subpixels of several adjacent pixels can be collectively addressed by subpixel rendering to present the appropriate brightness and color of each pixel specified in display data 106 (e.g., pixel data). However, it is understood that in some embodiments, display data 106 can be programmed at the subpixel level, so that display data 106 can directly address individual subpixels without subpixel rendering. Because three primary colors (red, green, and blue) are typically required to represent full color, a specially designed subpixel arrangement can be provided for display 102, combined with a subpixel rendering algorithm, to achieve an appropriate apparent color resolution. In some embodiments, the resolutions of red, green, and blue colors are equal to each other. In other embodiments, the resolutions of red, green, and blue colors may not be exactly the same.

[0060] Figure 2A The example shown illustrates a side-by-side patterned architecture where luminescent material of one color is deposited through a metallic shadow mask, while other color areas are blocked by the mask. In another example, a white OLED (WOLED+CF) patterned architecture with color filters can be applied to display panel 210. In the WOLED+CF architecture, a stack of luminescent material forms a white light-emitting layer. The color of each individual subpixel is defined by another layer of color filters of a different color. Because the organic luminescent material does not need to be patterned through a metallic shadow mask, the WOLED+CF patterned architecture can increase resolution and display size. Figure 2BAn example of a WOLED+CF patterned architecture applied to a display panel 210 is shown. In this embodiment, the display panel 210 includes a driving circuit layer 216, a light-emitting layer 236, a color filter layer 238, and an encapsulation layer 239. In this example, the light-emitting layer 236 includes a stack of light-emitting sublayers and emits white light. The color filter layer 238 may be included in a color filter array having a plurality of color filters 240, 242, 244, and 246 corresponding to sub-pixels 202, 204, 206, and 208. Figure 2B In this context, A, B, C, and D represent four different color filters, such as, but not limited to, red, green, blue, yellow, cyan, magenta, or white. Color filters 240, 242, 244, and 246 can be formed from a resin film containing dyes or pigments of the desired color. Depending on the characteristics of the respective color filter (e.g., color, thickness, etc.), sub-pixels can exhibit different colors and brightness. Encapsulation layer 239 can include an encapsulation glass substrate or a substrate manufactured using thin-film encapsulation (TFE) technology. Driving circuit layer 216 can include a pixel circuit array comprising LTPS, IGZO, or OTFT transistors. Display panel 210 can include any other suitable components, such as a polarizing layer or a touch panel (not shown).

[0061] Figure 3 It is shown according to one embodiment Figure 1 The diagram shows a plan view of a display 102 including multiple drivers. In this embodiment, the display panel 210 includes a subpixel array 300 (e.g., OLED), multiple pixel circuits (not shown), and multiple on-panel drivers, including a light-emitting driver 302, a gate scan driver 304, and a source write driver 306. The pixel circuits are operatively coupled to the subpixel array 300 and the on-panel drivers 302, 304, and 306. In this embodiment, the light-emitting driver 302 is configured to cause the subpixel array 300 to emit light in each frame. It can be understood that although... Figure 3 The diagram shows a single light-emitting driver 302, but in some embodiments, multiple light-emitting drivers can cooperate with each other.

[0062] In this embodiment, the gate scan driver 304 sequentially applies multiple scan signals S0-Sn, generated based on control signals 108 from control logic 104, to the scan lines (also referred to as gate lines) of each row of subpixels in the subpixel array 300. The scan signals S0-Sn are applied to the gate of the switching transistor in each pixel circuit during scan / charge to turn on the switching transistor, allowing the source write driver 306 to write the data signal of the corresponding subpixel. As described in detail below, the order in which the scan signals are applied to each row of the subpixel array 300 (i.e., the gate scan order) may differ in different embodiments. In some embodiments, not all subpixel rows are scanned in each frame. It can be understood that, although... Figure 3 The diagram shows a gate scan driver 304, but in some embodiments, multiple gate scan drivers can cooperate with each other to scan the subpixel array 300.

[0063] In this embodiment, the source write driver 306 is configured to write display data received from the control logic 104 into the sub-pixel array 300 in each frame. For example, the source write driver 306 can simultaneously apply data signals D0-Dm to the data lines (also called source lines) of each column of sub-pixels. That is, the source write driver 306 may include one or more shift registers, digital-to-analog converters (DACs), multiplexers (MUXs), and arithmetic circuitry for controlling the timing of the voltage applied to the source of the switching transistors of each pixel circuit (i.e., during scan / charge in each frame) and the magnitude of the voltage applied according to the grayscale of the display data 106. It can be understood that, although Figure 3 The figure shows a source write driver 306, but in some implementations, multiple source write drivers can cooperate with each other to apply data signals to the data lines of each column of subpixels.

[0064] As described above, the system and method for image data compression for a display panel can be executed by processor 114 or control logic 104. Processor 114 can be any processor capable of generating display data 106 (e.g., pixel data) in each frame and providing the display data 106 to control logic 104. Processor 114 can be, for example, a GPU, AP, APU, or GPGPU. Control logic 104 can receive other data, such as, but not limited to, control instructions 118 generated by processor 114. Figure 1 (Optional) or test signal ( Figure 2A (Not shown in the image). The display data 106 stream transmitted from processor 114 to control logic 104 may include raw display data and / or compensation data for pixels on display panel 210.

[0065] As described above, processor 114 can be any processor capable of generating display data 106 (e.g., pixel data and / or compensation data) for each frame and providing the display data 106 to control logic 104. Processor 114 can be, for example, a GPU, AP, APU, or GPGPU. Processor 114 can also generate other data, such as, but not limited to, control instructions 118. Figure 1 (Optional) or test signal ( Figure 2A (Not shown in the diagram), and provides them to control logic 104. The display data 106 stream transferred from processor 114 to control logic 104 may include raw display data and / or compensation data for pixels on display panel 210. In this embodiment, calibration is performed by processor 114. In other embodiments of this disclosure, calibration may be performed by control logic 104 or by a processor independent of the display system. The description of the embodiments should not be construed as limiting the present disclosure.

[0066] Figure 4 Some embodiments of the present disclosure are shown for compressing display panels (e.g., combining...) Figure 2A and Figure 2B The above-described flowchart illustrates a method 400 for processing pixel data of the display panel 210. It is understood that the operations shown in method 400 are not exhaustive; other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously or in different sequences. Figure 4 The execution sequence is shown.

[0067] like Figure 4 As shown, method 400 can begin with operation 402, in which multiple pixels of display panel 210 are grouped into multiple consecutive blocks, each block comprising a pixel array with M rows and N columns, where M and N are positive integers. Figures 5A-5D Multiple blocks of different sizes are shown in operation 402 for compressing pixel data according to different embodiments of this disclosure. For example, Figure 5A An exemplary block 510 is shown, where M=N=2, and multiple pixels of the display panel 210 are grouped into multiple 2×2 blocks. Figure 5B An exemplary block 520 is shown, where M=2, N=4, and multiple pixels of the display panel 210 are grouped into multiple 2×4 blocks. Figure 5C An exemplary block 530 is shown, where M=1, N=8, and multiple pixels of the display panel 210 are grouped into multiple 1×8 blocks. Figure 5D An exemplary block 540 is shown, where M=N=4, and multiple pixels of the display panel 210 are grouped into multiple 4×4 blocks. The size of each dimension of the block can be designed according to the needs of data compression.

[0068] In some implementations, prior to operation 402, data from multiple pixels of the display panel 210 is preprocessed to facilitate data compression. Figure 6 A flowchart of a method 600 for preprocessing pixel data prior to operation 402, according to some embodiments of this disclosure, is shown. It is understood that the operations shown in method 600 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously, or in different sequences. Figure 6 The execution sequence is shown.

[0069] like Figure 6 As shown, preprocessing method 600 can begin with operation 602, in which, in response to data from multiple pixels including three data channels, the data of pixels on display panel 210 is transformed from RGB space to YUV color space or YCbCr color space. Compared to RGB space, YUV color space is designed to facilitate data encoding and transmission and reduce data size and information errors. The transformation can be performed by a transformation matrix T as shown in formulas (1) and (2), where [i0, i1, i2] are vectors formed by the red, green, and blue grayscale values ​​of each pixel of the input image data, respectively, and [o0, o1, o2] are vectors formed by the output data of the YUV or YCbCr color space. In some embodiments, in response to data from multiple pixels including fewer than three data channels, operation 602 can be omitted.

[0070]

[0071] like Figure 6 As shown, the preprocessing method 600 can start from operation 604, in which the data of multiple pixels is downsampled to facilitate compression. Figure 7 An embodiment is shown. Figure 6 The downsampling process is described in the method for compressing pixel data. The downsampling method involves extracting a pixel data point Dvalue from an a×b pixel array, where a and b are positive integers, and the values ​​of a and b are recorded for subsequent decompression. The extracted pixel data Dvalue includes one of the following: average, median, maximum, minimum, specified value, and gradient value. The average is the average of the grayscale values ​​of the a×b pixels. The median is the median of the grayscale values ​​of the a×b pixels. The maximum is the maximum grayscale value of the a×b pixels. The minimum is the minimum grayscale value of the a×b pixels. The specified value is the grayscale value of the pixel located at a predetermined position within the a×b pixels array. The gradient value is the grayscale value of the pixel at the position with the largest gradient change within the a×b pixels array.

[0072] like Figure 6As shown, preprocessing method 600 can begin with operation 606, in which the data of multiple pixels is transformed from the time domain to the frequency domain. In some embodiments, the time-frequency transformation can be performed by executing a convolution process. The convolution matrix used in the time-frequency transformation can be preset. For example, the convolution formula used in one embodiment is shown in the following formula (3). Dvalue is the downsampled value of a×b pixels. MQ, C0, and C1 are transfer matrices, which can be set as needed. Fvalue is the transferred data in the frequency domain.

[0073]

[0074] like Figure 6 As shown, the preprocessing method 600 can start from operation 608, in which the data of multiple pixels in the frequency domain are quantized. Figure 8 An embodiment is shown. Figure 6 The quantization process of the method for preprocessing pixel data. The transmitted data is generated by at least one quantization parameter, and then rounded up or down to obtain quantized data. For example, three quantization formulas used in some embodiments of this disclosure are shown below, where Fvalue is the transmitted data after domain transmission, Q1 and Q2 are two parameters used to quantize the transmitted data Fvalue, and Qvalue is the quantized data. As shown below, formula (4) uses a rounding down function to quantize the transmitted data, formula (5) uses a rounding up function to quantize the transmitted data, and formula (6) uses a rounding function to quantize the transmitted data. The two parameters Q1 and Q2 can be designed as needed. The three formulas shown herein are for illustrative purposes and should not be construed as limiting the present disclosure.

[0075]

[0076] like Figure 4 As shown, after data preprocessing, method 400 proceeds to operation 404, in which a pixel pattern is selected for the current block from a plurality of pixel patterns. Multiple indices are assigned to each of the plurality of pixel patterns. Each pixel pattern comprises a pixel array with M rows and N columns, meaning that the plurality of pixel patterns have the same shape and size as each of the plurality of pixel blocks. In some embodiments, in operation 402, the plurality of pixels are grouped into a plurality of 4×4 blocks, such as... Figure 5D The exemplary block 540 shown is an example. Therefore, the multiple pixel pattern is designed to include a 4×4 pixel array to conform to the size and shape of the multiple blocks.

[0077] In this disclosure, a portion of the pixels in the pixel array of each pixel pattern are compressed. In some embodiments, the number of compressed pixels in the pixel array of each pixel pattern differs from that of other pixel patterns. In some embodiments, the positions of the compressed pixels in the pixel array of each pixel pattern differ from those of other pixel patterns. Figure 9 An eight-pixel pattern, each having a 4×4 pixel array, is shown according to one embodiment. (e.g.) Figure 9 As shown, the pixels retained in each pixel pattern represent pixels with higher weights than the compressed pixels (i.e., the blank spaces in each pixel pattern). The distribution of the retained pixels across multiple pixel patterns can be designed to cover the distribution of pixels with higher weights after time-frequency transformation. The number of pixel patterns can be designed based on the block size and shape, as well as the data compression ratio. The number of pixel patterns can be designed as needed. The larger the number of pixel patterns, the longer it takes to select a pixel pattern for the current block from among the multiple pixel patterns. There is a trade-off between the accuracy of the pixel patterns and the efficiency of the compression process. The number of pixel patterns shown in this disclosure is exemplary and should not be construed as a limitation of this disclosure.

[0078] In some implementations, a first method can be used to select a pixel pattern for the current block. First, the first method includes selecting a first group of pixels and a second group of pixels from the current block based on each of the plurality of pixel patterns. Figure 9 Taking pixel patterns as an example, for pixel pattern 1, the first group of pixels includes the pixels at positions (1,1), (2,2), (3,3), and (4,4) in the current block corresponding to pixel pattern 1, and the second group of pixels includes the remaining twelve pixels in the current block. For pixel pattern 2, the first group of pixels includes the pixel at position (1,1) in the current block corresponding to pixel pattern 2, and the second group of pixels includes the remaining fifteen pixels in the current block. For pixel pattern 3, the first group of pixels includes the pixels at positions (1,1), (1,2), (2,1), (2,2), (3,3), (3,4), (4,3), and (4,4) in the current block corresponding to pixel pattern 3, and the second group of pixels includes the remaining eight pixels in the current block. This method also applies to other pixel patterns.

[0079] Secondly, the first method includes calculating a first average value of a first group of pixels and a second average value of a second group of pixels. Still using... Figure 9Taking pixel patterns as an example, for pixel pattern 1, the first average value of pixel pattern 1 is the average value of Q0, Q1, Q2, and Q3 located at positions (1,1), (2,2), (3,3), and (4,4) in the current block, and the second average value of pixel pattern 1 is the average value of the remaining twelve pixels in the current block. In this embodiment, eight first average values ​​and eight second average values ​​are obtained for each of the eight pixel patterns. For each pixel pattern, the first average value is compared with a minimum average threshold, and the second average value is compared with a maximum average threshold. Then, in response to the first average value corresponding to the pixel pattern being greater than the minimum average threshold and the second average value corresponding to the pixel pattern being less than the maximum average threshold, a pixel pattern is assigned to the current block.

[0080] In some implementations, more than one pixel pattern is assigned to the current block. For example, in Figure 9 Of the eight pixel modes mentioned above, the first average value of pixel mode 1 and the first average value of pixel mode 6 are both greater than the minimum average threshold, while the second average value of pixel mode 1 and the second average value of pixel mode 6 are both less than the maximum average threshold. Then, selection continues from pixel mode 1 and pixel mode 6. Pixels in the first group are retained, while pixels in the second group are compressed during compression, with a larger first average value and a smaller second average value retaining more valid information about the current block. In some implementations, a pixel mode can be selected from more than one pixel mode by comparing the first average value corresponding to pixel mode 1 and the first average value corresponding to pixel mode 6, and then the pixel mode with the larger first average value is assigned to the current block. In some implementations, the first average value corresponding to pixel mode 1 is equal to the first average value corresponding to pixel mode 6, then the second average value corresponding to pixel mode 1 and the second average value corresponding to pixel mode 6 are compared, and then the pixel mode with the smaller second average value is assigned to the current block.

[0081] In some implementations, a second method can be used to select pixel patterns for the current block. First, a third group of pixels is selected from the current block based on each of the plurality of pixel patterns. The third group of pixels is located at the same positions as the uncompressed pixels in that pixel pattern. Then, the sum of the third group of pixels is calculated for each pixel pattern. Finally, the pixel pattern corresponding to the largest sum is assigned to the current block. In some implementations, no pixel pattern can produce a first average value greater than a minimum average threshold or a second average value less than a maximum average threshold. Then, a second method can be used to select pixel patterns for that block. The second method can be used independently or as a supplement to the first method.

[0082] like Figure 4As shown, after selecting a pixel mode for the current block, method 400 continues to operation 406, in which the similarity between the current block and the previous block is obtained.

[0083] In some implementations, the similarity includes a first difference between the values ​​of a first group of pixels in the current block and the values ​​of a first group of pixels in the previous block. A preset similarity is the maximum value of the first difference. The similarity satisfies the preset similarity if the first difference is less than the maximum value of the first difference. In some implementations, the similarity includes a second difference between the value of the i-th pixel in the current block and the value of the i-th pixel in the previous block, where i is a positive integer and M×N ≥ i ≥ 2. The preset similarity is the maximum value of the second difference, and the similarity satisfies the preset similarity if the second difference is less than the maximum value of the second difference. In some implementations, the similarity includes a third difference obtained by accumulating at least a portion of the second difference from the second pixel to the (M×N)-th pixel. The preset similarity is the maximum value of the third difference, and the similarity satisfies the preset similarity if the second difference is less than the maximum value of the second difference.

[0084] like Figure 4 As shown, method 400 then proceeds to operation 408 or operation 410, in which the current block is encoded based on the similarity between the current block and the previous block. In some embodiments, the similarity between the current block and the previous block meets a preset similarity, and then proceeds to operation 408 to encode the current block using a first encoding mode. In some embodiments, the similarity between the current block and the previous block does not meet the preset similarity, and then proceeds to operation 410 to encode the current block using a second encoding mode. The first encoding mode includes an index of a pixel pattern assigned to the current block. The second encoding mode includes the index of the pixel pattern assigned to the current block plus a first amount of content, and the bit width of the first encoding mode is shorter than the bit width of the second encoding mode.

[0085] In some implementations, if the similarity between the current block and the previous block does not meet a preset similarity, method 400 further includes obtaining the flatness between the current block and the previous block before proceeding to operation 410. In some implementations, if the flatness between the current block and the previous block meets a preset flatness, the current block is then encoded using a third encoding mode. In some implementations, if the flatness between the current block and the previous block does not meet the preset flatness, the current block is then encoded using a second encoding mode. The third encoding mode includes the index of the pixel pattern assigned to the current block plus a second amount of content. The second amount of content is less than a first amount of content, and the bit width of the third encoding mode is shorter than the bit width of the second encoding mode but longer than the bit width of the first encoding mode.

[0086] In some embodiments, the flatness includes a first ratio vector obtained by dividing a current block by the absolute value or the average value of an internal vector of the current block. The internal vector is an M-dimensional vector or N-dimensional vector including the first pixel of the current block. The preset flatness includes the average value of the first ratio vector and the peak value of the first ratio vector. In some embodiments, if the average value of the first ratio vector is less than the average value of the first ratio vector and the maximum value of the first ratio vector is less than the peak value of the first ratio vector, the flatness conforms to the preset flatness. In some embodiments, the flatness includes a second ratio obtained by comparing at least one of the maximum value, the minimum value, or the average value of the 2nd to the (M×N)th pixels of the current block with the value of the first pixel of the current block. The preset flatness is a preset range [a, b], where a and b are positive numbers and a<1<b, and in response to the second ratio being within the preset range [a, b], the flatness conforms to the preset flatness.

[0087] In some embodiments, the flatness between the current block and the previous block does not conform to the preset flatness. Before proceeding to operation 410, the method 400 further includes acquiring the capacity of a buffer configured to store compressed images, wherein the capacity of the buffer is updated based on the bit width of the encoding mode of the current block after each block is compressed. In some embodiments, if the capacity of the buffer is less than a capacity threshold, the current block is encoded through a fourth encoding mode. In some embodiments, if the capacity of the buffer is greater than or equal to the capacity threshold, the current block is encoded through a second encoding mode. The fourth encoding mode includes an index assigned to the pixel mode of the current block plus a third number of contents. The third number of contents is less than the first number of contents and greater than the second number of contents, and the bit width of the fourth encoding mode is shorter than the bit width of the second encoding mode and longer than the bit width of the third encoding mode.

[0088] After operation 408 or operation 410, the compression of the current block is completed, and the compressed data of the current block may be stored in the memory 116 of the display system, or other storage devices, such as the flash memory or Static Random-Access Memory (SRAM) of the display system. The compressed data may be in the form of Figure 10The compressed data is saved in the format shown. Each block's compressed data includes an index segment and a data segment. Checksum data is assigned to the compressed data for each image to verify the compressed data, and can be obtained through Cyclic Redundancy Check (CRC) or other available CAPTCHAs. The index segment of each block has the same length, and the length of the data segment of each block depends on the similarity between the current block and the previous block. In this disclosure, the data segment length of the current block is shortest when the similarity between the current block and the previous block meets a preset similarity, compared to other cases where the similarity between the current block and the previous block does not meet the preset similarity. In some embodiments, when the input image has high consistency and the similarity between any two adjacent blocks is high, the compression efficiency and compressed storage space of the input image will be significantly improved without sacrificing the quality of the compressed image.

[0089] The compressed data of the input image can be decompressed by the reverse process of compression. In some implementations, refer to... Figure 11 A method 1100 for decompressing compressed images is provided. For example... Figure 11 As shown, method 1100 first proceeds to operation 1102, in which the data segment and index segment of the current block are retrieved from memory 116 or other storage device used to store compressed data of the current block. The index segment of the current block indicates the data mode of the current block, and the length of the data segment of the current block indicates the encoding mode used in the compression of the current block. The data of the current block can be obtained using the index segment and data segment stored in memory 116.

[0090] like Figure 11 As shown, method 1100 first continues to operation 1104. In operation 1104, the data obtained during operation 1102 is dequantized using the dequantization formula used in operation 608, and the two parameters Q1 and Q2 are the same as the two parameters Q1 and Q2 used in operation 608. The inverse formulas of the three formulas used in operation 608 are shown below, where formula (7) is the inverse formula (4), formula (8) is the inverse formula (5), formula (9) is the inverse formula (6), Block_value is the data of the current block obtained during operation 1102, and IQvalue is the dequantized data after operation 1104.

[0091] (7) (8) (9) like Figure 11As shown, method 1100 first proceeds to operation 1106, in which the dequantized data IQvalue is inversely transformed from the frequency domain to the time domain. In some embodiments, the frequency-time transformation can be performed by performing a convolution process. The convolution matrix used in the frequency-time transformation is the inverse matrix of the matrix used in operation 606. For example, the convolution formula (10) used in one embodiment is shown below, where iMQ, iC0, and iC1 are the inverse matrices of matrices MQ, C0, and C1. IDvalue is the transmitted data in the time domain.

[0092]

[0093] like Figure 11 As shown, method 1100 first proceeds to operation 1108, in which the transmitted data IDvalue is upsampled based on the reciprocal of the downsampling ratio used in operation 604. Methods for performing upsampling include equivalent upsampling and interpolation upsampling. By using equivalent upsampling, the upsampled data in the current block is identical to the transmitted data IDvalue. By using interpolation upsampling, the upsampled data in the current block is obtained by linear interpolation based on the IDvalue.

[0094]

[0095] like Figure 11 As shown, method 1100 first proceeds to operation 1110, in which the upsampled data is transformed from the YUV or YCbCr color space to the RGB space to obtain the final decompressed data of the input image. The transformation can be performed by the inverse transformation matrix iT of the transformation matrix T as shown in equation (11), and iT × T = 1, as shown in equation (12). [IDvalue0, IDvalue1, IDvalue2] are vectors formed by the luminance, first chromaticity, and second chromaticity values ​​of each pixel of the upsampled data, respectively, and [d0, d1, d2] are vectors formed by the decompressed data in the RGB color space. In some embodiments, in response to data for multiple pixels including fewer than three data channels, operation 1110 can be omitted.

[0096] The above detailed description of this disclosure, along with the examples described therein, is for illustrative and descriptive purposes only and is not intended to be limiting. Therefore, this disclosure covers all modifications, variations, or equivalents within the spirit and scope of the fundamental underlying principles disclosed and claimed herein.

Claims

1. A method for compressing image data for a display panel, characterized in that, include: The display panel is divided into multiple consecutive pixel blocks, each pixel block consisting of a pixel array with M rows and N columns; Multiple pixel patterns are preset for the pixel block. Each pixel pattern corresponds to a pixel array with the same size as the pixel block. Only a portion of the pixels in each pixel pattern are retained for compressed representation. A unique pixel pattern index is assigned to each pixel pattern. Select a pixel pattern for the current pixel block; Obtain the similarity between the current pixel block and the previous pixel block; When the similarity meets the preset similarity condition, the current pixel block is encoded using the first encoding mode, wherein the first encoding mode only includes the pixel pattern index; When the similarity does not meet the preset similarity condition, the current pixel block is encoded using the second encoding mode, or the current pixel block is encoded using the third encoding mode when the preset flatness condition is met. in: The second encoding mode includes the pixel pattern index and a first amount of additional information; The third encoding mode includes the pixel pattern index and a second amount of additional information; The first quantity is greater than the second quantity; and The bit widths of the first encoding mode, the second encoding mode, and the third encoding mode increase sequentially.

2. The method according to claim 1, characterized in that, Different pixel modes retain different numbers of pixels and / or different pixel positions to correspond to different pixel weight distributions.

3. The method according to claim 1, characterized in that, Selecting a pixel mode for the current pixel block includes: Based on each pixel pattern, select the first pixel group from the current pixel block that corresponds to the reserved pixel position in that pixel pattern; Calculate the average or sum value of the first pixel group; The pixel pattern with the largest average or sum value is determined as the pixel pattern of the current pixel block.

4. The method according to claim 1, characterized in that, The similarity includes the difference in pixel value between at least one pixel in the current pixel block and the corresponding pixel in the previous pixel block.

5. The method according to claim 4, characterized in that, The similarity is obtained by accumulating the differences in pixel values ​​between multiple pixels in the current pixel block and the corresponding pixels in the previous pixel block.

6. The method according to claim 1, characterized in that, The flatness is determined based on the ratio between the maximum, minimum, or average value of multiple pixels in the current pixel block and the reference pixel value.

7. The method according to claim 1, characterized in that, The additional information includes residual information or compensation information for recovering pixels that were not retained.

8. The method according to claim 1, characterized in that, Also includes: Get the buffer capacity used to store compressed image data; When the buffer capacity is less than the capacity threshold, the current pixel block is encoded using an encoding mode with a smaller bit width.

9. A display system, comprising a display panel and a processor, characterized in that, The processor is configured to perform the method according to any one of claims 1–8.

10. A system for display, comprising: A display with multiple pixels; The processor is configured to compress the data of the plurality of pixels in the following manner: The plurality of pixels are grouped into a plurality of consecutive blocks, each block comprising a pixel array having M rows and N columns, where M and N are positive integers; Select a pixel pattern for the current block from multiple pixel patterns, where each pixel pattern includes a pixel array with M rows and N columns, the number of compressed pixels in the pixel array of each pixel pattern is different from the other pixel patterns, and the position of the compressed pixels in the pixel array of each pixel pattern is different from the other pixel patterns. Get the similarity between the current block and the previous block; In response to the similarity meeting a preset similarity, the current block is encoded using a first encoding mode, wherein the first encoding mode includes an index of a pixel pattern assigned to the current block; In response to the similarity not meeting the preset similarity, the flatness between the current block and the previous block is obtained; In response to the flatness conforming to a preset flatness, the current block is encoded using a third encoding mode, wherein the third encoding mode includes the index of the pixel mode assigned to the current block plus a second amount of content; In response to the flatness not conforming to a preset flatness, the current block is encoded using a second encoding mode, wherein the second encoding mode includes the index of the pixel pattern assigned to the current block plus a first quantity of content, and the first quantity of content is greater than a second quantity of content; and The bit width of the first encoding mode is shorter than the bit width of the third encoding mode, and the bit width of the third encoding mode is shorter than the bit width of the second encoding mode.

Images