FPGA-based logo chain storage and broadcasting method and device

Abstract

Embodiments of the present application provide a LOGO chain storage and playing method and device based on FPGA, the method comprising: binding and packing single frame filling data and key value data of a LOGO, and encapsulating a chain information header in the header; sequentially linking one or more single LOGO chain frame chains in a preset playing order through a next packet address pointer in the information header; traversing and analyzing the chain frame chain corresponding to the current playing LOGO through a LOGO global ID index, and sequentially reading each frame data packet; analyzing the chain information header section of the read data packet, performing security check, and determining the reading address of the next frame according to the check result and a preset playing mode to realize playing; and after adaptive format conversion of the LOGO frame data that passes the check, superimposing and outputting the LOGO frame data with background video to realize superimposition processing of static LOGO, dynamic LOGO and rolling caption bar in multiple systems, multiple channels and multiple sequences.

Description

Technical Field

[0001] This application relates to the fields of professional video processing for broadcast television, FPGA hardware acceleration, and embedded real-time systems, specifically to an FPGA-based method and apparatus for chained storage and broadcasting of logos. Background Technology

[0002] Current broadcast logo (station logo, corner logo, graphic subtitle) processing technology still has the following performance or functional limitations, making it unable to meet the needs of large-scale broadcast systems for multi-logo linkage, complex playback sequences, and dynamic online editing: Linear storage has poor flexibility. If you need to modify the playback sequence, splice logo clips, or customize loop rules, you must rewrite all the data. You cannot complete the sequence editing online, which is not suitable for the needs of quick replay changes and temporary insertions in live streaming scenarios.

[0003] The management of multiple logo groups is complex and consumes a lot of logic resources. In linear storage solutions, each independent logo needs to be configured with a complete set of address, length and frame number registers. When multiple logos are played in linkage or multiple channels of logos are played synchronously, there are too many register configurations and playback control logics, resulting in high FPGA (Field Programmable Gate Array) logic resource consumption.

[0004] The playback modes are limited, and complex sequence control cannot be achieved. The existing solution can only achieve basic playback modes such as forward, reverse and full loop, and cannot achieve complex playback logic such as segment looping, specified frame jump, seamless splicing of multiple logos, and conditional trigger switching. It cannot adapt to complex broadcasting scenarios such as dynamic subtitle bars, program packaging animations, and emergency logo insertion.

[0005] Low storage resource utilization and inability to reuse frame data: In linear storage solutions, even if multiple LOGO sequences have the same frame data, they need to be stored repeatedly, and frame-level reuse cannot be achieved; when the same LOGO is broadcast on multiple channels, data needs to be written repeatedly in each channel partition, resulting in insufficient storage space, and storage overhead increases linearly in large multi-channel systems.

[0006] The linear continuous storage scheme has weak sequence-level fault tolerance. When a single frame error causes a chain of failures, it is very easy for the entire subsequent LOGO sequence to play out of order or for the address to go out of bounds. Summary of the Invention

[0007] To address one of the aforementioned technical deficiencies, this application provides an FPGA-based method and apparatus for chained storage and playback of logos.

[0008] According to a first aspect of the embodiments of this application, a method for chained storage and playback of LOGO based on FPGA is provided, comprising the following steps: The single-frame fill data and key-value data of the logo are bound and packaged, and a chain information header is encapsulated in its header to form a chain single-frame data packet containing a chain information header segment, a fill data segment and a key-value data segment. The chain information header segment at least contains a next packet address pointer pointing to the storage address of the next frame data packet and a verification field. Multiple chained single-frame data packets are stored in a non-contiguous address space of an external memory. During the storage process, a cyclic redundancy check (CRC) is calculated, and the packets are linked sequentially according to a preset playback order through the next packet address pointer in each data packet to form one or more single-LOGO chained frame chains. Based on the vertical synchronization signal of the video output, the FPGA hardware traverses and parses the chain of frames corresponding to the currently playing logo, and reads the data packets of each frame in sequence. The chained information header segment of the read data packet is parsed, a security check is performed, and the reading address of the next frame is determined according to the check result and the preset playback mode, so as to realize at least one of the following: sequential playback, loop playback, segment jump or multi-LOGO splicing playback. After adaptive format conversion of the verified LOGO frame data, it is overlaid with the background video and output.

[0009] In an optional embodiment of this application, the chained information header segment further includes: a frame header synchronization code, a global LOGO ID, a frame sequence number, a frame type, a playback control word, a pointer to the previous packet address, a pixel bit width, a pixel format, a link CRC checksum, and a data CRC checksum. The chained information header segment has a fixed byte length to meet hardware address alignment requirements. In an optional embodiment of this application, the frame type is used to identify the attributes of the chained single-frame data packet, the attributes including static single frame, first frame of sequence, middle frame of sequence, last frame of sequence, multiplexed frame, or jump frame; the playback control word includes at least one parameter selected from loop count, frame duration, or jump trigger condition. In an optional embodiment of this application, the single-LOGO chained frame chain is a doubly linked circular list, wherein the address pointer of the previous packet of the first frame of the sequence points to the last frame of the sequence, and the address pointer of the next packet of the last frame of the sequence points to the first frame of the sequence; the chained frame chains of different LOGOs are indexed and uniformly managed in the global LOGO storage list through their global IDs, and the global storage list is divided into independent partitions according to the broadcast channel ID, and the addresses between channels are isolated.

[0010] In an optional embodiment of this application, the method further includes: If the CRC check of the current frame fails, a first-level fault tolerance is triggered: the correct data of the previous frame is read back and reused according to the address pointer of the previous packet for playback, while skipping the address pointer of the erroneous frame and directly addressing the frame data pointed to by the address pointer of the next packet of the erroneous frame to ensure continuous playback of the sequence; if the link CRC check of the current frame fails or the address pointer illegally goes out of bounds, a second-level fault tolerance is triggered: the FPGA automatically jumps to the first frame of the current LOGO sequence to re-loop playback and reports the fault information to the CPU through the register; if multiple consecutive frames fail the check, the static backup frame is locked for playback to avoid system crash.

[0011] In an optional embodiment of this application, the method further includes a non-intrusive online update step for the LOGO data: employing an A / B mutual exclusion double-buffered storage partitioning mechanism, wherein the playback partition is used for current playback, and the update partition is used to receive new or modified chained frame data; during the video field blanking period, the playback base address is seamlessly switched from the playback partition to the update partition to complete the online update or sequence editing of the LOGO data. The storage controller maintains a reference count for each data packet. The count is incremented by 1 when a frame is bound to a data packet, and decremented by 1 when a frame is unbound and deleted. When the reference count reaches zero, the hardware automatically releases the storage space occupied by that frame. In an optional embodiment of this application, the method further includes a frame multiplexing step: when multiple different LOGO chained frame chains need to use the same frame of LOGO data, the frame data packet is stored only once in the external memory, and in each chained frame chain that needs the frame, the address pointer at the corresponding position points to the same storage address. According to a second aspect of the embodiments of this application, an FPGA-based LOGO chain storage and playback device is provided, comprising: The encapsulation module is used to bind and package the single-frame fill data and key-value data of the LOGO, and encapsulate a chain information header in its header to form a chain single-frame data packet containing a chain information header segment, a fill data segment and a key-value data segment. The chain information header segment at least contains a next packet address pointer pointing to the storage address of the next frame data packet and a verification field. The linking module is used to store multiple chained single-frame data packets in a non-contiguous address space of an external memory. During the storage process, the cyclic redundancy check (CRC) is calculated, and the packets are linked sequentially according to a preset playback order through the next packet address pointer in each data packet to form one or more single-LOGO chained frames. The reading module is used to read the data packets of each frame sequentially by traversing and parsing the chain of frames corresponding to the currently playing logo based on the vertical synchronization signal of the video output by the FPGA hardware. The verification module is used to parse the chained information header segment of the read data packet, perform security verification, and determine the reading address of the next frame according to the verification result and the preset playback mode, so as to realize at least one of the following: sequential playback, loop playback, segment jump or multi-LOGO splicing playback. The output module is used to adaptively convert the verified LOGO frame data into a new format and then overlay it onto the background video for output.

[0012] According to a third aspect of the embodiments of this application, a computer device is provided, comprising: Memory; Processor; and Computer programs; The computer program is stored in the memory and configured to be executed by the processor to implement the FPGA-based LOGO chain storage and broadcasting method.

[0013] According to a fourth aspect of the embodiments of this application, a computer-readable storage medium is provided having a computer program stored thereon; the computer program is executed by a processor to implement the FPGA-based LOGO chain storage and playback method.

[0014] The FPGA-based LOGO chained storage and playback method provided in this application embodiment binds and packages the single-frame fill data and key-value data of the LOGO, and encapsulates a chained information header in its header to form a chained single-frame data packet containing a chained information header segment, a fill data segment, and a key-value data segment. The chained information header segment at least includes a next-packet address pointer pointing to the storage address of the next frame data packet and a check field. Multiple chained single-frame data packets are stored in a non-contiguous address space of external memory. During storage, a Cyclic Redundancy Check (CRC) is calculated, and the next-packet address pointers in each data packet are linked sequentially according to a preset playback order to form one or more single-LOGO chained frames. Based on video output... The vertical synchronization signal is traversed and parsed by the FPGA hardware to the chained frame chain corresponding to the currently playing logo, and each frame data packet is read sequentially. The chained information header of the read data packet is parsed, security verification is performed, and the reading address of the next frame is determined according to the verification result and the preset playback mode, realizing at least one of sequential playback, loop playback, segment jump or multi-logo splicing playback. After adaptive format conversion of the verified logo frame data, it is superimposed with the background video and output. In professional equipment such as multi-channel switchers, multi-screen splitters and broadcast servers in broadcast live scenarios, it can realize the superimposition processing of static logos, dynamic logos and scrolling subtitles with multiple standards, multiple channels and multiple sequences. Attached Figure Description

[0015] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 A flowchart illustrating the FPGA-based LOGO chain storage and playback method provided in this application embodiment; Figure 2 A schematic diagram of the LOGO single-frame data packet encapsulation structure with link pointer provided for an embodiment of this application; Figure 3 This is a schematic diagram of a multi-channel logo chain connection provided in an embodiment of this application; Figure 4 This is a schematic diagram of a three-layer linked storage architecture provided in an embodiment of this application; Figure 5 A schematic diagram illustrating the entire process of LOGO playback control based on a linked list, as provided in this application embodiment; Figure 6 This is a schematic diagram of the double-buffered, non-intrusive online update and sequence editing process provided in the embodiments of this application; Figure 7 A schematic diagram of a double-buffered, non-interference online update and sequence editing process provided in another embodiment of this application; Figure 8 A schematic diagram of the structure of the FPGA-based LOGO chain storage and playback device provided in the embodiments of this application; Figure 9 A schematic diagram of the structure of an FPGA-based LOGO chain storage and playback device provided in another embodiment of this application. Detailed Implementation

[0016] To make the technical solutions and advantages of the embodiments of this application clearer, the exemplary embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0017] See Figure 1 This application provides a method for chained storage and playback of logos based on FPGA, including the following steps: S110, bind and package the single-frame fill data and key-value data of the LOGO, and encapsulate a chain information header in its header to form a chain single-frame data packet containing a chain information header segment, a fill data segment and a key-value data segment, wherein the chain information header segment at least contains a next packet address pointer pointing to the storage address of the next frame data packet and a verification field. S120, multiple chained single-frame data packets are stored in the non-contiguous address space of external memory. During the storage process, cyclic redundancy check (CRC) is calculated, and the packets are sequentially linked according to the next packet address pointer in each data packet in a preset playback order to form one or more single-LOGO chained frame chains. The external memory includes, but is not limited to, non-volatile / volatile memory such as DDR, HBM, SRAM, and Flash. S130, based on the vertical synchronization signal of the video output, the FPGA hardware traverses and parses the chain of frames corresponding to the currently playing LOGO, and reads the data packets of each frame in sequence. S140, parse the chain information header segment of the read data packet, perform security verification, and determine the reading address of the next frame according to the verification result and the preset playback mode, so as to realize at least one of sequential playback, loop playback, segment jump or multi-LOGO splicing playback; S150 performs adaptive format conversion on the verified LOGO frame data and then overlays it with the background video for output.

[0018] In an optional embodiment of this application, in step S110, the chained information header segment further includes: frame header synchronization code, LOGO global ID, frame sequence number, frame type, playback control word, previous packet address pointer, pixel bit width, pixel format, link CRC checksum, and data CRC checksum. The chained information header segment has a fixed byte length to meet hardware address alignment requirements. The CRC check rules are as follows: the link CRC16 uses the CRC-16-CCITT standard, with a generator polynomial of 0x1021 and an initial value of 0xFFFF. The calculation range is all content within the chained information header except for the checksum field. The data CRC12 uses the CRC-12 standard, with a generator polynomial of 0x80F. The calculation range is all bytes of the padding data segment and the key value data segment.

[0019] In an optional embodiment of this application, the frame type is used to identify the attributes of the chained single-frame data packet, the attributes including static single frame, first frame of sequence, middle frame of sequence, last frame of sequence, multiplexed frame, or jump frame; the playback control word includes at least one parameter selected from loop count, frame duration, or jump trigger condition. In an optional embodiment of this application, the LOGO integrated data packet encapsulation structure with link pointers includes a chained storage of dedicated link pointers and a sequence control field, forming a standardized single-frame data packet. See [link to relevant documentation]. Figure 2 A single frame data packet is fixed to a three-segment continuous structure consisting of a chained header segment, a padding data segment, and a key-value data segment. The chained header segment is shown in Table 1 below. The chained header segment in Table 1 is a fixed 64 bytes and is hardware aligned.

[0020] Table 1

[0021] In an optional embodiment of this application, the fill data segment stores the fill data of the logo, using the broadcast standard YUV / RGB format; the key value data segment stores the Alpha aliasing key value data of the logo, with the storage space fixed at 1 / 2 of the same size fill data segment, and is continuously bound to the fill data segment for storage; the FPGA has built-in hardware address calculation logic, the key data segment start address = data packet base address + 64-byte information header length + fill data total length, and only the start address of the data packet needs to be obtained to automatically complete the synchronous reading of the two data streams.

[0022] In an optional embodiment of this application, in step S120, see... Figure 3 The single-LOGO chained frame chain is a doubly linked circular list, wherein the address pointer of the previous packet of the first frame of the sequence points to the last frame of the sequence, and the address pointer of the next packet of the last frame of the sequence points to the first frame of the sequence; the chained frame chains of different LOGOs are indexed and uniformly managed in the global LOGO storage list through their global IDs. The global storage list is divided into independent partitions according to the broadcast channel ID, and the addresses between channels are isolated.

[0023] In an optional embodiment of this application, the method further includes: If the CRC check of the current frame fails, a first-level fault tolerance is triggered: the correct data of the previous frame is read back and reused according to the address pointer of the previous packet for playback, while skipping the address pointer of the erroneous frame and directly addressing the frame data pointed to by the address pointer of the next packet of the erroneous frame to ensure continuous playback of the sequence; if the link CRC check of the current frame fails or the address pointer illegally goes out of bounds, a second-level fault tolerance is triggered: the FPGA automatically jumps to the first frame of the current LOGO sequence to re-loop playback and reports the fault information to the CPU through the register; if multiple consecutive frames fail the check, the static backup frame is locked for playback to avoid system crash.

[0024] In an optional embodiment of this application, the method further includes a frame multiplexing step: when multiple different LOGO chain frame chains need to use the same frame LOGO data, the frame data packet is stored only once in the external memory, and the address pointers at the corresponding positions in each chain frame chain that needs the frame point to the same storage address. The pointer linking enables the multiplexing of single frame data in multiple sequences and multiple channels, improves storage space utilization, and reduces the storage hardware cost of multi-channel large systems.

[0025] In one optional embodiment of this application, the CPU transmits only one LOGO data packet to the external storage area each time it receives a VSync frame interrupt. This distributes the large volume of data across the blanking period of each frame, avoiding sudden congestion of bus bandwidth and ensuring that the real-time processing of the core video stream is not affected. For frame multiplexing scenarios, the same frame data only needs to be transmitted once, eliminating the need for repeated transmission and effectively reducing PCIe bus bandwidth usage.

[0026] In an optional embodiment of this application, see [link to relevant documentation]. Figure 4 This application, based on packet encapsulation with link pointers, designs a three-layer progressive chained storage architecture to achieve structured, dynamically editable, and highly reusable LOGO storage management, compatible with double-buffered partitioning and multi-channel address isolation designs. The first layer: single-frame chained data packets. A single-frame LOGO data packet is the smallest storage and playback unit. Through built-in upper and lower packet address pointers, it achieves flexible linking with other frames, eliminating the need for contiguous address storage and allowing for distribution across any available address space in the external storage area. The second layer: Single-logo chained frame chain. All data packets of a single logo are linked in playback order through address pointers to form a one-way / two-way circular linked list, called a single-logo chained frame chain: Static logo: Only one frame data packet is needed, the pointer points to itself, forming a self-circular linked list. During playback, the frame data is continuously read without repeated storage; Dynamic logo: In playback order, N frame data packets are linked sequentially through pointers. The pointer of the previous packet of the first frame points to the last frame, and the pointer of the next packet of the last frame points to the first frame, forming a circular linked list; pointers can also be configured to implement specified frame jumps and segment loops according to playback needs without modifying the data storage location; Frame reuse mechanism: When multiple logo sequences need to use the same frame data, only the frame data packet needs to be stored once. The pointers of multiple sequences can all point to the frame address, realizing frame-level storage reuse and improving storage space utilization. The third layer is a global logo storage list. All individual logo frames are linked together and indexed by their global logo IDs, forming a global logo storage list within the external storage area. This list stores each logo's ID, first frame address, sequence length, playback attributes, and channel binding information. The FPGA only needs to traverse this global list to manage all logos uniformly. When playing multiple channels or multiple logo groups, there's no need to configure independent registers for each channel, simplifying the control logic. It also supports multi-channel designs by dividing the external storage area into a shared memory area and independent linked list partitions based on channel IDs. Channels are address-isolated, supporting up to 256 channels of parallel, independent chained logo playback.

[0027] This application presents an FPGA-based LOGO chain storage and playback method that enables flexible playback, breaks free from the address constraints of linear storage, adopts a three-layer chain storage architecture, and decouples the playback sequence from the storage address through address pointers. It supports dynamic splicing, online editing, segment looping, and arbitrary jumping, adapting to the needs of rapid rebroadcasting, emergency insertion, and complex program packaging in broadcast live scenarios.

[0028] In an optional embodiment of this application, see [link to relevant documentation]. Figure 5 This application features a multi-channel parallel pipeline design, with each broadcast channel corresponding to an independent linked list parsing, frame verification, format conversion, and playback control pipeline. The channels operate in parallel without resource conflicts. Simultaneously, based on the pixel bit width and pixel format fields in the data packet, it automatically completes the matching and conversion with the broadcast format without the need for pre-transcoding. One set of hardware logic is compatible with multiple mainstream video formats.

[0029] In one optional embodiment of this application, the size of a single frame data packet is automatically calculated based on the number of rows and columns of pixels in the logo; the maximum number of frames that can be stored and the number of linked lists are automatically calculated based on the total available capacity of the storage area, which can adapt to the full-size coverage of small corner marks from 16×16 pixels to 4K full-screen dynamic logos of 3840×2160 pixels, and is compatible with SD / HD / 2K / 4K video signals.

[0030] In an optional embodiment of this application, the method further includes a non-intrusive online update step for LOGO data: an A / B mutually exclusive double-buffered storage partitioning mechanism is adopted, wherein the playback partition is used for current playback, and the update partition is used to receive new or modified chained frame data; during the video field blanking period, the playback base address is seamlessly switched from the playback partition to the update partition to complete the online update or sequence editing of the LOGO data; the storage controller maintains a reference count for each frame data packet, incrementing the count by 1 when the frame chain binds to the frame, and decrementing the count by 1 when the frame chain is unbound and deleted; when the reference count reaches zero, the hardware automatically releases the storage space occupied by the frame. In an optional embodiment of this application, see [link to relevant documentation]. Figure 6 and Figure 7 Each LOGO chain of frames corresponds to two independent storage partitions: a playback area and an update area. During normal playback, the FPGA only reads the linked list data in the playback area. When updating the LOGO sequence, the CPU constructs a new linked list and modifies pointer links in the update area. After all this is completed, the playback base address is seamlessly switched during the VSync blanking period, resulting in no broadcast interruptions or screen flickering, meeting the requirements for safe broadcasting. For online linked list editing scenarios, it supports non-intrusive modification of single-frame pointers without rewriting the entire sequence. Only the address pointer of the corresponding frame needs to be modified in the update area, and the change takes effect immediately, enabling online editing of the sequence.

[0031] This application removes the strong binding between storage address and playback order by embedding the next packet address pointer, sequence control parameters, and link verification information within the LOGO data packet, enabling dynamic splicing, flexible jumping, frame-level reuse, and online editing of LOGO sequences; it achieves unified group management of multiple LOGOs and multiple channels through a global storage linked list, greatly simplifying playback control logic; and through a link-level fault tolerance mechanism, it ensures that a single frame error does not affect the stable broadcast of the entire sequence, adapting to the needs of large-scale multi-channel broadcasting systems.

[0032] In one optional embodiment of this application, the FPGA, based on the video output vertical synchronization interrupt (VSync), implements chained playback control that is strictly synchronized with the video timing. No real-time CPU intervention is required; the hardware handles the linked list traversal, address jumps, and sequence playback, supporting flexible playback modes across all scenarios: When the static logo self-loop playback frame type is identified as a static single frame, the FPGA locks the frame address and continuously reads the frame data in a loop, achieving stable static display without pointer jumps and low logic overhead. For dynamic sequence forward and reverse playback, in forward playback, upon the arrival of each VSync interrupt, the FPGA automatically addresses the next frame based on the next packet address pointer of the current frame; in reverse playback, it addresses the previous frame based on the previous packet address pointer, eliminating the need for complex address accumulation calculations and the risk of address out-of-bounds errors. For full sequence looping, the next packet pointer of the last frame points to the first frame, and after playing to the last frame, it automatically jumps back to the first frame, achieving uninterrupted looping; for segment looping, by configuring pointers for specified frames, the first and last frames of a segment within the sequence are formed into a loop sub-chain, achieving loop playback of the specified segment without modifying data storage. Seamless multi-logo splicing playback: By setting the pointer of the next packet of the last frame of the previous logo to the address of the first frame of the next logo, seamless splicing playback of multiple logo sequences can be achieved without rewriting data. Sequence editing can be completed online, adapting to temporary program packaging and switching in live broadcast scenarios. Specified frame locking monitoring: The software can issue a specified frame address and locking command. The FPGA pauses automatic linked list traversal, fixes the reading of and playback of the specified frame, and achieves fixed-point monitoring of the screen; In case of emergency insertion: The pointer of the next packet of the currently playing frame can be directly modified to jump to the emergency logo sequence without interruption of broadcast.

[0033] In an optional embodiment of this application, a four-level security verification mechanism is adopted, specifically including: the first level is frame header synchronization code verification to verify the validity of the data packet start identifier; the second level is LOGO global ID and channel ID binding verification to prevent multi-channel crosstalk and misplay; the third level is frame sequence number continuity verification to verify the correctness of the sequence playback order; and the fourth level is data CRC verification to verify the integrity of the frame data. Based on this, a link CRC verification is added to verify the chained information header and the next packet address pointer, ensuring the accuracy of link jumps.

[0034] In an optional embodiment of this application, a chain-like link-level fault tolerance mechanism is added on the basis of single-frame four-level security verification to solve the cascading failure of the sequence caused by single-frame errors: when a single-frame verification fails, the FPGA automatically backtracks to read the correct data of the previous frame according to the address pointer of the previous packet, while skipping the address pointer of the erroneous frame and directly addressing the address of the next packet of the erroneous frame, ensuring that the sequence playback is uninterrupted and without stuttering; when the link CRC verification fails or the address pointer is invalid, the FPGA automatically locks the address of the first frame of the current sequence and jumps to the beginning of the sequence to replay, avoiding FPGA system crashes caused by address out-of-bounds errors; all abnormal scenarios report fault information to the CPU in real time through registers, including the address of the erroneous frame, the fault type, and the fault tolerance processing result, which facilitates maintenance personnel to quickly locate the problem and does not affect normal broadcasting throughout the process.

[0035] In an optional embodiment of this application, the FPGA-based LOGO chain storage and broadcasting method is implemented based on a Xilinx 7 Series FPGA, adapted to a 16-channel 4K@60fps ultra-high-definition multi-channel broadcasting server, and compatible with multi-channel systems. The specific implementation is as follows: First, hardware platform configuration FPGA main chip: Xilinx 7 Series FPGA, meeting the requirements of 16-channel 4K video processing and linked storage logic resources; External storage: 8 x 4Gb DDR4 chips, 256-bit data bus width, 1200MHz operating frequency, 4GB total available storage space; Control link: PCIe Gen3 x8 interface, enabling control command interaction and DMA data transfer between CPU and FPGA; Video format: Compatible with 4K UHD (3840×2160@60fps), HD 1080P@60fps, and YUV422 10bit mainstream broadcast format; Channel Capabilities: The architecture is scalable to support 256 channels. In this embodiment, 16 channels can be used to broadcast independent logos in parallel. A single channel can support a maximum of 256 independent logos in a chain sequence.

[0036] Second, data packet format configuration Chained information header segment: Fixed 64 bytes, 32-bit hardware aligned, including fields such as frame header synchronization code, LOGO global ID, frame sequence number, up and down packet address pointers, playback control word, checksum, etc. Fill data segment: Taking the HD 1920×1080 LOGO as an example, in YUV422 8bit format, the length of the fill data per frame = 1920×1080×2Byte = 4147200Byte; Key-value data segment: Single-channel 8-bit format, with a fixed length of 1 / 2 of the padding data segment, i.e., 2073600 bytes, and is stored continuously bound to the padding data segment; The total length of a single frame data packet is: 64Byte+4147200Byte+2073600Byte=6220864Byte.

[0037] Third, chained storage configuration DDR address space allocation: The range 0x00000000~0xBFFFFFFF is allocated from the total 4GB physical storage space as a dedicated LOGO chained storage area, with a total capacity of 3GB (the remaining 1GB is used for video frame buffering, system control interaction, and other functions). This dedicated area adopts a two-level storage architecture, divided into a global public shared storage area and 16 independent private partitions for each channel. Global shared storage area: address range 0x00000000~0x07FFFFFF, capacity 128MB, used to store reusable public LOGO frame data for all channels and the head of the global LOGO storage linked list; the linked list pointers of all channels can access the address in this area, realizing cross-channel frame-level multiplexing, while not destroying the address isolation of channel private data.

[0038] Independent private partition for each channel: occupies the remaining 2944MB of space in the dedicated area, which is divided into 16 completely isolated private partitions. The capacity of a single private partition is 184MB, which only stores the LOGO sequence data exclusive to this channel to avoid crosstalk between private data from multiple channels.

[0039] Single LOGO chained frame chain: Taking a 30-frame HD dynamic logo sequence as an example, the 30-frame sequence occupies a total of about 178MB, which can be completely stored in a single-channel 184MB private partition; the data packets within the sequence are linked sequentially by 32-bit address pointers according to the preset playback order. The address pointer of the previous packet of the first frame points to the last frame of the sequence, and the address pointer of the next packet of the last frame points to the first frame of the sequence, forming a doubly circular linked list; the FPGA only needs to configure the address of the first frame of the sequence, and can automatically complete the control of loop playback, segment jump, sequence splicing, etc. based on VSync timing, without the need for continuous address storage.

[0040] Frame multiplexing implementation: When all 16 channels need to broadcast the same static frame of the overall logo, only one copy of the frame data packet is stored in the global public shared storage area. The address pointers of the corresponding positions in the private linked list of each channel directly point to the same storage address in the public area, without the need to store it repeatedly in the private partition of each channel. Compared with the scheme of storing each channel independently, a total of 15 copies of frame data storage space is saved.

[0041] Global storage linked list: A global LOGO storage linked list is constructed in the low address segment of the global public shared storage area to uniformly index all LOGO frame chains in the private partitions of the 16 channels and the multiplexed frames in the public area. The linked list entries contain information such as the global ID of the LOGO, the physical address of the first frame, the number of valid frames in the sequence, playback control attributes, and the bound channel number. The FPGA only needs to traverse the global linked list once to complete the unified scheduling and management of multiple LOGOs and multiple channels in the entire system. There is no need to configure an independent address register for each LOGO, which effectively reduces the resource consumption of the FPGA control logic.

[0042] Fourth, playback control implementation Normal loop playback: Every time the FPGA receives a 4K@60fps VSync interrupt (16.6ms), it automatically addresses the next frame according to the next packet address pointer of the current frame. The 30-frame sequence completes one loop playback, which is synchronized with the video frame rate, without frame skipping or loss of synchronization. The specific implementation of sequence splicing is as follows: the pointer of the last frame of the program opening logo sequence is set to the address of the first frame of the main program logo sequence, so as to achieve seamless switching of the logo from the opening to the main program without rewriting data, and the editing can be completed online; Emergency interruption implementation: Upon receiving the emergency interruption instruction, the CPU constructs an emergency LOGO sequence in the update area, modifies the next packet pointer of the current playback frame to point to the first frame of the emergency sequence, and completes the switching within the VSync blanking period, with no broadcast interruption throughout.

[0043] Fifth, fault tolerance and uninterrupted updates Fault tolerance: When the CRC check of a certain frame of data fails, the FPGA automatically reuses the correct data from the previous frame, skips the erroneous frame, and directly addresses the next packet address of the erroneous frame. The sequence playback is smooth and uninterrupted, and at the same time, the fault information is reported to the CPU through the register. Uninterrupted Update: A / B dual buffer partitions are used. During normal playback, the linked list in area A is read. When updating the LOGO sequence, the data packet writing and linked list pointer modification are completed in area B. After verification, the system seamlessly switches to area B during the VSync blanking period, with no screen flickering or playback interruption throughout the entire process.

[0044] In an optional embodiment of this application, the application flow of the FPGA-based LOGO chain storage and playback method includes: Step 1: Power-on initialization process Upon system power-up, the FPGA completes logic initialization, DDR controller calibration, and PCIe link initialization. The linked memory area completes address allocation and enters the ready state. The CPU configures basic parameters to the FPGA register group via the PCIe bus, including DDR memory base address, number of LOGO channels, video standard parameters, and global linked list start address. The CPU transmits the LOGO data packets to the corresponding DDR partition in batches through the frame interrupt synchronous DMA mechanism. During the storage process, the cyclic redundancy check (CRC) is calculated, and a single LOGO chain frame chain and a global storage linked list are constructed to complete the linked list pointer linking and verification. Configure the LOGO playback parameters and channel binding relationship, set the playback enable register, and start the FPGA chain playback control.

[0045] The second step is the normal broadcast process. When each VSync frame synchronization interruption occurs, the chain sequence playback control module locks the current playback frame address and sends a read command to the DDR storage control module; Read the corresponding LOGO data packet from DDR, send it to the linked list parsing and frame addressing module, extract the upper and lower packet address pointers and playback control words, and pre-calculate the playback address of the next frame. The data packet enters the frame header parsing and multi-level verification module, which extracts the pre-stored data CRC and link CRC in the data packet and compares them item by item with the CRC value calculated in real time during storage. This completes the four-level security verification and link CRC verification. If the verification fails, link-level fault tolerance processing is triggered. If the verification passes, the subsequent process begins. Based on the format parameters in the data packet, the adaptive format conversion module is entered, and fill and key value data that match the broadcast format are output. The data is sent to the multi-channel video overlay module to complete the Alpha overlay of the logo and background video, and output the final video signal; After the current frame is played, the FPGA automatically updates the playback pointer according to the pre-calculated address of the next frame, waits for the next VSync interrupt to arrive, and enters the playback process of the next frame, repeating the cycle.

[0046] The third step is the online non-disruptive update and sequence editing process. After receiving the LOGO update / sequence edit command, the CPU determines the currently active playback partition and locks the inactive partition as the update area; The process of writing new data packets, modifying linked list pointers, and editing sequence splicing is completed in the update area without affecting the normal playback in the playback area. After the new linked list is constructed, the CPU verifies the integrity of the linked list and the validity of the pointers. Once it confirms that there are no errors, it waits for the video field blanking period to arrive. During the blanking period, the FPGA seamlessly switches the playback base address to the update area, completing the uninterrupted update / editing of the LOGO sequence, with no screen interruption or flicker throughout the process; After the switch is complete, the original playback partition is released and used as a backup partition for the next update.

[0047] The FPGA-based LOGO chain storage and playback method described in this application adds a link-level fault tolerance mechanism on the basis of single-frame data verification and fault tolerance. This can avoid the sequential chain playback failure caused by single-frame data errors and address pointer abnormalities, ensuring continuous and stable playback without image distortion.

[0048] The FPGA-based LOGO chain storage and playback method of this application features fully automated playback control. All chain traversal, address jumps, and sequence playback are automatically completed by the FPGA hardware without real-time CPU intervention. The CPU only needs to complete the initial configuration and anomaly monitoring, thereby improving the overall stability of the machine.

[0049] See Figure 8 This application provides an FPGA-based LOGO chain storage and playback device, including: The encapsulation module 810 is used to bind and package the single-frame fill data and key-value data of the LOGO, and encapsulate a chain information header in its header to form a chain single-frame data packet containing a chain information header segment, a fill data segment and a key-value data segment. The chain information header segment at least includes a next packet address pointer pointing to the storage address of the next frame data packet and a verification field. The linking module 820 is used to store multiple chained single-frame data packets in a non-contiguous address space of an external memory. During the storage process, a cyclic redundancy check (CRC) is calculated, and the packets are linked sequentially according to a preset playback order through the next packet address pointer in each data packet to form one or more single-LOGO chained frames. The reading module 830 is used to read the data packets of each frame sequentially by traversing and parsing the chained frame chain corresponding to the currently playing LOGO based on the vertical synchronization signal of the video output by the FPGA hardware. The verification module 840 is used to parse the chain information header segment of the read data packet, perform security verification, and determine the reading address of the next frame according to the verification result and the preset playback mode, so as to realize at least one of the following: sequential playback, loop playback, segment jump or multi-LOGO splicing playback. The output module 850 is used to adaptively convert the verified LOGO frame data into a new format and then overlay it onto the background video for output.

[0050] In one optional embodiment of this application, an FPGA pipeline hardware architecture is adopted, with an end-to-end processing latency of ≤2 lines of video cycle, supporting real-time processing of 16 channels of 4K@60fps ultra-high-definition video. The core functional modules of the system are as follows: Figure 9 As shown, it specifically includes: Register configuration module: Enables control information exchange between the CPU and FPGA, receives LOGO linked list configuration, playback control commands, and channel binding parameters, and simultaneously returns playback status, fault information, and storage status.

[0051] PCIe DMA control module: Based on frame interrupt triggering, it completes the DDR write transmission of LOGO data packets and supports multiplexing of single frame data.

[0052] Multi-channel chained storage control module: Independent storage partitions are divided according to channel ID, enabling reading and writing of LOGO data packets, real-time CRC calculation, chained address management, storage partition isolation, and compatibility with double buffer partitioning mechanism.

[0053] Linked list parsing and frame addressing module: Parses the address pointers of the preceding and following packets and the playback control words in the data packet, automatically completes the calculation and addressing of the next frame address, and supports linked list traversal, jump and loop control.

[0054] Frame header parsing and multi-level verification module: compatible with four-level security verification mechanism, completes frame synchronization code, channel ID, frame sequence number, and CRC data verification, and adds link CRC verification to perform link-level fault tolerance processing.

[0055] Full-format adaptive conversion module: Compatible conversion logic, automatically completes the matching and conversion with the broadcast format based on the pixel width and format parameters in the data packet, and outputs fill and key value data that conform to the standard.

[0056] Chain sequence playback control module: Based on VSync frame synchronization signal, it completes the playback control of chain sequence, supports full-mode playback such as forward, reverse, loop, jump, splicing, etc., and realizes multi-channel logo synchronous broadcast.

[0057] Multi-channel video overlay module: Based on fill and key data, it completes the alpha overlay of the logo and corresponding background video of each channel, and outputs the final multi-channel video signal.

[0058] This application provides a computer device, including: Memory; Processor; and Computer programs; The computer program is stored in the memory and configured to be executed by the processor to implement the FPGA-based LOGO chain storage and playback method. The processor can be a programmable logic chip, including but not limited to FPGAs, CPLDs, and other devices whose logic functions can be configured through programming; application-specific integrated circuits (ASICs) can implement equivalent hardware logic functions and are also suitable for the architecture implementation of this solution.

[0059] This application provides a computer-readable storage medium on which a computer program is stored; the computer program is executed by a processor to implement the FPGA-based LOGO chain storage and playback method.

[0060] The device and storage medium provided in this embodiment have the same technical effects as the methods described above.

[0061] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The solutions in the embodiments of this application can be implemented in various computer languages, such as C, VHDL, Verilog, the object-oriented programming language Java, and the interpreted scripting language JavaScript.

[0062] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0063] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0064] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0065] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0066] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0067] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0068] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0069] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A method for chained storage and playback of logos based on FPGA, characterized in that, Includes the following steps: ‌ The single-frame fill data and key-value data of the logo are bound and packaged, and a chain information header is encapsulated in its header to form a chain single-frame data packet containing a chain information header segment, a fill data segment and a key-value data segment. The chain information header segment at least contains a next packet address pointer pointing to the storage address of the next frame data packet and a verification field. Multiple chained single-frame data packets are stored in a non-contiguous address space of an external memory. During the storage process, a cyclic redundancy check (CRC) is calculated, and the packets are linked sequentially according to a preset playback order through the next packet address pointer in each data packet to form one or more single-LOGO chained frame chains. Based on the vertical synchronization signal of the video output, the FPGA hardware traverses and parses the chain of frames corresponding to the currently playing logo, and reads the data packets of each frame in sequence. The chained information header segment of the read data packet is parsed, a security check is performed, and the reading address of the next frame is determined according to the check result and the preset playback mode, so as to realize at least one of the following: sequential playback, loop playback, segment jump or multi-LOGO splicing playback. After adaptive format conversion of the verified LOGO frame data, it is overlaid with the background video and output.

2. The method according to claim 1, characterized in that, The chained information header segment also includes: frame header synchronization code, LOGO global ID, frame sequence number, frame type, playback control word, previous packet address pointer, pixel bit width, pixel format, link CRC checksum, and data CRC checksum. The chained information header segment has a fixed byte length to meet hardware address alignment requirements.

3. The method according to claim 2, characterized in that, The frame type is used to identify the attributes of the chained single-frame data packet, and the attributes include static single frame, first frame of sequence, middle frame of sequence, last frame of sequence, multiplexed frame, or jump frame; the playback control word includes at least one parameter among loop count, frame duration, or jump trigger condition.

4. The method according to claim 2, characterized in that, The single-logo chained frame chain is a doubly linked circular list, in which the address pointer of the previous packet of the first frame of the sequence points to the last frame of the sequence, and the address pointer of the next packet of the last frame of the sequence points to the first frame of the sequence; the chained frame chains of different logos are indexed and uniformly managed in the global logo storage list through their global IDs. The global storage list is divided into independent partitions according to the broadcast channel ID, and the addresses between channels are isolated.

5. The method according to claim 2, characterized in that, The method further includes: If the CRC check of the current frame fails, a first-level fault tolerance is triggered: the correct data of the previous frame is read back and reused according to the address pointer of the previous packet for playback, while skipping the address pointer of the erroneous frame and directly addressing the frame data pointed to by the address pointer of the next packet of the erroneous frame to ensure continuous playback of the sequence; if the link CRC check of the current frame fails or the address pointer illegally goes out of bounds, a second-level fault tolerance is triggered: the FPGA automatically jumps to the first frame of the current LOGO sequence to re-loop playback and reports the fault information to the CPU through the register; if multiple consecutive frames fail the check, the static backup frame is locked for playback to avoid system crash.

6. The method according to claim 1, characterized in that, The method also includes a non-intrusive online update step for LOGO data: an A / B mutual exclusion double-buffered storage partitioning mechanism is adopted, where the playback partition is used for current playback, and the update partition is used to receive new or modified chained frame data; during the video field blanking period, the playback base address is seamlessly switched from the playback partition to the update partition to complete the online update or sequence editing of the LOGO data. The storage controller maintains a reference count for each data packet frame. The count is incremented by 1 when the frame chain binds to the frame and decrements by 1 when the frame chain is unbound and deleted. When the reference count reaches zero, the hardware automatically releases the storage space occupied by the frame.

7. The method according to claim 1, characterized in that, The method further includes a frame multiplexing step: when multiple different LOGO chain frame chains need to use the same frame LOGO data, the frame data packet is stored only once in the external memory, and in each chain frame chain that needs the frame, the address pointer at the corresponding position points to the same storage address.

8. A FPGA-based LOGO chain storage and playback device, characterized in that, include: ‌ The encapsulation module is used to bind and package the single-frame fill data and key-value data of the LOGO, and encapsulate a chain information header in its head to form a chain single-frame data packet containing a chain information header segment, a fill data segment and a key-value data segment. The chain information header segment at least contains a next packet address pointer pointing to the storage address of the next frame data packet and a verification field. The linking module is used to store multiple chained single-frame data packets in a non-contiguous address space of an external memory. During the storage process, the cyclic redundancy check (CRC) is calculated, and the packets are linked sequentially according to a preset playback order through the next packet address pointer in each data packet to form one or more single-LOGO chained frames. The reading module is used to read the data packets of each frame sequentially by traversing and parsing the chain of frames corresponding to the currently playing logo based on the vertical synchronization signal of the video output by the FPGA hardware. The verification module is used to parse the chained information header segment of the read data packet, perform security verification, and determine the reading address of the next frame according to the verification result and the preset playback mode, so as to realize at least one of the following: sequential playback, loop playback, segment jump or multi-LOGO splicing playback. The output module is used to adaptively convert the verified LOGO frame data into a new format and then overlay it onto the background video for output.

9. A computer device, characterized in that, include: Memory; processor; as well as Computer programs; The computer program is stored in the memory and configured to be executed by the processor to implement the FPGA-based LOGO chain storage and broadcasting method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, It stores a computer program; the computer program is executed by a processor to implement the FPGA-based LOGO chain storage and playback method as described in any one of claims 1 to 7.

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