Image acquisition device and vehicle

Abstract

The application relates to an image acquisition device and a vehicle, and relates to the technical field of image acquisition. The device comprises an image sensor and a plurality of analog-to-digital conversion units; the image sensor comprises a plurality of light-sensitive pixels for acquiring original pixel signals; each analog-to-digital conversion unit comprises a gain adjustment unit and a conversion unit, the gain adjustment unit is used for determining a target gain according to a gear control signal, and the original pixel signal is processed according to the target gain to obtain a gain adjustment signal and output to the conversion unit, and the conversion unit is used for obtaining image data for image display according to the gain adjustment signal. Through each analog-to-digital conversion unit, the quantization output of the analog signal to the digital signal with multiple gains can be realized, so that the dynamic range of the image acquisition device can be expanded, a smaller number of analog-to-digital converters can be used, and the vehicle can be configured with an intelligent driving mode, and the image data acquisition is performed by the image acquisition device in the intelligent driving mode.

Description

Technical Field

[0001] This application relates to the field of image acquisition technology, and in particular to an image acquisition device and vehicle. Background Technology

[0002] With the rapid development of machine vision, autonomous driving, industrial inspection and other fields, higher and higher requirements are being placed on the imaging performance of image sensors. For example, in application scenarios such as vehicle vision and security monitoring, image acquisition devices need to have a wide data dynamic range in order to retain the details of both highlight and low-light areas in the same frame, so as to avoid overexposure in bright areas or loss of details in dark areas.

[0003] In related technologies, analog-to-digital conversion units typically employ a fixed-gain readout method, where the raw pixel signal output from the photosensitive pixel is directly input to a comparator for quantization. If the image acquisition device requires a wide dynamic range, multiple sets of analog-to-digital conversion units need to be set up, resulting in high costs. Therefore, how to extend the data dynamic range of image acquisition devices is a pressing technical problem that needs to be solved. Summary of the Invention

[0004] This application provides an image acquisition device to at least partially solve the above-mentioned technical problems.

[0005] To achieve the above objectives, according to a first aspect of this application, an image acquisition device is provided, comprising: An image sensor includes several photosensitive pixels for acquiring raw pixel signals; A plurality of analog-to-digital conversion units; each of the analog-to-digital conversion units includes a gain adjustment unit and a conversion unit; The gain adjustment unit is connected to the photosensitive pixel and the conversion unit, and is used to determine the target gain according to the gear control signal, process the original pixel signal according to the target gain to obtain a gain adjustment signal and output it to the conversion unit; the conversion unit is used to obtain image data for image display according to the gain adjustment signal. The gain adjustment unit includes an amplifier and at least one gain optimization circuit. The amplifier includes a first input terminal connected to the photosensitive pixel, a second input terminal for receiving a reference signal, and an output terminal connected to the conversion unit. The gain optimization circuit includes a second capacitor and a second switching device. The second capacitor and the second switching device are connected in series between the first input terminal and the output terminal of the amplifier. The second capacitor is connected to the feedback loop of the amplifier when the second switching device is turned on.

[0006] Optionally, the gear control signal includes a first gear signal; the gain adjustment unit further includes a first switching device and a first capacitor; The first switching device and the first capacitor are connected in parallel between the first input terminal and the first output terminal of the amplifier; The first switching device is used to receive the first gear signal and turn on or off according to the first gear signal. The first capacitor is bypassed when the first switching device is on and connected to the feedback loop of the amplifier when the first switching device is off, so as to adjust the target gain of the amplifier.

[0007] Optionally, the gear control signal includes a second gear signal; The second switching device is used to receive the second gear signal and to turn on or off according to the second gear signal. The second capacitor is connected in parallel with the first capacitor and connected to the feedback loop when the second switching device is on, and disconnected from the first capacitor when the second switching device is off.

[0008] Optionally, the conversion unit includes a comparison circuit and a counter; The comparison circuit is used to determine the range of the gain adjustment signal and convert the gain adjustment signal into a binary sequence within the range. The counter is used to count the binary sequence to obtain the image data.

[0009] Optionally, the comparison circuit includes a reference signal source, a selection switch group, and a comparator; The reference signal source is used to provide a ramp reference voltage, a first ramp signal with an amplitude range covering a first range, and a second ramp signal with an amplitude range covering a second range; wherein the first range and the second range do not overlap, and the ramp reference voltage is the boundary value between the first range and the second range. The selection switch group is connected between the reference signal source and the comparator, and is used to transmit one of the ramp reference voltage, the first ramp signal and the second ramp signal to the comparator. The comparator includes a first input terminal connected to the gain adjustment unit to receive the gain adjustment signal, a second input terminal connected to the selection switch group, and an output terminal connected to the counter.

[0010] Optionally, during the first time period, the selection switch group transmits the ramp reference voltage to the comparator, so that the comparator compares the ramp reference voltage with the gain adjustment signal, and outputs a first level signal when the comparison result is that the ramp reference voltage is greater than the gain adjustment signal, and outputs a second level signal when the comparison result is that the ramp reference voltage is less than the gain adjustment signal; In the second time period following the first time period, the selection switch group transmits the first ramp signal to the comparator based on the first level signal, so that the comparator quantizes the gain adjustment signal within the first range to obtain the binary sequence, and transmits the second ramp signal to the comparator based on the second level signal, so that the comparator quantizes the gain adjustment signal within the second range to obtain the binary sequence.

[0011] Optionally, a plurality of the photosensitive pixel arrays are arranged, and each column of photosensitive pixels is connected to two of the analog-to-digital conversion units respectively; In the case where two adjacent rows of photosensitive pixels are simultaneously selected, the raw pixel signals collected by the photosensitive pixels in the two adjacent rows are output to their respective analog-to-digital conversion units for synchronous conversion.

[0012] Optionally, it may also include a first switching switch group and a second switching switch group; For each of the two analog-to-digital converters connected to the photosensitive pixels in each column, a first switching group is connected between one analog-to-digital converter and the photosensitive pixels in the corresponding column, and a second switching group is connected between the other analog-to-digital converter and the photosensitive pixels in the corresponding column, so that the raw pixel signals collected by the photosensitive pixels in odd-numbered rows and the raw pixel signals collected by the photosensitive pixels in even-numbered rows can be selectively transmitted to different analog-to-digital converters.

[0013] Optionally, the first switching group includes a third switching device and a fourth switching device; the second switching group includes a fifth switching device and a sixth switching device. The third switching device includes a first terminal connected to each of the odd-numbered rows of photosensitive pixels, a second terminal connected to the analog-to-digital conversion unit, and a control terminal that receives the first switching signal; The fourth switching device includes a first terminal connected to the photosensitive pixels of each of the even-numbered rows, a second terminal connected to the analog-to-digital conversion unit, and a control terminal that receives the second switching signal; The fifth switching device includes a first terminal connected to each of the odd-numbered rows of photosensitive pixels, a second terminal connected to the analog-to-digital conversion unit, and a control terminal that receives the second switching signal; The sixth switching device includes a first terminal connected to the photosensitive pixels of each of the even-numbered rows, a second terminal connected to the analog-to-digital conversion unit, and a control terminal connected to the first switching signal; The first switching signal and the second switching signal are a set of signals with opposite phases.

[0014] According to a second aspect of this application, a vehicle is provided, including a controller and the aforementioned image acquisition device; the controller is configured to output a gear control signal to the image acquisition device to control the image acquisition device to process the raw pixel signal with a target gain.

[0015] In summary, in the image acquisition device of this application embodiment, by integrating a gain adjustment unit and a conversion unit in each analog-to-digital conversion unit, each analog-to-digital conversion unit can both perform programmable gain adjustment on the original pixel signal and complete analog-to-digital conversion. The gain adjustment unit determines the target gain according to the level control signal and processes the original pixel signal, which can enable the original pixel signal output by the same photosensitive pixel to obtain different amplification factors. The target gain is adjusted by the second capacitor and the second switching device, so that the gain adjustment signal has different target gains. Then, the conversion unit converts the gain adjustment signal into image data, which can realize the quantization output of analog signal to digital signal. In this way, the dynamic range of the image acquisition device can be expanded and a smaller number of analog-to-digital converters can be used.

[0016] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0019] Figure 1 This is a schematic diagram of an image acquisition device provided in an exemplary embodiment of this application; Figure 2 This is a circuit connection diagram of the analog-to-digital conversion unit provided in an exemplary embodiment of this application; Figure 3 This is a schematic diagram showing the connection between the analog-to-digital conversion unit and the image sensor provided in an exemplary embodiment of this application; Figure 4 This is a schematic diagram of the overall architecture of the image acquisition device provided in an exemplary embodiment of this disclosure; Figure 5 This is a schematic diagram of the vehicle architecture provided in an exemplary embodiment of this disclosure.

[0020] Explanation of reference numerals in the attached figures: 10, image sensor; 20, analog-to-digital conversion unit; 21, gain adjustment unit; 211, gain optimization circuit; 22, conversion unit; 221, comparator circuit; 222, reference signal source; 223, selection switch group; 224, counter; 30, first switching switch group; 40, second switching switch group; U1, amplifier; U2, comparator; K1, first switching device; K2, second switching device; K3, third switching device; K4, fourth switching device; K5, fifth switching device; K6, sixth switching device; C1, first capacitor; C2, second capacitor. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0022] According to the first aspect of this application, referring to Figure 1 This disclosure provides an image acquisition device, including an image sensor 10 and a plurality of analog-to-digital conversion units 20. The image sensor 10 includes a plurality of photosensitive pixels for acquiring raw pixel signals; a plurality of analog-to-digital conversion units 20; each analog-to-digital conversion unit 20 includes a gain adjustment unit 21 and a conversion unit 22; wherein the gain adjustment unit 21 is connected to the photosensitive pixels and the conversion unit 22, and is used to determine a target gain according to a level control signal, and process the raw pixel signal according to the target gain to obtain a gain adjustment signal and output it to the conversion unit 22; the conversion unit 22 is used to obtain image data for image display according to the gain adjustment signal. The gain adjustment unit 21 includes an amplifier U1 and at least one gain optimization circuit 211. The amplifier U1 includes a first input terminal connected to the photosensitive pixels, a second input terminal for receiving a reference signal, and an output terminal connected to the conversion unit 22; the gain optimization circuit 211 includes a second capacitor C2 and a second switching device K2, the second capacitor C2 and the second switching device K2 being connected in series between the first input terminal and the output terminal of the amplifier U1, and the second capacitor C2 being connected to the feedback loop of the amplifier U1 when the second switching device K2 is turned on.

[0023] The gain adjustment unit 21 has its input connected to the output of the photosensitive pixel, receiving the raw pixel signal acquired by the photosensitive pixel. Its output is connected to the input of the conversion unit 22, outputting a gain adjustment signal to the conversion unit 22. The gain adjustment unit 21 determines the target gain based on the level control signal and amplifies or attenuates the raw pixel signal according to the target gain to obtain the gain adjustment signal. The level control signal is a digital control signal generated by the control logic of the image acquisition device, used to select the operating level of the gain adjustment unit 21. Different target gains correspond to different amplification factors, allowing the same raw pixel signal to be amplified to different amplitude ranges.

[0024] As an example, the gain adjustment unit 21 enables the image acquisition device to provide signal outputs with different gains during a single exposure. In low-light scenes, the original pixel signal amplitude is small, so a higher target gain can be selected to amplify the signal and improve the signal-to-noise ratio of weak signals. In high-light scenes, the original pixel signal amplitude is large, so a lower target gain can be selected to avoid the signal exceeding the quantization range of the conversion unit 22 and becoming saturated. Through the fusion processing of multi-gain signals, the dynamic range of the image sensor 10 can be effectively expanded, enabling the image acquisition device to simultaneously retain detailed information in both highlight and low-light areas.

[0025] As an example, conversion unit 22 receives the gain adjustment signal output by gain adjustment unit 21 and converts the analog gain adjustment signal into digital image data. The image data is a digital code characterizing the intensity of the original pixel signal light. It can be transmitted to an image signal processor (ISP) for processing the raw data output by image sensor 10, and ultimately used for image display. The quantization accuracy and conversion speed of conversion unit 22 determine the imaging quality and frame rate of the image acquisition device.

[0026] In the above embodiments, by integrating a gain adjustment unit 21 and a conversion unit 22 into each analog-to-digital conversion unit 20, each analog-to-digital conversion unit 20 can both perform programmable gain adjustment on the original pixel signal and complete analog-to-digital conversion. The gain adjustment unit 21 determines the target gain according to the gear control signal and processes the original pixel signal, so that the original pixel signal output by the same photosensitive pixel can obtain different amplification factors. The target gain is adjusted by the second capacitor C2 and the second switching device K2, so that the gain adjustment signal has different target gains. Then, the conversion unit 22 converts the gain adjustment signal into image data, which can realize the quantization output of analog signal to digital signal. In this way, the dynamic range of the image acquisition device can be expanded and a smaller number of analog-to-digital converters can be used.

[0027] In some embodiments, the gear control signal includes a first gear signal; the gain adjustment unit 21 further includes a first switching device K1 and a first capacitor C1; the first switching device K1 and the first capacitor C1 are connected in parallel between the first input terminal and the output terminal of the amplifier U1; wherein, the first switching device K1 is used to connect to the first gear signal and to be turned on or off according to the first gear signal, and the first capacitor C1 is bypassed when the first switching device K1 is turned on and connected to the feedback loop of the amplifier U1 when the first switching device K1 is turned off, so as to adjust the target gain of the amplifier U1.

[0028] In this configuration, amplifier U1, together with the first switching device K1 and the first capacitor C1, constitutes a capacitive feedback programmable gain amplifier (PGA). Amplifier U1 can be implemented using a high-gain, low-noise operational amplifier (OPAMP). Amplifier U1 includes three ports: a first input terminal, a second input terminal, and an output terminal. The first input terminal is connected to the photosensitive pixel to receive the raw pixel signal output by the photosensitive pixel; the second input terminal is used to input a reference signal, which is a stable DC reference voltage, providing the DC operating point for amplifier U1; the output terminal is connected to the conversion unit 22 to output a gain adjustment signal to the conversion unit 22. Amplifier U1 operates in a closed-loop negative feedback state, utilizing the virtual short and virtual open characteristics of operational amplifier U1 to achieve precise amplification of the input signal. The first switching device K1 and the first capacitor C1 are connected in parallel between the first input terminal and the output terminal of amplifier U1, forming the feedback loop of amplifier U1. The first switching device K1 can be a semiconductor switch controlled by a digital signal, such as a metal-oxide-semiconductor field-effect transistor (MOSFET), whose on and off states are controlled by a first position signal.

[0029] The first gear signal controls the on / off state of the first switching device K1. When the first gear signal is active, the first switching device K1 is on; when the first gear signal is inactive, the first switching device K1 is off. When the first switching device K1 is on, the first capacitor C1 is bypassed by the first switching device K1, that is, the two ends of the first capacitor C1 are short-circuited by the first switching device K1, and the first capacitor C1 does not participate in the feedback loop of the amplifier U1. At this time, the feedback path of the amplifier U1 is the on-resistance of the first switching device K1 (approximately short-circuited), and the amplifier U1 operates in unity-gain buffered state. Unity-gain buffering means that the voltage gain of the amplifier U1 is 1, and the output signal is equal in amplitude to the input signal, which can play the role of impedance transformation and buffer isolation. In the unity-gain mode, the gain adjustment unit 21 does not amplify the original pixel signal, but only buffers the output, which is suitable for high-light scenes where the amplitude of the original pixel signal is already large enough, or as a reference mode for gain calibration.

[0030] When the first switching device K1 is disconnected, the first capacitor C1 is connected to the feedback loop of amplifier U1, becoming the feedback capacitor. At this time, the closed-loop gain of amplifier U1 is determined by the ratio of the first capacitor C1 to the equivalent capacitance at the input terminal. Since the first capacitor C1 is connected to the feedback loop, the gain of amplifier U1 is no longer unity gain, but a fixed gain value determined by the capacitance value of the first capacitor C1. For example, when the capacitance value of the first capacitor C1 is small, the corresponding gain is high, thus it is a high gain setting, suitable for situations where the amplitude of the original pixel signal is small in low-light scenes. By amplifying the weak signal to the optimal quantization range of conversion unit 22 through a higher gain, the quantization accuracy and signal-to-noise ratio of the weak signal are improved. The parallel structure of the first switching device K1 and the first capacitor C1 allows the gain adjustment unit 21 to switch between unity gain and high gain states through the first level signal.

[0031] It should be noted that the first input terminal of amplifier U1 can be an inverting input terminal and the second input terminal can be a non-inverting input terminal, so that the first switching device K1 and the first capacitor C1 are connected in parallel between the first input terminal and the output terminal to form a feedback network.

[0032] Reference Figure 2 In some embodiments, the gear control signal includes a second gear signal, the second switching device K2 is used to connect to the second gear signal and turn on or off according to the second gear signal, the second capacitor C2 is connected in parallel with the first capacitor C1 and connected to the feedback loop when the second switching device K2 is on, and disconnected from the first capacitor C1 when the second switching device K2 is off.

[0033] As an example, the gain optimization circuit 211 is used to expand the number of gain levels. The second capacitor C2 and the second switching device K2 are connected in series, and the entire series branch is connected between the first input and output terminals of amplifier U1. Together with the parallel branch of the first switching device K1 and the first capacitor C1, it forms the feedback loop of amplifier U1. The capacitance value of the second capacitor C2 can be the same as or different from that of the first capacitor C1, depending on the required gain level.

[0034] The on / off state of the second switching device K2 is controlled by the second gear signal, which is independent of the first gear signal and can be controlled separately. When the second gear signal is at an active level, the second switching device K2 is on; when the second gear signal is at an inactive level, the second switching device K2 is off. When the second switching device K2 is on and the first switching device K1 is off, the second capacitor C2 is connected to the feedback loop of the amplifier U1 through the second switching device K2, in parallel with the first capacitor C1. At this time, the total capacitance of the feedback loop is the sum of the capacitance values ​​of the first capacitor C1 and the second capacitor C2. Due to the increase in parallel capacitance, the closed-loop gain of the amplifier U1 decreases accordingly. Therefore, this gear is a low-gain gear, which is suitable for situations where the amplitude of the original pixel signal is moderate in medium light intensity scenes, adjusting the signal to the quantization range of the conversion unit 22 through a lower gain. When the second switching device K2 is off, the electrical connection between the second capacitor C2 and the feedback loop is broken, and the second capacitor C2 does not participate in the feedback of the amplifier U1. At this point, the capacitance of the feedback loop is only the first capacitor C1 (provided that the first switching device K1 is open), and the amplifier U1 operates at a high gain level determined solely by the first capacitor C1. The disconnecting resistance of the second switching device K2 needs to be large enough to ensure that the second capacitor C2 does not affect the feedback loop through the leakage current of the switch.

[0035] By combining different combinations of the first and second level signals, the gain adjustment unit 21 can achieve the following three gain levels: First position: First switching device K1 is on, and second switching device K2 is in any state. At this time, first capacitor C1 is bypassed by first switching device K1, and second capacitor C2 is short-circuited by the on first switching device K1 regardless of whether it is connected or not. Amplifier U1 operates in unity-gain buffer state with a target gain of 1, which serves as a calibration reference.

[0036] Second position: First switching device K1 is off, and second switching device K2 is off. At this time, only the first capacitor C1 is connected in the feedback loop, and the total feedback capacitance is the capacitance value of the first capacitor C1. Amplifier U1 operates in a high-gain state, which is suitable for low-light scenes and can amplify the original pixel signal with a small amplitude at a high rate.

[0037] Third position: First switching device K1 is off, and second switching device K2 is on. At this time, the first capacitor C1 and the second capacitor C2 are connected in parallel to the feedback loop, and the total feedback capacitance is the sum of the capacitance values ​​of the two capacitors. Amplifier U1 operates in a low-gain state, which is suitable for medium lighting scenes and can amplify the original pixel signal with a moderate amplitude at a lower magnification.

[0038] Thus, through the combined control of the first and second gain signals, the gain adjustment unit 21 can switch between unity gain, high gain, and low gain levels. In the actual image readout process, the raw pixel signal of the same photosensitive pixel can be processed and converted sequentially using different gain levels to obtain multiple sets of image data with different gains. The subsequent image signal processing unit can fuse the multi-gain image data, using low-gain or unity-gain data in highlight areas to avoid saturation, and high-gain data in low-gain areas to improve the signal-to-noise ratio, thereby synthesizing an image with a wider dynamic range.

[0039] Furthermore, the gain optimization circuit 211 can be configured with multiple sets, that is, multiple sets of series branches of the second capacitor C2 and the second switching device K2. By using different combinations of the series branch switches, a greater number of gain levels can be achieved, further refining the step of gain adjustment and adapting to more complex lighting scenarios.

[0040] In the above embodiments, amplifier U1, in conjunction with the first switching device K1, the first capacitor C1, and the gain optimization circuit 211, can constitute a capacitor feedback type programmable gain amplifier U1. When the first switching device K1 is turned on, the first capacitor C1 is bypassed, and amplifier U1 can operate in a unity-gain buffer state, performing impedance transformation and buffered output on the original pixel signal. When the first switching device K1 is turned off, the first capacitor C1 is connected to the feedback loop, and amplifier U1 can obtain a high gain determined by the first capacitor C1. The gain optimization circuit 211 controls whether the second capacitor C2 is connected in parallel with the first capacitor C1 through the second switching device K2, which can further provide a low gain level on the basis of high gain. By combining the first level signal and the second level signal, three levels of unity gain, high gain, and low gain can be realized. After multi-gain processing of the same original pixel signal, multi-gain data can be fused in subsequent processing, which can expand the dynamic range of the image acquisition device.

[0041] In some embodiments, the conversion unit 22 includes a comparison circuit 221 and a counter 224; the comparison circuit 221 is used to determine the range of the gain adjustment signal and convert the gain adjustment signal into a binary sequence within the range; the counter 224 is used to count the binary sequence to obtain image data.

[0042] Here, a binary sequence refers to a digital signal sequence composed of two states: high level and low level. Comparison circuit 221 compares the gain adjustment signal with a reference signal and outputs a binary sequence reflecting the comparison result. The process by which comparison circuit 221 determines the range of the gain adjustment signal is as follows: the gain adjustment signal is compared with one or more reference voltages, and the voltage range within which the gain adjustment signal falls is determined based on the comparison result. After determining the range, comparison circuit 221 continuously compares the gain adjustment signal with the corresponding reference signal within that range, outputting a binary sequence. The level flip of the binary sequence corresponds to the moment when the gain adjustment signal and the reference signal are equal; the position of this moment reflects the amplitude of the gain adjustment signal.

[0043] The counter 224 receives the binary sequence output by the comparator circuit 221, counts the binary sequence, and converts the level flipping moments output by the comparator circuit 221 into digital count values, which are the image data. At the start of the analog-to-digital conversion, the counter 224 is reset to zero, and the reference ramp signal changes at a constant rate from its initial value. Driven by the clock signal, the counter 224 begins to accumulate clock pulses. When the level flipping of the binary sequence output by the comparator circuit 221 occurs, the counter 224 stops counting or latches the current count value, which at this point represents the amplitude of the gain adjustment signal.

[0044] Reference Figure 2 In some embodiments, the comparator circuit 221 includes a reference signal source 222, a selection switch group 223, and a comparator U2. The reference signal source 222 is used to provide a ramp reference voltage, a first ramp signal whose amplitude range covers a first range, and a second ramp signal whose amplitude range covers a second range. The first range and the second range do not overlap, and the ramp reference voltage is the boundary value between the first range and the second range. The selection switch group 223 is connected between the reference signal source 222 and the comparator U2, and is used to transmit one of the ramp reference voltage, the first ramp signal, and the second ramp signal to the comparator U2. The comparator U2 includes a first input terminal connected to the gain adjustment unit 21 to receive a gain adjustment signal, a second input terminal connected to the selection switch group 223, and an output terminal connected to the counter 224.

[0045] The reference signal source 222 is the reference signal generation module of the comparator circuit 221, used to generate a ramp reference voltage, a first ramp signal, and a second ramp signal. The first and second ramp signals are linearly varying voltage signals. The amplitude range of the first ramp signal covers a first measurement range, which is the lower half of the quantization range, extending from a lower starting value to a middle boundary value. The amplitude range of the second ramp signal covers a second measurement range, which is the upper half of the quantization range, extending from a middle boundary value to a higher ending value. The first and second measurement ranges do not overlap; they are connected end-to-end, jointly covering the entire quantization range. The first and second ramp signals have the same slope and the same signal swing. The first ramp signal starts from a lower starting value, rises linearly at a constant rate, and ends after reaching the middle boundary value; its amplitude is denoted as ΔV. The second ramp signal starts from the middle boundary value, continues to rise linearly at the same constant rate, and ends after reaching a higher ending value; its amplitude is also ΔV. The two ramp signals are connected end-to-end to cover the entire quantization range from the starting value to the ending value, with a total variation amplitude of 2ΔV. The ramp reference voltage is a constant DC voltage, the value of which is equal to the boundary between the first and second ranges, i.e., the ending value of the first ramp signal and the starting value of the second ramp signal. The ramp reference voltage serves as the boundary reference for the range of the gain adjustment signal.

[0046] As an example, a selection switch group 223 is connected between the reference signal source 222 and the comparator U2 to select one of the three signals provided by the reference signal source 222 for transmission to the comparator U2. The selection switch group 223 includes a first sub-switch K21, a second sub-switch K22, and a third sub-switch K23. The first sub-switch K21 controls the transmission of the ramp reference voltage, the second sub-switch K22 controls the transmission of the first ramp signal, and the third sub-switch K23 controls the transmission of the second ramp signal. The on / off state of the three sub-switches is controlled by the control logic according to the switching timing, ensuring that only one sub-switch is on at any given time, thus guaranteeing that only one signal is transmitted to the comparator U2. Since the three signals from the reference signal source 222 are continuously generated, the unselected signal is not connected to the comparator U2 by disconnecting the corresponding sub-switch.

[0047] As an example, comparator U2 is used to compare the gain adjustment signal with the reference signal transmitted by the selection switch group 223 and output the comparison result. Comparator U2 includes a first input terminal, a second input terminal, and an output terminal. The first input terminal is connected to the gain adjustment unit 21 and receives the gain adjustment signal; the second input terminal is connected to the selection switch group 223 and receives the selected reference signal (ramp reference voltage, first ramp signal, or second ramp signal). By splitting the entire quantization range into two non-overlapping sub-ranges and quantizing them using the first ramp signal and the second ramp signal respectively, the ramp change amplitude of a single comparison can be shortened from 2ΔV to ΔV while maintaining the same quantization accuracy. This reduces the quantization time of comparator U2 by about half and improves the efficiency of analog-to-digital conversion.

[0048] In some embodiments, during a first time period, the selection switch group 223 transmits a ramp reference voltage to the comparator U2, so that the comparator U2 compares the ramp reference voltage with the gain adjustment signal, and outputs a first level signal when the comparison result is that the ramp reference voltage is greater than the gain adjustment signal, and outputs a second level signal when the comparison result is that the ramp reference voltage is less than the gain adjustment signal; during a second time period after the first time period, the selection switch group 223 transmits a first ramp signal to the comparator U2 based on the first level signal, so that the comparator U2 quantizes the gain adjustment signal to obtain a binary sequence within a first range, and transmits a second ramp signal to the comparator U2 based on the second level signal, so that the comparator U2 quantizes the gain adjustment signal to obtain a binary sequence within a second range.

[0049] As an example, the first time period is the range determination stage. During this period, the first sub-switch K21 in the selector switch group 223 is turned on, while the second sub-switch K22 and the third sub-switch K23 are turned off. The ramp reference voltage provided by the reference signal source 222 is transmitted to the second input terminal of the comparator U2 through the first sub-switch K21. The comparator U2 compares the ramp reference voltage with the gain adjustment signal connected to the first input terminal and outputs the corresponding level signal according to the comparison result.

[0050] When the comparison result shows that the ramp reference voltage is greater than the gain adjustment signal, comparator U2 outputs a first-level signal, indicating that the amplitude of the gain adjustment signal is lower than the ramp reference voltage, i.e., lower than the boundary value between the first and second ranges. Therefore, the gain adjustment signal is within the first range. When the comparison result shows that the ramp reference voltage is less than the gain adjustment signal, comparator U2 outputs a second-level signal, indicating that the amplitude of the gain adjustment signal is higher than the ramp reference voltage, i.e., higher than the boundary value. Therefore, the gain adjustment signal is within the second range. The duration of the first time period is short, and only one comparison is needed to determine the range of the gain adjustment signal. The first-level or second-level signal output by comparator U2 is latched and used as the basis for selecting the ramp signal in the second time period.

[0051] As an example, the second time period is the quantization phase, which takes place after the first time period. During the second time period, the selection switch group 223 selects the corresponding ramp signal to be transmitted to comparator U2 based on the comparison result of the first time period: if the output of the first time period is a first level signal (the gain adjustment signal is within the first range), then the second sub-switch K22 in the selection switch group 223 is turned on, and the first sub-switch K21 and the third sub-switch K23 are turned off. The first ramp signal provided by the reference signal source 222 is transmitted to the second input terminal of comparator U2 through the second sub-switch K22. Comparator U2 continuously compares the first ramp signal with the gain adjustment signal within the first range. The first ramp signal rises linearly from a lower initial value. When the amplitude of the first ramp signal is lower than that of the gain adjustment signal, comparator U2 outputs a level; when the amplitude of the first ramp signal rises to equal that of the gain adjustment signal, the comparator U2 output flips, obtaining the flip time of the binary sequence. Counter 224 starts counting at the beginning of the second time period and latches the count value when the output of comparator U2 flips. This count value is the quantization result of the gain adjustment signal within the first range.

[0052] If the output of the first time period is a second-level signal (the gain adjustment signal is within the second range), then the third sub-switch K23 in the selection switch group 223 is turned on, and the first sub-switch K21 and the second sub-switch K22 are turned off. The second ramp signal provided by the reference signal source 222 is transmitted to the second input terminal of the comparator U2 through the third sub-switch K23. The comparator U2 continuously compares the second ramp signal with the gain adjustment signal within the second range. The second ramp signal rises linearly from the middle boundary value. When its amplitude rises to equal the gain adjustment signal, the output of the comparator U2 flips, the counter 224 latches the count value, and the quantization result of the gain adjustment signal within the second range is obtained.

[0053] Thus, compared to using a single-ramp signal covering the entire quantization range (with a variation amplitude of 2ΔV), this embodiment uses a ramp signal covering only half the quantization range (with a variation amplitude of ΔV) during the quantization stage. The rise time of the ramp signal is halved, thus shortening the quantization time of comparator U2 accordingly and improving the efficiency of analog-to-digital conversion by approximately double. Simultaneously, since the slopes of the first and second ramp signals are the same as in the single-ramp scheme, the quantization accuracy (i.e., the voltage step size corresponding to each count value) remains unchanged. Although the range determination in the first time period adds some time overhead, since only one comparison is needed, the time is much shorter than the quantization time in the second time period. Therefore, the overall conversion time is still significantly shorter than the traditional single-ramp scheme.

[0054] In the above embodiment, the comparator circuit 221 first compares the gain adjustment signal with the ramp reference voltage in the first time period to determine the range of the gain adjustment signal; then, in the second time period, it selects either the first ramp signal or the second ramp signal based on the range determination result, and performs accurate quantization within the corresponding range. The reference signal source 222 continuously generates the ramp reference voltage, the first ramp signal, and the second ramp signal simultaneously. One of them is selected by the three sub-switches of the selection switch group 223, and the unselected signal is not connected, which ensures the stability of the ramp signal. The first ramp signal and the second ramp signal have the same slope, the same swing amplitude, and are connected end to end, each covering half of the quantization range. Compared with a single ramp covering the entire quantization range, the ramp rise time can be shortened by about half, improving the analog-to-digital conversion efficiency. The counter 224 counts the clock pulses in the second time period, and latches the count value when the comparator U2 flips, which can convert the amplitude of the gain adjustment signal into digital image data. In this way, the conversion speed can be improved while maintaining the quantization accuracy, so as to support high frame rate imaging.

[0055] In some embodiments, a plurality of photosensitive pixel arrays are arranged, and each column of photosensitive pixels is connected to two analog-to-digital conversion units 20 respectively; wherein, when the photosensitive pixels of two adjacent rows are selected at the same time, the original pixel signals collected by the photosensitive pixels of the two adjacent rows are output to their respective corresponding analog-to-digital conversion units 20 for synchronous conversion.

[0056] As an example, several photosensitive pixels are arranged in a two-dimensional array on a pixel chip. Each photosensitive pixel in the array is uniquely identified by its row and column number. The row decoder and row drive circuit sequentially select the photosensitive pixels in the corresponding row according to the readout timing, causing the selected row's photosensitive pixels to output their raw pixel signals. In this embodiment, a dual-row synchronous readout method is used, simultaneously selecting two adjacent rows of photosensitive pixels each time. For example, the first and second rows are selected simultaneously, or the third and fourth rows are selected simultaneously. The two simultaneously selected rows of photosensitive pixels each output their raw pixel signals, and the raw pixel signals of the two rows are processed in parallel at the column level.

[0057] As an example, each column of photosensitive pixels is connected to two analog-to-digital converters (ADCs) 20, both of which can receive the raw pixel signals output by the photosensitive pixels in that column. When photosensitive pixels in two adjacent rows are simultaneously selected, the raw pixel signals acquired by the photosensitive pixels in one row (e.g., the previous row) are output to one ADC 20 in that column, while the raw pixel signals acquired by the photosensitive pixels in the other row (e.g., the next row) are output to the other ADC 20 in that column. The two ADCs 20 operate synchronously, each performing gain adjustment and analog-to-digital conversion on the received raw pixel signals. Since the two ADCs 20 are independent parallel processing channels, the conversion of the two rows can be performed simultaneously without time-sharing.

[0058] Reference Figure 3 Compared to selecting only one row of photosensitive pixels at a time, this embodiment simultaneously outputs the raw pixel signals of all columns in that row to the column-level analog-to-digital converter 20 for conversion before selecting the next row. This allows processing two rows at a time, doubling the frame rate. For example, selecting only one row of photosensitive pixels at a time requires N single-row conversion cycles to read N rows of pixels, where N is a positive integer; while in this embodiment, selecting two rows of photosensitive pixels at a time requires only N / 2 conversion cycles to read N rows of pixels. Combined with... Figure 3 The photosensitive pixels of the first and second rows are selected at time t1. The processing of the raw pixel data of the first and second rows can be completed before time t1+ΔT, where ΔT is the conversion period. At time t1+ΔT, the photosensitive pixels of the third and fourth rows are selected. The processing of the raw pixel data of the third and fourth rows can be completed before time t1+2ΔT, and so on.

[0059] In related technologies, to simultaneously obtain high-gain and low-gain image data, the raw pixel signal of a row of pixels needs to be input to two analog-to-digital converters (ADCs) 20 simultaneously—one for high-gain conversion and the other for low-gain conversion. Therefore, when reading out two rows simultaneously, each column requires four ADCs 20. In this embodiment, each ADC 20 integrates a gain adjustment unit 21, which can switch the gain at different time periods via a level control signal. Therefore, the same ADC 20 can process high-gain and low-gain signals at different time periods, i.e., the same ADC 20 processes signals with different gains at different time periods, achieving time-division multiplexing. Thus, only two ADCs 20 are needed per column to support simultaneous dual-row readout and multiple gain conversions.

[0060] It should be noted that the two analog-to-digital conversion units 20 process the raw pixel signals of two adjacent rows respectively. When processing one row of signal, each analog-to-digital conversion unit 20 can switch between different gain levels through the gain adjustment unit 21 to obtain multi-gain image data of the same row of signal. The specific gain switching timing can be determined according to the actual situation. For example, the current row can be converted to high gain first and then to low gain, or other timing can be used. No specific limitation is made here.

[0061] In some embodiments, a first switching group 30 and a second switching group 40 are also included; for the two analog-to-digital converters 20 connected to each column of photosensitive pixels, the first switching group 30 is connected between one analog-to-digital converter 20 and the photosensitive pixels of the corresponding column, and the second switching group 40 is connected between the other analog-to-digital converter 20 and the photosensitive pixels of the corresponding column, so that the raw pixel signals collected by the photosensitive pixels in odd-numbered rows and the raw pixel signals collected by the photosensitive pixels in even-numbered rows can be selectively transmitted to different analog-to-digital converters 20 respectively.

[0062] As an example, the first switching group 30 and the second switching group 40 are column-level signal routing circuits, with each column of photosensitive pixels corresponding to a first switching group 30 and a second switching group 40. For each column of two analog-to-digital converters 20 connected, the first switching group 30 is connected between one of the analog-to-digital converters 20 (denoted as the first analog-to-digital converter 20) and the photosensitive pixels of that column, and the second switching group 40 is connected between the other analog-to-digital converter 20 (denoted as the second analog-to-digital converter 20) and the photosensitive pixels of that column.

[0063] The first switching group 30 controls whether the raw pixel signal output by the photosensitive pixels in that column is transmitted to the first analog-to-digital converter 20. The second switching group 40 controls whether the raw pixel signal output by the photosensitive pixels in that column is transmitted to the second analog-to-digital converter 20. By cooperating with the two switching groups, the raw pixel signals acquired by the photosensitive pixels in odd-numbered rows and the raw pixel signals acquired by the photosensitive pixels in even-numbered rows can be selectively transmitted to different analog-to-digital converters 20.

[0064] Specifically, when two adjacent rows (one odd-numbered row and one even-numbered row) are simultaneously selected, the following two allocation methods can be achieved through the on / off configuration of the first switching switch group 30 and the second switching switch group 40: In the first allocation method, the original pixel signals of the odd-numbered rows are transmitted to the first analog-to-digital converter (ADC) unit 20 through the first switching switch group 30, and the original pixel signals of the even-numbered rows are transmitted to the second ADC unit 20 through the second switching switch group 40. In this case, the first ADC unit 20 processes the odd-numbered row signals, and the second ADC unit 20 processes the even-numbered row signals. In the second allocation method, the original pixel signals of the even-numbered rows are transmitted to the first ADC unit 20 through the first switching switch group 30, and the original pixel signals of the odd-numbered rows are transmitted to the second ADC unit 20 through the second switching switch group 40. In this case, the first ADC unit 20 processes the even-numbered row signals, and the second ADC unit 20 processes the odd-numbered row signals. In this way, the two analog-to-digital converters 20 can be switched by switching the control signal of the switch group, so that they can alternately acquire signals of odd and even rows. This can balance the workload of the two analog-to-digital converters 20 and avoid performance imbalance caused by a certain analog-to-digital converter 20 continuously processing a certain type of row signal.

[0065] In some embodiments, the first switching group 30 includes a third switching device K3 and a fourth switching device K4; the second switching group 40 includes a fifth switching device K5 and a sixth switching device K6; the third switching device K3 includes a first end connected to each odd-numbered row of photosensitive pixels, a second end connected to the analog-to-digital converter 20, and a control end connected to a first switching signal; the fourth switching device K4 includes a first end connected to each even-numbered row of photosensitive pixels, a second end connected to the analog-to-digital converter 20, and a control end connected to a second switching signal; the fifth switching device K5 includes a first end connected to each odd-numbered row of photosensitive pixels, a second end connected to the analog-to-digital converter 20, and a control end connected to a second switching signal; the sixth switching device K6 includes a first end connected to each even-numbered row of photosensitive pixels, a second end connected to the analog-to-digital converter 20, and a control end connected to the first switching signal; wherein the first switching signal and the second switching signal are a set of signals with opposite phases.

[0066] As an example, the first and second switching signals are a pair of signals with opposite phases; that is, when the first switching signal is active, the second switching signal is inactive, and when the first switching signal is inactive, the second switching signal is active. The first and second switching signals will not be active or inactive simultaneously, ensuring that at any given time, signals in odd-numbered rows and even-numbered rows have definite routing paths.

[0067] As an example, when the first switching signal is active and the second switching signal is inactive, the third switching device K3 is turned on, and the original pixel signals of the odd-numbered rows are transmitted to the first analog-to-digital converter unit 20 through the third switching device K3; the sixth switching device K6 is turned on, and the original pixel signals of the even-numbered rows are transmitted to the second analog-to-digital converter unit 20 through the sixth switching device K6; the fourth switching device K4 is turned off, and the even-numbered row signals do not pass through the first switching switch group 30; the fifth switching device K5 is turned off, and the odd-numbered row signals do not pass through the second switching switch group 40. At this time, the first analog-to-digital converter unit 20 processes the odd-numbered row signals, and the second analog-to-digital converter unit 20 processes the even-numbered row signals.

[0068] When the first switching signal is invalid and the second switching signal is valid, the fourth switching device K4 is turned on, and the original pixel signals of even-numbered rows are transmitted to the first analog-to-digital converter (ADC) unit 20 through the fourth switching device K4; the fifth switching device K5 is turned on, and the original pixel signals of odd-numbered rows are transmitted to the second ADC unit 20 through the fifth switching device K5; the third switching device K3 is turned off, and the signals of odd-numbered rows do not pass through the first switching switch group 30; the sixth switching device K6 is turned off, and the signals of even-numbered rows do not pass through the second switching switch group 40. At this time, the first ADC unit 20 processes the signals of even-numbered rows, and the second ADC unit 20 processes the signals of odd-numbered rows. By flipping the levels of the first and second switching signals, the two ADC units 20 can be alternately acquired, that is, before the switch, the first ADC unit 20 acquires the odd-numbered rows and the second ADC unit 20 acquires the even-numbered rows, and after the switch, the first ADC unit 20 acquires the even-numbered rows and the second ADC unit 20 acquires the odd-numbered rows.

[0069] Reference Figure 3In odd-numbered columns, the original pixel signals of odd-numbered rows are assigned to the first analog-to-digital converter (ADC) unit 20, and the original pixel signals of even-numbered rows are assigned to the second ADC unit 20; similarly, in even-numbered columns, the original pixel signals of even-numbered rows are assigned to the first ADC unit 20, and the original pixel signals of odd-numbered rows are assigned to the second ADC unit 20. From the perspective of the entire pixel array, the allocation of the original pixel signals to the two ADC units 20 exhibits a checkerboard pattern: odd-numbered rows in odd-numbered columns and even-numbered rows in even-numbered columns are assigned to the same ADC unit 20 (the first ADC unit 20), while even-numbered rows in odd-numbered columns and odd-numbered rows in even-numbered columns are assigned to another ADC unit 20 (the second ADC unit 20). In other words, in the two-dimensional array, the original pixel signals of two adjacent pixels (regardless of whether they are adjacent in the row or column direction) are always assigned to different ADC units 20. If all columns use the same switching signal configuration, all odd-numbered rows are processed by one analog-to-digital converter (ADC) unit 20, and all even-numbered rows are processed by another ADC unit 20. When there is unevenness in the image content between rows (e.g., odd rows are generally brighter and even rows are generally darker), the workload and data characteristics of the two ADC units 20 may differ significantly. With a checkerboard staggered distribution, the pixels processed by each ADC unit 20 are evenly distributed in the array, and the statistical characteristics of the input signals of the two ADC units 20 are more similar. This helps maintain consistent operating states between the two ADC units 20 and reduces performance differences caused by uneven load. Furthermore, because the pixels processed by each ADC unit 20 are spatially staggered, even if there are differences in gain or offset between the two ADC units 20, these differences manifest as a checkerboard-like fixed-pattern noise in the image, which is more easily perceived by the human eye than row-striped fixed-pattern noise.

[0070] In the above embodiments, by configuring two analog-to-digital converters 20 in each column and cooperating with switching groups, synchronous readout and parallel conversion of adjacent rows of photosensitive pixels can be achieved. Simultaneous readout of two rows improves readout efficiency and increases the imaging frame rate without increasing the operating frequency of the analog-to-digital converters 20. The first switching group 30 and the second switching group 40 are cross-connected through the third switching device K3, the fourth switching device K4, the fifth switching device K5, and the sixth switching device K6. Combined with the first and second switching signals with opposite phases, the original pixel signals of odd-numbered rows and even-numbered rows can be selectively routed to the two analog-to-digital converters 20 respectively. By flipping the control signal, alternating acquisition by the two analog-to-digital converters 20 can be achieved, balancing the load of the two converters and making the readout mode more flexible.

[0071] Reference Figure 4As an example of the overall architecture of an image acquisition device, the device can adopt a three-dimensional stacked configuration with pixel chips and logic chips stacked vertically. The pixel chip, located on the upper layer, performs photoelectric conversion. Its central area contains an effective pixel array composed of several photosensitive pixels, while the peripheral area of ​​the effective pixel array contains pixel-level transmission, reset, and gating transistor circuits. The logic chip, located on the lower layer, performs signal readout and processing functions. It integrates functional circuits such as a row decoder, row driver, several analog-to-digital converters 20, a voltage control module, and a ramp generator. The pixel chip and logic chip are electrically connected through vertical contacts located on the outer periphery of the chip, allowing control signals generated by the logic chip to be transmitted to the pixel chip, and raw pixel signals output by the pixel chip to be transmitted to the logic chip for processing.

[0072] In this image acquisition device, the row decoder and row driver can be located on the logic chip, together forming the row control module of the image acquisition device. The row decoder receives the externally input row address signal, decodes the row address to generate a row selection control signal; the row driver receives the row selection control signal output by the row decoder, enhances its driving capability, and transmits it to the pixel chip through vertical contacts to control the photosensitive pixels of the corresponding row to perform exposure reset and signal readout. The row decoder and row driver can simultaneously select two adjacent rows of photosensitive pixels to support dual-row synchronous readout mode. The analog-to-digital conversion unit 20 is arranged in a column-level structure in the central area of ​​the logic chip, with each column of photosensitive pixels corresponding to two analog-to-digital conversion units 20. Each analog-to-digital conversion unit 20 integrates a gain adjustment unit 21 and a conversion unit 22. The gain adjustment unit 21 performs programmable gain processing on the original pixel signal, and the conversion unit 22 converts the gain-adjusted analog signal into digital image data. The operating timing and gain level of the analog-to-digital conversion unit 20 are configured by the control signal output by the voltage control module. The voltage control module is located on the logic chip and can be used to provide a reference signal. The ramp generator is located on the logic chip and is the reference signal generation module of the comparator circuit 221 in the conversion unit 22. It is used to simultaneously and continuously generate a ramp reference voltage, a first ramp signal, and a second ramp signal.

[0073] Reference Figure 5 According to a second aspect of this application, a vehicle is provided, including a controller and the aforementioned image acquisition device; the controller is configured to output a gear control signal to the image acquisition device to control the image acquisition device to process the raw pixel signal at a target gain. This vehicle possesses all the beneficial effects of the aforementioned image acquisition device, which will not be elaborated further herein.

[0074] In addition, the vehicle may include a display device connected to the image acquisition device for receiving image data and displaying it based on the image data.

[0075] The vehicle can be a gasoline-powered vehicle, a plug-in hybrid electric vehicle, or a new energy vehicle, etc., and this disclosure does not specifically limit it. The vehicle in this embodiment can be configured with an intelligent driving mode, in which relevant image data can be acquired through an image acquisition device.

[0076] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0077] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0078] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0079] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. An image acquisition device, characterized in that, include: An image sensor includes several photosensitive pixels for acquiring raw pixel signals; A plurality of analog-to-digital conversion units; each of the analog-to-digital conversion units includes a gain adjustment unit and a conversion unit; The gain adjustment unit is connected to the photosensitive pixel and the conversion unit, and is used to determine the target gain according to the gear control signal, process the original pixel signal according to the target gain to obtain a gain adjustment signal and output it to the conversion unit; the conversion unit is used to obtain image data for image display according to the gain adjustment signal. The gain adjustment unit includes an amplifier and at least one gain optimization circuit. The amplifier includes a first input terminal connected to the photosensitive pixel, a second input terminal for receiving a reference signal, and an output terminal connected to the conversion unit. The gain optimization circuit includes a second capacitor and a second switching device. The second capacitor and the second switching device are connected in series between the first input terminal and the output terminal of the amplifier. The second capacitor is connected to the feedback loop of the amplifier when the second switching device is turned on.

2. The image acquisition device according to claim 1, characterized in that, The gear control signal includes a first gear signal; the gain adjustment unit further includes a first switching device and a first capacitor; The first switching device and the first capacitor are connected in parallel between the first input terminal and the first output terminal of the amplifier; The first switching device is used to receive the first gear signal and turn on or off according to the first gear signal. The first capacitor is bypassed when the first switching device is on and connected to the feedback loop of the amplifier when the first switching device is off, so as to adjust the target gain of the amplifier.

3. The image acquisition device according to claim 2, characterized in that, The gear control signal includes a second gear signal; The second switching device is used to receive the second gear signal and to turn on or off according to the second gear signal. The second capacitor is connected in parallel with the first capacitor and connected to the feedback loop when the second switching device is on, and disconnected from the first capacitor when the second switching device is off.

4. The image acquisition device according to claim 3, characterized in that, The conversion unit includes a comparator circuit and a counter; The comparison circuit is used to determine the range of the gain adjustment signal and convert the gain adjustment signal into a binary sequence within the range. The counter is used to count the binary sequence to obtain the image data.

5. The image acquisition device according to claim 4, characterized in that, The comparison circuit includes a reference signal source, a selection switch group, and a comparator; The reference signal source is used to provide a ramp reference voltage, a first ramp signal with an amplitude range covering a first range, and a second ramp signal with an amplitude range covering a second range; wherein the first range and the second range do not overlap, and the ramp reference voltage is the boundary value between the first range and the second range. The selection switch group is connected between the reference signal source and the comparator, and is used to transmit one of the ramp reference voltage, the first ramp signal and the second ramp signal to the comparator. The comparator includes a first input terminal connected to the gain adjustment unit to receive the gain adjustment signal, a second input terminal connected to the selection switch group, and an output terminal connected to the counter.

6. The image acquisition device according to claim 5, characterized in that, During the first time period, the selection switch group transmits the ramp reference voltage to the comparator, so that the comparator compares the ramp reference voltage with the gain adjustment signal, and outputs a first level signal when the comparison result is that the ramp reference voltage is greater than the gain adjustment signal, and outputs a second level signal when the comparison result is that the ramp reference voltage is less than the gain adjustment signal; In the second time period following the first time period, the selection switch group transmits the first ramp signal to the comparator based on the first level signal, so that the comparator quantizes the gain adjustment signal within the first range to obtain the binary sequence, and transmits the second ramp signal to the comparator based on the second level signal, so that the comparator quantizes the gain adjustment signal within the second range to obtain the binary sequence.

7. The image acquisition device according to claim 1, characterized in that, A plurality of the aforementioned photosensitive pixel arrays are arranged, and each column of the photosensitive pixels is connected to two of the aforementioned analog-to-digital conversion units; In the case where two adjacent rows of photosensitive pixels are simultaneously selected, the original pixel signals collected by the photosensitive pixels in the two adjacent rows are output to their respective analog-to-digital conversion units for synchronous conversion.

8. The image acquisition device according to claim 7, characterized in that, It also includes a first switching switch group and a second switching switch group; For each of the two analog-to-digital converters connected to the photosensitive pixels in each column, a first switching group is connected between one analog-to-digital converter and the photosensitive pixels in the corresponding column, and a second switching group is connected between the other analog-to-digital converter and the photosensitive pixels in the corresponding column, so that the raw pixel signals collected by the photosensitive pixels in odd-numbered rows and the raw pixel signals collected by the photosensitive pixels in even-numbered rows can be selectively transmitted to different analog-to-digital converters.

9. The image acquisition device according to claim 8, characterized in that, The first switching group includes a third switching device and a fourth switching device; the second switching group includes a fifth switching device and a sixth switching device. The third switching device includes a first terminal connected to each of the odd-numbered rows of photosensitive pixels, a second terminal connected to the analog-to-digital conversion unit, and a control terminal that receives the first switching signal; The fourth switching device includes a first terminal connected to the photosensitive pixels of each of the even-numbered rows, a second terminal connected to the analog-to-digital conversion unit, and a control terminal that receives the second switching signal; The fifth switching device includes a first terminal connected to each of the odd-numbered rows of photosensitive pixels, a second terminal connected to the analog-to-digital conversion unit, and a control terminal that receives the second switching signal; The sixth switching device includes a first terminal connected to the photosensitive pixels of each of the even-numbered rows, a second terminal connected to the analog-to-digital conversion unit, and a control terminal connected to the first switching signal; The first switching signal and the second switching signal are a set of signals with opposite phases.

10. A vehicle, characterized in that, Includes a controller and the image acquisition device according to any one of claims 1 to 9; The controller is used to output a gear control signal to the image acquisition device to control the image acquisition device to process the original pixel signal with a target gain.

Images