Analog-digital conversion circuit, photoelectric conversion device, image pickup device, and mobile body

Abstract

An AD conversion circuit, an optical-electric conversion device, an imaging device, and a mobile body are provided. The AD conversion circuit includes a delta sigma AD converter including an integration circuit, a holding circuit configured to hold a signal output from the integration circuit, a switching circuit configured to switch an input to the AD converter between an input terminal of the AD conversion circuit and the holding circuit, a digital demodulation circuit configured to generate a digital signal based on a signal output from the AD converter, a digital gain adjustment circuit configured to perform gain adjustment on a signal output from the digital demodulation circuit, and an acquisition circuit. The acquisition circuit acquires a correction value based on the digital signal output from the digital demodulation circuit in accordance with a reference signal supplied to the input terminal, and performs gain adjustment in the digital gain adjustment circuit based on the correction value in an AD conversion mode.

Description

Technical Field

[0001] This disclosure relates to AD conversion circuits, photoelectric conversion devices, imaging devices, and moving bodies. Background Technology

[0002] Japanese Patent Application Publication No. 2024-153548 discloses a two-stage continuous-time ΔΣ analog-to-digital (AD) converter that performs high-order and low-order bit conversion in a time-division manner, as a technique for miniaturizing ΔΣ AD converters. Furthermore, Japanese Patent Application Publication No. 2024-153548 discloses a technique that arranges a digital gain adjustment circuit for gain adjustment of digital signals to improve the nonlinear distortion of the ΔΣ AD converter caused by gain errors in the amplifier circuit.

[0003] The gain error of the ΔΣ AD converter disclosed in Japanese Patent Application Publication No. 2024-153548 can vary with changes in, for example, temperature and supply voltage. This variation in gain error implies a change in the optimal value of the correction used in the digital gain adjustment circuit. Summary of the Invention

[0004] Some embodiments of this disclosure provide advantageous techniques for improving the nonlinearity error of ΔΣ AD converters.

[0005] According to some embodiments, an AD conversion circuit is provided, configured to operate in multiple modes including an AD conversion mode and a correction value acquisition mode, wherein in the AD conversion mode, a signal supplied to an input terminal is AD converted, the AD conversion circuit comprising: a ΔΣ AD converter including an integrating circuit configured to integrate a difference signal; a holding circuit configured to hold a signal corresponding to a voltage output from the integrating circuit; a switching circuit configured to switch the signal to be supplied to the ΔΣ AD converter between a signal supplied to the input terminal and a signal held in the holding circuit; and a digital demodulation circuit configured to adjust the signal based on the difference signal. The AD converter outputs a ΔΣ modulation signal to generate a digital signal; and a digital gain adjustment circuit is configured to adjust the gain of the signal output from the digital demodulation circuit, wherein the AD conversion circuit further includes an acquisition circuit configured to, in the correction value acquisition mode, obtain a correction value based on the digital signal output from the digital demodulation circuit according to a correction value obtained from the input terminal, and perform gain adjustment in the digital gain adjustment circuit based on the correction value.

[0006] The features of this disclosure will become apparent from the following description of embodiments with reference to the accompanying drawings. The following description of the embodiments is given by way of example. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating an example configuration of an AD conversion circuit according to an embodiment;

[0008] Figure 2A and Figure 2B It is shown Figure 1 Timing diagram of an example of the timing of the operation of the AD conversion circuit;

[0009] Figure 3 It shows that you have obtained Figure 1 A flowchart illustrating an example of the sequence of correction values ​​in the AD conversion circuit;

[0010] Figure 4 It is shown Figure 1 A circuit diagram illustrating an example configuration of a ΔΣ AD converter in the AD conversion circuit.

[0011] Figure 5 It is shown Figure 1 A circuit diagram illustrating an example configuration of a ΔΣ AD converter in the AD conversion circuit.

[0012] Figure 6 It is shown Figure 1 A circuit diagram illustrating an example configuration of a ΔΣ AD converter in the AD conversion circuit.

[0013] Figure 7 It is shown Figure 1 A block diagram of a modified example of the AD conversion circuit in the diagram;

[0014] Figure 8 It shows that you have obtained Figure 7 A flowchart illustrating an example of the sequence of correction values ​​in the AD conversion circuit;

[0015] Figure 9 This is a diagram illustrating an example configuration of a photoelectric conversion device including an AD conversion circuit according to an embodiment;

[0016] Figure 10 It is shown Figure 9 A circuit diagram illustrating an example configuration of the readout circuit for a photoelectric conversion device.

[0017] Figure 11 It is shown Figure 9 A block diagram illustrating an example configuration of the AD conversion circuit for a photoelectric conversion device.

[0018] Figure 12 This is a block diagram illustrating an example configuration of a photoelectric conversion system including an AD conversion circuit according to an embodiment; and

[0019] Figure 13A and Figure 13BThis is a diagram illustrating an example configuration of a moving body including an AD conversion circuit according to an embodiment. Detailed Implementation

[0020] In the following, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments are not intended to limit the scope of the claims. Several features are described in the embodiments, but not all such features are required, and several such features can be appropriately combined. Furthermore, in the drawings, the same reference numerals are given the same or similar configuration, and redundant descriptions thereof are omitted.

[0021] Reference Figures 1 to 13A and Figure 13B An AD conversion circuit for converting analog signals into digital signals is described according to embodiments of the present disclosure. Figure 1 This is a block diagram illustrating an example configuration of the AD conversion circuit 1 according to the present disclosure. Figure 2A and Figure 2B This is a timing diagram showing an example of the operating timing of the AD conversion circuit 1. Figure 3 This is a flowchart illustrating an example of a sequence of corrected values ​​obtained in AD conversion circuit 1.

[0022] The AD conversion circuit 1 is configured, for example, as a two-stage ΔΣ AD converter. The AD conversion circuit 1 can be a continuous-time AD conversion circuit including a continuous-time integrator, or a hybrid AD conversion circuit including both a continuous-time integrator and a discrete-time integrator. The AD conversion circuit 1 converts the analog signal supplied to the input terminal IN into a digital signal and outputs the digital signal from the output terminal OUT. The AD conversion circuit 1 is configured to operate in multiple modes, including an AD conversion mode and a correction value acquisition mode. In the AD conversion mode, the signal supplied to the input terminal IN is AD converted. In the correction value acquisition mode, the correction value during gain adjustment in the digital gain adjustment circuit 60 is obtained. In the AD conversion mode, nonlinear errors caused by variations in the gain error of the ΔΣ AD converter 10 can be improved. The configuration and operation of the AD conversion circuit 1 will be described in detail below.

[0023] The AD conversion circuit 1 may include a ΔΣ AD converter 10 and a switching circuit 30. The AD conversion circuit 1 may also include a residual voltage holding circuit 20, a digital demodulation circuit 40, and a reconstruction circuit 50. Furthermore, the AD conversion circuit 1 may include an acquisition circuit 70 to acquire a correction value in a correction value acquisition mode. The AD conversion circuit 1 may also include a control circuit 80 for controlling the acquisition circuit 70, a memory 90 for storing the correction value, and an analog signal switching circuit 100 serving as a switching circuit other than the switching circuit 30. The AD conversion circuit 1 is sometimes configured without the analog signal switching circuit 100, which will be described later.

[0024] The ΔΣ AD converter 10 may include an integrating circuit for integrating the difference signal. The ΔΣ AD converter 10 receives a supply of an analog signal used as the output from the switching circuit 30 and outputs a time-series ΔΣ modulated signal. The residual voltage holding circuit 20 is a holding circuit that holds a signal corresponding to the voltage output from the integrating circuit of the ΔΣ AD converter 10. The switching circuit 30 switches the signal to be supplied to the ΔΣ AD converter 10 between a signal supplied to the input terminal IN and a signal held in the residual voltage holding circuit 20. The digital demodulation circuit 40 generates (demodulates) a multi-bit digital signal corresponding to the time-series ΔΣ modulated signal output from the ΔΣ AD converter 10. The demodulated digital signal is supplied to the acquisition circuit 70 and the digital gain adjustment circuit 60, respectively.

[0025] Next, the configuration for obtaining the correction value used in the gain adjustment of the digital gain adjustment circuit 60 will be described. The control circuit 80 controls the acquisition circuit 70, the memory 90, and the analog signal switching circuit 100. The control circuit 80 supplies control signal C1 to the analog signal switching circuit 100, control signals C2 and C3 to the acquisition circuit 70, and control signals C2 and C4 to the memory 90. The analog signal switching circuit 100 performs switching control between terminal T1, where a reference signal (reference voltage) for obtaining the correction value is input, and terminal T2, where an analog signal to be converted in the AD conversion mode is input. The analog signal switching circuit 100 supplies the signal to terminal T1 or terminal T2 selected by the switching control to the switching circuit 30 via the input terminal IN. The acquisition circuit 70, controlled by control signals C2 and C3, processes the acquisition of a correction value to reduce the nonlinearity error of the ΔΣ AD converter 10 relative to the output from the digital demodulation circuit 40, and outputs the processing result as a correction value to the memory 90. In the correction value acquisition mode, the acquisition circuit 70 obtains the correction value based on the digital signal output from the digital demodulation circuit 40, according to the correction value acquisition reference signal supplied to the input terminal IN. The memory 90, controlled by control signals C2 and C4, holds the correction value obtained by the acquisition circuit 70 and outputs the correction value to the digital gain adjustment circuit 60.

[0026] In AD conversion mode, the digital gain adjustment circuit 60 adjusts the gain of the demodulated digital signal based on the correction value stored in the memory 90. The gain-adjusted digital signal is then supplied to the reconstruction circuit 50. The reconstruction circuit 50 generates an output digital signal based on the gain-adjusted digital signal.

[0027] Next, we will refer to Figure 2A and Figure 2B This section describes an example of how to operate the AD conversion circuit 1. Figure 2Aand Figure 2B Shown in time series Figure 1 The correction values ​​shown are obtained using a reference signal, an analog signal, control signals C1 to C4, a reset signal, a switching signal, a hold circuit reset signal, and a sampling signal. Furthermore, Figure 2A and Figure 2B Similarly, it is shown in time series. Figure 1 The operation of the ΔΣAD converter 10, residual voltage holding circuit 20, digital demodulation circuit 40, reconstruction circuit 50, acquisition circuit 70, memory 90 and digital gain adjustment circuit 60 shown.

[0028] As described above, the AD conversion circuit 1 is configured to operate in multiple modes, including an AD conversion mode and a correction value acquisition mode for obtaining correction values, in which the signal supplied to the input terminal IN is converted by the AD converter. Figure 2A and Figure 2B In the operation shown, the time period from time t1 to time t10 is the time period during which the AD conversion circuit 1 operates in the correction value acquisition mode. The time period from time t11 onwards is the time period during which the AD conversion circuit 1 operates in the AD conversion mode. The operation of the AD conversion circuit 1 will be explained below in the order of correction value acquisition mode and AD conversion mode. Here, the operation in the correction value acquisition mode will be explained by illustrating the case of using two types of voltage reference signals (that is, reference signal V0 and reference signal V1).

[0029] First, the sequence until the correction value is obtained in the correction value acquisition mode will be described. During the time period from time t1 to time t10, the control signal C1 changes to a high state, and the analog signal switching circuit 100 selects the terminal T1 to which the reference signal is supplied. During the time period from time t1 to time t5, the reference signal V0 is supplied to terminal T1. During the time period from time t1 to time t2, the reset signal changes to a high state to reset the ΔΣ AD converter 10 and the digital demodulation circuit 40. During the same time period from time t1 to time t2, the holding circuit reset signal changes to a high state to reset the residual voltage holding circuit 20. Furthermore, during the same time period from time t1 to time t2, the control signal C2 changes to a high state to reset the acquisition circuit 70 and the memory 90. During the time period from time t1 to time t3, the switching signal changes to a high state, and the switching circuit 30 connects to the analog signal switching circuit 100, such that the output from the analog signal switching circuit 100 is supplied to the ΔΣ AD converter 10 via the input terminal IN. Then, the reference signal V0 is input to the ΔΣ AD converter 10. The reference signal V0 input to the ΔΣ AD converter 10 is amplified or attenuated by a coefficient determined by the design values ​​of the internal circuitry of the ΔΣ AD converter 10, and is held as an internal voltage (0) in the residual voltage holding circuit 20. The coefficient determined by the design values ​​includes errors in gain and offset caused by, for example, the DC gain of the amplifier present inside the ΔΣ AD converter 10 or the residual voltage holding circuit 20. Let gain be a coefficient determined by the design values ​​of the internal circuitry of the ΔΣ AD converter 10, er be the gain error, and of be the offset, then the internal voltage (0) is given by equation (1): [0030 Internal Voltage] ...(1)

[0030] Then, at time t3, the sampling signal changes to a low state, and the residual voltage holding circuit 20 holds the internal voltage (0). At the same time t3, the switching signal changes to a low state, and the internal voltage (0) used as the output from the residual voltage holding circuit 20 is input to the ΔΣ AD converter 10. During the period from time t3 to time t4, the reset signal changes to a high state to reset the ΔΣ AD converter 10 and the digital demodulation circuit 40. During the period from time t4 to time t5, the ΔΣ AD converter 10 performs AD conversion on the internal voltage (0), and the digital demodulation circuit 40 demodulates the ΔΣ modulated signal output from the ΔΣ AD converter 10. The multi-bit demodulated signal of the internal voltage (0) obtained at this time is represented as the AD conversion value (0).

[0031] At time t5, the AD conversion value (0) is supplied to the acquisition circuit 70, and the acquisition circuit 70 holds the AD conversion value (0). The acquisition circuit 70 may include a memory (not shown) for holding the AD conversion value (0). During the period from time t5 to time t6, the reset signal changes to a high state to reset the ΔΣ AD converter 10 and the digital demodulation circuit 40. During the same period from time t5 to time t6, the holding circuit reset signal changes to a high state to reset the residual voltage holding circuit 20. Furthermore, during the same period from time t5 to time t6, the signal supplied to terminal T1 of the analog signal switching circuit 100 changes to the reference signal V1.

[0032] Then, during the period from time t6 to time t9, similar to the period from time t2 to time t5 described above, the reference signal V1 is used to operate the ΔΣ AD converter 10, the residual voltage holding circuit 20, the digital demodulation circuit 40, and the acquisition circuit 70, thereby obtaining the AD conversion value (1). At time t9, the reset signal changes to a high state to reset the ΔΣ AD converter 10 and the digital demodulation circuit 40. At the same time t9, the holding circuit reset signal changes to a high state to reset the residual voltage holding circuit 20. Furthermore, at the same time t9, the control signal C3 changes to a high state, and the acquisition circuit 70 begins processing to obtain a correction value using the AD conversion value (0) and the AD conversion value (1) held in the acquisition circuit 70. At the same time t9, the control signal C4 changes to a high state to write the correction value obtained by the acquisition circuit 70 into the memory 90, and the memory 90 holds these correction values. The correction value is obtained by digitizing the gain error er and offset of expressed by equation (1), and is expressed as Dig(er) and Dig(of), respectively.

[0033] In the correction value acquisition mode, the switching circuit 30 switches to supply a reference signal V0 to the ΔΣ AD converter 10 during the time period from time t1 to time t3, and to supply a voltage signal to the ΔΣ AD converter 10 during the time period from time t3 to time t5, which is based on the voltage output from the integrating circuit of the AD conversion circuit 1 at the end of the time period from time t1 to time t3, and thus maintained in the residual voltage holding circuit 20. Additionally, the switching circuit 30 switches to supply a reference signal V1 to the ΔΣ AD converter 10 during the time period from time t5 to time t7, and to supply a voltage signal to the ΔΣ AD converter 10 during the time period from time t7 to time t9, which is based on the voltage output from the integrating circuit of the AD conversion circuit 1 at the end of the time period from time t5 to time t7, and thus maintained in the residual voltage holding circuit 20. The acquisition circuit 70 obtains the correction value based on the AD conversion value (0) generated by the digital demodulation circuit 40 from the ΔΣ modulated signal output from the ΔΣ AD converter 10 during the time period from time t3 to time t5, which is used as a digital signal. In other words, the acquisition circuit 70 similarly obtains the correction value based on the AD conversion value (1) generated by the digital demodulation circuit 40 from the ΔΣ AD converter 10 during the time period from time t7 to time t9, which is used as a digital signal.

[0034] Here, in the correction value acquisition mode, multiple types of reference signals, including reference signals V0 and V1, are supplied, and the acquisition circuit 70 acquires the correction value based on multiple digital signals (AD conversion value (0) and AD conversion value (1)) corresponding to the multiple types of reference signals V0 and V1 output from the digital demodulation circuit 40. However, for example, when the temperature characteristics or the characteristics of the variation with respect to the power supply voltage are known for at least either the gain error er or the offset of, the acquisition circuit 70 may acquire the correction value based on the AD conversion value corresponding to a reference signal.

[0035] Next, an operational example in the AD conversion mode after time t10 will be described. At time t10, the control signal C1 changes to a low state, and the analog signal switching circuit 100 selects the terminal T2 supplied with the analog signal. At the same time t10, the switching signal changes to a high state, and the switching circuit 30 connects to the analog signal switching circuit 100, such that the output from the analog signal switching circuit 100 is supplied to the ΔΣ AD converter 10 via the input terminal IN. Then, the analog signal is input to the ΔΣ AD converter 10. Therefore, at time t10, the analog signal is supplied to the ΔΣ AD converter 10. At time t11, the reset signal changes to a low state, and the ΔΣ AD converter 10 begins AD conversion corresponding to the higher-order bit string. At the same time t11, the residual voltage holding circuit 20 begins sampling the residual voltage output from the integrator of the ΔΣ AD converter 10, and the digital demodulation circuit 40 begins demodulation processing of the higher-order bit string corresponding to the ΔΣ modulated signal output from the ΔΣ AD converter 10. At time t12, after the AD conversion corresponding to the higher-order bit string ends, the residual voltage holding circuit 20 holds the voltage signal corresponding to the residual voltage of the ΔΣ AD converter 10, and the reconstruction circuit 50 obtains the multi-bit demodulated signal corresponding to the higher-order bit string. At the same time t12, the switching signal changes to a low state, and the switching circuit 30 switches to supply the voltage signal held in the residual voltage holding circuit 20 to the ΔΣ AD converter 10. During the period from time t12 to time t13, the reset signal changes to a high state to reset the ΔΣ AD converter 10 and the digital demodulation circuit 40. At time t13, the reset signal changes to a low state, the ΔΣ AD converter 10 begins the AD conversion corresponding to the lower-order bit string, and the digital demodulation circuit 40 begins the demodulation processing of the lower-order bit string corresponding to the ΔΣ modulation signal output from the ΔΣ AD converter 10. At time t14, after the demodulation process corresponding to the low-order bit string is completed, the digital gain adjustment circuit 60 begins digital gain adjustment for the multi-bit demodulated signal corresponding to the low-order bit string based on the correction value obtained in the correction value acquisition mode. At this time, assuming Dlsb is the multi-bit demodulated signal corresponding to the low-order bit string, the digitally gain-adjusted multi-bit demodulated signal Dlsb_cor is given by equation (2) using Dig(er) and Dig(of):

[0036] ...(2)

[0037] After time t15, the reconstruction circuit 50 uses a multi-bit demodulated signal equivalent to a low-order bit string with digital gain adjustment and a multi-bit demodulated signal equivalent to a high-order bit string to output the final ADC result (0).

[0038] Figure 3The sequence of correction values ​​obtained in the AD conversion circuit 1 described above is shown. (Refer to...) Figure 3 illustrate Figure 2A and Figure 2B The operation of the AD conversion circuit 1 in the correction value acquisition mode shown, and the calculation method for obtaining the correction value.

[0039] In the correction value acquisition sequence, firstly, in step S301, the AD conversion value acquisition count is determined. In the above description, the AD conversion value acquisition count is 2 used to obtain the AD conversion values ​​(0) and (1). The AD conversion value acquisition count K can be any number greater than 2. However, as mentioned above, the AD conversion value acquisition count K can be any number greater than 1. Based on the acquisition count, K types of voltage signals are prepared as reference signals for obtaining the correction value. The digital values ​​of the internal voltages obtained using coefficients determined by the design values ​​of the ΔΣ AD converter 10 and the K types of reference signals are used in the calculation of the obtained correction value, as described below.

[0040] Then, in each of steps S302 to S306, the ΔΣ AD converter 10, residual voltage holding circuit 20, digital demodulation circuit 40, and acquisition circuit 70 are used to obtain an AD conversion value (N) using one of K types of reference signals. As described above, the AD conversion value (N) is stored in the memory of the acquisition circuit 70, etc. After obtaining the AD conversion value (N), if the value of N is less than K in step S307, the count value N of the obtained count is incremented by 1 in step S308 to become N+1. Then, each of steps S302 to S306 is performed again using another reference signal to obtain the AD conversion value (N+1). These operations are repeated K times, and after the K times of obtaining the AD conversion value are completed, the process moves to step S309 to perform the calculation of the correction value for obtaining the digital value using the internal voltage and the AD conversion value of the K times in the acquisition circuit 70. The correction value obtained in the acquisition circuit 70 is stored in the memory 90.

[0041] The method for calculating the correction value will be illustrated using an example of obtaining a count K=2 from the AD conversion value. V0 represents the reference signal for obtaining the correction value when the AD conversion value is obtained for the first time, Vint0 represents the internal voltage (0) of the ΔΣ AD converter 10 generated when V0 is supplied, and Dig(Vint0) represents the digital value of Vint0. V1 represents the reference signal when the AD conversion value is obtained for the second time, Vint1 represents the internal voltage (1) of the ΔΣ AD converter 10 generated when V1 is supplied, and Dig(Vint1) represents the digital value of Vint1. Furthermore, Vint0_e and Vint1_e represent the internal voltages (0) and (1) respectively containing the error caused by the ΔΣ AD converter 10, etc. (e.g., residual voltage holding circuit 20), and Dig_AD(Vint0_e) and Dig_AD(Vint1_e) represent the AD conversion values ​​(0) and (1) respectively. The relationship between the digital value of the internal voltage (0) Dig(Vint0) and the AD conversion value Dig_AD(Vint0_e) is given by equation (3):

[0042] ...(3) Similarly, the relationship between Dig_AD(Vint1_e) and Dig(Vint1) is given by equation (4):

[0043] ...(4) According to equations (3) and (4), Dig(er) and Dig(of) are given by equations (5) and (6):

[0044] ...(5)

[0045] ...(6)

[0046] The error and offset are calculated as shown in equations (5) and (6), and the digital gain adjustment, represented by equation (2), is applied to the demodulated digital signal corresponding to the low-order bit string. This reduces the error in the internal circuitry of the ΔΣ AD converter 10. In this way, the AD conversion circuit 1 according to this embodiment can digitally correct the nonlinear error generated in the ΔΣ AD converter 10 to reduce the nonlinear error.

[0047] When multiple AD conversion values ​​are obtained, as mentioned above, the reference voltage can have the same value when obtaining each AD conversion value. For example... Figure 2A and Figure 2BAs shown, a correction value acquisition mode can be performed before the start of the AD conversion mode. For example, when activating the device including the AD conversion circuit 1 (e.g., the photoelectric conversion device PEC described later), operations in the correction value acquisition mode can be performed to obtain a correction value. During device startup and operation, the device temperature may change. With this in mind, the correction value acquisition mode can be performed at any time during the AD conversion mode. The correction value obtained in the correction value acquisition mode does not always need to be written to memory 90 after acquisition and can be directly supplied from the acquisition circuit 70 to the digital gain adjustment circuit 60.

[0048] Figure 4 This is a circuit diagram showing an example configuration of the ΔΣ AD converter 10. Figure 4 The configuration of a second-order continuous-time ΔΣ AD converter is shown as an example of the configuration of ΔΣ AD converter 10. ΔΣ AD converter 10 may include a first integrator 110, a second integrator 120 connected to the output of the first integrator, a comparator 130, a digital-to-analog (DA) converter 140, and a multiplexer 141. The first integrator 110 may include, for example, resistors 101 and 105, capacitor 102, switch 103, and amplifier 104. The second integrator 120 may include, for example, resistors 111 and 115, capacitor 112, switch 113, and amplifier 114.

[0049] The ADC input signal, used as the input signal for the ΔΣ AD converter 10, is connected to one terminal of resistor 101 of the first integrator 110. The other terminal of resistor 101 is connected to one terminal each of switch 103, capacitor 102, and resistor 105, as well as amplifier 104. The other terminals of switch 103 and capacitor 102 are connected to the output of amplifier 104, and the output from the first integrator 110 is supplied to one terminal of resistor 111 of the second integrator 120. The second integrator 120 can be configured similarly to the first integrator 110, and its output is input to comparator 130. Comparator 130 compares the output of the integrating circuit formed by the first and second integrators 110 and a reference signal. Digital demodulation circuit 40 is connected to the output of comparator 130 and receives the output from comparator 130. The output from comparator 130 is input to DA converter 140 via multiplexer 141. The DA converter 140 converts the output from the comparator 130 into an analog signal and supplies this analog signal to the integrator circuit. More specifically, the output from the DA converter 140 is supplied to the other terminal of resistor 105 of the first integrator 110 and the other terminal of resistor 115 of the second integrator 120. Node 121, which serves as the output of the integrator circuit (more specifically, the output of the second integrator 120), is connected to the residual voltage holding circuit 20. The residual voltage holding circuit 20 holds a signal corresponding to the voltage output from the integrator circuit.

[0050] exist Figure 4 In the ΔΣ AD converter 10 shown, capacitors 102 and 112 are reset when the reset signal is high. When the reset signal is low, the first integrator 110 integrates the voltage difference between the ADC input signal and the DA converter 140. The second integrator 120 integrates the voltage difference between the output of the first integrator 110 and the DA converter 140. The comparator 130 compares the voltage difference between the output of the second integrator 120 and a reference signal using a clock signal (not shown). Figure 4 When the DAC control signal shown is low, multiplexer 141 selects the output of comparator 130, and DA converter 140 outputs an analog voltage corresponding to the output of comparator 130. In this way, first integrator 110 and second integrator 120 can each be continuous-time integrators. DA converter 140 outputs an analog voltage corresponding to the input according to a 1-bit transfer function given, for example, equation (7):

[0051] ...(7) Where: DACin is the output of comparator 130, Vr is the reference voltage (not shown) in ΔΣ AD converter 10, DACOUT is the output of DA converter 140, and the reference voltage is 0. In AD conversion mode, Figure 4 The second-order continuous-time ΔΣ AD converter 10 shown repeatedly performs integration, comparison, and DA conversion until the reset signal changes from a low state to a high state.

[0052] This will be explained in Figure 4 This is an example of a method for calculating the digital value of the internal voltage required to obtain the correction value in the circuit shown. First, when the DAC control signal is high, multiplexer 141 selects a DAC reference value. DA converter 140 converts the selected DAC reference value DA into a reference voltage Vr. The reference voltage Vr used as the conversion result is input to resistor 105 of first integrator 110. Furthermore, an ADC input signal Va, used as an arbitrary voltage value, is supplied to resistor 101 of first integrator 110. First integrator 110 integrates the voltage difference between the input signal Va and the reference voltage Vr during integration time Ts and outputs the result to second integrator 120. Second integrator 120 integrates the voltage difference between the output of first integrator 110 and the reference voltage Vr during integration time Ts and outputs the result as internal voltage Vint to node 121. At this time, let C1 and C2 be the capacitance values ​​of capacitors 102 and 112, respectively, and let R... 11 R 12 and R 21 and R 22 Given the resistance values ​​of resistors 101, 105, 111, and 115, the internal voltage Vint can be approximated by equation (8):

[0053] ...(8)

[0054] In equation (8), the capacitance values ​​C1 and C2, and the resistance value R 11 R 12 and R 21 and R 22 The reference voltage Vr and integration time Ts are determined by the design values, therefore the internal voltage Vint can be calculated during the circuit design phase. Figure 4 In this context, a voltage-controlled current source can be used as a replacement for resistor 105 of the first integrator 110 and resistor 115 of the second integrator 120. When a voltage-controlled current source with a current value I1 is used as a replacement for resistor 105, and a voltage-controlled current source with a current value I2 is used as a replacement for resistor 115, equation (8) can be approximated by equation (9):

[0055] ...(9) As described above, the digital value Dig(Vint) of the internal voltage Vint calculated according to equation (8) or (9) is held in the acquisition circuit 70 as the AD conversion value.

[0056] exist Figure 4 In the circuit configuration shown, errors are generated in the gain and offset of the internal voltage Vint due to the characteristics of amplifiers 104 and 114. The internal voltage Vint containing the error is denoted as the internal voltage Vint_e. In the correction value acquisition mode, similar to equations (3) and (4), the relationship between the AD conversion value Dig_AD(Vint_e) obtained by performing AD conversion on the internal voltage Vint_e and the digital value Dig(Vint) is given by equation (10):

[0057] ...(10) Dig(er) and Dig(of) in Equation (10) can be obtained in the above correction value acquisition mode.

[0058] exist Figure 4 In the configuration shown, the ΔΣ AD converter 10 is configured as a second-order continuous-time ΔΣ AD converter. Both the comparator 130 and the DA converter 140 in the ΔΣ AD converter 10 have a 1-bit configuration. However, multiple bits can also be used to configure the comparator 130 and the DA converter 140, increasing the number of resistors 105 in the first integrator 110 and the number of resistors 115 in the second integrator 120 according to the resolution of the comparator 130 and the DA converter 140, and connecting the resistors 105 and 115 in parallel. Using multiple bits to configure the comparator 130 and the DA converter 140 can increase the AD conversion speed of the ΔΣ AD converter 10. Alternatively, a third-order or higher-order ΔΣ AD converter can be configured by adding one or more integrators between the second integrator 120 and the comparator 130. Increasing the number of integrators can increase the AD conversion speed of the ΔΣ AD converter 10.

[0059] Figure 5 This is a circuit diagram illustrating another configuration example of the ΔΣ AD converter 10, and shows a second-order continuous-time ΔΣ AD converter with a feedforward path. Figure 5 The illustrated ΔΣ AD converter 10 includes a first integrator 110 and a second integrator 150. The second integrator 150 is connected to the output of the first integrator 110 and includes a resistor 151, a capacitor 152, a switch 153, and an amplifier 154. The first integrator 110 has a... Figure 4 The configuration shown is similar to the configuration. In Figure 5In the configuration shown, comparator 160 is a 4-input comparator that compares the ADC input signal, the output from the first integrator 110, and the output from the second integrator 150, which are input to the integrating circuit consisting of the first integrator 110 and the second integrator 150, with a reference signal. The ADC input signal is the signal input to the first integrator 110.

[0060] The output from the first integrator 110 is input to one terminal of resistor 151 of the second integrator 150, and the other terminal of resistor 151 is connected to one terminal each of switch 153 and capacitor 152, as well as amplifier 154. The other terminals of switch 153 and capacitor 152 are connected to the output of amplifier 154. Node 121, serving as the output of the integrating circuit (more specifically, the output of the second integrator 120), is connected to residual voltage holding circuit 20. Similar to... Figure 4 In the configuration shown, the ΔΣ modulated signal, used as the output from comparator 160, is supplied to multiplexer 141 and digital demodulation circuit 40. The output from DA converter 140, which receives the output from multiplexer 141, is supplied to the other terminal of resistor 105 of first integrator 110. Even in Figure 5 In the configuration shown, the first integrator 110 and the second integrator 150 are also continuous-time integrators. Figure 5 The circuit operation of the ΔΣ AD converter 10 shown can be similar to Figure 4 The operation of the ΔΣ AD converter 10 is shown.

[0061] This will be explained in Figure 5 The circuit shown illustrates an example of a method for calculating the digital value of the internal voltage required to obtain the correction value. First, when the DAC control signal is high, multiplexer 141 selects a DAC reference value. DA converter 140 converts the selected DAC reference value DA into a reference voltage Vr. The reference voltage Vr, used as the conversion result, is input to resistor 105 of the first integrator 110. Furthermore, an ADC input signal Va, used as an arbitrary voltage value, is supplied to resistor 101 of the first integrator 110. The first integrator 110 integrates the voltage difference between the input signal Va and the reference voltage Vr during the integration time Ts and outputs the result to the second integrator 150. The second integrator 150 integrates the output from the first integrator 110 during the integration time Ts and outputs the result as the internal voltage Vintf to node 121. At this time, let C3 be the capacitance value of capacitor 152, and R... 23 If the resistance value of resistor 151 is given, then it is similar to equation (8), and the internal voltage Vintf is approximated by equation (11):

[0062] ...(11)

[0063] Similar to equation (8), the internal voltage Vintf can be calculated during the circuit design phase. Figure 5 In this context, a voltage-controlled current source can be used as a replacement for resistor 105 in the first integrator 110. When a voltage-controlled current source with a current value I1 is used as a replacement for resistor 105, equation (11) can be approximated by equation (12):

[0064] ...(12) As described above, the digital value Dig(Vintf) of the internal voltage Vintf calculated according to equation (11) or (12) is held in the acquisition circuit 70 as an AD conversion value.

[0065] exist Figure 5 In the circuit configuration shown, errors are generated in the gain and offset of the internal voltage Vintf due to the characteristics of amplifiers 104 and 154. The internal voltage Vintf containing the error is denoted as the internal voltage Vintf_e. In the correction value acquisition mode, similar to equation (10), the relationship between the AD conversion value Dig_AD(Vintf_e) obtained by performing AD conversion on the internal voltage Vintf_e and the digital value Dig(Vintf) is given by equation (13):

[0066] ...(13) Dig(er) and Dig(of) in equation (13) can be obtained in the above correction value acquisition mode.

[0067] exist Figure 5 In the configuration shown, the amplitude of the signals output from the first integrator 110 and the second integrator 150 can be suppressed by the path through which the ADC input signal is input to comparator 160. This can suppress the effects of nonlinearity in amplifiers 104 and 154. Therefore, the nonlinear distortion characteristics of the ΔΣ AD converter 10 can be improved.

[0068] exist Figure 5In the configuration shown, the ΔΣ AD converter 10 is configured as a second-order continuous-time ΔΣ AD converter. Both the comparator 160 and the DA converter 140 in the ΔΣ AD converter 10 have a 1-bit configuration. However, multiple bits can also be used to configure a 4-input comparator 160 and DA converter 140, increasing the number of resistors 105 in the first integrator 110 according to the resolution of the comparator 160 and DA converter 140, and connecting the resistors 105 in parallel. Alternatively, a third-order or higher-order continuous-time ΔΣ AD converter can be configured by adding one or more integrators between the second integrator 150 and the comparator 160. Increasing the number of bits in the comparators and DA converters, as well as the number of integrators, can increase the AD conversion speed of the ΔΣ AD converter 10.

[0069] Figure 6 This is a circuit diagram illustrating another configuration example of the ΔΣ AD converter 10, and also shows a second-order hybrid ΔΣ AD converter with a feedforward path. The second-order hybrid ΔΣ AD converter is a ΔΣ AD converter that uses a continuous-time integrator as the first integrator and a discrete-time integrator as the second integrator connected to the output of the first integrator. Figure 6 The illustrated ΔΣ AD converter 10 includes a first integrator 110 and a second integrator 170. The second integrator 170 includes capacitors 171 and 172, switches 173, 174, 175, 176, and 177, and an amplifier 178. Apart from the second integrator 170, Figure 6 The configuration of the ΔΣ AD converter 10 shown can be similar to Figure 5 The configuration shown is as described below. Therefore, the connection relationships between the building elements of the second integrator 170 will be described below, and descriptions of relationships that may be similar to those described above will be omitted as appropriate.

[0070] The output from the first integrator 110 is input to one terminal of switch 174 of the second integrator 170, and the other terminal of switch 174 is connected to one terminal of each of capacitor 171 and switch 175. The other terminal of capacitor 171 is connected to one terminal of each of switches 176 and 177, and the other terminal of switch 176 is connected to one terminal of each of switch 173 and capacitor 172, as well as one input of amplifier 178. The other terminals of each of switch 173 and capacitor 172 are connected to the output of amplifier 178. The other terminals of each of switches 175 and 177, as well as another input of amplifier 178, are connected to a reference voltage. Node 121, which serves as the output of the integrating circuit (more specifically, the output of the second integrator 170), is connected to residual voltage holding circuit 20. Figure 6 The circuit operation of the ΔΣ AD converter 10 shown can be similar to Figure 4The circuit operation of the ΔΣ AD converter 10 shown is illustrated.

[0071] This will be explained in Figure 6 An example of a method for calculating the digital value of the internal voltage required to obtain the correction value in the circuit shown. First, when the DAC control signal is high, multiplexer 141 selects a DAC reference value. DA converter 140 converts the selected DAC reference value DA into a reference voltage Vr. The reference voltage Vr used as the conversion result is input to resistor 105 of first integrator 110. In addition, ADC input signal Va, used as an arbitrary voltage value, is supplied to resistor 101 of first integrator 110. First integrator 110 integrates the voltage difference between input signal Va and reference voltage Vr during integration time Ts and outputs the result to second integrator 170. Second integrator 170 integrates the output from first integrator 110 during integration time Ts and outputs the result as internal voltage Vinth to node 121. At this time, assuming C4 and C5 are the capacitance values ​​of capacitors 171 and 172, then similar to equation (8), the internal voltage Vinth is approximated by equation (14):

[0072] ...(14) Similar to equations (8) and (11), the internal voltage Vinth can be calculated during the circuit design phase. Figure 6 In this context, a voltage-controlled current source can be used as a replacement for resistor 105 in the first integrator 110. When a voltage-controlled current source with a current value I1 is used as a replacement for resistor 105, equation (14) can be approximated by equation (15):

[0073] ...(15) As described above, the digital value Dig(Vinth) of the internal voltage Vinth calculated according to equation (14) or (15) is held in the acquisition circuit 70 as an AD conversion value.

[0074] exist Figure 6 In the circuit configuration shown, errors are generated in the gain and offset of the internal voltage Vinth due to the characteristics of amplifiers 104 and 178. The internal voltage Vinth containing the error is denoted as the internal voltage Vinth_e. In the correction value acquisition mode, similar to equations (10) and (13), the relationship between the AD conversion value Dig_AD(Vinth_e) obtained by performing AD conversion on the internal voltage Vinth_e and the digital value Dig(Vinth) is given by equation (16):

[0075] ...(16) Dig(er) and Dig(of) in equation (16) can be obtained in the above correction value acquisition mode.

[0076] Figure 6 The illustrated ΔΣ AD converter 10 is a hybrid ΔΣ AD converter in which the integrating circuit consists of a first integrator 110 used as a continuous-time integrator and a second integrator 170 used as a discrete-time integrator. Compared to using only a continuous-time integrator, the hybrid ΔΣ AD converter can suppress noise caused by clock jitter, which causes problems in continuous-time integrators, and suppress characteristic variations caused by manufacturing deviations of passive components such as capacitors.

[0077] exist Figure 6 In the configuration shown, the ΔΣ AD converter 10 is configured as a second-order hybrid ΔΣ AD converter. Both the comparator 160 and the DA converter 140 in the ΔΣ AD converter 10 have a 1-bit configuration. However, multiple bits can also be used to configure a 4-input comparator 160 and DA converter 140, increasing the number of resistors 105 in the first integrator 110 according to the resolution of the comparator 160 and DA converter 140, and connecting the resistors 105 in parallel. Alternatively, a third-order or higher-order hybrid ΔΣ AD converter can be configured by adding one or more discrete-time integrators between the second integrator 150 and the comparator 160. Increasing the number of bits in the comparators and DA converters, as well as the number of integrators, can increase the AD conversion speed of the ΔΣ AD converter 10.

[0078] Figure 7 It is shown Figure 1 The block diagram shows a modified example of the AD conversion circuit 1. Figure 7 In the AD conversion circuit 1 shown, with Figure 1 Unlike the AD conversion circuit 1 shown, the obtaining circuit 70 includes an averaging circuit 71. The remaining configurations can be similar to those described above, therefore the averaging circuit 71 will be described primarily below, and descriptions of configurations that may be similar to those described above will be omitted as appropriate.

[0079] The averaging circuit 71 may include a memory for holding the acquired values ​​corresponding to the correction values ​​obtained by the acquisition circuit 70 described above. The averaging circuit 71 averages the held acquired values. The averaged acquired value is output as a correction value from the acquisition circuit 70 (averaging circuit 71) to the memory 90. To control the operation of the averaging circuit 71, the control circuit 80 supplies a control signal C5 to the averaging circuit 71.

[0080] Figure 8 Show Figure 7 The correction value sequence is obtained in the AD conversion circuit 1 shown. (Referencing...) Figure 8 The description includes the operation of the averaging circuit 71 and the AD conversion circuit 1, as well as the calculation method used to obtain the correction value. Figure 8 In the obtained sequence shown, steps S302 to S308 are... Figure 3 The steps shown in obtaining the sequence are similar.

[0081] First, in step S801, the AD conversion value acquisition count is determined. The AD conversion value acquisition count K can be any number of 2 or greater than 2. However, as mentioned above, the AD conversion value acquisition count K can be any number of 1 or greater than 1. Determination and Reference Figures 1 to 6 The obtained value acquisition count corresponds to the obtained correction value acquired by the described acquisition circuit 70. The obtained value acquisition count L can be any number of 2 or greater than 2.

[0082] Then, in each of steps S302 to S306, the ΔΣ AD converter 10, residual voltage holding circuit 20, digital demodulation circuit 40, and acquisition circuit 70 are used to obtain an AD conversion value (N) using one of K types of reference signals. As described above, the AD conversion value (N) is stored in the memory of the acquisition circuit 70, etc. After obtaining the AD conversion value (N), if the value of N is less than K in step S307, the count value N of the AD conversion value acquisition count is incremented by 1 in step S308 to become N+1. Then, each of steps S302 to S306 is performed again using another reference signal to obtain the AD conversion value (N+1). These operations are repeated K times, and after the K acquisitions of the AD conversion value are completed, the process moves to step S802 to perform calculations in the acquisition circuit 70 to obtain an acquired value using the digital value of the internal voltage and the K AD conversion values. The acquired value obtained in the acquisition circuit 70 is stored in the memory (not shown) of the averaging circuit 71, etc. After obtaining the acquired value in step S802, if the value of M is less than L in step S803, then in step S804, the count value M of the acquired value is incremented by 1 to become M+1. These operations are repeated L times, and after the L acquisitions of the acquired value are completed, the process moves to step S805 to perform calculations in the averaging circuit 71 to obtain a correction value by averaging the acquired values. The correction value obtained in the averaging circuit 71 is stored in the memory 90. Figure 8 The sequence shown can be considered as follows: In the correction value acquisition mode, the acquisition circuit 70 acquires the digital signal output from the digital demodulation circuit 40 multiple times based on the same type of reference signal, and obtains the correction value based on each of the multiple acquired digital signals.

[0083] The obtained values ​​(the values ​​obtained through the digital gain error er and offset of) are represented as Dig(er)[0], Dig(er)[1], Dig(er)[2], ..., Dig(er)[L] and Dig(of)[0], Dig(of)[1], Dig(of)[2], ..., Dig(of)[L]. Here, let Dig_ave(er) and Dig_ave(of) be the correction values ​​obtained by averaging multiple obtained values, then the averaging process performed by the averaging circuit 71 is given by equations (17) and (18):

[0084] ...(17)

[0085] ...(18)

[0086] The correction value generated by the averaging process according to equations (17) and (18) is stored in memory 90. Based on this correction, similar to the above description, the digital gain adjustment circuit 60 makes adjustments in the AD conversion mode. For example, the digital gain adjustment circuit 60 can perform gain adjustment on the digital signal of the low-order bit string based on the correction value.

[0087] Since the AD conversion value of the internal voltage used to obtain the correction value contains noise from the ΔΣ AD converter 10, the obtained correction value may vary only in a single correction value calculation. Therefore, by using the averaging process of the averaging circuit 71, the influence of noise from the ΔΣ AD converter 10, etc., can be reduced, thereby obtaining a correction value in which the variation caused by noise is suppressed.

[0088] An application example of the above AD conversion circuit 1 will be explained. Figure 9 The diagram illustrates a configuration of a photoelectric conversion device (PEC) using the AD conversion circuit 1 according to the present disclosure. The PEC can be configured as a solid-state image sensing device that senses and outputs an image. Alternatively, the PEC can be configured as a device that senses an image and outputs a signal obtained from the sensed image.

[0089] The photoelectric conversion device PEC may include, for example, a pixel array (an array composed of multiple pixels, each including a photoelectric converter) 200, a vertical drive circuit 210, a readout circuit 220, a control circuit 240, and a signal processing circuit 230. The readout circuit 220 may include multiple current sources 222 respectively connected to multiple vertical lines 250, and an AD conversion circuit 223 for performing AD conversion on signals output from pixels in a selected row to the vertical lines 250. The aforementioned AD conversion circuit 1 is applicable as each AD conversion circuit 223 of the readout circuit 220.

[0090] The photoelectric conversion device PEC can be configured to read the reset level from each pixel and the optical signal level generated by the photoelectric conversion from the pixel array 200 using the readout circuit 220. The readout circuit 220 can be configured to output digital signals of the reset level and optical signal levels. The signal processing circuit 230 can be configured to perform CDS processing on the digital signals of the reset level and optical signal levels, and output the CDS-processed signal. Since the offset generated in the ΔΣ AD converter 10 is removed by CDS processing, the acquisition of the offset correction value expressed by equation (2) can be omitted. In this case, the correction value can be obtained using, for example, only a reference voltage. This simplifies the computational processing for obtaining the correction value and reduces the circuit size of the acquisition circuit 70. Furthermore, this shortens the time for obtaining the correction value. As a result, for example, the number of correction value acquisition modes inserted between AD conversion modes can be increased, thereby achieving higher accuracy AD conversion.

[0091] The pixel array 200, vertical drive circuit 210, readout circuit 220, control circuit 240, and signal processing circuit 230 can be arranged on a single substrate, distributed across multiple substrates and then stacked, or divided into multiple chips. The photoelectric conversion device PEC can be a CMOS image sensor. The photoelectric conversion device PEC can be a front-side illumination sensor or a rear-side illumination sensor.

[0092] Figure 10 It is shown Figure 9 The circuit diagram shows an example configuration of the readout circuit 220. Figure 10 The diagram illustrates a configuration of a readout circuit 220 connected to a vertical line 250. In addition to the aforementioned current source 222 and AD conversion circuit 223, the readout circuit 220 may also include a limiting circuit 221. The limiting circuit 221 includes a transistor 2211 connected to the vertical line 250 and limiting the voltage level according to a limiting voltage supplied to the gate. The transistor 2211 may be, for example, an NMOS transistor. Figure 10 In the illustrated configuration, vertical line 250 is connected to the source of transistor 2211, which serves as an NMOS transistor, current source 222, and AD conversion circuit 223. The drain of transistor 2211 is connected to, for example, a power supply voltage, and as described above, a limiting voltage is supplied from a voltage generation circuit (not shown) to its gate. Limiting circuit 221 is a circuit used to limit the voltage level (e.g., maximum voltage) of vertical line 250, the signal line from which the photoelectric converter, which serves as a pixel, outputs its signal. Limiting circuit 221 allows for variable control of the voltage to be limited by controlling the limiting voltage.

[0093] For example, in the correction value acquisition mode, the limiting voltage applied to the limiting circuit 221 is supplied to the gate of the transistor 2211 as a reference voltage for obtaining the correction value. Therefore, it is possible to obtain the correction value without using... Figure 1 The correction value is obtained in the case of the analog signal switching circuit 100 shown. Therefore, as Figure 11 As shown, the AD conversion circuit 1 may not include the analog signal switching circuit 100. In this case, the control signal C1 used to control the analog signal switching circuit 100 also becomes unnecessary. Therefore, the signal generation circuit of the control circuit 80 used to generate the control signal C1 and the analog signal switching circuit 100 can be omitted, thereby miniaturizing the AD conversion circuit 1.

[0094] like Figure 11 As shown, the vertical line 250, which serves as the signal line supplied with the analog signal output from the photoelectric converter of the pixel, is connected to the input terminal IN. In AD conversion mode, an analog signal is supplied from the photoelectric conversion element of the pixel, and in correction value acquisition mode, a limiting circuit 221 is used to supply a reference voltage to the vertical line 250. However, this configuration is not limited to this, and the vertical line 250, which serves as the signal line supplied with the analog signal output from the photoelectric converter of the pixel, and the signal line supplied with the reference signal can also be arranged separately. In this case, the analog signal switching circuit 100 connects the input terminal IN to the terminal T2 connected to the vertical line 250 in AD conversion mode, and connects the input terminal IN to the terminal T1 connected to the signal line supplied with the reference signal in correction value acquisition mode.

[0095] The following describes an example of a photoelectric conversion system using a photoelectric conversion device (PEC). Figure 12 This is a block diagram illustrating the configuration of a photoelectric conversion system 1200 according to an embodiment. The photoelectric conversion system 1200 according to this embodiment includes a photoelectric conversion device 1215. In this case, the aforementioned photoelectric conversion device PEC can be used as the photoelectric conversion device 1215. The photoelectric conversion system 1200 can be used, for example, as a camera system. Specific examples of camera systems are digital still cameras, digital video cameras, and surveillance cameras. Figure 12 An example of a digital still camera (video recording device) is shown as a photoelectric conversion system 1200.

[0096] Figure 12 The photoelectric conversion system 1200 shown includes a photoelectric conversion device 1215, a lens 1213 that forms an optical image of a subject on the photoelectric conversion device 1215, an aperture 1214 that changes the amount of light passing through the lens 1213, and a baffle 1212 that protects the lens 1213. The lens 1213 and the aperture 1214 form an optical system for concentrating light onto the photoelectric conversion device 1215. A photoelectric conversion system used for imaging is also referred to as an imaging system.

[0097] The photoelectric conversion system 1200 includes a signal processor 1216 for processing the output signal from the photoelectric conversion device 1215. The signal processor 1216 performs signal processing operations as needed to correct and compress the input signal, thereby outputting a result signal. The photoelectric conversion system 1200 also includes a buffer memory 1206 for temporarily storing image data and an external interface unit (external I / F) 1209 for communicating with an external computer or the like. Furthermore, the photoelectric conversion system 1200 includes a recording medium 1211, such as a semiconductor memory, for recording or reading image data, and a recording medium control interface (recording medium control I / F) 1210 for recording or reading from the recording medium 1211. The recording medium 1211 can be incorporated into the photoelectric conversion system 1200 or can be detachable. Additionally, wireless communication between the recording medium control I / F 1210 and the recording medium 1211, or communication from the external I / F 1209, is possible.

[0098] Furthermore, the photoelectric conversion system 1200 includes a general-purpose control / computation unit 1208 that performs various calculations and controls the entire digital still camera, and a timing generation unit 1217 that outputs various timing signals to the photoelectric conversion device 1215 and the signal processor 1216. Here, timing signals can be input from external sources, and the photoelectric conversion system 1200 only needs to include at least the photoelectric conversion device 1215 and the signal processor 1216 for processing the output signals from the photoelectric conversion device 1215. The timing generation unit 1217 can be incorporated into the photoelectric conversion device. The general-purpose control / computation unit 1208 and the timing generation unit 1217 can be configured to perform part or all of the control functions of the photoelectric conversion device 1215.

[0099] The photoelectric conversion device 1215 outputs an image signal to the signal processor 1216. The signal processor 1216 performs predetermined signal processing on the image signal output from the photoelectric conversion device 1215 and outputs image data. The signal processor 1216 also uses the image signal to generate an image. Furthermore, the signal processor 1216 can perform distance calculations on the signal output from the photoelectric conversion device 1215. Note that the signal processor 1216 and the timing generation unit 1217 can be incorporated into the photoelectric conversion device. That is, the signal processor 1216 and the timing generation unit 1217 can each be mounted on a substrate on which pixels are arranged, or they can be mounted on another substrate. A camera system capable of acquiring higher quality images can be realized by using a photoelectric conversion device including the aforementioned AD conversion circuit.

[0100] Reference Figure 13A and Figure 13B A photoelectric conversion system and a moving body according to another embodiment are described. Figure 13A and Figure 13B The figures illustrate configuration examples of the photoelectric conversion system or the moving body according to this embodiment. In this embodiment, an example depicting a vehicle-mounted camera is used as the photoelectric conversion system.

[0101] Figure 13A and Figure 13B An example of a vehicle system and an optoelectronic conversion system incorporated into the vehicle system for imaging is shown. The optoelectronic conversion system 1301 includes an optoelectronic conversion device 1302, an image preprocessor 1315, an integrated circuit 1303, and an optical system 1314. The optical system 1314 forms an optical image of a subject on the optoelectronic conversion device 1302. The optoelectronic conversion device 1302 converts the optical image of the subject formed by the optical system 1314 into an electrical signal. The optoelectronic conversion device 1302 can be any of the optoelectronic conversion devices described above. The image preprocessor 1315 performs predetermined signal processing on the signal output from the optoelectronic conversion device 1302. The functionality of the image preprocessor 1315 can be incorporated into the optoelectronic conversion device 1302. In the optoelectronic conversion system 1301, at least two sets of the optical system 1314, the optoelectronic conversion device 1302, and the image preprocessor 1315 are provided, and the outputs of the image preprocessors 1315 from each set are input to the integrated circuit 1303.

[0102] Integrated circuit 1303 is a dedicated integrated circuit for a camera system and includes an image processor 1304 with a memory 1305, an optical ranging unit 1306, a ranging calculation unit 1307, an object recognition unit 1308, and an anomaly detection unit 1309. The image processor 1304 performs image processing (such as image processing and defect correction) on the output signals from various image preprocessors 1315. The memory 1305 temporarily stores captured images and stores the locations of defects in the captured images. The optical ranging unit 1306 performs focusing or ranging of the subject. The ranging calculation unit 1307 calculates ranging information based on multiple image data acquired by multiple photoelectric conversion devices 1302. The object recognition unit 1308 identifies subjects such as vehicles, roads, road signs, and people. When an anomaly is detected in the photoelectric conversion device 1302, the anomaly detection unit 1309 notifies the main control unit 1313 of the anomaly.

[0103] Integrated circuit 1303 can be implemented by dedicated hardware, software modules, or a combination thereof. Alternatively, integrated circuit 1303 can be implemented by a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), or a combination thereof.

[0104] The main control unit 1313 comprehensively controls the operation of the photoelectric conversion system 1301, vehicle sensor 1310, and control unit 1320. Alternatively, without providing the main control unit 1313, the photoelectric conversion system 1301, vehicle sensor 1310, and control unit 1320 can each have their own communication interface and send / receive control signals via a communication network (e.g., the CAN standard).

[0105] Integrated circuit 1303 has the following functions: by receiving control signals from the main control unit 1313 or through its own control unit, it sends control signals or setting values ​​to each photoelectric conversion device 1302.

[0106] The photoelectric conversion system 1301 is connected to the vehicle sensor 1310 and can detect the vehicle's driving status (such as vehicle speed, yaw rate, and steering angle), the external environment of the vehicle, and the status of other vehicles and obstacles. The vehicle sensor 1310 also functions as a distance information acquisition unit to obtain distance information to objects. Furthermore, the photoelectric conversion system 1301 is connected to a driver support control unit 1311 that performs various driver support operations (such as automatic steering, adaptive cruise control, and collision avoidance functions). More specifically, regarding the collision detection function, based on the detection results from the photoelectric conversion system 1301 and the vehicle sensor 1310, a collision with other vehicles or obstacles is estimated, or the presence / absence of a collision is determined. This allows for control to avoid a collision when a collision is estimated, or activation of safety devices upon a collision.

[0107] Furthermore, the photoelectric conversion system 1301 is also connected to an alarm device 1312, which generates an alarm to the driver based on the judgment result of the collision judgment unit. For example, if the collision judgment unit indicates a high probability of collision, the main control unit 1313 performs vehicle control to avoid a collision or reduce damage by braking, releasing the accelerator pedal, or suppressing engine output. The alarm device 1312 emits alarms such as sounds, displays alarm information on a display unit such as a car navigation system or dashboard, and applies vibrations to the seat belt or steering wheel to alert the user.

[0108] According to this disclosure, techniques that are advantageous in improving the nonlinearity error of ΔΣ AD converters can be provided.

[0109] While this disclosure has been described with reference to embodiments, it should be understood that this disclosure is not limited to the disclosed embodiments. The scope of the appended claims should be given the broadest interpretation to cover all such modifications and equivalent structures and functions.

Claims

1. An analog-to-digital (ADC) conversion circuit configured to operate in multiple modes, including an ADC conversion mode and a correction value acquisition mode, wherein in the ADC conversion mode, a signal supplied to an input terminal is ADC converted, the ADC conversion circuit comprising: A ΔΣ AD converter, which includes an integrating circuit configured to integrate the difference signal; A holding circuit is configured to hold a signal corresponding to the voltage output from the integrating circuit; A switching circuit is configured to switch the signal to be supplied to the ΔΣ AD converter between a signal supplied to the input terminal and a signal held in the holding circuit. A digital demodulation circuit configured to generate a digital signal based on a ΔΣ modulation signal output from the ΔΣ AD converter; and A digital gain adjustment circuit is configured to adjust the gain of the signal output from the digital demodulation circuit. The AD conversion circuit further includes an acquisition circuit configured to, in the correction value acquisition mode, obtain a correction value based on the digital signal output from the digital demodulation circuit, according to a correction value acquisition reference signal supplied to the input terminal. In the AD conversion mode, the gain adjustment in the digital gain adjustment circuit is performed based on the correction value.

2. The AD conversion circuit according to claim 1, wherein, In the correction value acquisition mode, the switching circuit switches to supply the reference signal to the ΔΣ AD converter during a first time period, and to supply the ΔΣ AD converter with a voltage signal held in the holding circuit based on the voltage output from the integrating circuit at the end of the first time period during a second time period. The obtaining circuit obtains the correction value based on the digital signal generated by the digital demodulation circuit from the ΔΣ modulation signal output from the ΔΣ AD converter in the second time period.

3. The AD conversion circuit according to claim 1, wherein, In the correction value acquisition mode, multiple types of reference signals, including the reference signal, are supplied, and The obtaining circuit obtains the correction value based on multiple digital signals corresponding to multiple types of reference signals output from the digital demodulation circuit.

4. The AD conversion circuit according to claim 1, wherein, In the correction value acquisition mode, the acquisition circuit acquires the digital signal output from the digital demodulation circuit multiple times based on a reference signal of the same type, and acquires the correction value based on each digital signal among the multiple acquired digital signals.

5. The AD conversion circuit according to claim 1, wherein, In the AD conversion mode, the switching circuit switches to supply the signal supplied to the input terminal to the ΔΣ AD converter during a third time period, and supplies the ΔΣ AD converter with a voltage signal held in the holding circuit based on the voltage output from the integrating circuit at the end of the third time period during a fourth time period. The digital demodulation circuit generates a higher-order bit string digital signal based on the output from the ΔΣ AD converter in the third time period, and generates a lower-order bit string digital signal based on the output from the ΔΣ AD converter in the fourth time period. The digital gain adjustment circuit adjusts the gain of the digital signal of the low-order bit string based on the correction value.

6. The AD conversion circuit according to claim 1, wherein, The ΔΣ AD converter further includes: a comparator configured to compare the output from the integrator circuit with a reference signal; and a DA converter configured to convert the output from the comparator into an analog signal and supply the analog signal to the integrator circuit.

7. The AD conversion circuit according to claim 6, wherein, The digital demodulation circuit is connected to the output of the comparator.

8. The AD conversion circuit according to claim 6, wherein, The integrator circuit includes a first integrator and a second integrator connected to the output of the first integrator.

9. The AD conversion circuit according to claim 8, wherein, The comparator compares the output from the second integrator with the reference signal.

10. The AD conversion circuit according to claim 8, wherein, The comparator compares the signal input to the integrator circuit, the output from the first integrator, and the output from the second integrator with the reference signal.

11. The AD conversion circuit according to claim 8, wherein, The first integrator and the second integrator each include a continuous-time integrator.

12. The AD conversion circuit according to claim 8, wherein, The first integrator includes a continuous-time integrator, and The second integrator includes a discrete-time integrator.

13. The AD conversion circuit of claim 1, further comprising another switching circuit different from the switching circuit, the other switching circuit comprising a first terminal from which an analog signal is supplied from the photoelectric converter of the photoelectric conversion device, and a second terminal from which the reference signal is supplied, and configured to connect the first terminal to the input terminal in the AD conversion mode and to connect the second terminal to the input terminal in the correction value acquisition mode.

14. A photoelectric conversion device, comprising: Photoelectric converter; as well as An AD conversion circuit, which is an AD conversion circuit according to any one of claims 1 to 13, and is configured to convert the analog signal output from the photoelectric converter into a digital signal.

15. A photoelectric conversion device, comprising: Photoelectric converter; as well as An AD conversion circuit, which is an AD conversion circuit according to any one of claims 1 to 12, and is configured to convert an analog signal output from the photoelectric converter into a digital signal. The photoelectric conversion device further includes: The first signal line is supplied with the analog signal output from the photoelectric converter; A second signal line, wherein the reference signal is supplied to the second signal line; and Another switching circuit, unlike the aforementioned switching circuit, is configured to connect the first signal line and the input terminal in the AD conversion mode, and to connect the second signal line and the input terminal in the correction value acquisition mode.

16. A photoelectric conversion device, comprising: Photoelectric converter; as well as An AD conversion circuit, which is an AD conversion circuit according to any one of claims 1 to 12, and is configured to convert an analog signal output from the photoelectric converter into a digital signal. The photoelectric conversion device further includes a signal line connected to the input terminal, and an analog signal output from the photoelectric converter is supplied to the signal line. In the correction value acquisition mode, the reference signal is supplied to the signal line.

17. The photoelectric conversion device according to claim 16, further comprising a limiting circuit configured to limit the voltage level of the signal line. in, The limiting circuit includes a transistor connected to the signal line and configured to limit the voltage level according to a limiting voltage supplied to the gate. The reference signal is set via the limiting voltage.

18. A camera device, comprising: The photoelectric conversion device according to claim 14; as well as A signal processor configured to process signals output from the photoelectric conversion device.

19. A mobile body, characterized in that... Includes the camera device according to claim 18.

Images