Controllable time synchronization multi-interface wireless edge gateway and clustering multi-hop networking method

Abstract

The application discloses a controllable time synchronization multi-interface wireless edge gateway and a clustering multi-hop networking method, and belongs to the technical field of wireless communication and edge gateway, wherein the gateway adopts a layered hardware architecture of wired access-protocol conversion-wireless forwarding, and is composed of an integrated connector, an interface unit, a logic control and protocol conversion unit, a level conversion unit and a star flash wireless communication unit from the signal flow direction, and is simultaneously provided with a hierarchical power supply unit and an electromagnetic compatibility protection circuit, so that bidirectional transparent data transmission of a star RS422 serial bus, an Ethernet wired bus and a star flash wireless network can be realized. The networking method adopts a star clustering multi-hop topology, relies on a star flash native synchronization mechanism to realize network time synchronization better than 1 millisecond, and realizes logical full-duplex communication between nodes through centralized time slot scheduling. The application is suitable for cabin wireless communication and wired bus interconnection scenes.

Description

Technical Field

[0001] This invention belongs to the field of wireless communication and edge gateway technology, specifically relating to a multi-interface wireless edge gateway with controllable time synchronization, and having the ability to configure time synchronization parameters, schedule wireless links, and forward data across communication domains. Background Technology

[0002] In densely populated scenarios such as cabin communication, different electronic devices typically need to exchange data via various wired interfaces such as RS422 serial bus and Ethernet bus. As the number of devices and the types of business data increase, using numerous point-to-point wired connections easily increases the number of cables, interface conversion devices, and system integration and maintenance complexity. To reduce the scale of wired connections, wireless communication is increasingly being used for data transmission between devices, but corresponding interface conversion and data forwarding devices still need to be set up between the existing wired bus and wireless network.

[0003] Existing interface conversion devices are typically designed for a single wired interface or a single data format. When spatial data packets carried by an RS422 interface and UDP-encapsulated data carried by an Ethernet interface are simultaneously accessed on a wireless network, separate interface processing and protocol conversion stages are often required. It is difficult to uniformly complete multi-interface access, data frame parsing, protocol conversion, routing processing, and wireless forwarding within a single device. Data interaction between multiple independent devices may also increase processing stages and forwarding latency, which is detrimental to system miniaturization and centralized management.

[0004] For clustered multi-hop networks composed of multiple wireless communication domains, data relay between different domains is also required. If wireless transmission and reception, cross-domain forwarding, and time synchronization are handled by different devices or processing stages, it is difficult to coordinate the data transmission, reception, and upper-layer delivery times of each node. Especially when periodic, time-sensitive services coexist with reliable transmission services, fixed transmission and retransmission methods cannot simultaneously meet the requirements of data timing consistency and transmission reliability, and time errors may accumulate during multi-hop forwarding.

[0005] Therefore, a wireless edge gateway is needed that can uniformly access multiple wired interfaces such as RS422 and Ethernet, complete data parsing, protocol conversion and routing forwarding on the gateway side, and configure the time synchronization anchor point, scheduling time slot, transmission period and link type of the wireless link, so as to realize the wireless transmission of multi-interface service data, cross-communication domain forwarding and coordinated control of multi-node data output timing. Summary of the Invention

[0006] This invention provides a controllable time synchronization multi-interface wireless edge gateway and a clustered multi-hop networking method based on the StarFlash protocol. Its purpose is to solve the problems of existing multi-interface wired-to-wireless devices being scattered and independent in dense cabin equipment scenarios, having poor cross-domain forwarding and timing coordination across multiple communication domains, making it difficult to simultaneously meet high timeliness and reliable transmission, and being unfavorable for system miniaturization and centralized management.

[0007] Firstly, the purpose of this invention is to provide a controllable time-synchronized multi-interface wireless edge gateway, including a logic control and protocol conversion unit, an interface unit, a star-flash wireless communication unit, and a power supply unit.

[0008] The interface unit includes an RS422 interface circuit and an Ethernet interface circuit, forming a multi-interface wired access terminal of the gateway, used to connect to the external RS422 serial bus and Ethernet bus to realize bidirectional conversion between external wired signals and internal logic levels; the interface unit is bidirectionally connected to the logic control and protocol conversion unit; the RS422 serial bus carries service data in spatial data packet format, and the Ethernet bus carries spatial data packet service data encapsulated by the UDP protocol;

[0009] The logic control and protocol conversion unit adopts a ZYNQ on-chip computing unit to complete service data parsing, protocol conversion, routing processing, wireless forwarding control, and time synchronization and time slot scheduling parameter configuration on the gateway side. It integrates a processor (PS) and a programmable logic unit (PL). The PL handles bidirectional conversion between spatial data packets carried by the RS422 interface and UART serial data supported by the StarSpark wireless module. The PS runs a lightweight TCP / IP protocol stack to encapsulate and decapsulate Ethernet UDP / IP packets and interacts with the PL via the AXI bus. The PS also manages overall system resources.

[0010] The Star Flash wireless communication unit is used to establish wireless transceiver links and cross-communication domain forwarding links, including at least two independent Star Flash wireless modules. Each Star Flash wireless module is bidirectionally connected to the logic control and protocol conversion unit, wherein at least one Star Flash wireless module is configured as a data transmission link and at least one Star Flash wireless module is configured as a data reception link.

[0011] The power supply unit is connected to an external DC power supply and generates multiple working voltages of different levels through multi-stage voltage conversion, which power the logic control and protocol conversion unit, the interface unit, and the starlight wireless communication unit respectively.

[0012] Furthermore, a preferred solution is provided: the processing of Ethernet higher-layer protocols includes Ethernet packet encapsulation and parsing, and the overall system resource control includes interface parameter configuration and wireless module configuration.

[0013] Furthermore, a preferred embodiment is provided: the StarSpark wireless communication unit includes four StarSpark wireless modules, which are divided into two independent transceiver link pairs, each corresponding to a different StarSpark communication domain; the logic control and protocol conversion unit performs transparent forwarding of the data transmitted between the two transceiver link pairs, thus forming a cross-cluster bridging node hardware architecture.

[0014] Furthermore, a preferred embodiment is provided: the RS422 interface circuit includes a differential transceiver chip, a terminal impedance matching network, and a surge protection circuit.

[0015] Furthermore, a preferred embodiment is provided: the Ethernet interface circuit includes a PHY chip and a voltage-type PHY port transformer in sequence, and the PHY chip is connected to the logic control and protocol conversion unit through the GMII interface.

[0016] Furthermore, a preferred embodiment is provided: the power supply unit includes a first-stage step-down module and a second-stage step-down module; the first-stage step-down module is used to convert the externally input 12V DC voltage into a 5V DC voltage; the second-stage step-down module is used to convert the 5V DC voltage into 3.3V and 1.8V DC voltages respectively, providing power to each unit in stages.

[0017] Furthermore, a preferred solution is provided: the programmable logic (PL) terminal of the logic control and protocol conversion unit is designed with a hardware state machine for space data packet processing and RS422 serial protocol conversion logic, which is used to complete frame identification, parsing and routing processing of space data packets from the RS422 interface, and convert them into serial data format adapted to the StarSpark module; at the same time, the serial data stream from the StarSpark module is reframed into space data packets and then output to the RS422 interface.

[0018] Furthermore, a preferred embodiment is provided: the processor PS of the logic control and protocol conversion unit runs a lightweight TCP / IP protocol stack and performs encapsulation and decapsulation of Ethernet UDP data; the programmable logic PL is interconnected with the processor PS via an AXI bus.

[0019] Furthermore, a preferred embodiment is provided: the system further includes an electromagnetic compatibility protection unit, which is equipped with multi-level filtering and surge suppression devices at the power input port, common-mode suppression and surge protection devices at the differential transceiver chip, and decoupling and transient protection devices at the radio frequency link.

[0020] Furthermore, a preferred solution is provided: the system also includes a connector that integrates RS422 differential signal pins, Ethernet differential signal pins, star flash module pins and power pins, realizing integrated signal and power supply connections for the node to the outside world.

[0021] Compared with the prior art, the advantages of the present invention are:

[0022] (1) By setting up RS422 interface circuit and Ethernet interface circuit, and using the ZYNQ on-chip computing unit to parse, encapsulate and convert spatial data packets and UDP / IP messages, the present invention can realize bidirectional data transmission between multiple wired interfaces and wireless networks within the same gateway, reduce the number of independent interface conversion devices and connecting cables, and improve system integration.

[0023] (2) By configuring multiple independent Star Flash wireless modules, the present invention can establish wireless transmission links and wireless reception links respectively, and through two sets of independent transmission and reception links, it can achieve transparent forwarding of cross-cluster and cross-domain service data, thereby improving the flexibility of wireless network networking and expansion.

[0024] (3) The present invention is based on the time and frequency synchronization mechanism of the Star Flash SLE protocol. By configuring the system scheduling time slot, event group time synchronization anchor point, transmission period and data link type, and using cross-cluster bridging nodes to realize clock alignment between adjacent communication domains, the wireless transmission timing can be controlled according to the service timeliness and reliability requirements, thereby improving the timing consistency of multi-node data transmission and upper layer delivery.

[0025] This invention is applicable to scenarios involving in-cabin wireless communication and wired bus interconnection. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0027] Figure 1 This is a block diagram of the overall architecture of the controllable time synchronization multi-interface wireless edge gateway described in Implementation Method 1.

[0028] Figure 2 This is a schematic diagram of the pin assignment of the HJ30J-100ZKW2P7 connector described in Embodiment 1.

[0029] Figure 3 This is a schematic diagram of the RS422 interface circuit in this invention;

[0030] Figure 4 The circuit diagram of the HX5120NLT network port transformer described in Embodiment 1;

[0031] Figure 5 The circuit diagram of the RTL8211F-CG PHY chip described in Embodiment 1 is shown below.

[0032] Figure 6 The RS422 differential interface circuit described in Implementation Method 1;

[0033] Figure 7 The ZYNQ core control circuit described in Implementation Method 1;

[0034] Figure 8 The Ethernet PHY physical layer interface circuit described in Implementation Method 1;

[0035] Figure 9 This is a simplified schematic diagram of the architecture of the ZYNQ logic control and protocol conversion unit in this invention;

[0036] Figure 10 The interface circuit diagram of the StarSpark Module 255BE-63 described in Embodiment 1;

[0037] Figure 11 This is a schematic diagram of the hierarchical power supply architecture of the power supply unit in this invention;

[0038] Figure 12 This is the circuit diagram for the 12V to 5V voltage conversion described in Implementation Method 1;

[0039] Figure 13 The circuit described in Implementation Method 1 is a 5V to 3.3V and 1.8V converter.

[0040] Figure 14 This is a schematic diagram illustrating the pairing relationship between the bridging node and the management nodes on both sides.

[0041] Figure 15 This is a schematic diagram of the star-shaped clustered multi-hop communication topology described in this invention;

[0042] Figure 16 This is a test data diagram showing the maximum number of networks per node of the StarSpark module described in Implementation Method 3. Detailed Implementation

[0043] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application can also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods are omitted so as not to obscure the description of this application with unnecessary detail.

[0044] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0045] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0046] Implementation Method 1

[0047] This embodiment provides a multi-interface wireless edge gateway with controllable time synchronization based on the StarFlash protocol, such as... Figure 1 As shown, the controllable time synchronization multi-interface wireless edge gateway based on the StarSpark protocol provided in this embodiment adopts a layered hardware architecture of wired access—protocol conversion—wireless forwarding. The gateway consists of an integrated connector, an interface unit, a logic control and protocol conversion unit, a level conversion unit, and a StarSpark wireless communication unit in sequence from the signal flow direction. It is also equipped with a hierarchical power supply unit and an electromagnetic compatibility protection circuit, which can realize bidirectional transparent data transmission between the onboard RS422 serial bus, the Ethernet wired bus, and the StarSpark wireless network, and supports cross-cluster bridging networking of dual StarSpark communication domains.

[0048] The integrated connector will be further described below:

[0049] The integrated connector is primarily responsible for receiving and transmitting RS422 and LAN signals, as well as connecting to an external power source. This embodiment uses an HJ30J-100ZKW2P7 connector for connecting RS422, Ethernet, and other signals. Figure 2 As shown, it mainly includes 4 RS422 differential signal pairs, 4 Gigabit Ethernet differential pairs, and other onboard bus signals, such as 4-channel StarScan module UART. In addition, this connector is also responsible for connecting to an external +12V power supply.

[0050] The interface unit will be further described below:

[0051] The interface unit is directly connected to the integrated connector and includes an RS422 interface circuit and an Ethernet interface circuit, used to interface with the external wired bus on the satellite and complete the bidirectional conversion between external bus signals and internal logic levels.

[0052] The RS422 interface circuit supports multiple RS422 signals, each of which includes a differential transceiver chip, a terminal impedance matching network, and an interface protection device. It interfaces with the onboard RS422 serial bus, carries standard format space data packet service data, converts external differential signals into single-ended logic levels and sends them to the logic control and protocol conversion unit, and simultaneously converts internal logic signals into RS422 differential signals for output.

[0053] This implementation uses the MAX3490EESA chip as the control chip for transmitting and receiving RS422 protocol signals, realizing the conversion between differential signals and TTL signals, and thus realizing the transmission and reception of RS422 protocol signals and full-duplex communication. Its pin distribution is shown in Table 1.

[0054] Table 1 Pinout of MAX3490EESA Chip

[0055]

[0056] This implementation design incorporates four RS422 signals, with the interface circuit design as follows: Figure 3 As shown. For the power supply section, the MAX3490EESAA chip uses a 3.3V power supply. Its VCCA pin is connected to the VCC_3V3 power supply, and a 0.1μF ceramic capacitor C32 is connected in parallel to filter out high-frequency power ripple and ensure stable power supply. The GNDY pin is directly grounded, forming a complete power supply loop. For the signal side, the RS422_CH4_R33R and RS422_CH4_T33R signals on the ZYNQ side are connected to the RO and DI pins of the chip through current-limiting resistors R86 and R87, respectively, to realize data reception and transmission. The chip's output pins B, Z, and Y lead out RS422_CH4_A, RS422_CH4_B / Z, and RS422_CH4_Y differential signals, respectively, and 120Ω terminating resistors R43 and R44 are connected in parallel between the AY lines to achieve bus impedance matching and reduce signal reflection. Each differential signal on the bus is protected against ESD by a PSM712 bidirectional transient suppression diode to suppress electrostatic discharge and surge voltage, and protect the interface circuit from overvoltage damage.

[0057] The Ethernet interface circuit consists of a voltage-type PHY transformer and a PHY chip. The PHY chip is connected to the logic control and protocol conversion unit via a GMII interface, interfacing with the onboard Ethernet bus to carry space data packets encapsulated using the UDP protocol. In this embodiment, the PHY chip is an RTL8211F-CG PHY chip, the voltage-type PHY transformer is an HX5120NLT, and the Ethernet interface uses an HJ30J-100ZKW2P7 high-speed connector.

[0058] The logic control and protocol conversion unit will be further explained below:

[0059] In this embodiment, the logic control and protocol conversion unit uses a ZYNQ series on-chip computing unit (SoC) to simulate the computing unit, realizing the protocol conversion between wired communication protocols such as RS422 and Ethernet and the communication interface protocols supported by the StarScan module. The overall circuit is as follows: Figures 6-8 As shown. The core of the circuit is the ZYNQ-7020 core board, which integrates an ARM Cortex-A9 dual-core processor and an FPGA logic unit. These are responsible for high-level protocol and application logic, as well as low-level interface control and protocol conversion, respectively, making them key components for logic control and protocol conversion. ZYNQ organically combines the processor and FPGA. The flexibly programmable FPGA allows for the customization of peripherals and accelerators with different functions, providing a feasible solution for deploying anomaly detection methods. A simplified model of the ZYNQ internal architecture is shown below. Figure 9 As shown in the diagram, the circuit comprises two main parts: a processing system consisting of a dual-core ARM processor and various processor peripherals (the PS side) and a programmable logic section (PL side). These two parts are interconnected via an AXI bus. The core function of the circuit is to achieve bidirectional conversion between serial and Ethernet protocols and the communication interface protocols supported by the StarScan module, which is accomplished collaboratively by the PL and PS. The PL section is responsible for low-level protocol parsing and conversion. The current focus is on converting RS422 spatial data packets and Ethernet data to UART serial data. The PS section is responsible for handling higher-level Ethernet protocols and overall system resource management. The handling of higher-level Ethernet protocols includes Ethernet packet encapsulation and parsing, and the overall system resource management includes interface parameter configuration and wireless module configuration. For example, in the data transmission path: the PS encapsulates application layer data into UDP / IP packets using a lightweight TCP / IP protocol stack and sends them through the Ethernet interface; in the reception path: the PS receives UDP / IP packets through the Ethernet interface, decapsulates them using LwIP, and obtains the application layer data.

[0060] The control circuit primarily ensures its intended function through power supply and pin assignment design. For the power supply design, the ZYNQ-7020's VCC pin is connected to a 5V power supply, with a parallel decoupling capacitor filtering out power ripple to ensure stable chip operation; the GND pin is directly grounded, forming a complete circuit. For the pin assignment design, the ZYNQ's GPIO pins are connected to external interface circuits for transmitting control signals and data; the high-speed interface connects to the PHY chip within the ZYNQ via dedicated pins for data transmission and reception.

[0061] Furthermore, the circuit enables inter-device communication via multiple types of serial and Ethernet interfaces, with protocol conversion implemented through the ZYNQ-7020's FPGA logic for each interface. For the RS422 serial interface, the RS422 transmitter and receiver are connected to the ZYNQ's FPGA via GPIO pins; an external RS422 transceiver converts TTL / CMOS levels to RS422 differential signals. The Ethernet differential signals are connected to the ZYNQ's GMII interface (i.e., Gigabit Media Independent Interface) via dedicated pins, and the RTL8211F-CG Ethernet PHY chip converts the differential signals to digital signals, enabling Ethernet physical layer connections.

[0062] In this embodiment, pins B33_L2_P_T22, B13_L19_P_R6, B13_L20_N_U4, and B13_L10_N_Y10 are used as input ports for RS422 protocol signals, and pins B33_L2_N_U22, B13_L19_N_T6, B13_L20_P_T4, and B13_L10_P_Y11 are used to output RS422 protocol signals to the interface circuit. Additionally, the VCC_5V pin is used as the chip's power supply signal. Pins B34_L16_P, B34_L16_N, B34_L13_P, B34_L13_N, B33_L6_N, B33_L6_P, B33_L8_P, and B33_L8_N are used as the input and output ports for the StarSpark protocol signals, enabling signal interaction with the 255BE-63 StarSpark module. Later, after StarSpark opens its SPI interface, higher-speed SPI communication can be established with the StarSpark module, replacing the currently used UART communication.

[0063] The level conversion unit will be further explained below:

[0064] The level conversion unit is located between the logic control and protocol conversion unit and the StarSpark wireless communication unit. It uses a resistor voltage divider circuit or a dedicated level conversion chip to achieve logic level matching and complete the bidirectional conversion between the working levels of the ZYNQ chip and the StarSpark module.

[0065] The following is a further explanation of the aforementioned star-flash wireless communication unit:

[0066] To support the multi-domain star topology of the wireless communication network composed of wireless communication nodes and enable cross-cluster and cross-domain data forwarding, this implementation adopts a four-module hardware architecture at the bridging node hardware level. It configures four independent StarSpark wireless modules, divided into two independent transceiver link pairs. That is, two pairs of StarSpark wireless modules are integrated within the same node, and the two transceiver link pairs correspond to two different StarSpark communication domains. ZYNQ serves as the core processing platform, enabling unified management and data relay of the wireless links on both sides. The pairing relationship is as follows: Figure 14 As shown. Each transceiver link pair includes one data sending module and one data receiving module. Both StarScan modules within the same group are configured as slaves, and they are paired with the corresponding management node (configured as master) in the StarScan communication domain. Data routing is determined by the management node's transmission. The left management node sends data to the bridging node, and the bridging node can only send data to the right management node for reception. The same applies to the data stream on the other side.

[0067] This implementation uses the 255BE-63 StarScan wireless communication module. This module can both extend the wireless network access capability of the master control device and also serve as a standalone dedicated network controller. Its operating modes support independent operation or external slave device connection. The module has comprehensive peripheral resources, integrating on-chip SRAM cache and Flash program storage, enabling independent firmware operation. The circuit is as follows... Figure 10 As shown. The VCC_3V3 external power supply is directly connected to the module's 3V3 power supply pin, providing the module's main power supply voltage. Multiple GND pins on the module are uniformly connected to the system GND, ensuring the stability of the power circuit and signal reference ground. The RESET pin is controlled by the main controller M3; a low level completes the module's hardware reset. DBG_UART_RX and DBG_UART_TX serve as debug serial ports, connecting to the main controller's debug port for firmware logging and program debugging downloads. The UART1_TX and UART1_RX pins connect to the main controller M3's serial port, serving as a data interaction channel between the module and the main controller, enabling AT command transmission and reception and business data transmission. The module reserves multiple GPIO pins, with some pins designed as floating reserves, allowing for expansion with buttons, indicator lights, peripheral acquisition, and other extended functions as needed. The module integrates Wi-Fi 6, BLE, and SLE star-flash communication units based on the built-in WS63 chip. It can be powered on and operated independently with the external 3.3V power supply circuit. It can achieve interconnection with the main controller through the serial port and quickly realize functions such as wireless networking and star-flash near-field communication.

[0068] The following is a further explanation of the hierarchical power supply unit:

[0069] The tiered power supply unit includes a first-stage step-down module and a second-stage step-down module, employing a two-stage step-down tiered power supply to ensure stable power supply to each module. Specific voltage distribution is as follows: Figure 11 As shown.

[0070] The first-stage step-down module is used to convert the externally input 12V DC voltage into 5V DC voltage through a DC-DC power supply circuit;

[0071] The second-stage step-down module is used to convert the 5V DC voltage into 3.3V and 1.8V DC voltages respectively.

[0072] Furthermore, this embodiment uses an LM2596HVS-5.0 DC / DC module power supply to convert 12V to 5V, and its circuit diagram is as follows. Figure 12 As shown. The VCC_12V external power supply is directly connected to the chip's Vin pin, providing the main input voltage; the GND pin is connected to the system common ground; the TAB pin is the chip's heat dissipation pin, which is left floating in this design and can be connected to the PCB ground plane as needed to optimize heat dissipation; the ON# / OFF pin is directly grounded, enabling the chip at a low level, and it is always in working state after power-on, requiring no external start / stop control. A C39 (680μF) electrolytic capacitor is connected in parallel at the input terminal to filter out input power noise and suppress power spike disturbances. The LM2596HVS-5.0 is a fixed 5V output model. The chip's Feedback pin is directly shorted to the 5V output terminal, relying on the chip's internal integrated voltage divider network to complete the output closed-loop regulation, eliminating the need for external voltage divider resistors. The chip's Output pin is connected to an external 1N5824 Schottky freewheeling diode and an FXL0630-330-M power inductor to form a freewheeling circuit. The diode provides a freewheeling path for the inductor when the internal switching transistor is turned off, reducing conduction losses. Finally, the circuit is designed with a filter. The power inductor and the C40 (220μF) electrolytic capacitor at the output end together form an LC filter network. The inductor stores the switching cycle energy and smooths the output pulsating current, while the output electrolytic capacitor filters out low-frequency output ripple and finally outputs a stable VCC_5V power supply.

[0073] Furthermore, this embodiment uses the MP2143 chip for voltage conversion from 5V to 3.3V and 1.8V, and its circuit diagram is as follows. Figure 13 As shown.

[0074] In the 5V to 1.8V circuit, the VCC_5V external power supply is directly connected to the chip's VIN pin to provide the main input voltage; PGND and AGND are the power ground and analog ground, respectively, and the two pins are grounded nearby to distinguish the power loop and the signal loop, reducing the interference of switching noise on the feedback signal. The EN pin is pulled up to the input 5V via R59 (4.7K), and the chip remains enabled after power-on without requiring an external control signal; the PG pin is pulled up to VCC_5V via R55 (4.7K) as a power-ready indicator pin. The MP2143DJ-LF-Z sets the output voltage through the feedback voltage divider network of the FB pin. R57 (10KΩ) and R61 (20KΩ) form a voltage divider circuit: one end of R57 is connected to the VCC_1V8 output, and the other end is connected to the FB pin; one end of R61 is connected to the FB pin, and the other end is grounded.

[0075] Finally, a filtering design was implemented for the circuit. The chip's SW pin is connected to a power inductor, which stores energy and smooths the output current. The inductor and the output capacitor together form an LC filter network. Multiple capacitors (C44, C45, C46) are connected in parallel at the VCC_1V8 output. Larger capacitors filter low-frequency ripple, while smaller ceramic capacitors filter high-frequency ripple. Input capacitor C4 is connected in parallel to the VIN pin to suppress input voltage disturbances and stabilize the chip's power supply.

[0076] The electromagnetic compatibility protection circuit described below will be further explained:

[0077] This implementation uses an external 12V DC power supply at the power interface and arranges multi-stage filtering and surge suppression devices at the input end. External electromagnetic interference and surge impact are suppressed by components such as common-mode inductors, varistors and transient voltage suppression diodes. At the same time, the coupling of power supply noise to sensitive circuits is reduced by partitioned power supply, single-point grounding and ground plane integrity design within the board.

[0078] The RS422 interface conforms to the TIA / EIA-422 standard specification. It uses a differential driver chip, along with terminating resistors, surge protection devices, and common-mode chokes to form the interface circuit, which improves the ability to resist common-mode interference while ensuring signal integrity.

[0079] The Ethernet interface uses an RGMII interface between the MAC and PHY. Signal isolation and common-mode noise suppression are achieved between the PHY and the HJ30J-100ZKW2P7 high-speed connector through an isolation network transformer and a common-mode inductor. Shielded twisted-pair cables are used for external connection lines to ensure that the radiated emissions and sensitivity of the link to external radio frequency fields meet the limit requirements of GJB151B RE102 and RS103.

[0080] In the radio frequency section, decoupling capacitors and transient protection devices are added to the power supply end of the star flash module. Crosstalk between the antenna and digital circuits is reduced through reasonable wiring and grounding design near the radio frequency traces and antenna.

[0081] Based on the above scheme, the workflow of the multi-interface wireless edge gateway with controllable time synchronization based on the StarFlash protocol described in this embodiment is as follows:

[0082] (1) Wired-to-Wireless Transmission Process: The host computer transmits data to the ZYNQ computing platform via connectors and interface circuits. The designed ZYNQ program performs the communication protocol conversion between the typical onboard wired communication protocol RS422 and Ethernet data. Specifically, it controls the transmission and reception of RS422 and Ethernet data, and converts the data to the communication protocols supported by the StarSpark module. Specifically, the ZYNQ implements the transmission and reception control of RS422 space data packet protocol data and Ethernet protocol data. Furthermore, the ZYNQ converts received RS422 space data packet frames or Ethernet data packets into a data stream conforming to the StarSpark module's wireless communication protocol and sends it to the StarSpark communication module. The StarSpark communication module then converts the data stream into a signal for wireless transmission to the target wireless terminal. Conversely, data received from the StarSpark module is converted into RS422 or Ethernet data and sent to the host computer.

[0083] Implementation Method 2

[0084] This embodiment provides a clustered multi-hop networking method based on the StarSpark protocol, applied to the controllable time synchronization multi-interface wireless edge gateway based on the StarSpark protocol described in Embodiment 1, such as... Figure 15 As shown, the gateway comprises three types of functional nodes: cluster management nodes (G nodes), terminal nodes (T nodes), and cross-cluster bridging nodes. All nodes adopt a hardware architecture of ZYNQ on-chip computing units + multi-channel satellite flash wireless modules. The cluster management nodes and terminal nodes are configured with at least two independent satellite flash modules (each responsible for the transmit and receive links), while the cross-cluster bridging nodes are configured with four independent satellite flash modules (forming two sets of transmit / receive link pairs, respectively connecting to two adjacent clusters). The method includes:

[0085] S1. Construction of star-shaped clustered multi-hop communication topology:

[0086] This implementation constructs a wireless network comprising 12 independent clusters, each cluster corresponding to an independent StarSignal communication domain. Network domains can be divided according to onboard mission subsystems, with different physical channels configured for different communication domains to reduce interference between them. Each cluster employs a star topology: one cluster management node is configured as the cluster's central node, and four terminal nodes are configured as the cluster's slave nodes. Adjacent clusters are connected via one cross-cluster bridging node, with a total of 11 bridging nodes configured, forming a scalable star-shaped multi-hop communication topology.

[0087] Hardware configuration rules:

[0088] Cluster management node: Both of the two star-flash modules are configured as management nodes, with one module serving as the transmitting link and the other as the receiving link;

[0089] Terminal Nodes: Both of the two StarScan modules are configured as terminal nodes, with one module serving as the receiving link and the other as the transmitting link, corresponding one-to-one with the transmitting and receiving links of the management node;

[0090] Bridging Nodes: All four StarSpark modules are configured as terminal nodes, divided into two transceiver pairs. The first pair connects to the management node of the left cluster, and the second pair connects to the management node of the right cluster. Transparent data forwarding is achieved between the two pairs of links through the ZYNQ programmable logic (PL) terminal.

[0091] This natively supported multi-domain architecture not only simplifies the software logic of bridging nodes but also avoids the complex interference problems associated with traditional full-duplex relays. When nodes join the network, a combination of non-contention-based access and centralized scheduling is used, avoiding link conflicts caused by a large number of nodes competing for distributed resources, thus greatly improving networking efficiency and gateway throughput.

[0092] S2, Communication Network Management:

[0093] S21: During the initialization phase, the management node sends a StarBlink broadcast frame within the corresponding communication domain to initiate network access. Terminal nodes receive the broadcast frame for the corresponding channel and report their own node capability information to the management node. The management node assigns a unique node address within the cluster to each terminal node, completing intra-cluster networking. Data interaction between all terminal nodes within the cluster is intelligently scheduled and transparently forwarded by the management node, without software intervention in the underlying addressing. During data forwarding, the ZYNQ's PL terminal parses the destination address field of the spatial data packet, matches it against the intra-cluster node address table, and completes data forwarding through the corresponding StarBlink module. The PS terminal is responsible for network management functions such as node status monitoring and parameter configuration.

[0094] S21: Cross-cluster data transmission:

[0095] Cross-cluster data transmission employs a path label forwarding mechanism, specifically:

[0096] At the application layer, the ZYNQ PS end reads the destination ID and address fields of the spatial data packet, adds a path label to the header of the data packet, and the path label includes: the path cluster, the destination cluster, and the destination node, which are used to determine the transmission direction and complete the routed fixed-point transmission.

[0097] At the network layer, the processor inside the StarSpark chip performs table lookups and forwards data based on the path labels carried in the header of the service data packets. After cross-cluster data arrives at the T-node side of the bridging node, it is transparently transmitted by the internal software queue to the G-node side interface of the bridging node, and then sent to the next-hop target cluster according to the coordinated orthogonal time slots. Since the isolation and scheduling at the physical layer are all guaranteed by the StarSpark native protocol stack, the implementation of cross-cluster routing software is greatly simplified, requiring only the management of service queues and the mapping of next-hop IDs.

[0098] S3, synchronized time across the entire network:

[0099] The network-wide time synchronization is achieved based on the time-frequency synchronization mechanism of the StarSignal SLE protocol, which is divided into physical layer time-frequency initial synchronization and data link layer collaborative time scheduling synchronization, ultimately achieving a network-wide synchronization accuracy of better than 1ms.

[0100] S31, Physical Layer Time-Frequency Synchronization:

[0101] A fixed-duration system time slot of 125μs is defined as the time granularity for the initial transmission of data in connectionless links. A system scheduling time slot with a basic granularity of 25μs is defined as the scheduling time reference for connected links. This allows the initial transmission time of the synchronous data link to be flexibly configured from 25μs to 125μs according to service characteristics, thus providing a highly granular scheduling reference for time synchronization during high-concurrency access by multiple devices. At the frame structure level, this method adopts a composite wireless frame structure consisting of a physical layer frame header and a physical layer data portion. The frame header consists of a preamble signal, a synchronization signal, and physical layer control information. The four defined wireless frame types provide preamble lengths from 10μs to 16μs and synchronization sequence configurations from 32 bits to a maximum of 126 bits, respectively. The system can achieve time and frequency synchronization initialization with different precisions according to the selected frame type and synchronization sequence length. The StarSpark SLE access layer explicitly lists "frequency and time synchronization" as one of the basic transmission services provided by the physical layer to the data link layer, ensuring that the transmitting and receiving parties can complete high-quality time and frequency alignment at the beginning of communication.

[0102] Meanwhile, the physical layer synchronization of StarSpark SLE further enhances stability through broadcast frame arrangement and frequency hopping mechanism: the transmission of basic broadcast frames and extended broadcast frames is strictly arranged according to the preset time interval (minimum offset of 300 microseconds) and time window, providing a clear time domain synchronization reference for node discovery and access process; in the frequency domain, frequency hopping communication is realized through predefined broadcast channels and frequency hopping sequences, effectively resisting interference from complex electromagnetic environment within the satellite and ensuring the reliability of synchronous broadcast.

[0103] S32, Link Layer Event Group Synchronization:

[0104] For synchronous services involving multiple nodes, an event group time synchronization anchor mechanism is adopted: the management node defines a unified event group time synchronization anchor and event group time synchronization reference point within the cluster, and the sending node determines the transmission delay based on the time interval between the arrival of the service data packet at the reference point to ensure that the data arrives at the receiving node within the agreed time slot; at the synchronization anchor point, all receiving nodes uniformly deliver the received service data packets to the upper layer application in sequence to ensure the timing consistency of data output from multiple nodes.

[0105] For periodic services with extremely high timeliness requirements, a synchronous data link is used. In this link, each data packet has only a limited number of retransmission opportunities. If no acknowledgment is received within a specified time, it is discarded directly. By replacing "reliability priority" with a "time priority" strategy, strict synchronization of data output from multiple devices in multi-event group collaboration is ensured, avoiding output misalignment and cumulative delay caused by unlimited retransmission.

[0106] S33, Time synchronization across the entire network:

[0107] The network-wide time synchronization is based on the StarFlash multi-domain time-frequency synchronization mechanism, which uses bridging nodes to align the clocks of adjacent clusters and achieve network-wide time synchronization.

[0108] Overall, StarSpark SLE 1.0 constructs a complete, layered, and collaborative synchronization system: the physical layer achieves high-precision initial time-frequency alignment through refined frame structure and synchronization signal design; the data link layer completes link-level collaborative scheduling based on event group time synchronization anchors and synchronous data link mechanisms; and the network layer combines broadcast frames and frequency hopping mechanisms to achieve full network synchronization coordination. Under the premise of low power consumption, it can achieve time synchronization accuracy better than 1 millisecond, with ample design margin. The StarSpark SLB mode can achieve high-precision synchronization at the microsecond or even sub-microsecond level. The SLE mode adopted in this solution achieves a balance between power consumption and performance, and based on a 4MHz bandwidth, a maximum physical layer rate of 12Mbps, and an end-to-end processing capability of 250 microseconds, it can fully adapt to the requirements of low-power, high-precision wireless synchronization.

[0109] S4. Tiered time-slot resource scheduling:

[0110] Since the underlying structure of StarSpark adopts a deterministic superframe and wireless frame structure, the channel and time slot management of this invention no longer requires writing a complex time division multiple access state machine through FPGA, but is directly implemented by configuring the master-slave mode of StarSpark chip.

[0111] A hierarchical time slot mechanism is adopted for resource scheduling. All time slot resources are uniformly allocated by the management node, and a non-contention-based access method is used to avoid link conflicts. The specific implementation process is as follows:

[0112] S41. Time slot capability reporting: The terminal node reports its own time slot scheduling capability to the management node, including the supported system scheduling time slot range (25μs / 50μs / 75μs / 100μs / 125μs) and the supported link type (synchronous data link / asynchronous data link).

[0113] S42. Service requirement matching: Based on the transmission service quality requirements of the satellite services and the time slot scheduling capabilities reported by the terminal nodes, the management node configures a scheduling time slot of corresponding length and transmission period for each data link, generates an intra-cluster time slot scheduling table, and distributes it to all terminal nodes; the terminal nodes perform data transmission and reception in the corresponding time slot according to the scheduling table.

[0114] This closed-loop design, with centralized control by management nodes and reporting capabilities from terminal nodes, ensures that the SLE network can maintain deterministic transmission timing under high load conditions, avoiding conflicts and retransmissions caused by distributed contention, thereby significantly improving channel utilization in high-concurrency scenarios.

[0115] From the perspective of the physical implementation of the frame structure, the ultra-short frame design of StarSpark SLE is a crucial support for the efficient operation of the time slot system. With a 4MHz bandwidth, the ultra-short frame length of SLE is only 49 microseconds, the adjustable transmit / receive cycle is further reduced to 75 microseconds, and the interval between two transmissions is 248 microseconds. In contrast, even with a maximum bandwidth of 2Mbps, traditional Bluetooth Low Energy technology still requires a frame length of 92 microseconds and an interval of up to 7.5 milliseconds between transmissions. The resulting idle waiting time significantly restricts the interaction frequency and response speed. StarSpark SLE, by compressing the basic time unit to the microsecond level and shortening the frame interval to hundreds of microseconds, makes the air interface arrangement more compact and dense. This not only reduces the end-to-end latency to about one-thirtieth of traditional Bluetooth but also provides approximately thirty times the amount of interactive information in the same amount of time. This microsecond-level basic time granularity lays a solid time benchmark for subsequent time slot layering and event group orchestration, enabling SLE to achieve a high rate of return and rapid response while maintaining low power consumption.

[0116] In actual service transmission, StarSpark SLE further realizes customized scheduling strategies for different service requirements by organically combining time slots with synchronous and asynchronous data links. Synchronous data links are mainly used for periodic, time-sensitive services; data packets are discarded if no acknowledgment is received within a limited time after transmission, thus ensuring strict time synchronization of data output. Asynchronous data links, on the other hand, handle services requiring reliable transmission; the sending node continuously retransmits data if it does not receive a response from the other end. When configuring these two types of links, the management node can dynamically adjust the data packet sending window and retransmission strategy based on time slot parameters, thereby simultaneously addressing the differentiated quality of service requirements of time-sensitive and reliability-sensitive services within the same network. Extensive academic research and experimental testing further demonstrate that optimizing centralized media access control algorithms based on time slot scheduling, such as the application of an enhanced earliest deadline first scheduling algorithm, can improve time slot utilization by approximately 19.3%, task completion rate by approximately 23.7%, and reduce average response time by 0.15 seconds, significantly enhancing the task scheduling capability and real-time stability of the SLE network under high load and dynamic environments.

[0117] Implementation Method 3

[0118] This embodiment is a further example illustrating the clustered multi-hop networking method based on the Starflash protocol described in Embodiment 2.

[0119] This implementation uses a development board with a star-flash module and matching antennas to build several wireless nodes, completing point-to-point pass-through tests, multi-node networking tests, and connectivity tests at different speeds and frequency bands. During testing, some nodes connect to the host computer via serial ports to generate and receive test data; other nodes connect to the test control computer via Ethernet to record timestamps and link status. The test data is a pseudo-random bitstream generated by the protocol interface tool. Error rates are statistically analyzed, reception timestamps are recorded, and the operational status is observed under different speeds, distances, and topologies.

[0120] The requirements are to support networking of no less than 12 sub-clusters and 60 wireless nodes, and to support multi-domain networks.

[0121] First, based on the SDKs of the Hi2821 and Hi3863 StarSpark modules, the maximum number of networks that a single node can form was tested. The test results are as follows. Figure 16 As shown, the Hi2821 model supports 1-to-6 networking, and the Hi3863 model supports 1-to-8 networking.

[0122] For multi-cluster, multi-domain networks, this solution introduces four roles in the system architecture: global management node, cluster management node, inter-cluster relay node, and ordinary wireless node. Network scale is expanded through a clustered multi-hop structure. Each cluster contains at least one cluster management node and several ordinary nodes, and can be configured with one to two inter-cluster relay nodes as needed. Based on 5 nodes per cluster, 12 clusters can achieve a total of sixty wireless nodes. If the number of nodes in some clusters increases, the total number of nodes can be further expanded.

[0123] In terms of protocol design, the link layer and network layer employ an addressing method using cluster numbers plus node numbers. The address space is far greater than the requirement of 60 nodes, and the routing algorithm plans paths on a cluster-by-cluster basis, preventing a linear increase in complexity with the number of nodes in a single cluster. In the software implementation, the topology management module maintains cluster and node tables, while the global management node manages forwarding paths between different clusters using path labels and address lists. Multi-domain networks are implemented by adding a domain identifier field to the network identifier. Different domains can use different starband channel configurations, different timing plans, and routing strategies. A single physical machine can join one or more domains based on its configuration, and isolation and interoperability between domains are achieved through the global management node.

[0124] In summary, considering the combined hardware connectivity, address space, and software management capabilities, this solution can be considered to meet the performance requirements in terms of network scale and multi-domain network support.

[0125] To further quantify and verify the reliability of wireless transmission, this implementation method conducted parameter influence tests in an office electromagnetic environment. With a fixed distance of 1 meter between two nodes, the packet error rate (PER) was tested under different bandwidths, transmit powers, and wireless frame types. The results are as follows:

[0126] 1. The impact of bandwidth on PER

[0127] Tests were conducted using bandwidths of 1MHz, 2MHz, and 4MHz, with a fixed transmit power of 10dBm and GFSK wireless frame type. The results showed that the PER was 0.07% with a bandwidth of 1MHz, 0.14% with a bandwidth of 2MHz, and 0.22% with a bandwidth of 4MHz. Wider bandwidth results in lower power spectral density, a corresponding decrease in the received signal-to-noise ratio, and a higher PER. If high data rate is not a primary requirement, a bandwidth of 1MHz or 2MHz is preferred.

[0128] 2. The impact of transmit power on PER:

[0129] With a fixed 4MHz bandwidth and GFSK wireless frame type, the impact of transmit power on PER in the range of -6dBm to 20dBm was tested: PER was 1.46% at -6dBm transmit power, and decreased continuously with increasing transmit power, stabilizing above 14dBm, and dropping to 0.08% at 20dBm. A minimum operating power of 14dBm is recommended to ensure sufficient margin for transmission reliability.

[0130] 3. The impact of wireless frame type on PER:

[0131] With a fixed bandwidth of 4MHz and a transmit power of 10dBm, the PER of GFSK and QPSK frame types was compared: the PER of GFSK frame type was 0.22%, while the PER of QPSK frame type with Polar channel coding was 0.07%. The QPSK scheme has significantly better anti-interference capability than GFSK, so QPSK frame type should be preferred.

[0132] Testing and verification show that all performance indicators of this system meet the design requirements with sufficient margin. At the time synchronization level, the synchronization error of nodes within a single cluster reaches hundreds of microseconds, and the overall network synchronization accuracy remains better than 1ms after multi-hop cascading. At the communication level, based on dual-path independent star-flash modules and time slot scheduling, logical full-duplex communication between any nodes can be achieved. With the hardware capabilities and software configuration in place, the transceiver channels can support 2.4GHz and 5.8GHz. The required transmission rate for both frequencies covers the range of 100Kbps to 1Mbps, and stable transmission is possible at various speeds. In open outdoor environments, point-to-point communication distance using the matching omnidirectional antenna can reach approximately 300-400 meters while maintaining a low bit error rate. When installed within the satellite, the typical distance between nodes is between 1 meter and several meters; the required distance of 4 meters is much smaller than the maximum coverage distance of the star-flash in free space. Even considering the signal attenuation caused by the internal metal structure of the module, by reasonably selecting relay locations and clustering planning, an effective transmission distance of more than four meters can be ensured between any two nodes via single-hop or multi-hop paths. Within the entire operating frequency band, between any two spatial wireless transceiver nodes, under receiver threshold level conditions, the bit error rate does not exceed [value missing]. The frame error rate is no greater than The interface is compatible with both RS422 and Ethernet on-board bus interfaces, enabling end-to-end transparent transmission of space data packets.

[0133] It is understood that the present invention has been described through some embodiments, and those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the invention. Furthermore, under the teachings of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of the present invention.

Claims

1. A controllable time-synchronized multi-interface wireless edge gateway, characterized in that, It includes a logic control and protocol conversion unit, an interface unit, a starlight wireless communication unit, and a power supply unit; The interface unit includes an RS422 interface circuit and an Ethernet interface circuit, used to interface with the external wired bus on the satellite to realize bidirectional conversion between external wired signals and internal logic levels. The interface unit is bidirectionally connected to the logic control and protocol conversion unit. The external wired bus on the satellite includes an RS422 serial bus and an Ethernet bus. The RS422 serial bus carries service data in spatial data packet format, and the Ethernet bus carries service data in spatial data packet format encapsulated by UDP protocol. The logic control and protocol conversion unit adopts a ZYNQ on-chip computing unit, which integrates a processor PS end and a programmable logic PL end. The programmable logic PL end is used to perform bidirectional protocol conversion between RS422 protocol, Ethernet protocol and StarSpark interface protocol. The processor PS end is used to process Ethernet higher-level protocols and control the overall system resources. The Star Flash wireless communication unit includes at least two independent Star Flash wireless modules. Each Star Flash wireless module is bidirectionally connected to the logic control and protocol conversion unit. At least one Star Flash wireless module is configured as a data transmission link and at least one Star Flash wireless module is configured as a data reception link. The power supply unit is connected to an external DC power supply and generates multiple working voltages of different levels through multi-stage voltage conversion, which power the logic control and protocol conversion unit, the interface unit, and the starlight wireless communication unit respectively.

2. The controllable time synchronization multi-interface wireless edge gateway according to claim 1, characterized in that, The StarSpark wireless communication unit includes four StarSpark wireless modules, which are divided into two independent transceiver link pairs. The two transceiver link pairs correspond to two different StarSpark communication domains. The logic control and protocol conversion unit performs transparent forwarding of the data transmitted between the two transceiver link pairs, forming a cross-cluster bridging node hardware architecture.

3. The controllable time synchronization multi-interface wireless edge gateway according to claim 1, characterized in that, The Ethernet interface circuit includes a PHY chip and a voltage-type PHY port transformer in sequence. The PHY chip is connected to the logic control and protocol conversion unit through the GMII interface.

4. The controllable time synchronization multi-interface wireless edge gateway according to claim 1, characterized in that, The power supply unit includes a first-stage step-down module and a second-stage step-down module; the first-stage step-down module is used to convert the externally input 12V DC voltage into a 5V DC voltage; the second-stage step-down module is used to convert the 5V DC voltage into 3.3V and 1.8V DC voltages respectively, providing power to each unit in stages.

5. The controllable time synchronization multi-interface wireless edge gateway according to claim 1, characterized in that, The programmable logic (PL) terminal of the logic control and protocol conversion unit is equipped with a hardware state machine for space data packet processing and RS422 serial protocol conversion logic. This logic is used to perform frame identification, parsing, and routing processing on space data packets from the RS422 interface, and convert them into a serial data format compatible with the StarSpark module. At the same time, the serial data stream from the StarSpark module is reframed into space data packets and then output to the RS422 interface.

6. The controllable time synchronization multi-interface wireless edge gateway according to claim 1, characterized in that, The processor PS of the logic control and protocol conversion unit runs a lightweight TCP / IP protocol stack and performs encapsulation and decapsulation of Ethernet UDP data; the programmable logic PL is interconnected with the processor PS via an AXI bus.

7. The controllable time synchronization multi-interface wireless edge gateway according to claim 1, characterized in that, The system also includes an electromagnetic compatibility protection unit, which is equipped with multi-level filtering and surge suppression devices at the power input port, common-mode suppression and surge protection devices at the differential transceiver chip, and decoupling and transient protection devices at the radio frequency link.

8. The controllable time synchronization multi-interface wireless edge gateway according to claim 1, characterized in that, The system also includes a connector that integrates RS422 differential signal pins, Ethernet differential signal pins, star flash module pins, and power pins to achieve integrated signal and power supply connections for the node to the outside world.

9. A clustered multi-hop networking method, characterized in that, The method, applied to a multi-interface wireless edge gateway with controllable time synchronization as described in any one of claims 1-8, comprises: S1: Construct a star-shaped clustered multi-hop communication topology, set up several clusters, each cluster is configured with a management node and several terminal nodes, adjacent clusters are connected through bridging nodes, and the division of management nodes and terminal nodes within a cluster is completed based on the star flash communication domain mechanism; S2: The management node performs intelligent scheduling and transparent forwarding of communication data of terminal nodes within the same cluster; when transmitting across clusters, path tags are used to identify the data transmission path, and the bridging node performs transparent forwarding of cross-domain data. S3: Based on the Star Flash SLE time-frequency synchronization mechanism, combined with the data link layer event group time synchronization anchor mechanism and the synchronous data link mechanism, network time synchronization is achieved; S4: A hierarchical time slot mechanism is adopted for resource scheduling. A fixed-duration system base time slot is set as the smallest unit for time synchronization and resource occupation between devices in the connectionless state; and an adjustable-granularity scheduling time slot is set for data transmission on connected links.

10. The clustered multi-hop networking method according to claim 9, characterized in that, In S4, the scheduling time slots are customized according to the link type and service characteristics: the terminal node reports the supported scheduling time slot length to the management node through capability indication information, and the management node allocates corresponding time slot parameters for asynchronous data links or synchronous data links according to the supported scheduling time slot length reported by the terminal node and in combination with the service transmission quality requirements.

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