Data transmission method, electronic device, storage medium and program product

Abstract

The application relates to the technical field of communication, and discloses a data transmission method, an electronic device, a storage medium and a program product. In the data transmission method, a chip system can first determine N first time slots and S second time slots, wherein the first time slots and the second time slots are adjacent time slots, the first time slots and the second time slots are related to service information, N and S are positive integers; then two chips (for example, a first chip and a second chip) in the chip system can work in time-sharing cooperation time slots, the first chip can perform data transmission in the N first time slots, and the second chip can perform data transmission in the S second time slots. In this way, the data transmission method can control two chips in the same chip system to work in time-sharing cooperation time slots, avoid the problem that the two chips interfere with each other when concurrently running, and thus can guarantee data transmission efficiency and system performance.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a data transmission method, electronic device, storage medium, and program product. Background Technology

[0002] In daily life, an increasing number of electronic devices (such as mobile phones, desktop computers, and laptops) can access the internet via Wireless Fidelity (Wi-Fi) technology. Users can use these devices to watch online videos and conduct real-time communication. In public places such as offices, shopping malls, and campuses, because a large number of electronic devices may connect to wireless routers via Wi-Fi, wireless routers may limit the Wi-Fi speed of each electronic device to balance the internet access needs of these devices and ensure the reasonable allocation of network resources. This may result in some electronic devices not being able to obtain sufficient bandwidth for data transmission via Wi-Fi.

[0003] Considering the above scenario, a Wi-Fi chip is typically added to electronic devices. When two Wi-Fi chips operate concurrently, the wireless router recognizes them as two independent devices and allocates separate bandwidth to each, thereby ensuring the data transmission rate of the electronic device.

[0004] However, due to space constraints in electronic devices, the antenna isolation between the two Wi-Fi chips may be insufficient. When the two Wi-Fi chips are running concurrently, there may be mutual interference in the data transmission between them. Summary of the Invention

[0005] This application provides a data transmission method, electronic device, storage medium, and program product to solve the problem of mutual interference in data transmission when two chips in the same device are running concurrently.

[0006] In a first aspect, embodiments of this application provide a data transmission method applied to a chip system, the chip system including a first chip and a second chip. The method includes: determining N first time slots and S second time slots, wherein the first time slots and the second time slots are adjacent time slots; wherein the first time slots are used to transmit first data corresponding to the first chip and cache second data corresponding to the second chip, and the second time slots are used to cache the first data corresponding to the first chip and transmit the second data corresponding to the second chip, the first time slots and the second time slots are related to service information, and N and S are positive integers; based on the above N first time slots and S second time slots, the first chip and the second chip respectively perform data transmission.

[0007] In the data transmission method provided in this application embodiment, the first chip can transmit data within N first time slots, and the second chip can transmit data within S second time slots, avoiding the problem of mutual interference when the two chips run concurrently, thereby ensuring data transmission efficiency and system performance.

[0008] In one possible implementation of the first aspect above, the service information includes service priority, the quantity of service data, or the transmission requirements of service data. The first time slot and the second time slot are related to the service information as follows: the service priority of the first chip is higher than the service priority of the second chip; or, the quantity of service data of the first chip is greater than the quantity of service data of the second chip; or, the transmission requirements of the service data of the first chip are higher than the transmission requirements of the service data of the second chip, and the first time slot is greater than the second time slot; or, the service priority of the first chip is lower than the service priority of the second chip; or, the quantity of service data of the first chip is less than the quantity of service data of the second chip; or, the transmission requirements of the service data of the first chip are lower than the transmission requirements of the service data of the second chip, and the first time slot is less than the second time slot.

[0009] For example, if the service type of the first chip is a front-end application service and the service type of the second chip is a back-end background service, since the service priority of the front-end application service is usually higher than that of the back-end background service, the amount of service data of the front-end application service is usually higher than that of the back-end background service, and the transmission requirements of the service data of the front-end application service are usually higher than those of the back-end background service, the first time slot determined by the chip system is larger than the second time slot.

[0010] It's understandable that foreground applications, such as user-triggered and user-interactive services, require real-time data transmission. Therefore, more time slots need to be allocated to foreground applications to transmit more data. Background applications, on the other hand, can be services that don't require user interaction and can transmit data when the system is idle. Therefore, fewer time slots can be allocated to background applications.

[0011] It's understandable that data transmission requirements can include latency, data transmission rate, and other factors. For example, gaming applications have high latency requirements, needing latency of less than 100 milliseconds. On the other hand, background updates in applications have lower data transmission rate requirements and can be performed during periods of network idle time.

[0012] In one possible implementation of the first aspect described above, a physical connection channel exists between the first chip and the second chip. The method further includes: at the beginning of a first time slot, the first chip sends a first notification to the first device and the second chip respectively, the first notification instructing the first chip to begin data transmission with the first device; at the end of the first time slot, the first chip sends a second notification to the first device and the second chip respectively, the second notification instructing the first chip to stop data transmission with the first device; at the beginning of a second time slot, the second chip sends a third notification to the first device and the first chip respectively, the third notification instructing the second chip to begin data transmission with the first device; at the end of the second time slot, the second chip sends a fourth notification to the first device and the first chip respectively, the fourth notification instructing the second chip to stop data transmission with the first device.

[0013] For example, the physical connection channel may include GPIO signal lines or serial bus, etc.

[0014] It is understood that the first chip can send a first notification and a second notification to the second chip via a physical connection channel, and the second chip can also send a third notification and a fourth notification to the first chip via the same physical connection channel. Furthermore, the first chip can send the first notification and the second notification to the first device via wireless communication, and the second chip can also send the third notification and the fourth notification to the first device via wireless communication.

[0015] In some embodiments, both the first chip and the second chip can include an active state and a sleep state. During a first time slot, the first chip can be in the active state, transmitting data with the first device, while the second chip can be in the sleep state, ceasing data transmission with the first device. During a second time slot, the first chip can be in the sleep state, ceasing data transmission with the first device, while the second chip can be in the active state, transmitting data with the first device.

[0016] It is understandable that in some chip systems, the specifications of the first chip and the second chip may be inconsistent. This could prevent the first chip and the second chip from transmitting data with the first device only in their own working time slots. Consequently, in some time slots, the first chip and the second chip may transmit data with the first device simultaneously, affecting data transmission efficiency. In the embodiments of this application, the first chip can obtain the third and fourth notifications, i.e., the state of the second chip, through a physical connection channel. The second chip can also obtain the first and second notifications, i.e., the state of the first chip, through the physical connection channel. This enables coordinated operation between the first chip and the second chip.

[0017] In one possible implementation of the first aspect described above, the method further includes: the first chip or the second chip adjusting the first time slot or the second time slot according to the state of data transmission.

[0018] It is understandable that during data transmission, if the first chip needs to stop data transmission with the first device at the end of the first time slot, the first device will stop data transmission only after the currently transmitting data transmission is completed to avoid data loss. Therefore, to ensure the coordinated operation of the first chip and the second chip, the first chip or the second chip can adjust the first time slot or the second time slot according to the data transmission status.

[0019] In one possible implementation of the first aspect above, adjusting the first or second time slot according to the state of data transmission includes: if the transmission of a portion of the data corresponding to the first or second time slot is not completed at the end of the first or second time slot, then increasing the time slot length of the first or second time slot to transmit the remaining data.

[0020] It is understandable that increasing the time slot length can prevent the first chip and the second chip from transmitting data with the first device at the same time, thereby avoiding mutual interference between the first chip and the second chip and ensuring data transmission efficiency.

[0021] In one possible implementation of the first aspect above, there is no physical connection channel between the first chip and the second chip, and the method further includes: the first chip and the second chip acquiring a time synchronization flag from the processor, and adjusting the start and end times of the first time slot and / or the start and end times of the second time slot based on the time synchronization flag.

[0022] It is understandable that, without a physical connection between the first and second chips, they cannot directly notify each other of their status. Therefore, the first and second chips can synchronize their time using a time synchronization flag sent by the processor to achieve coordinated operation and avoid mutual interference.

[0023] In one possible implementation of the first aspect described above, the method further includes: detecting that the first device limits the maximum amount of data transmitted per unit time, or detecting interference between the first chip and the second chip.

[0024] Secondly, embodiments of this application provide a data transmission method applied to a first device. The method includes: responding to a transmission request for first data corresponding to a first chip in a chip system, transmitting the first data with the first chip and caching the second data corresponding to a second chip in the chip system within N first time slots; and responding to a transmission request for the second data corresponding to the second chip in the chip system, transmitting the second data with the second chip and caching the first data within S second time slots; wherein the first time slot and the second time slot are adjacent time slots, the first time slot and the second time slot are related to the service information of the chip system, and N and S are positive integers.

[0025] The data transmission method provided in this application embodiment can enable the first chip and the second chip in the chip system to transmit data with the first device respectively, and the data transmission of the first chip and the data transmission of the second chip will not interfere with each other, thereby ensuring data transmission efficiency.

[0026] In one possible implementation of the second aspect above, the service information includes service priority, the quantity of service data, or the data transmission requirements of the service. The first time slot and the second time slot are related to the service information as follows: the service priority of the first chip is higher than the service priority of the second chip; or, the quantity of service data of the first chip is greater than the quantity of service data of the second chip; or, the transmission requirements of the service data of the first chip are higher than the transmission requirements of the service data of the second chip, and the first time slot is greater than the second time slot; or, the service priority of the first chip is lower than the service priority of the second chip; or, the quantity of service data of the first chip is less than the quantity of service data of the second chip; or, the transmission requirements of the service data of the first chip are lower than the transmission requirements of the service data of the second chip, and the first time slot is less than the second time slot.

[0027] In one possible implementation of the second aspect described above, the method further includes: receiving a first notification at the beginning of a first time slot, the first notification instructing a first chip to begin data transmission with a first device; and receiving a second notification at the end of the first time slot, the second notification instructing the first chip to stop data transmission with the first device; receiving a third notification at the beginning of a second time slot, the third notification instructing a second chip to begin data transmission with the first device; and receiving a fourth notification at the end of the second time slot, the fourth notification instructing the second chip to stop data transmission with the first device.

[0028] In one possible implementation of the second aspect above, the method further includes: at the end of the first time slot or the second time slot, the transmission of a portion of the data corresponding to the first time slot or the second time slot is not completed, and the first time slot or the second time slot is a time slot after the first chip or the second chip increases the time slot length according to the data transmission status, and the increased time slot length is used to transmit the portion of data.

[0029] It is understandable that if the first device has not completed transmitting the corresponding portion of data for the first time slot at the end of the first time slot, the first device will stop data transmission with the first chip after that portion of data transmission is completed. In this case, the first chip can increase the time slot length of the first time slot, and the increased time slot length will be used to transmit that portion of data. Similarly, if the first device has not completed transmitting the corresponding portion of data for the second time slot at the end of the second time slot, the first device will stop data transmission with the second chip after that portion of data transmission is completed. In this case, the second chip can increase the time slot length of the second time slot, and the increased time slot length will be used to transmit that portion of data.

[0030] In one possible implementation of the second aspect described above, the method further includes limiting the maximum amount of data transmitted per unit time.

[0031] For example, the first device can be a router, and the first chip and the second chip can be Wi-Fi chips. When the first device is connected to a large number of electronic devices, the first device can limit the data transmission rate of each electronic device (referred to as a Wi-Fi speed-limiting scenario). It can be understood that when the first device limits the data transmission rate of each connected electronic device, if the chip system connects to the first device via Wi-Fi and transmits data with the first device through the first chip and the second chip, the first device can recognize the first chip and the second chip as chips in two separate devices, thereby improving the data transmission rate of the chip system.

[0032] Thirdly, embodiments of this application provide an electronic device including a chip system for performing the data transmission method mentioned in the first aspect and any possible implementation thereof.

[0033] Fourthly, embodiments of this application provide an electronic device, including: a memory for storing instructions executed by one or more processors of the electronic device, and a processor, which is one of the one or more processors of the electronic device, for executing the first aspect and any possible implementation thereof, or the data transmission method mentioned in the second aspect and any possible implementation thereof.

[0034] Fifthly, embodiments of this application provide a readable storage medium storing instructions that, when executed on an electronic device, cause the electronic device to perform the first aspect and any possible implementation thereof, or the data transmission method mentioned in the second aspect and any possible implementation thereof.

[0035] In a sixth aspect, embodiments of this application provide a computer program product comprising computer instructions that, when executed by an electronic device, enable the electronic device to execute the computer program code of the data transmission method mentioned in the first aspect and any possible implementation thereof, or in the second aspect and any possible implementation thereof. Attached Figure Description

[0036] Figure 1 According to some embodiments of this application, a schematic diagram of a data transmission scenario in a mobile phone including a single Wi-Fi chip is shown;

[0037] Figure 2A According to some embodiments of this application, a schematic diagram of a data transmission scenario for a mobile phone including dual Wi-Fi chips is shown;

[0038] Figure 2B According to some embodiments of this application, a schematic diagram of a scenario in which data transmission between two Wi-Fi chips in a mobile phone interferes with each other is shown;

[0039] Figure 3 According to some embodiments of this application, a flowchart of a data transmission method is shown;

[0040] Figure 4 According to some embodiments of this application, a flowchart of another data transmission method is shown;

[0041] Figure 5A According to some embodiments of this application, a schematic diagram of data transmission characteristics in a rate-limited scenario is shown;

[0042] Figure 5B According to some embodiments of this application, a schematic diagram is shown of a first chip occupying a portion of its space to perform data transmission in a speed-limited scenario;

[0043] Figure 6 According to some embodiments of this application, a schematic diagram of a data transmission process is shown;

[0044] Figure 7 According to some embodiments of this application, a schematic diagram of the structure of a chip system 100 is shown;

[0045] Figure 8A According to some embodiments of this application, a schematic diagram of a data transmission process is shown when there is a physical connection channel between a first chip and a second chip in a chip system 100.

[0046] Figure 8BAccording to some embodiments of this application, a schematic diagram of another data transmission process is shown when there is a physical connection channel between a first chip and a second chip in a chip system 100.

[0047] Figure 9A According to some embodiments of this application, a schematic diagram of a data transmission process is shown when there is no physical connection channel between the first chip and the second chip in the chip system 100.

[0048] Figure 9B According to some embodiments of this application, a schematic diagram of another data transmission process is shown when there is no physical connection channel between the first chip and the second chip in the chip system 100.

[0049] Figure 10 According to some embodiments of this application, a schematic diagram of the hardware structure of an electronic device is shown. Detailed Implementation

[0050] The illustrative embodiments of this application include, but are not limited to, a data transmission method, an electronic device, a storage medium, and a program product. The data transmission method of this application will be described below with reference to specific embodiments.

[0051] As described in the background section, when a large number of electronic devices are connected to a wireless router via Wi-Fi, the wireless router limits the Wi-Fi speed for each electronic device. For example, as Figure 1 As shown, if the Wi-Fi chip in a mobile phone uses the Wi-Fi 6 standard and employs an 80MHz bandwidth and 2×2 MIMO configuration, its theoretical maximum data transfer rate is 1.2 gigabits per second (Gb / s), meaning the Wi-Fi link supports a data transfer rate of 1.2 Gb / s. However, after the wireless router limits the speed, the actual Wi-Fi speed of the electronic device can only reach a maximum of 80 megabits per second (Mb / s), or 10 megabytes per second (MB / s). This can result in the actual usable data transfer rate of the electronic device being far lower than the data transfer rate supported by the Wi-Fi link.

[0052] In some embodiments, an additional Wi-Fi chip is added to the electronic device, meaning the electronic device includes two Wi-Fi chips, such as... Figure 2AAs shown, when two Wi-Fi chips operate concurrently, the wireless router recognizes them as two independent devices and allocates separate bandwidth to each to improve data transmission rates. However, if the antenna isolation between the two Wi-Fi chips in the electronic device is insufficient, data transmission can interfere with each other when the two Wi-Fi chips operate concurrently.

[0053] For example, if one Wi-Fi chip (e.g., the main chip) in an electronic device uses channel 36 in the 5.2GHz band for data transmission, and another Wi-Fi chip (e.g., the secondary chip) uses channel 149 in the 5.8GHz band for data transmission, then theoretically, the data transmissions of the main and secondary chips will not interfere with each other when running concurrently. However, if the antenna isolation between the main and secondary chips is insufficient, then... Figure 2B As shown, if the main chip is receiving a signal while the secondary chip is sending data, the signal received by the main chip will be affected, which may cause the noise power to be greater than the signal power, thus causing the main chip to be unable to demodulate the signal normally and the data reception to fail.

[0054] In view of this, embodiments of this application provide a data transmission method. In this method, a chip system can first determine N first time slots and S second time slots. Then, two chips in the chip system (e.g., a first chip and a second chip) can work collaboratively in a time-division manner based on the N first time slots and S second time slots. The first and second time slots are adjacent time slots. The first time slot is used to transmit first data corresponding to the first chip and buffer second data corresponding to the second chip. The second time slot is used to buffer the first data corresponding to the first chip and transmit the second data corresponding to the second chip. The first and second time slots are related to service information, and N and S are positive integers. That is, the first chip can perform data transmission within the N first time slots, and the second chip can perform data transmission within the S second time slots.

[0055] For example, if a second includes a first time slot (e.g., 700 milliseconds) and a second time slot (e.g., 300 milliseconds), then within the first 700 milliseconds of that second, the first chip can transmit first data to the first device, and the first device can cache second data. Within the last 300 milliseconds of that second, the second chip can transmit second data to the first device, and the first device can cache first data.

[0056] For example, if a second includes a first time slot (e.g., 700 milliseconds) and a second time slot (e.g., 300 milliseconds), and the first chip is connected to the first device and the second chip is connected to the second device, then within the first 700 milliseconds of the second, the first chip can transmit first data with the first device, and the second device can cache second data; within the last 300 milliseconds of the second, the second chip can transmit second data with the second device, and the first device can cache first data.

[0057] Thus, the data transmission method provided in this application can control two chips in the same chip system to work in a time-sharing manner, avoiding the problem of mutual interference when the two chips run concurrently, thereby ensuring data transmission efficiency and system performance.

[0058] For example, the first chip and the second chip mentioned in this application can be wireless communication chips, such as Wi-Fi chips, and the first device and the second device can be routers, switches, etc. It is understood that this application does not limit the chip type of the first chip and the second chip, and this application does not specifically limit the first device and the second device; the first device can be any device capable of communicating with two chips in the same chip system.

[0059] In some embodiments, when the chip system detects that the current scenario is a rate-limited scenario or a concurrent scenario, it can execute the data transmission method mentioned in this application. A rate-limited scenario refers to the first device and / or the second device limiting the maximum amount of data transmitted per unit time, while a concurrent scenario refers to data transmission between the first chip and the second chip interfering with each other.

[0060] In some embodiments, the chip system may first drive a first chip, which can then transmit data with a first device. If the chip system detects that the first device limits the maximum amount of data transmitted per unit time, it drives a second chip, and then determines N first time slots and S second time slots. Subsequently, based on the N first time slots and S second time slots, the first chip and the second chip can respectively transmit data with the first device.

[0061] The following is combined with Figure 3 The flowchart shown illustrates a data transmission method provided in an embodiment of this application.

[0062] In some embodiments, the method can be applied to a chip system, which includes a first chip and a second chip.

[0063] like Figure 3 As shown, the method includes:

[0064] S301, determine N first time slots and S second time slots, wherein the first time slots and the second time slots are adjacent time slots.

[0065] In some embodiments, the chip system may first determine N first time slots and S second time slots, wherein the first time slots are used to transmit first data corresponding to the first chip and cache second data corresponding to the second chip, and the second time slots are used to cache the first data corresponding to the first chip and transmit the second data corresponding to the second chip. The first and second time slots are related to service information, and N and S are positive integers.

[0066] In some embodiments, business information includes business priority, the amount of business data, or the transmission requirements of business data.

[0067] For example, the first time slot is greater than the second time slot in the following cases: the service priority of the first chip is higher than the service priority of the second chip, or the amount of service data of the first chip is greater than the amount of service data of the second chip, or the transmission demand of the service data of the first chip is higher than the transmission demand of the service data of the second chip.

[0068] For example, the first time slot is smaller than the second time slot in the following situations: the service priority of the first chip is lower than the service priority of the second chip, or the amount of service data of the first chip is less than the amount of service data of the second chip, or the transmission requirement of the service data of the first chip is less than the transmission requirement of the service data of the second chip.

[0069] For example, the first time slot is equal to the second time slot in the following cases: the service priority of the first chip is equal to the service priority of the second chip, or the amount of service data of the first chip is equal to the amount of service data of the second chip, or the transmission requirements of the service data of the first chip are equal to the transmission requirements of the service data of the second chip.

[0070] For example, if the service type of the first chip is a front-end application service and the service type of the second chip is a back-end background service, since the service priority of the front-end application service is usually higher than that of the back-end background service, the amount of service data of the front-end application service is usually higher than that of the back-end background service, and the transmission requirements of the service data of the front-end application service are usually higher than those of the back-end background service, the first time slot determined by the chip system is larger than the second time slot.

[0071] It's understandable that foreground applications, such as user-triggered and user-interactive services, require real-time data transmission. Therefore, more time slots need to be allocated to foreground applications to transmit more data. Background applications, on the other hand, can be services that don't require user interaction and can transmit data when the system is idle. Therefore, fewer time slots can be allocated to background applications.

[0072] For example, assuming the first chip's service is a high-priority service and the second chip's service is a low-priority service, the chip system can determine that the first time slot is 70% and the second time slot is 30%. That is, within a unit of time (1 second), the first time slot is 700 milliseconds and the second time slot is 300 milliseconds.

[0073] For example, assuming the number of service data items in the first chip is 20 and the number of service data items in the second chip is 5, the chip system can determine that the first time slot is 80% and the second time slot is 20%. That is, in a unit of time (1 second), the first time slot is 800 milliseconds and the second time slot is 200 milliseconds.

[0074] For example, suppose the first chip is a business type with high data transmission requirements (such as game application business), and the second chip is a business type with low data transmission requirements (such as application background update background), then the chip system can determine that the first time slot is 80% and the second time slot is 20%, that is, in a unit of time (1 second), the first time slot is 800 milliseconds and the second time slot is 200 milliseconds.

[0075] It's understandable that data transmission requirements can include latency, data transmission rate, and other factors. For example, gaming applications have high latency requirements, needing latency of less than 100 milliseconds. On the other hand, background updates in applications have lower data transmission rate requirements and can be performed during periods of network idle time.

[0076] S302, based on N first time slots and S second time slots, the first chip and the second chip respectively perform data transmission.

[0077] In some embodiments, the first chip and the second chip perform data transmission based on N first time slots and S second time slots, respectively. That is, the first chip can perform data transmission within N first time slots, and the second chip can perform data transmission within S second time slots.

[0078] Specifically, if the first of N first time slots precedes the first of S second time slots, then the first chip performs data transmission within the first first time slot. Within the first second time slot, the first chip stops data transmission, and the second chip begins data transmission. Then, within the second first time slot, the second chip stops data transmission, and the first chip begins data transmission again, and so on.

[0079] It is understandable that the first chip can perform data transmission first, meaning the first time slot out of N first time slots precedes the first second time slot out of S second time slots. Alternatively, the second chip can perform data transmission first, meaning the first time slot out of N first time slots follows the first second time slot out of S second time slots.

[0080] In this application, the first chip performs data transmission in the first time slot, and the second chip performs data transmission in the second time slot. This enables the two chips in the chip system to work in a time-sharing manner, avoiding the problem of mutual interference when the two chips run concurrently, thereby ensuring data transmission efficiency and system performance.

[0081] In some embodiments, both the first chip and the second chip can include an active state and a sleep state. During a first time slot, the first chip can be in the active state to transmit data, while the second chip can be in the sleep state to stop transmitting data; during a second time slot, the first chip can be in the sleep state to stop transmitting data, while the second chip can be in the active state to transmit data.

[0082] In this embodiment of the application, the first chip and the second chip can respectively transmit data with the first device.

[0083] In some embodiments, a physical connection channel exists between the first chip and the second chip. This physical connection channel may include a general-purpose input / output (GPIO) signal line or a serial bus, etc. At the beginning of the first time slot, the first chip sends a first notification to both the first device and the second chip, instructing the first chip to begin data transmission with the first device. At the end of the first time slot, the first chip sends a second notification to both the first device and the second chip, instructing the first chip to stop data transmission with the first device. At the beginning of the second time slot, the second chip sends a third notification to both the first device and the first chip, instructing the second chip to begin data transmission with the first device. At the end of the second time slot, the second chip sends a fourth notification to both the first device and the first chip, instructing the second chip to stop data transmission with the first device.

[0084] It is understood that the first chip can send a first notification and a second notification to the second chip via a physical connection channel, and the second chip can also send a third notification and a fourth notification to the first chip via the same physical connection channel. Furthermore, the first chip can send the first notification and the second notification to the first device via wireless communication, and the second chip can also send the third notification and the fourth notification to the first device via wireless communication.

[0085] In this embodiment of the application, the first chip can be connected to the first device and transmit data with the first device in the first time slot, and the second chip can be connected to the second device and transmit data with the second device in the second time slot.

[0086] In some embodiments, a physical connection channel exists between the first chip and the second chip, with the first chip connected to the first device and the second chip connected to the second device. At the beginning of a first time slot, the first chip sends a first notification to both the first device and the second chip, instructing the first chip to begin data transmission with the first device. At the end of the first time slot, the first chip sends a second notification to both the first device and the second chip, instructing the first chip to stop data transmission with the first device. At the beginning of a second time slot, the second chip sends a third notification to both the second device and the first chip, instructing the second chip to begin data transmission with the second device. At the end of the second time slot, the second chip sends a fourth notification to both the second device and the first chip, instructing the second chip to stop data transmission with the second device.

[0087] For ease of explanation, the following description will use the example of the first chip and the second chip transmitting data with the first device, respectively.

[0088] In some embodiments, the first and second notifications described above may include the state of the first chip; the first notification may indicate that the first chip has switched to an active state, and the second notification may indicate that the first chip has switched to a sleep state. The third and fourth notifications described above may include the state of the second chip; the third notification may indicate that the second chip has switched to an active state, and the fourth notification may indicate that the second chip has switched to a sleep state.

[0089] It is understandable that in some chip systems, the specifications of the first chip and the second chip may be inconsistent. This could prevent the first chip and the second chip from transmitting data with the first device only in their own working time slots. Consequently, in some time slots, the first chip and the second chip may transmit data with the first device simultaneously, affecting data transmission efficiency. In the embodiments of this application, the first chip can obtain the third and fourth notifications, i.e., the state of the second chip, through a physical connection channel. The second chip can also obtain the first and second notifications, i.e., the state of the first chip, through the physical connection channel. This enables coordinated operation between the first chip and the second chip.

[0090] In some embodiments, the first chip or the second chip can adjust the first time slot or the second time slot according to the state of data transmission.

[0091] It is understandable that during data transmission, if the first chip needs to stop data transmission with the first device at the end of the first time slot, the first device will stop data transmission only after the currently transmitting data transmission is completed to avoid data loss. Therefore, to ensure the coordinated operation of the first chip and the second chip, the first chip or the second chip can adjust the first time slot or the second time slot according to the data transmission status.

[0092] In some embodiments, if the transmission of a portion of the data corresponding to the first time slot is incomplete at the end of the first time slot, the time slot length is increased to transmit that portion of the data. This portion of data may be data that the first device is transmitting but has not yet completed at the end of the first time slot. Alternatively, if the transmission of a portion of the data corresponding to the second time slot is incomplete at the end of the second time slot, the time slot length is increased to transmit that portion of the data. This portion of data may also be data that the first device is transmitting but has not yet completed at the end of the second time slot.

[0093] It is understandable that increasing the time slot length can prevent the first chip and the second chip from transmitting data with the first device at the same time, thereby avoiding mutual interference between the first chip and the second chip and ensuring data transmission efficiency.

[0094] In some embodiments, at the end of the first time slot, the second chip can switch from a sleep state to an active state. If the transmission of a portion of the data corresponding to the first time slot is incomplete, i.e., the second chip has not received the second notification sent by the first chip, the second chip can wait for the first chip to complete the transmission of that portion of the data. After the transmission of that portion of the data is completed, the second chip can receive the second notification sent by the first chip, and then the second chip can send a third notification to the first device to transmit data with the first device. At the end of the second time slot, the first chip can switch from a sleep state to an active state. If the transmission of a portion of the data corresponding to the second time slot is incomplete, i.e., the first chip has not received the fourth notification sent by the second chip, the first chip can wait for the second chip to complete the transmission of that portion of the data. After the transmission of that portion of the data is completed, the first chip can receive the fourth notification sent by the second chip, and then the first chip can send a first notification to the first device to transmit data with the first device.

[0095] It is understood that when the first chip is in active state, it can transmit data with the first device; when the first chip is in sleep state, it cannot transmit data with the first device. After the first chip completes the aforementioned partial data transmission, it can switch from active state to sleep state and send a second notification to the first device to stop data transmission with the first device. Similarly, when the second chip is in active state, it can transmit data with the first device; when the second chip is in sleep state, it cannot transmit data with the first device. After the second chip completes the aforementioned partial data transmission, it can switch from active state to sleep state and send a fourth notification to the first device to stop data transmission with the first device.

[0096] It should be noted that both the first chip and the second chip transmit data and send notifications to the first device via the channel. During data transmission between the first chip and the first device, the first chip cannot send a second notification to the first device, and similarly, during data transmission between the second chip and the first device, the second chip cannot send a fourth notification to the first device.

[0097] In some embodiments, at the beginning and end of the first time slot, the first chip may send a status acquisition instruction to the second chip to obtain the status of the second chip, and at the beginning and end of the second time slot, the second chip may send a status acquisition instruction to the first chip to obtain the status of the first chip.

[0098] If the first chip needs to increase the length of the first time slot, the second chip can send a status acquisition command to the first chip at the end of the first time slot before the increase. At this time, the second chip can detect that the first chip is in a working state, and can then start channel listening to monitor the status of the channel corresponding to the first chip. The status of the channel corresponding to the first chip includes a busy state and an idle state. When the second chip detects that the status of the channel corresponding to the first chip changes from a busy state to an idle state, the second chip can send a status acquisition command to the first chip again. At this time, the second chip can detect that the first chip is in a sleep state. Afterwards, the second chip can send a third notification to the first device to start data transmission with the first device.

[0099] When the second chip needs to increase the length of the second time slot, the first chip can send a status acquisition command to the second chip at the end of the second time slot before the increase. At this time, the first chip can detect that the second chip is in a working state, and can then start channel listening to monitor the status of the channel corresponding to the second chip. The status of the channel corresponding to the second chip includes a busy state and an idle state. When the first chip detects that the status of the channel corresponding to the second chip changes from a busy state to an idle state, the first chip can send a status acquisition command to the second chip again. At this time, the first chip can detect that the second chip is in a sleep state. Afterwards, the first chip can send a first notification to the first device to start data transmission with the first device.

[0100] It can be understood that if the channel corresponding to the first or second chip is in a busy state, it means that the first or second chip is transmitting data with the first device; if the channel corresponding to the first or second chip is in an idle state, it means that the first or second chip has stopped transmitting data with the first device. Therefore, by monitoring the channel status of each other, the first or second chip can avoid mutual interference, thereby ensuring data transmission efficiency.

[0101] In some embodiments, there is no physical connection channel between the first chip and the second chip. The first chip and the second chip obtain time synchronization flags from the processor and adjust the start and end times of the first time slot and / or the start and end times of the second time slot based on the time synchronization flags.

[0102] It is understandable that, without a physical connection between the first and second chips, they cannot directly notify each other of their status. Therefore, the first and second chips can synchronize their time using a time synchronization flag sent by the processor to achieve coordinated operation and avoid mutual interference.

[0103] Specifically, the processor can periodically send time synchronization flags to the first and second chips. For example, the processor can send a time synchronization flag to the first and second chips every second. The first and second chips can include timers, and after receiving the time synchronization flag, the first and second chips can set the duration of the timers within the chips.

[0104] For example, if the timer in the first chip is a first timer and the timer in the second chip is a second timer, before the first time slot begins, the first chip can set the duration of the first timer to be equal to the first time slot, and the second chip can set the duration of the second timer to be equal to the first time slot. After the first and second timers have finished timing, the first chip can stop data transmission with the first device, and the second chip can start data transmission with the first device. Before the second time slot begins, the second chip can set the duration of the second timer to be equal to the second time slot, and the first chip can set the duration of the first timer to be equal to the second time slot. After the first and second timers have finished timing, the second chip can stop data transmission with the first device, and the first chip can start data transmission with the first device.

[0105] It is understandable that if the timer duration is equal to the first time slot, then after the timer expires, the first chip can switch from the working state to the sleep state and can send a second notification to the first device; the second chip can switch from the sleep state to the working state and can send a third notification to the first device. If the timer duration is equal to the second time slot, then after the timer expires, the first chip can switch from the sleep state to the working state and can send a first notification to the first device; the second chip can switch from the working state to the sleep state and can send a fourth notification to the first device.

[0106] For example, if the first time slot is 700 milliseconds and the second time slot is 300 milliseconds, and the processor sends a time synchronization flag to the first chip and the second chip every second before the first time slot, then the first chip can first set the duration of the first timer to 700 milliseconds and start data transmission with the first device. The second chip can first set the duration of the first timer to 700 milliseconds and remain in sleep mode. After the first and second timers have finished running, the first chip can set the duration of the first timer back to 300 milliseconds, switch to sleep mode, and stop data transmission with the first device. Similarly, the second chip can also set the duration of the first timer back to 300 milliseconds, switch to working mode, and start data transmission with the first device.

[0107] In some embodiments, when the duration of the first timer and the second timer is set to the first time slot, if the transmission of part of the data corresponding to the first time slot is not completed, the first chip can re-set the duration of the first timer to the second time slot at the end of the timer. The first chip can then delay sending the second notification to the first device until the transmission of that part of the data is complete. Furthermore, the second chip can also re-set the duration of the second timer to the second time slot. The second chip can then enable channel listening to monitor the status of the channel corresponding to the first chip. When the second chip detects that the status of the channel corresponding to the first chip changes from busy to idle, the second chip can send a third notification to the first device to begin data transmission with the first device.

[0108] If the duration of the first and second timers is set to the second time slot, and the transmission of some data corresponding to the second time slot is incomplete, the second chip can reset the duration of the second timer to the first time slot at the end of the timer period. The second chip can then delay sending the fourth notification to the first device until the transmission of that portion of data is complete. Furthermore, the first chip can also reset the duration of the first timer to the first time slot and enable channel listening to monitor the status of the channel corresponding to the second chip. When the first chip detects that the status of the channel corresponding to the second chip has changed from busy to idle, the first chip can send the first notification to the first device to begin data transmission.

[0109] In this way, the first or second chip can avoid mutual interference by monitoring the channel status of the other chip, thereby ensuring data transmission efficiency.

[0110] The following is combined with Figure 4 The flowchart shown illustrates another data transmission method provided in the embodiments of this application.

[0111] In some embodiments, the method may be applied to the first device mentioned in this application. For example... Figure 4 As shown, the method includes:

[0112] S401 responds to the transmission request of the first data corresponding to the first chip in the chip system, and transmits the first data with the first chip and caches the second data corresponding to the second chip in the chip system within N first time slots.

[0113] In some embodiments, the first device may respond to the transmission request of the first data corresponding to the first chip in the chip system, and transmit the first data with the first chip and cache the second data corresponding to the second chip in the chip system within N first time slots.

[0114] S402 responds to the transmission request of the second data corresponding to the second chip in the chip system, and transmits the second data with the second chip and buffers the first data within S second time slots.

[0115] In some embodiments, the first device can respond to the transmission request of the second data corresponding to the second chip in the chip system, and transmit the second data with the second chip and buffer the first data within S second time slots. Here, the first and second time slots are adjacent time slots, and the first and second time slots are related to the service information of the chip system, where N and S are positive integers. The relationship between the first and second time slots and the service information of the chip system can be referred to the relevant description in S301 above, and will not be repeated here.

[0116] In some embodiments, at the beginning of a first time slot, a first device receives a first notification instructing a first chip to begin data transmission with the first device, and at the end of the first time slot, the first device receives a second notification instructing the first chip to stop data transmission with the first device. At the beginning of a second time slot, the first device receives a third notification instructing a second chip to begin data transmission with the first device, and at the end of the second time slot, the first device receives a fourth notification instructing the second chip to stop data transmission with the first device.

[0117] In some embodiments, at the end of the first time slot or the second time slot, the transmission of a portion of the data corresponding to the first time slot or the second time slot is not yet complete. The first time slot or the second time slot is a time slot after the first chip or the second chip increases the time slot length according to the data transmission status. The increased time slot length is used to transmit the portion of the data.

[0118] It is understandable that if the first device has not completed transmitting the corresponding portion of data for the first time slot at the end of the first time slot, the first device will stop data transmission with the first chip after that portion of data transmission is completed. In this case, the first chip can increase the time slot length of the first time slot, and the increased time slot length will be used to transmit that portion of data. Similarly, if the first device has not completed transmitting the corresponding portion of data for the second time slot at the end of the second time slot, the first device will stop data transmission with the second chip after that portion of data transmission is completed. In this case, the second chip can increase the time slot length of the second time slot, and the increased time slot length will be used to transmit that portion of data.

[0119] In some embodiments, the first device or the second device may limit the maximum amount of data transmitted per unit time, i.e., limit the data transmission rate.

[0120] For example, the first or second device can be a router, and the first and second chips can be Wi-Fi chips. When the number of electronic devices connected to the first or second device is relatively large, the first or second device can limit the data transmission rate of each electronic device (referred to as a Wi-Fi speed limiting scenario). It can be understood that when the first device limits the data transmission rate of each connected electronic device, if the chip system connects to the first device via Wi-Fi and transmits data with the first device through the first and second chips respectively, the first device can recognize the first and second chips as chips in two separate devices, thereby improving the data transmission rate of the chip system.

[0121] Thus, the data transmission method provided in this application embodiment can enable the first chip and the second chip in the chip system to transmit data separately, and the data transmission of the first chip and the data transmission of the second chip will not interfere with each other, thereby ensuring data transmission efficiency.

[0122] For ease of understanding, the following uses a router as the first device and Wi-Fi chips as the second chip as an example to illustrate the data transmission method provided in this application embodiment in a Wi-Fi speed-limited scenario.

[0123] The following is based on Figure 5A and Figure 5B The characteristics of data transmission in rate-limited scenarios are described.

[0124] Reference Figure 5A After a router limits the data transfer rate of a connected electronic device or chip, it distributes the data across that device or chip evenly. For example, if the router limits the data transfer rate of a first chip to 10MB / s, it will transfer 1MB of data to the first chip every 100 milliseconds. In other words, as long as the amount of data transferred by the router within a given time period (e.g., within one second) is less than the limited amount, the data transfer rate can be considered to meet the router's rate-limiting requirements.

[0125] During data transmission, if an electronic device or chip connected to the router enters a sleep state, the router will cache the downlink data until the sleep device or chip wakes up and switches to an active state, at which point data transmission with that device or chip will resume. If too much data is cached for that device or chip, exceeding the router's data caching threshold, the cached data will be discarded.

[0126] Specifically, such as Figure 5BAs shown, after data transmission between the router and the first chip begins, the router first transmits 5MB of data corresponding to the first chip within 500 milliseconds, and the first chip remains active during this 500 milliseconds. After the 5MB data transmission is complete, the first chip switches to sleep mode, and then switches back to active mode after another 500 milliseconds. During the 500 milliseconds the first chip is in sleep mode, the router caches the 5MB of data corresponding to the first chip within that 500 milliseconds. After the first chip switches back to active mode, the router transmits data with the first chip within 500 milliseconds, first transmitting the cached 5MB of data, and then transmitting the 5MB of data that needs to be sent to the first chip within that 500 milliseconds. After the transmission is complete, the first chip switches back to sleep mode.

[0127] Thus, for the router, the amount of data transmitted to the first chip every second is 10MB, which complies with the router's speed limiting rules.

[0128] It is understandable that, since a key characteristic of Wi-Fi speed-limited scenarios is that the data transmission rate supported by the link is much greater than the data transmission rate limited by the router, electronic devices or chips can complete data transmission even if they only use a portion of the time slots.

[0129] The following is combined with Figure 6 The diagram shown illustrates a data transmission process, illustrating a data transmission method provided in an embodiment of this application.

[0130] In some embodiments, when the chip system detects that it is currently in a Wi-Fi speed-limited scenario, it can determine N first time slots corresponding to the first chip and S second time slots corresponding to the second chip. Then, based on the N first time slots and S second time slots, the first chip and the second chip respectively transmit data with the router. This data transmission process can be referred to... Figure 6 .

[0131] It is understandable that, since the first and second chips operate in a rate-limited scenario, either the first or second chip only needs to occupy a portion of the time slots to transmit data with the router, thus completing the data transmission limit imposed by the router. Furthermore, by coordinating their time slots, both the first and second chips can operate in the highest rate-limited scenario (i.e., the data transmission rate can be the highest rate within the router's limits), while also avoiding mutual interference between the two chips.

[0132] like Figure 6As shown, both the first and second time slots are 500 milliseconds. During the first 500 milliseconds, the first chip is initially in an active state, transmitting data, while the second chip is in a sleep state. The first device can transmit 5MB of first data to the first chip, and the first device can buffer 5MB of second data. During the second 500 milliseconds, the first chip can switch from an active state to a sleep state, ceasing data transmission with the first device, while the second chip can switch from a sleep state to an active state. The first device can transmit the 5MB of second data buffered in the previous 500 milliseconds, as well as the 5MB of data to be transmitted in the current 500 milliseconds, to the second chip, and the first device can buffer the 5MB of first data in the current 500 milliseconds. This process continues in this manner.

[0133] In this way, the first chip and the second chip can transmit data with the first device respectively, the data transmission rate can meet the speed limit rules of the first device, and they will not interfere with each other.

[0134] The following is combined with Figure 7 The schematic diagram shown illustrates the structure of a chip system 100 provided in an embodiment of this application.

[0135] like Figure 7 As shown, a chip system 100 provided in this application embodiment includes a processor 101, a first chip 102 and a second chip 103, wherein the processor 101 includes a scene recognition module 1011, a time slot arbitration module 1012, a first chip driver module 1013 and a second chip driver module 1014.

[0136] The scene recognition module 1011 can be used to identify the current scene of the chip system 100, such as a speed-limited scene, a concurrent scene (i.e. a scene where data transmission needs to be performed in parallel by two chips), etc.

[0137] The time slot arbitration module 1012 can be used to determine the N first time slots corresponding to the first chip 102 and the S second time slots corresponding to the second chip 103 in the chip system 100.

[0138] The first chip driver module 1013 can be used to drive the first chip 102.

[0139] The second chip driver module 1014 can be used to drive the second chip 103.

[0140] The first chip 102 and the second chip 103 can be used to transmit data with other devices (such as the first device).

[0141] The following is based on Figure 7 The chip system 100 shown, taking a router 200 as the first device, and the first chip and the second chip respectively transmitting data with the first device as an example, is combined with... Figure 8Aand Figure 8B This application introduces a data transmission method provided by an embodiment.

[0142] In some embodiments, there is a physical connection channel between the first chip 102 and the second chip 103.

[0143] like Figure 8A As shown, in this data transmission method, the scene recognition module 1011 identifies that the current scene requires data transmission from both the first chip and the second chip, such as a rate-limited scene or a concurrent scene. The scene recognition module 1011 can then send a time slot arbitration command to the time slot arbitration module 1012. The time slot arbitration module 1012 can perform time slot arbitration to determine N first time slots and S second time slots. Afterwards, the time slot arbitration module 1012 can send a drive command and the first time slots to the first chip driver module 1013, and can also send the drive command and the second time slots to the second chip driver module 1014. Then, the first chip driver module 1013 can send the first time slots to the first chip 102 and send a first drive command to drive the first chip 102; the second chip driver module 1014 can send the second time slots to the second chip 103 and send a second drive command to drive the second chip 103.

[0144] During data transmission, at the beginning of each first time slot, the first chip 102 can send a first notification to the second chip 103, which may indicate that the first chip 102 has switched to an active state. At the end of each first time slot, the first chip 102 can send a second notification to the second chip 103, which may indicate that the first chip 102 has switched to a sleep state. Furthermore, at the beginning of each second time slot, the second chip 103 can send a third notification to the first chip 102, which may indicate that the second chip 103 has switched to an active state. At the end of each second time slot, the second chip 103 can send a fourth notification to the first chip 102, which may indicate that the first chip has switched to a sleep state.

[0145] It is understood that the first chip 102 can obtain the status of the second chip 103 through a physical connection channel, and the second chip 103 can obtain the status of the first chip 102 through a physical connection channel. In this way, the first and second chips can work together in a coordinated manner, thereby avoiding mutual interference and ensuring data transmission efficiency.

[0146] In some embodiments, the data transmission method provided in this application can be referred to Figure 8B .like Figure 8B As shown, the method includes:

[0147] S801, the scene recognition module 1011 recognizes speed-limited scenes or concurrent scenes.

[0148] It is understandable that when the scene recognition module 1011 recognizes that the current scene is a speed-limited scene or a concurrent scene, it can determine that data transmission needs to be performed with the router 200 through the first chip 102 and the second chip 103 respectively.

[0149] S802, the scene recognition module 1011 sends a time slot arbitration command to the time slot arbitration module 1012.

[0150] S803, the time slot arbitration module 1012 determines the first time slot and the second time slot based on business information.

[0151] In some embodiments, the time slot arbitration module 1012 can determine N first time slots and S second time slots based on service information. The first and second time slots are related to the service information, as can be seen from the relevant description in S301 above, which will not be repeated here.

[0152] It is understandable that after the time slot arbitration module 1012 determines the first time slot and the second time slot, if the first chip 102 is driven and the second chip 103 is not driven, the time slot arbitration module 1012 can also instruct the second chip driver module 1014 to send a second driving command to the second chip 103 to drive the second chip 103. In this case, the first chip 102 can be considered the main chip and the second chip 103 the secondary chip. If neither the first chip 102 nor the second chip 103 is driven, the time slot arbitration module 1012 can instruct the first driver module 1013 to send a first driving command to the first chip 102 to drive the first chip 102, and can instruct the second chip driver module 1014 to send a second driving command to the second chip 103 to drive the second chip 103.

[0153] It should be noted that the above-mentioned main chip and sub-chip are merely illustrative descriptions, and this application does not limit the first chip and the second chip to have a main-sub relationship.

[0154] S804A, the time slot arbitration module 1012 sends the second time slot to the second chip 103.

[0155] S804B, the time slot arbitration module 1012 sends the first time slot to the first chip 102.

[0156] S805, the first chip 102 sends the first notification to the second chip 103 and the router 200.

[0157] In some embodiments, the first time slot is longer than the second time slot. After receiving the first time slot, the first chip 102 can first switch its state to the working state and send a first notification to the second chip 103 and the router 200.

[0158] It is understandable that the moment when the first chip 102 sends the first notification can be considered as the start time of the first time slot.

[0159] For example, the first notification could be a trigger frame.

[0160] S806, the first chip 102 transmits data with the router 200.

[0161] It is understandable that after receiving the first notification, router 200 can begin data transmission with the first chip 102.

[0162] S807, the first chip 102 sends a second notification to the second chip 103 and the router 200.

[0163] It is understandable that the moment when the first chip 102 sends the second notification is the moment when the first time slot ends, and after the first chip 102 sends the second notification, it can switch to a sleep state.

[0164] S808, the second chip 103 sends a third notification to the first chip 102 and the router 200.

[0165] In some embodiments, after receiving the second notification, the second chip 103 can switch to an operating state and send a third notification to the first chip 102 and the router 200. After receiving the second notification, the router 200 can stop data transmission with the first chip 102.

[0166] It is understood that during the first time slot mentioned above, the second chip 103 is in a sleep state. Furthermore, the moment when the second chip 103 sends the third notification can be considered the start of the second time slot.

[0167] For example, a third notification could be a trigger frame.

[0168] S809, the second chip 103 transmits data with the router 200.

[0169] It is understandable that after receiving the third notification, router 200 can begin data transmission with the second chip 103.

[0170] S810, the second chip 103 sends a fourth notification to the first chip 102 and the router 200.

[0171] It is understandable that the moment when the second chip 103 sends the fourth notification is the moment when the second time slot ends, and after the second chip 103 sends the fourth notification, it can switch to a sleep state.

[0172] It should be noted that S805 to S810 above only illustrate the data transmission process within a first time slot and a second time slot. In subsequent data transmission processes, the process described in S805 to S810 can be repeated.

[0173] It is understandable that after receiving the second time slot, the second chip 103 can also switch its state to the working state and send a third notification to the first chip 102 and the router 200. That is, the above S808 to S810 can also be executed before S805 to S807.

[0174] Thus, the data transmission method provided in this application can avoid the problem of mutual interference when two chips in the same chip system run concurrently, thereby ensuring data transmission efficiency and system performance.

[0175] The following is based on Figure 7 The chip system 100 shown, taking a router 200 as the first device, and the first chip and the second chip respectively transmitting data with the first device as an example, is combined with... Figure 9A and Figure 9B This application introduces a data transmission method provided by an embodiment.

[0176] In some embodiments, there is no physical connection channel between the first chip 102 and the second chip 103.

[0177] like Figure 9A As shown, in this data transmission method, the scene recognition module 1011 identifies that the current scene requires both the first chip and the second chip to transmit data with the first device. For example, if the current scene is a speed-limited scene or a concurrent scene, the scene recognition module 1011 can send a time slot arbitration command to the time slot arbitration module 1012. The time slot arbitration module 1012 can perform time slot arbitration to determine N first time slots and S second time slots. Then, the time slot arbitration module 1012 can send a drive command and the first time slots to the first chip driver module 1013, and can also send the drive command and the second time slots to the second chip driver module 1014. Afterwards, the first chip driver module 1013 can send the first time slots to the first chip 102 and send a first drive command to drive the first chip 102; the second chip driver module 1014 can send the second time slots to the second chip 103 and send a second drive command to drive the second chip 103.

[0178] During data transmission, the processor 101 can periodically send time synchronization markers to the first chip and the second chip. The first chip and the second chip can each include a timer, and upon receiving the time synchronization marker, the duration of the timer within the chip can be set.

[0179] It is understandable that, without a physical connection between the first and second chips, they cannot directly notify each other of their status. Therefore, the first and second chips can synchronize their time using a time synchronization flag sent by the processor to achieve coordinated operation and avoid mutual interference.

[0180] In some embodiments, the data transmission method provided in this application can be referred to Figure 9B .like Figure 9B As shown, the method includes:

[0181] S901, the scene recognition module 1011 recognizes speed-limited scenes or concurrent scenes.

[0182] S902, Scene Recognition Module 1011 sends Time Slot Arbitration Command.

[0183] S903, the time slot arbitration module 1012 determines the first time slot and the second time slot based on business information.

[0184] The above S901 to S903 can be referred to the relevant descriptions of S801 to S803 mentioned above, and will not be repeated here.

[0185] S904A, the time slot arbitration module 1012 sends the second time slot and time synchronization mark to the second chip 103.

[0186] S904B, the time slot arbitration module 1012 sends the first time slot and time synchronization flag to the first chip 102.

[0187] It is understandable that, since there is no physical connection channel between the first chip and the second chip, the time slot arbitration module 1012 can send time synchronization flags to the first chip 102 and the second chip 103. The first chip 102 and the second chip 103 can synchronize their time through the time synchronization flags to achieve coordinated operation and avoid mutual interference.

[0188] S905, the first chip 102 sends the first notification to the router 200.

[0189] In some embodiments, if the first chip 102 includes a first timer, before the first chip 102 sends the first notification (i.e., before the first time slot begins), the first chip 102 may set the duration of the first timer to be equal to the first time slot.

[0190] S906, the first chip 102 transmits data with the router 200.

[0191] S907, the first chip 102 sends a second notification to the router 200.

[0192] In some embodiments, after the first timer in the first chip 102 finishes timing, the first chip 102 can send a second notification to the router 200 to stop data transmission with the router 200.

[0193] S908, the second chip 103 sends a third notification to router 200.

[0194] In some embodiments, the second chip 103 includes a second timer. Before the first chip 102 sends the first notification (i.e., before the first time slot begins), the second chip 103 can set the duration of the second timer to be equal to the first time slot. After the second timer expires, the second chip 103 can send a third notification to the router 200. Furthermore, the second chip 103 can again set the duration of the second timer to be equal to the second time slot.

[0195] In some embodiments, at the end of the second timer's timing, the second chip 103 can start channel listening to monitor the status of the channel corresponding to the first chip 102. If the second chip 103 detects that the channel corresponding to the first chip 102 is in an idle state, the second chip 103 can send a third notification to the first device to start data transmission with the first device.

[0196] It is understandable that when the second chip 103 re-sets the duration of the second timer to be equal to the second time slot, the second chip 103 can start channel listening. That is, during the timing of the second timer, after the second chip 103 has listened to the channel corresponding to the first chip 102 and found it to be in an idle state, the second chip 103 will start transmitting data with the first device.

[0197] S909, the second chip 103 transmits data with the router 200.

[0198] S910, the second chip 103 sends the fourth notification to router 200.

[0199] In some embodiments, after the second timer in the second chip 103 finishes timing, the second chip 103 can send a fourth notification to the router 200 to stop data transmission with the router 200.

[0200] It is understood that the second chip 103 and the router 200 transmit data and send notifications through the channel. When the second timer in the second chip 103 expires, the second chip 103 can reset the duration of the second timer to the first time slot. If the data corresponding to the second time slot is not fully transmitted, the channel corresponding to the second chip 103 is in a busy state. Only after this portion of the data transmission is complete can the second chip 103 send the fourth notification to the router 200.

[0201] S911, the time slot arbitration module 1012 sends a time synchronization flag to the first chip 102 and the second chip 103.

[0202] It is understood that the time slot arbitration module 1012 can periodically send time synchronization markers to the first chip 102 and the second chip 103. For example, it can send a faint time synchronization marker every 1 second.

[0203] It should be noted that S905 to S911 above only illustrates the data transmission process within a first time slot and a second time slot. In subsequent data transmission processes, the process described in S905 to S911 can be repeated.

[0204] It should be understood that the above Figure 8B and Figure 9B The order of the sequence numbers does not represent the execution order. For example, S804A and S804B can be executed in parallel, or S804A can be executed first and then S804B, or S804B can be executed first and then S804A. Similarly, S904A and S904B can be executed in parallel, or S904A can be executed first and then S904B, or S904B can be executed first and then S904A.

[0205] Thus, the data transmission method provided in this application can avoid the problem of mutual interference when two chips in the same chip system run concurrently, thereby ensuring data transmission efficiency and system performance.

[0206] This application provides a readable storage medium storing instructions that, when executed on an electronic device, cause the electronic device to perform the data transmission method mentioned in this application.

[0207] This application provides a computer program product that includes computer instructions. When executed by an electronic device, the electronic device executes the computer program code of the data transmission method mentioned in this application.

[0208] This application provides an electronic device, including a chip system, which is used to execute the data transmission method mentioned in this application.

[0209] This application also provides an electronic device, including: a memory for storing instructions executed by one or more processors of the electronic device, and a processor, which is one of the one or more processors of the electronic device, for executing the data transmission method mentioned in this application.

[0210] The electronic devices mentioned in the embodiments of this application include, but are not limited to, mobile stations (MS) and mobile terminals (MT). For example, electronic devices can be mobile phones, smart TVs, wearable devices, tablets, desktop computers, laptops, virtual reality (VR) devices, augmented reality (AR) devices, terminals in industrial control, terminals in self-driving vehicles, terminals in remote medical surgery, terminals in smart grids, terminals in transportation safety, terminals in smart cities, terminals in smart homes, and so on. The embodiments of this application do not limit the specific form of the electronic devices.

[0211] The hardware structure of the electronic device provided in the embodiments of this application will be described exemplarily below.

[0212] like Figure 10 As shown, the electronic device 00 may include a chip system 100, a processor 101, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, antenna 1, antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a sensor module 180, buttons 190, a motor 191, an indicator 192, a camera 193, a display screen 194, and a subscriber identification module (SIM) card interface 195, etc. The chip system 100 includes a first chip 102 and a second chip 103. The sensor module 180 may include a touch sensor 180K, etc., and the audio module 170 may include a microphone 170A, etc.

[0213] It is understood that the structures illustrated in the embodiments of the present invention do not constitute a specific limitation on the electronic device. In other embodiments of this application, the electronic device 00 may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0214] Processor 101 may include one or more processing units, such as a CPU, application processor (AP), modem processor, graphics processing unit (GPU), image signal processor (ISP), controller, video codec, digital signal processor (DSP), baseband processor, and / or neural network processor. Different processing units may be independent devices or integrated into one or more processors. In some embodiments, processor 101, in conjunction with chip system 100, can execute the data transmission methods mentioned in the embodiments of this application.

[0215] In some optional implementations, the processor 101 may include a scene recognition module 1011, a time slot arbitration module 1012, a first chip driver module 1013, and a second chip driver module 1014.

[0216] The charging management module 140 receives charging input from the charger. The power management module 141 connects to the battery 142, and the charging management module 140 connects to the processor 101. The power management module 141 receives input from the battery 142 and / or the charging management module 140 to power the processor 101, internal memory 121, display 194, camera 193, and wireless communication module 160, etc.

[0217] The electronic device 00 implements display functions through a GPU, a display screen 194, and an application processor. The GPU is a microprocessor for image processing, connecting the display screen 194 and the application processor. The display screen 194 is used to display images, videos, etc. The display screen 194 includes a display panel. In some embodiments, the electronic device 00 may include one or N displays screens 194, where N is a positive integer greater than 1.

[0218] Electronic device 00 can implement shooting functions through an ISP, camera 193, video codec, GPU, display 194, and application processor. The ISP is used to process data fed back by camera 193. Camera 193 is used to capture still images or videos. In some embodiments, electronic device 00 may include one or N cameras 193, where N is a positive integer greater than 1. The video codec is used to compress or decompress digital video.

[0219] The external memory interface 120 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the electronic device 00. The external memory card communicates with the processor 101 through the external memory interface 120 to perform data storage. The internal memory 121 can be used to store computer executable program code, which includes instructions.

[0220] Electronic device 00 can implement audio functions through audio module 170 and application processor, such as music playback and recording. Audio module 170 is used to convert digital audio information into analog audio signals for output, and also to convert analog audio input into digital audio signals. Audio module 170 can also be used for encoding and decoding audio signals.

[0221] The touch sensor 180K, also known as a "touch device," can be located on the display screen 194. The touch sensor 180K and the display screen 194 together form a touchscreen, also known as a "touchscreen." Buttons 190 include a power button, volume buttons, etc. The motor 191 can generate vibration alerts. The motor 191 can be used for incoming call vibration alerts or for touch vibration feedback. The indicator 192 can be an indicator light used to indicate charging status. The SIM card interface 195 is used to connect a SIM card.

[0222] It is understood that, as used herein, the term “module” may refer to or include, or be part of, an application-specific integrated circuit (ASIC), electronic circuitry, a processor (shared, dedicated, or grouped) and / or memory that executes one or more software or firmware programs, combinational logic circuitry, and / or other suitable hardware components that provide the described functionality.

[0223] It is understood that in the various embodiments of this application, the processor may be a microprocessor, a digital signal processor, a microcontroller, etc., and / or any combination thereof. According to another aspect, the processor may be a single-core processor, a multi-core processor, etc., and / or any combination thereof.

[0224] The embodiments disclosed in this application can be implemented in hardware, software, firmware, or a combination of these implementation methods. Embodiments of this application can be implemented as computer programs or program code executable on a programmable system, the programmable system including at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0225] Program code can be applied to input instructions to execute the functions described in this application and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, the processing system includes any system having a processor such as, for example, a digital signal processor, a microcontroller, an application-specific integrated circuit, or a microprocessor.

[0226] The program code can be implemented using a high-level procedural language or an object-oriented programming language to communicate with the processing system. Assembly language or machine language can also be used when needed. In fact, the mechanisms described in this application are not limited to any particular programming language. In either case, the language can be a compiled language or an interpreted language.

[0227] In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried or stored thereon on one or more temporary or non-temporary machine-readable (e.g., computer-readable) storage media, which may be read and executed by one or more processors. For example, the instructions may be distributed via a network or through other computer-readable media. Therefore, machine-readable media may include any mechanism for storing or transmitting information in a machine-readable (e.g., computer-readable) form, including but not limited to floppy disks, optical disks, optical discs, magneto-optical disks, read-only memory (ROM), random access memory (RAM), electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic cards or optical cards, flash memory, or tangible machine-readable storage for transmitting information (e.g., carrier waves, infrared signals, digital signals, etc.) using the Internet in the form of electrical, optical, acoustic, or other forms of propagated signals. Therefore, machine-readable media includes any type of machine-readable medium suitable for storing or transmitting electronic instructions or information in a machine-readable (e.g., computer-readable) form.

[0228] In the accompanying drawings, some structural or methodological features may be shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order may not be necessary. Rather, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. Furthermore, the inclusion of structural or methodological features in a particular figure does not imply that such features are required in all embodiments, and in some embodiments, these features may be omitted or may be combined with other features.

[0229] It should be noted that all units / modules mentioned in the device embodiments of this application are logical units / modules. Physically, a logical unit / module can be a physical unit / module, a part of a physical unit / module, or a combination of multiple physical units / modules. The physical implementation of these logical units / modules themselves is not the most important factor; the combination of functions implemented by these logical units / modules is the key to solving the technical problems proposed in this application. Furthermore, to highlight the innovative aspects of this application, the above-described device embodiments of this application have not introduced units / modules that are not closely related to solving the technical problems proposed in this application. This does not mean that the above-described device embodiments do not contain other units / modules.

[0230] It should be noted that in the examples and description of this application, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0231] Although this application has been illustrated and described with reference to certain embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made thereto without departing from the scope of this application.

Claims

1. A data transmission method, characterized in that, Applied to a chip system, the chip system including a first chip and a second chip, the method includes: N first time slots and S second time slots are determined, wherein the first time slots and the second time slots are adjacent time slots; wherein, The first time slot is used to transmit the first data corresponding to the first chip and to cache the second data corresponding to the second chip. The second time slot is used to cache the first data corresponding to the first chip and to transmit the second data corresponding to the second chip. The first time slot and the second time slot are related to service information. N and S are positive integers. Based on the N first time slots and the S second time slots, the first chip and the second chip respectively perform data transmission.

2. The method according to claim 1, characterized in that, The service information includes service priority, the quantity of service data, or the transmission requirements of service data. The first time slot and the second time slot are related to the service information, including: The service priority of the first chip is higher than that of the second chip; or, the amount of service data in the first chip is greater than that in the second chip; or, the transmission demand of the service data in the first chip is higher than that in the second chip, and the first time slot is larger than the second time slot; or... The service priority of the first chip is lower than that of the second chip, or the amount of service data of the first chip is less than that of the second chip, or the transmission requirement of the service data of the first chip is lower than that of the second chip, and the first time slot is smaller than the second time slot.

3. The method according to claim 1 or 2, characterized in that, The method further includes a physical connection channel between the first chip and the second chip. At the beginning of the first time slot, the first chip sends a first notification to the first device and the second chip respectively. The first notification instructs the first chip to start data transmission with the first device. At the end of the first time slot, the first chip sends a second notification to the first device and the second chip respectively. The second notification instructs the first chip to stop data transmission with the first device. At the start of the second time slot, the second chip sends a third notification to the first device and the first chip respectively. The third notification instructs the second chip to start data transmission with the first device. At the end of the second time slot, the second chip sends a fourth notification to the first device and the first chip respectively. The fourth notification instructs the second chip to stop data transmission with the first device.

4. The method according to claim 3, characterized in that, The method further includes: The first chip or the second chip adjusts the first time slot or the second time slot according to the state of the data transmission.

5. The method according to claim 4, characterized in that, The step of adjusting the first time slot or the second time slot according to the state of the data transmission includes: If the transmission of a portion of the data corresponding to the first or second time slot is not completed at the end of the first or second time slot, the time slot length of the first or second time slot is increased to transmit the portion of the data.

6. The method according to claim 1 or 2, characterized in that, There is no physical connection channel between the first chip and the second chip, and the method further includes: The first chip and the second chip acquire time synchronization markers from the processor, and adjust the start and end times of the first time slot and / or the start and end times of the second time slot based on the time synchronization markers.

7. The method according to any one of claims 1 to 6, characterized in that, The method further includes: The system detects that the first device limits the maximum amount of data transmitted per unit time, or detects that there is interference between the first chip and the second chip.

8. A data transmission method, characterized in that, Applied to a first device, the method includes: In response to the transmission request of the first data corresponding to the first chip in the chip system, within N first time slots, the first data is transmitted to the first chip, and the second data corresponding to the second chip in the chip system is buffered. In response to the transmission request of the second data corresponding to the second chip in the chip system, the second data is transmitted with the second chip within S second time slots, and the first data is buffered; wherein, The first time slot and the second time slot are adjacent time slots. The first time slot and the second time slot are related to the service information of the chip system. N and S are positive integers.

9. The method according to claim 8, characterized in that, The business information includes business priority, the amount of business data, or the data transmission requirements of the business. The first time slot and the second time slot are related to the business information, including: The service priority of the first chip is higher than that of the second chip; or, the amount of service data in the first chip is greater than that in the second chip; or, the transmission demand of the service data in the first chip is higher than that in the second chip, and the first time slot is larger than the second time slot; or... The service priority of the first chip is lower than that of the second chip, or the amount of service data of the first chip is less than that of the second chip, or the transmission requirement of the service data of the first chip is lower than that of the second chip, and the first time slot is smaller than the second time slot.

10. The method according to claim 8 or 9, characterized in that, The method further includes: At the beginning of the first time slot, a first notification is received, which instructs the first chip to start data transmission with the first device. At the end of the first time slot, a second notification is received, which instructs the first chip to stop data transmission with the first device. At the beginning of the second time slot, a third notification is received, which instructs the second chip to start data transmission with the first device. At the end of the second time slot, a fourth notification is received, which instructs the second chip to stop data transmission with the first device.

11. The method according to claim 10, characterized in that, At the end of the first time slot or the second time slot, the transmission of a portion of the data corresponding to the first time slot or the second time slot is not completed. The first time slot or the second time slot is a time slot after the first chip or the second chip increases the time slot length according to the data transmission status. The increased time slot length is used to transmit the portion of the data.

12. The method according to any one of claims 8 to 11, characterized in that, The method further includes: The maximum amount of data transmitted per unit time is limited.

13. An electronic device, characterized in that, It includes a chip system for performing the data transmission method according to any one of claims 1 to 7.

14. An electronic device, characterized in that, include: A memory for storing instructions executed by one or more processors of the electronic device, and a processor, being one of one or more processors of the electronic device, for performing the data transmission method according to any one of claims 1 to 7 or 8 to 12.

15. A readable storage medium, characterized in that, The readable storage medium stores instructions that, when executed on an electronic device, cause the electronic device to perform the data transmission method of any one of claims 1 to 7 or 8 to 12.

16. A computer program product, characterized in that, The computer program product includes computer instructions that, when executed by an electronic device, enable the electronic device to execute the computer program code of the data transmission method according to any one of claims 1 to 7 or 8 to 12.

Images