A multi-channel high-precision synchronous constant current LED driving circuit, system and method

Abstract

The application relates to a multi-path high-precision synchronous constant-current LED driving circuit, system and method. The circuit comprises a hierarchical isolated power supply module, a micro-processing control module and an LED constant-current driving module; the hierarchical isolated power supply module realizes high-efficiency DC-DC conversion by using a step-down chip in cooperation with a power inductor, and outputs a logic voltage with extremely low ripple via a linear voltage stabilizer; the micro-processing control module provides a stable system clock reference; the LED constant-current driving module operates in a cascade mode through two driving chips, and realizes constant-current output control of multiple paths of LEDs by using a built-in shift register mechanism. According to the application, the hierarchical isolated power supply is adopted, the LED power loop is powered by a high-efficiency 5V power supply, and the digital logic loop is powered by a low-noise 3.3V linear voltage stabilizing power supply, so that the heat generation and energy consumption of the whole machine are reduced, the influence of the ripple of the switching power supply on the gray scale counting and serial communication is reduced, and the light output stability is improved.

Description

Technical Field

[0001] This application relates to the field of circuit control, and in particular to a multi-channel high-precision synchronous constant current LED driving circuit, system, and method. Background Technology

[0002] Existing multi-channel constant current LED dimming control systems typically employ a microcontroller in conjunction with multi-channel constant current driver chips. Their basic structure often involves a single power supply, simple cascading of driver chips, and direct binding of the program to the physical channels. This type of solution can meet the requirements for LED lighting and basic brightness adjustment and has been used in scenarios such as equipment indicators and small lighting devices. A common implementation is as follows: an external DC power supply is stepped down in a single stage to simultaneously power the microcontroller, driver chips, and LED load; multiple constant current driver chips are cascaded only through serial data input and output connections, sharing a common basic clock and latch signal; the control program directly writes grayscale data according to the physical output order of the driver chips and generates the dimming cycle using a simple delay or timed refresh method; the output current mainly depends on the reference resistor setting of the driver chip, and usually lacks independent power-on protection and output current detection and calibration structures.

[0003] Traditional cascaded solutions often focus on the sequential shifting of serial data, lacking a unified reset, latch, and refresh timing design that matches the grayscale counting period. During the refresh process, multiple driver chips may experience data arrival and latching time differences, leading to asynchronous brightness updates across multiple channels. When the refresh frequency increases, without reserving necessary communication dead zones, serial timing and PWM windows can easily interfere with each other, causing waveform truncation, distortion, or linear grayscale decreases, affecting the smoothness and stability of brightness gradients. Summary of the Invention

[0004] Therefore, it is necessary to provide a multi-channel high-precision synchronous constant current LED driving circuit, system, and method for multi-channel brightness update synchronization to address the above-mentioned technical problems.

[0005] One type of multi-channel high-precision synchronous constant current LED driver circuit includes: Hierarchical isolation power supply module, microprocessor control module and LED constant current drive module; The graded isolation power supply module uses a step-down chip in conjunction with a power inductor to achieve efficient DC-DC conversion, and outputs a logic voltage with extremely low ripple via a linear regulator; The microprocessor control module provides a stable system clock reference; The LED constant current driver module operates by cascading two driver chips and utilizes its built-in shift register mechanism to achieve constant current output control for multiple LEDs.

[0006] Furthermore, the graded isolation power supply module adopts a two-level power supply architecture, which separates the power supply for LED power loads from the power supply for digital logic, including: a 112V to 5V DC-DC unit and a 5V to 3.3V LDO unit; 12V to 5V DC-DC unit: Uses TPS54340 step-down chip, externally configured with power inductor and freewheeling diode, and uses voltage divider resistors at the feedback end to obtain a stable 5V output for powering LED power loads; high and low capacitance filter capacitors are set at the input and output ends respectively, and the capacitor withstand voltage margin is reserved; the chip's soft-start function is used to suppress power-on surges to ensure high conversion efficiency and low heat generation.

[0007] 5V to 3.3V LDO unit: Employs ME6211 low dropout linear regulator to provide separate power to the microcontroller and driver chip logic circuits; two filter capacitors are connected in parallel at its input to filter out high-frequency switching noise introduced by the preceding DC-DC converter; a combined capacitor is set at the output to further smooth the voltage, thereby providing a stable, low-noise 3.3V logic power supply for serial transmission and grayscale counting.

[0008] Furthermore, the microprocessor control module specifically employs an STM32F103C8T6, equipped with an 8MHz high-speed external crystal oscillator, and frequency-multiplied to a 72MHz system clock via a phase-locked loop; it is equipped with an RC reset circuit consisting of resistors and capacitors to form a stable power-on delay; the BOOT pin is configured with a startup selection circuit, leading out the SWD dual-wire debug interface and the USART1 serial port, and reserving hardware button input pins to provide a control basis for system timing control, grayscale data transmission, and human-machine interaction.

[0009] Furthermore, the LED constant current drive module specifically comprises: Two TLC5940 chips are cascaded in a daisy chain, enabling multiple output channels. Unused channels can be reserved or configured to be off. High-precision constant current setting and detection circuit: The single-channel constant current output is set according to the chip output current calculation relationship; each LED output branch is connected in series with a precision sampling resistor. The voltage drop across the sampling resistor is measured by a multimeter and the actual output current is calculated for debugging, calibration and consistency verification. Hardware power-on self-locking protection circuit: The BLANK pin of each TLC5940 is uniformly pulled up to 3.3V through a resistor; before the microcontroller power-on reset and GPIO initialization are completed, BLANK is kept at a high level, the output of the driver chip is forcibly turned off, and all LEDs are turned off by default; after the main control is initialized, the software releases BLANK in sequence, thereby avoiding random flickering and instantaneous current surges at power-on; Synchronous cascaded routing: The SOUT pin of the front-end TLC5940 is connected to the SIN pin of the rear-end TLC5940. The two chips share the SCLK, XLAT, GSCLK and BLANK control signals. The STM32 timer multiplexed output stabilizes the GSCLK grayscale reference clock, while the relative timing of SCLK, XLAT and BLANK is controlled by software, so that the cascaded chips complete data shifting, latching and output updating within the same grayscale period.

[0010] Furthermore, it also includes: SWD debugging interface, USART asynchronous communication module and button circuit with software debouncing function; Furthermore, this invention also provides a multi-channel high-precision synchronous constant current LED driving system, comprising: Application interaction layer: responsible for key scanning and status management of the hierarchical isolation power supply module; Hardware mapping layer: Utilizes mapping tables to shield physical wiring differences and realize the reconstruction of logical brightness data into cascaded bit streams; The underlying driver transmission layer utilizes bit operations to simulate a synchronous serial protocol to drive the cascaded operation of LED constant current driver modules; multi-channel synchronous dimming and stable refresh are achieved through the GSCLK pulse generated by the hardware timer and the precise delay calibration of the microprocessor control module.

[0011] Furthermore, the hardware mapping layer specifically comprises: The user-defined grayscale data array represents the application layer's independent control requirements for the brightness of each LED. The hardware abstraction layer, based on predefined... The mapping table reorganizes user-level data to... In the cascaded buffer.

[0012] Furthermore, the specific steps for cascading LED constant current drive modules using bit manipulation to simulate a synchronous serial protocol are as follows: The program simulates synchronous serial protocol communication with a cascaded TLC5940 chip via software. During the transmission phase, the program uses a nested loop structure... Driven by the engine, 384 bits of serial data are sequentially shifted into the chip's shift register. After data transmission is complete, the drive engine controls... The pin generates a latch pulse, synchronously loading the data in the shift register into the PWM control register of each channel. Furthermore, to ensure electrical safety during power-up, this is enforced at the protocol layer. The pull-up logic on the pin continues until the data latching operation is completed.

[0013] Furthermore, multi-channel synchronous dimming and stable refresh are achieved through the GSCLK pulse generated by the hardware timer and the precise delay calibration of the microprocessor control module. Specifically: The main architecture adopts a state machine-based task polling architecture; during each refresh cycle, different branches are executed based on the global variable LED_Power_State: in the on state, periodic branches are executed. Reset to trigger the 4096-level grayscale counting inside the driver chip.

[0014] Furthermore, this invention also provides a method for driving multiple high-precision synchronous constant current LEDs, including: In the data preparation phase, firstly through The hardware mapping table resolves the differences between physical wiring and logic control, accurately filling the user-defined multi-channel brightness data into the 32-channel physical buffer. Subsequently, the drive engine enters the serial transmission stage, using bit operations to simulate the communication timing of the TLC5940. In the specific bit manipulation loop, data shifting is achieved through nested loops: the outer loop iterates through the 32 channels in the cascaded system, while the inner loop is responsible for stripping the 12-bit grayscale data of each channel bit by bit, starting from the most significant bit; for each bit of data sent, a level is first placed on the pin, and then pulled high. A rising edge on the pin forces the TLC5940's internal shift register to capture the bit; once all 384 bits of data required by the two cascaded chips have been shifted in, the program will generate a... The latch pulse; the rising edge of this pulse loads the data in the shift register into the internal grayscale control register in one go, thus ensuring the instantaneous synchronization of multiple LEDs when updating their brightness. This is achieved using the STM32's TIM1 timer. A stable square wave signal is generated on the pin as a reference for the grayscale control of the TLC5940, through communication with... The precise coordination of signals enabled the accurate display of 4096 gray levels in each frame.

[0015] This invention utilizes a tiered isolated power supply, with the LED power circuit powered by a high-efficiency 5V power supply and the digital logic circuit powered by a low-noise 3.3V linear regulated power supply. This reduces overall heat generation and energy consumption, while also minimizing the impact of switching power supply ripple on grayscale counting and serial communication, thereby improving the stability of light output. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a multi-channel high-precision synchronous constant current LED driving circuit in one embodiment; Figure 2 This is a block diagram of a multi-channel high-precision synchronous constant current LED driving system in one embodiment. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0018] Example 1: This embodiment provides, as follows: Figure 1 The multi-channel high-precision synchronous constant current LED driver circuit shown includes: Hierarchical isolation power supply module, microprocessor control module and LED constant current drive module; The graded isolation power supply module uses a step-down chip in conjunction with a power inductor to achieve efficient DC-DC conversion, and outputs a logic voltage with extremely low ripple via a linear regulator; The microprocessor control module provides a stable system clock reference; The LED constant current driver module operates by cascading two driver chips and utilizes its built-in shift register mechanism to achieve constant current output control for multiple LEDs.

[0019] 1. Hierarchical isolation power supply module (used to balance power supply efficiency and low noise in logic circuits) This module adopts a two-stage power supply architecture, separating the power supply for the LED power load from the power supply for the digital logic: (1) 12V to 5V DC-DC unit: The TPS54340 step-down chip is selected, and an external 10μH power inductor and 3A freewheeling diode are configured. The feedback terminal uses a 27kΩ and 5.1kΩ voltage divider resistor to obtain a stable 5V output for powering LED power loads. High and low capacitance filter capacitors are set at the input and output terminals respectively, and a margin is left for the capacitor voltage withstand. The chip's soft-start function is used to suppress power-on surges to ensure high conversion efficiency and low heat generation.

[0020] (2) 5V to 3.3V LDO unit: The ME6211 low dropout linear regulator is used to provide separate power to the logic circuits of the microcontroller and driver chip. A 100nF and a 1μF filter capacitor are connected in parallel at its input to filter out the high-frequency switching noise introduced by the DC-DC converter in the previous stage; a combined capacitor is set at the output to further smooth the voltage, thereby providing a stable and low-noise 3.3V logic power supply for serial transmission and grayscale counting.

[0021] 2. STM32 Minimum Control System The main control chip is an STM32F103C8T6, equipped with an 8MHz high-speed external crystal oscillator, which is multiplied to a 72MHz system clock via a phase-locked loop. It is equipped with an RC reset circuit consisting of a 10kΩ resistor and a 1μF capacitor to form a stable power-on delay. The BOOT pin is configured with a startup selection circuit, and leads out the SWD dual-wire debug interface and the USART1 serial port. Hardware button input pins are also reserved to provide a control basis for system timing control, grayscale data transmission and human-machine interaction.

[0022] 3. Dual TLC5940 cascaded constant current drive modules (used to improve constant current consistency, power-on safety, and synchronization) Two TLC5940 chips are cascaded in a daisy-chain configuration. In this embodiment, 15 output channels are enabled, while unused channels can be reserved or configured to be disabled. (1) High-precision constant current setting and detection circuit: The IREF pin of the driver chip is connected to a 649Ω precision reference resistor. The single-channel constant current output is set to about 60mA according to the chip output current calculation relationship. Each LED output branch is connected in series with a 33Ω precision sampling resistor. The voltage drop across the sampling resistor can be measured with a multimeter and the actual output current can be calculated for debugging, calibration and consistency verification, thereby reducing the impact of component error and temperature rise on brightness uniformity.

[0023] (2) Hardware power-on self-locking protection circuit: The BLANK pin of each TLC5940 is uniformly pulled up to 3.3V through a 10kΩ resistor. Before the microcontroller power-on reset and GPIO initialization are completed, BLANK is kept at a high level, the output of the driver chip is forcibly turned off, and all LEDs are turned off by default; after the main control is initialized, the software releases BLANK in sequence, thereby avoiding random flickering and instantaneous current surges during power-on.

[0024] (3) Synchronous cascaded wiring: The SOUT pin of the front-end TLC5940 is connected to the SIN pin of the rear-end TLC5940. The two chips share the SCLK, XLAT, GSCLK and BLANK control signals. The STM32 timer multiplexed output stabilizes the GSCLK grayscale reference clock. At the same time, the relative timing of SCLK, XLAT and BLANK is controlled by software, so that the cascaded chips can complete data shifting, latching and output updating within the same grayscale period.

[0025] 4. Human-computer interaction communication interface An onboard pull-up mechanical button is used to switch the LED master switch status locally; at the same time, a USART1 serial port is reserved with a default communication baud rate of 115200, which can be connected to a host computer to send multiple brightness data or control commands, thus taking into account both local operation and remote debugging and centralized control needs.

[0026] In this embodiment, after the external 12V DC power supply is input, it is stepped down to 5V by the TPS54340. One path supplies the LED driving load, and the other path is linearly regulated by the ME6211 to obtain a 3.3V logic power supply. The STM32 main controller collects button signals or receives grayscale data sent from the host computer's serial port, and reassembles the logic channel data into the Real_GS_Buffer hardware buffer through the LED_Map[] mapping table. Then, the software simulates a serial bus to transmit a 384-bit complete grayscale frame to two cascaded TLC5940 chips, and latches all channel data synchronously through the XLAT pulse. The TIM timer continuously outputs the GSCLK clock, and with the 4.3ms refresh cycle and BLANK control timing, it realizes 15 independent, synchronous, approximately 60mA constant current output of LEDs and 12-bit grayscale dimming. During the power-on and reset phases, the BLANK hardware pull-up turns the LEDs off by default, and they enter normal dimming operation after the main controller initialization is completed.

[0027] Example 2: This embodiment provides, as follows: Figure 2 The multi-channel high-precision synchronous constant current LED driving system shown includes: The application layer is responsible for the status management of key scanning and hierarchical isolation power supply modules; The hardware abstraction layer uses a mapping table to shield physical wiring differences and realizes the reconstruction of logical brightness data into a cascaded bit stream; The underlying driver layer uses bit operations to simulate a synchronous serial protocol to drive cascaded LED constant current driver modules. The physical hardware layer achieves multi-channel synchronous dimming and stable refresh through the GSCLK pulse generated by the hardware timer and the precise delay calibration of the microprocessor control module.

[0028] The software adopts a three-layer architecture, consisting of an application interaction layer, a hardware mapping layer, and a low-level driver transmission layer. The main program runs in a non-blocking state machine polling mode, and implements GPIO, timer, serial port, and button function initialization and operation control based on the STM32 standard library, facilitating portability and maintenance.

[0029] 1. Application Interaction Layer Define a global grayscale array GS_Data

[15] to store the independent grayscale values ​​of 15 LEDs, with a value range of 0 to 4095; define the overall switch state variable LED_Power_State to record the overall switch state of the system. The button detection function adopts a software debouncing method, periodically scanning the button level in the main loop, and flipping the overall on / off state after detecting a valid press to achieve local fast control.

[0030] 2. Hardware mapping layer: A custom fixed mapping table, LED_Map[], is used to establish a one-to-one correspondence between user-defined logical LED numbers and the 32 physical output channels of the cascaded TLC5940; a 32-channel hardware grayscale buffer, Real_GS_Buffer, is also set. During program execution, the 15 logical grayscale data channels are first reassembled into their corresponding physical channels based on LED_Map[], and then the underlying layer sends the complete grayscale frame. When the PCB is redesigned, LED positions are adjusted, or the channel order changes, usually only the mapping table needs to be modified, without rewriting the underlying serial transmission logic, thus reducing maintenance and debugging costs.

[0031] 3. Low-level driver transport layer (1) Software simulation of synchronous serial transmission: The program traverses 32 physical channels in a fixed order, outputting 12-bit grayscale data of each channel bit by bit from high bit to low bit, and controlling the data setup time and hold time according to the chip timing requirements. After all 384 bits of grayscale data of the two cascaded chips have been shifted, the XLAT latch pulse is output to update the brightness of all physical channels under the same latching action, thereby reducing the time difference caused by chip-by-chip or channel-by-channel refresh.

[0032] (2) Standardized timing correction and communication dead zone control methods A fixed 4.3ms full PWM refresh cycle is set. Within each cycle, the following steps are executed sequentially: pull BLANK high to reset the grayscale counter and turn off the output, send the complete 384-bit grayscale data, generate the XLAT synchronization latch pulse, release BLANK and start PWM counting. The program reserves approximately 5% communication dead time within the refresh cycle, making the maximum effective output window approximately 95%. This avoids conflicts between serial transmission time and the PWM output window, reduces the risk of waveform truncation and distortion in high-frequency refresh mode, and maintains smooth changes in the 4096 grayscale levels from 0 to 4095.

[0033] (3) System unified initialization function: After the system is powered on, GPIO, timer, serial port and key input are uniformly configured. During the initialization phase, BLANK is pulled high by default to turn off the LED. TIM1 is configured as PWM output mode and continuously outputs GSCLK grayscale reference clock to provide a stable counting reference for the internal grayscale counting of TLC5940.

[0034] This embodiment has the following advantages 1. Advantages in power supply system stability By using DC-DC and LDO hierarchical isolation power supply, the LED power circuit is powered by a high-efficiency 5V power supply, and the digital logic circuit is powered by a low-noise 3.3V linear regulated power supply. This reduces the overall heat generation and energy consumption, and also reduces the impact of switching power supply ripple on grayscale counting and serial communication, which helps to improve the stability of light output.

[0035] 2. Advantages of constant current consistency and power-on protection The output is set to approximately 60mA via a 649Ω reference resistor, and a measurable current verification path is provided via a 33Ω sampling resistor, facilitating the detection and calibration of the output current of each channel and improving the brightness consistency of multiple LEDs. The BLANK hardware pull-up circuit enables the LEDs to be turned off by default during the system power-on phase, eliminating the need for software initialization and reducing power-on flicker and instantaneous current surges.

[0036] 3. Advantages of synchronized dimming timing By using a fixed refresh cycle of 4.3ms, complete 384-bit grayscale frame transmission, XLAT synchronous latching, and approximately 5% communication dead zone control, the two cascaded driver chips are updated synchronously under the same timing, which helps to reduce high-frequency transmission waveform distortion and multi-channel refresh time difference, and achieves smooth dimming under 4096 grayscale commands.

[0037] 4. Advantages of hardware and software decoupling By setting up the LED_Map[] hardware mapping layer and the Real_GS_Buffer hardware buffer, the user logic channel is separated from the physical output channel. When the hardware wiring or LED arrangement changes, only the mapping relationship needs to be adjusted to adapt, while the underlying serial transmission process remains unchanged, thereby shortening the revision and debugging cycle.

[0038] 5. Comprehensive application value This system supports both local button control and serial port remote control. It features universal hardware components, a clear software structure, and complete test data. It is suitable for widespread use in multi-channel LED applications such as instrument backlighting, equipment status indication, small stage lighting, and landscape lighting. It has advantages such as good stability, strong maintainability, and low secondary development costs.

[0039] Example 3: Furthermore, this invention also provides a method for driving multiple high-precision synchronous constant current LEDs, including: In the data preparation phase, firstly through The hardware mapping table resolves the differences between physical wiring and logic control, accurately filling the user-defined multi-channel brightness data into the 32-channel physical buffer. Subsequently, the drive engine enters the serial transmission stage, using bit operations to simulate the communication timing of the TLC5940. In the specific bit manipulation loop, data shifting is achieved through nested loops: the outer loop iterates through the 32 channels in the cascaded system, while the inner loop is responsible for stripping the 12-bit grayscale data of each channel bit by bit, starting from the most significant bit; for each bit of data sent, a level is first placed on the pin, and then pulled high. A rising edge on the pin forces the TLC5940's internal shift register to capture the bit; once all 384 bits of data required by the two cascaded chips have been shifted in, the program will generate a... The latch pulse; the rising edge of this pulse loads the data in the shift register into the internal grayscale control register in one go, thus ensuring the instantaneous synchronization of multiple LEDs when updating their brightness. This is achieved using the STM32's TIM1 timer. A stable square wave signal is generated on the pin as a reference for the grayscale control of the TLC5940, through communication with... The precise coordination of signals enabled the accurate display of 4096 gray levels in each frame.

[0040] Example 4: This embodiment further discloses information based on Embodiment 1: This software system adopts a layered architecture: the application layer is responsible for key scanning and power status management; the hardware abstraction layer uses the LED_Map mapping table to shield physical wiring differences and realize the reconstruction of logical brightness data into a cascaded bit stream; the underlying driver layer uses bit operations to simulate a synchronous serial protocol to drive multiple TLC5940 chips to run in cascade. Through the GSCLK pulse generated by the hardware timer and the precise 4.3ms delay calibration by the software layer, the system finally achieves 12-bit high-resolution synchronous dimming and stable refresh of 15 LEDs.

[0041] Data stream switching and hardware mapping layer The system logic begins with a user-defined grayscale data array. This represents the application layer's requirement for independent control of the brightness of each LED. To address the inconsistency between the physical PCB trace order and the driver chip channel output, a hardware mapping layer was introduced. This layer is based on predefined... The mapping table reorganizes user-level data to... In the cascaded buffer. This design decouples application logic from physical routing, allowing hardware modifications to be made by simply adjusting the mapping table without refactoring the underlying driver.

[0042] Cascaded synchronous transmission The underlying driver module communicates with the cascaded TLC5940 chip via software simulation of a synchronous serial protocol. During the transmission phase, the program uses a nested loop structure... Driven by the system, 384 bits of serial data are sequentially shifted into the chip's shift register. After data transmission is complete, the drive engine controls... The pin generates a latch pulse, synchronously loading the data in the shift register into the PWM control register of each channel. Furthermore, to ensure electrical safety during power-up, the system enforces this at the protocol layer. The pull-up logic on the pin continues until the data latching operation is completed, thereby avoiding illegal outputs that may occur during the initialization phase.

[0043] Real-time task scheduling and timing correction The main program adopts a state machine-based task polling architecture. During each refresh cycle, the system executes different branches based on the global variable LED_Power_State: in the on state, the software performs precise calibration... (corresponding to 11,500) Operation cycle) Execution cycle A reset is initiated to trigger the 4096-level grayscale counting within the driver chip. This timing compensation technology ensures high synchronization between the main control chip and the external driver chip in the grayscale cycle, avoiding waveform truncation at maximum brightness. Simultaneously, the interaction module monitors the button status through non-blocking software debouncing logic, achieving smooth parallel operation of human-computer interaction and LED refresh tasks.

[0044] LED driver implementation The LED driver core of this system is through The function implementation is essentially a software-emulated SPI protocol customized for non-standard word length (12-bit) serial protocols. During the data preparation phase, the program first... The hardware mapping table resolves the discrepancy between physical wiring and logic control, accurately filling the 15 user-defined brightness data channels (GS_Data) into the 32-channel Real_GS_Buffer physical buffer. Subsequently, the driver engine enters the serial transmission phase, using bit operations to simulate the communication timing of the TLC5940. The following diagram shows the serial data input timing of the LED driver module from the datasheet.

[0045] In the specific bit manipulation loop, the program uses nested loops to shift data: the outer loop iterates through the 32 channels in the cascaded system, while the inner loop is responsible for stripping the 12-bit grayscale data of each channel bit by bit, starting from the most significant bit (MSB). For each bit of data sent, the program first sets a level on the $SIN$ pin, then pulls it high. A rising edge on the pin forces the internal shift register of the TLC5940 to capture the bit. Once all 384 bits of data required by the two cascaded chips have been shifted in, the program will generate a... Latch pulse. According to the datasheet specification, the rising edge of this pulse loads the data in the shift register into the internal grayscale control register all at once, ensuring instantaneous synchronization of the 15 LEDs when updating their brightness and effectively avoiding visual flickering caused by updating each LED one by one. To support PWM counting, the system utilizes the STM32's TIM1 timer... A stable square wave signal is generated on the pin. This hardware-generated clock signal serves as the reference for the TLC5940's grayscale control, and is transmitted via a signal to the pin. The precise coordination of signals enabled the accurate display of 4096 gray levels in each frame.

[0046] Communication module The communication module is responsible for the system's interaction logic with the external environment and users. Its core consists of local interaction logic driven by the Check_Key_Status function and a reserved remote communication interface based on USART1. For local interaction, the system monitors the input mode through the PA port. The program employs a software debouncing algorithm based on instruction cycles to eliminate physical bounce caused by the mechanical keys during the moment of closure. When a low-level signal is detected, the system enters a cycle containing approximately 20,000 cycles. The operation involves a delayed loop that reads the pin level again after avoiding the jitter window. Only if both checks pass will the system toggle the LED_Power_State variable, thereby changing the execution branch of the main loop. This logic ensures determinism in user interaction and prevents erroneous display state switching due to environmental noise.

[0047] In the underlying architecture of system communication, the main loop plays the role of timing scheduling. When the system is powered on, the program is not only responsible for detecting key presses, but also for controlling... The TLC5940 uses pins to manage the PWM refresh lifecycle. At the start of each refresh cycle, the program manually pulls the $BLANK$ pin high to reset the grayscale counter inside the TLC5940, and then releases the signal to start counting. Additionally, the system initializes the USART1 asynchronous communication interface, using the PA9 (TX) and PA10 (RX) pins to achieve 115200 bps full-duplex communication. This design provides hardware support for subsequent real-time brightness commands issued via a host computer or MATLAB.

[0048] Serial bit control program implementation In the underlying software implementation, the bitstream transmission process strictly follows the synchronous serial interface timing defined in the TLC5940 datasheet. The program simulates the SPI protocol through bit manipulation; within each bit transmission cycle, it first... Pin level pulled low, assuming The level switching of the data line provides the necessary physical setup time. Subsequently, the microcontroller, based on the logic state of the current bit in the buffer, ... The corresponding high and low levels are output on the pins. This is to meet the setup time requirements specified in the datasheet. Greater than and duration Greater than Due to strict constraints, the program triggers after ensuring the data line level is stable. The rising edge pulse of the pin drives the internal shift register of the chip to accurately capture the bit data.

[0049] Cascaded Data Frame Construction and Transmission Logic For the hardware architecture of the two cascaded chips in this design, the data transmission engine constructs a total length of 384 bits through a double-nested loop. The complete bitstream frame. According to the cascading principle shown in Figure 13 of the datasheet, the data stream flows out of the microcontroller's pins in a "daisy-chain" manner, passes through the shift register of the first chip, and then... Pins are passed to the cascaded end chip Input end. In terms of software logic execution, the program adopts a strategy of reverse iteration from channel 31 to channel 0, splitting and sending the 12-bit grayscale data of each channel. This filling method from far end to near end ensures that the data can accurately stop and align in the corresponding chip register position after the logic shift is completed, realizing precise channel addressing of 15 LEDs.

[0050] Data latching and display cycle synchronization After all 384 bits of data have been completely shifted into the cascaded chip's registers, the system will execute a critical latch pulse sequence to update the LED output state. According to the timing diagram in Figure 12, the program first pulls the latch high... The pin is used to force the output of all LED channels to shut down and synchronously reset the internal grayscale counter, then quickly pulled high and released. The pin generates a synchronous latch pulse. The rising edge of this pulse atomically loads the serial data in the shift register into the internal PWM-controlled latch. After latching, the system releases the latch. Pin and start the high frequency generated by the TIM1 timer. The counting pulse, using a software-calibrated delay window, ensures that the driver chip can complete 4096 grayscale counts before entering the next refresh cycle, thereby guaranteeing high consistency and linearity of display brightness.

[0051] Example 5: This embodiment further discloses the following based on Embodiment 1: This hardware system adopts a highly integrated modular architecture design, and the overall block diagram is shown in the figure below. Its core logic consists of three major arrays working together: power management, microprocessor control, and LED constant current drive. The power system uses an external 12V DC as its energy input source, utilizing a TPS54340 step-down chip in conjunction with... The power inductor enables efficient DC-DC conversion and outputs a 3.3V logic voltage with extremely low ripple via an ME6211 linear regulator, providing a clean power supply environment for the precision control circuit. The control hub uses an STM32F103C8T6 microcontroller based on the Cortex-M3 core, connected to an 8MHz high-speed external crystal oscillator to provide a stable system clock reference, ensuring the output accuracy of the grayscale counting pulses. At the driver execution level, the system uses two cascaded TLC5940 driver chips, utilizing their built-in shift register mechanism to achieve 12-bit high-resolution dimming and 60mA constant current output control for 15 LEDs. Furthermore, the circuit integrates an SWD debugging interface, a USART asynchronous communication module, and a button circuit with software debouncing capabilities, constructing a hardware platform with real-time dimming and high reliability protection.

[0052] 12V-5V DC-DC step-down circuit module description The TPS54340DDA is a step-down DC / DC converter chip from Texas Instruments (TI). It has an input voltage range of 4.5V to 42VDC, an adjustable output voltage (-2V to 45V), and a maximum output current of 3.5A. The switching frequency can be configured via pull-up resistors on the pins, adjustable from 100kHz to 2.5MHz. The quiescent current is 146uA under no-load conditions, and the quiescent loss is only 1uA when the enable pin is turned off. This module is suitable for applications with a 12V or 24VDC input power supply, providing 5VDC or 3.3VDC output to the system. It can also be used in applications with a 24VDC input and 12VDC output or a 5V input and 3.3V output. The following is a schematic diagram drawn using a domestic LCSC EDA module. Note 0: Capacitors C2 and C4 are power input decoupling capacitors and should be placed as close as possible to the chip pins during PCB layout. The input voltage range is 4.5V to 40V (limited by the reverse withstand voltage of the freewheeling diode and the withstand voltage of the input decoupling capacitor; the chip itself can reach a maximum of 42V). In practical applications, the withstand voltage of C2 should be approximately 40% higher than VIN. Note 1: R9 is the switching frequency setting resistor. Adjusting the resistance of R9 changes the switching frequency of the DC / DC converter. The adjustable frequency range is... to The calculation formula is:

[0053] The chip integrates a soft-start circuit. The soft-start time is related to the switching frequency; the higher the switching frequency, the shorter the soft-start time. The calculation formula is as follows:

[0054] Note 2: R10, C11, and C12 are used to improve the frequency and load response of this power supply circuit (TI provides an Excel calculation tool on their website). Note 3: L1 is the output inductor of the DC / DC converter. Its inductance value and current carrying capacity should be calculated based on the switching frequency and load size. Here, an inductor with a current carrying capacity of 5.5A is selected. Note 4: Resistors R3 and R11 are feedback resistors used to determine the output voltage. The feedback voltage is... That is, the following relation should be satisfied:

[0055] And the current flowing out of the feedback pin should not be less than That is, the resistance R11 must not exceed When output is required Reference value of feedback resistor when voltage is applied , When output is required At that time, the reference value of the feedback resistor , Note 5: The output voltage of this DC / DC circuit is adjustable; see Note 4 for adjustment method. The voltage rating of the output decoupling capacitor should be determined according to the output voltage, and a margin of approximately 40% should be maintained. Note 6: The voltage rating of the freewheeling diode D1 should be determined according to the actual input voltage. The maximum input voltage of this DC / DC chip can reach... At the same time, the maximum forward current of the freewheeling diode will also limit the maximum output current of the circuit. When the required output current is greater than... When using a diode with a higher current-carrying capacity, a diode with a larger current-carrying capacity should be selected. The freewheeling diode selected in this design has a current-carrying capacity of 3A. Note 7: The EN enable pin is enabled when high; to disable it, simply pull the EN pin low. The EN pin can be used to monitor low voltage through resistor voltage division.

[0056] 5V-3.3V LDO Circuit Module Description The ME6211 series is a high-precision, low-noise CMOS low-dropout linear regulator. With its low output noise, high ripple rejection ratio, low dropout voltage, and ultra-fast startup, it is an ideal choice for modern cutting-edge mobile devices. The chip integrates a reference voltage source, error amplifier, driver transistor, current limiter, and phase compensator. Its current limiter's foldback circuit provides effective short-circuit protection for the output pins and current limiting. Furthermore, the ME6211 is fully compatible with low-ESR ceramic capacitors, reducing system costs. Its excellent transient response and high PSRR across the entire frequency band ensure output stability under frequent load fluctuations. Combined with the CE pin enable control function in the circuit design, output shutdown can be achieved to significantly reduce overall power consumption. The following figure shows the pinout of this chip.

[0057] The circuit accepts a 5V DC power supply as input. It is a low-dropout linear regulator designed to stably convert the input voltage to a 3.3V output voltage. Note 0: Input filter capacitors C6 and C7 are connected between the input voltage and ground to filter out high-frequency noise from the input power supply, reducing the impact of power supply noise on the regulator. They also help stabilize the input voltage and prevent instability caused by transient changes in the input voltage.

[0058] Note 1: Output capacitors C8 and C9 are connected between the output terminal of the voltage regulator and ground. C9 is a 1uF capacitor used to smooth the output voltage, reducing output voltage ripple and noise. C8 is a 0.1uF capacitor, which works with C9 to provide additional high-frequency noise filtering. This configuration helps improve the stability of the voltage regulator and the quality of the output voltage.

[0059] MCU Minimum System Description Based on the STM32F103C8T6 datasheet and circuit design requirements, the following is a design description of the MCU minimum system core circuit: In terms of BOOT configuration, the STM32F103C8T6 determines the main system's boot mode through the voltage levels of the BOOT0 and BOOT1 pins during reset. When BOOT0 is low, the system boots from the main Flash memory, which is the normal program startup mode. When BOOT0 is high and BOOT1 is low, the system enters the built-in Bootloader mode, allowing firmware to be downloaded via serial port. In the schematic, these two pins are typically connected to 3.3V or GND with resistors or jumpers to ensure that the system can stably switch to the required boot space at different development stages (such as debugging or production).

[0060] To provide a stable system clock reference, the circuit employs an 8MHz high-speed external crystal oscillator (HSE) solution. This frequency, after being multiplied by an internal PLL, can drive the MCU to operate at a maximum of 72MHz. The oscillator circuit uses two external 12pF ceramic capacitors to meet the crystal oscillator's load capacitance requirements, ensuring reliable clock start-up and frequency accuracy. Based on the crystal oscillator load capacitance matching principle, the selection of its external capacitors should refer to the following formula:

[0061] in Parasitic capacitance of PCB traces and pins (usually 2-5pF). For applications requiring a real-time clock (RTC), the system also includes a 32.768kHz low-speed external crystal oscillator (LSE). This crystal oscillator is specifically designed to drive the internal RTC module, ensuring continuous clock counting even when the main power supply is off but the backup power supply (VBAT) is present. In terms of layout, the crystal oscillator should be placed as close as possible to the MCU's OSC32_IN and OSC32_OUT pins, and grounding should be used to reduce interference from high-frequency signals to its low-power oscillation circuitry.

[0062] For program debugging and communication interfaces, this design adopts the Serial Wire Debug (SWD) interface, using two pins, PA13 (SWDIO) and PA14 (SWCLK), to achieve firmware download and real-time simulation. Compared to the traditional JTAG interface, SWD only requires two signal lines to achieve complete debugging functionality, significantly saving PCB space. Simultaneously, the system is configured with the USART1 serial port as the primary debugging method, using the PA9 (TX) and PA10 (RX) pins for asynchronous communication with an external host computer. This serial port can not only be used for regular task log output but also, when BOOT0 is configured correctly, can be used in conjunction with the system bootloader for serial firmware updates.

[0063] In reset circuit design, the delay characteristics of the RC circuit are the physical basis for ensuring reliable system initialization, and its core working mechanism follows the capacitor charging formula:

[0064] At the moment of power-on ( ), due to capacitance The voltage across the pins cannot change abruptly, and the NRST pin level is maintained low to meet the pulse width requirement of the STM32's internal reset trigger. Over time, the pin voltage changes according to a time constant. Exponential increase, through selection resistance and capacitor The system can generate approximately The startup delay is much greater than the minimum reset pulse time specified in the chip manual, ensuring that the main power supply has reached stability and the internal clock source has started oscillating before the voltage crosses the logic high-level threshold and releases the reset state, thus avoiding random anomalies during program startup.

[0065] LED Constant Current Drive Circuit Module Description The TLC5940QPWPREP is a 16-channel high-performance LED constant current driver chip manufactured by Texas Instruments (TI). It features 12-bit (4096 levels) PWM grayscale control and 6-bit (64 levels) independent current calibration for each channel. Its input voltage range is 3V to 5.5V, with a maximum continuous current of 120mA per channel, and all output channels have a withstand voltage of up to 17V, making it ideal for driving multi-string LEDs or high-power lighting applications. The chip can be cascaded via a high-frequency synchronous serial interface (data rate up to 30MHz), maintaining extremely high brightness consistency and data refresh efficiency when multiple chips are used together.

[0066] According to the datasheet, the maximum output current The calculation formula is as follows:

[0067] in Typical value In this circuit, the following circuit is selected: Resistance, calculated as follows: The measured results meet the design specifications. Meanwhile, in the output circuit, a series connection is established. Current-limiting resistors are mainly used to assist in voltage drop testing and improve system heat distribution.

[0068] Note 1: The BLANK pin is connected in the circuit via... The resistor is pulled up to 3.3V. This is because during the initial power-up phase of the system, the MCU's GPIO pins are typically in a high-impedance state or have not yet completed initialization. At this time, the internal logic state of the driver chip is uncertain. If the BLANK pin is left floating, it may cause the LED to flicker randomly or draw an abnormally large current. External hardware pull-up ensures that this pin is at a high level by default at power-up, forcing the chip to shut down all channel outputs until the program runs stably and outputs valid control signals, thereby enhancing system safety and the visual effect of power-on.

[0069] Furthermore, the TLC5940's multi-chip cascade communication is achieved through its built-in serial shift register and its corresponding SIN (serial input) and SOUT (serial output) pins. In terms of hardware connection, the SOUT pin of the preceding chip is connected to the SIN pin of the following chip, forming a "daisy-chain" structure. All cascaded chips share the same SCLK (serial clock) and XLAT (data latch) control signal lines. Data enters the shift register from SIN on the rising edge of SCLK and is output to the next chip via SOUT on the falling edge of SCLK. This mechanism allows multiple chips to be logically treated as a single, continuous long shift register. In this dual-chip cascade circuit design, each chip has 192 bits of grayscale data space, and the controller needs to continuously send 384 bits of data to cover all channels of both drivers. After the data is completely shifted into the corresponding register position, the controller sends a high-level pulse to the XLAT pin to synchronously latch the data in the shift register into the PWM control logic of each channel, thereby ensuring the high synchronization of multiple LEDs during brightness refresh and the high efficiency of data transmission.

Claims

1. A multi-channel high-precision synchronous constant current LED driving circuit, characterized in that, include: Hierarchical isolation power supply module, microprocessor control module and LED constant current drive module; The graded isolation power supply module uses a step-down chip in conjunction with a power inductor to achieve efficient DC-DC conversion, and outputs a logic voltage with extremely low ripple via a linear regulator; The microprocessor control module provides a stable system clock reference; The LED constant current drive module operates by cascading two driver chips and utilizes its built-in shift register mechanism to achieve constant current output control of multiple LEDs. The output of the hierarchical isolation power supply module serves as the input to the microprocessor control module and the LED constant current drive module, providing power to them. The output of the microprocessor control module serves as the input to the LED constant current drive module, providing a stable system clock reference.

2. The multi-channel high-precision synchronous constant current LED driving circuit according to claim 1, characterized in that, The graded isolation power supply module adopts a two-level power supply architecture, which separates the power supply for LED power loads from the power supply for digital logic, including: a 112V to 5V DC-DC unit and a 5V to 3.3V LDO unit; 12V to 5V DC-DC unit: Uses TPS54340 step-down chip, externally configured with power inductor and freewheeling diode, and uses voltage divider resistors at the feedback end to obtain a stable 5V output for powering LED power loads; high and low capacitance filter capacitors are set at the input and output ends respectively, and the capacitors have a voltage tolerance margin; the chip's soft-start function is used to suppress power-on surges to ensure high conversion efficiency and low heat generation; 5V to 3.3V LDO unit: Employs ME6211 low dropout linear regulator to provide separate power to the microcontroller and driver chip logic circuits; two filter capacitors are connected in parallel at its input to filter out high-frequency switching noise introduced by the preceding DC-DC converter; a combined capacitor is set at the output to further smooth the voltage, thereby providing a stable, low-noise 3.3V logic power supply for serial transmission and grayscale counting.

3. The multi-channel high-precision synchronous constant current LED driving circuit according to claim 2, characterized in that, The microprocessor control module specifically uses an STM32F103C8T6, equipped with an 8MHz high-speed external crystal oscillator, and frequency multiplied to a 72MHz system clock via a phase-locked loop; it is equipped with an RC reset circuit consisting of resistors and capacitors to form a stable power-on delay; the BOOT pin is configured with a startup selection circuit, leading out the SWD dual-wire debug interface and the USART1 serial port, and reserving hardware button input pins to provide a control basis for system timing control, grayscale data transmission and human-machine interaction.

4. The multi-channel high-precision synchronous constant current LED driving circuit according to claim 1, characterized in that, The LED constant current drive module is specifically as follows: Two TLC5940 chips are cascaded in a daisy chain, enabling multiple output channels. Unused channels can be reserved or configured to be off. High-precision constant current setting and detection circuit: The single-channel constant current output is set according to the chip output current calculation relationship; each LED output branch is connected in series with a precision sampling resistor. The voltage drop across the sampling resistor is measured by a multimeter and the actual output current is calculated for debugging, calibration and consistency verification. Hardware power-on self-locking protection circuit: The BLANK pin of each TLC5940 is uniformly pulled up to 3.3V through a resistor; before the microcontroller power-on reset and GPIO initialization are completed, BLANK is kept at a high level, the output of the driver chip is forcibly turned off, and all LEDs are turned off by default; after the main control is initialized, the software releases BLANK in sequence, thereby avoiding random flickering and instantaneous current surges at power-on; Synchronous cascaded routing: The SOUT pin of the front-end TLC5940 is connected to the SIN pin of the rear-end TLC5940. The two chips share the SCLK, XLAT, GSCLK and BLANK control signals. The STM32 timer multiplexed output stabilizes the GSCLK grayscale reference clock, while the relative timing of SCLK, XLAT and BLANK is controlled by software, so that the cascaded chips complete data shifting, latching and output updating within the same grayscale period.

5. A multi-channel high-precision synchronous constant current LED driving circuit according to claim 1, characterized in that, Also includes: SWD debugging interface, USART asynchronous communication module and button circuit with software debouncing function.

6. A multi-channel high-precision synchronous constant current LED driving system, characterized in that, include: Application interaction layer: responsible for key scanning and status management of the hierarchical isolation power supply module; Hardware mapping layer: Utilizes mapping tables to shield physical wiring differences and realize the reconstruction of logical brightness data into cascaded bit streams; The underlying driver transmission layer utilizes bit operations to simulate a synchronous serial protocol to drive the cascaded operation of LED constant current driver modules; multi-channel synchronous dimming and stable refresh are achieved through the GSCLK pulse generated by the hardware timer and the precise delay calibration of the microprocessor control module.

7. A multi-channel high-precision synchronous constant current LED driving system according to claim 6, characterized in that, The hardware mapping layer is specifically as follows: The user-defined grayscale data array represents the application layer's independent control requirements for the brightness of each LED. The hardware abstraction layer, based on predefined... The mapping table reorganizes user-level data to... In the cascaded buffer.

8. A multi-channel high-precision synchronous constant current LED driving system according to claim 6, characterized in that, The specific steps for using bit manipulation to simulate a synchronous serial protocol to drive cascaded LED constant current drive modules are as follows: The program simulates synchronous serial protocol communication with a cascaded TLC5940 chip via software. During the transmission phase, the program uses a nested loop structure... Driven by the engine, 384 bits of serial data are sequentially shifted into the chip's shift register. After data transmission is complete, the drive engine controls... The pin generates a latch pulse, synchronously loading the data in the shift register into the PWM control register of each channel. Furthermore, to ensure electrical safety during power-up, this is enforced at the protocol layer. The pull-up logic on the pin continues until the data latching operation is completed.

9. A multi-channel high-precision synchronous constant current LED driving system according to claim 6, characterized in that, Multi-channel synchronous dimming and stable refresh are achieved through the GSCLK pulse generated by a hardware timer and precise delay calibration by the microprocessor control module. Specifically: The main architecture adopts a state machine-based task polling architecture; during each refresh cycle, different branches are executed based on the global variable LED_Power_State: in the on state, periodic branches are executed. Reset to trigger the 4096-level grayscale counting inside the driver chip.

10. A method for driving multi-channel high-precision synchronous constant current LEDs, characterized in that, include: In the data preparation phase, firstly through The hardware mapping table resolves the differences between physical wiring and logic control, accurately filling the user-defined multi-channel brightness data into the 32-channel physical buffer. Subsequently, the drive engine enters the serial transmission stage, using bit operations to simulate the communication timing of the TLC5940. In the specific bit manipulation loop, data shifting is achieved through nested loops: the outer loop iterates through the 32 channels in the cascaded system, while the inner loop is responsible for stripping the 12-bit grayscale data of each channel bit by bit, starting from the most significant bit; for each bit of data sent, a level is first placed on the pin, and then pulled high. A rising edge on the pin forces the TLC5940's internal shift register to capture the bit; once all 384 bits of data required by the two cascaded chips have been shifted in, the program will generate a... The latch pulse; the rising edge of this pulse loads the data in the shift register into the internal grayscale control register at once, thus ensuring the instantaneous synchronization of multiple LEDs when updating brightness; utilizing the STM32's TIM1 timer... A stable square wave signal is generated on the pin as a reference for the grayscale control of the TLC5940, through communication with... The precise coordination of signals enabled the accurate display of 4096 gray levels in each frame.

Images