A power supply circuit board with high-precision impedance control capability and a manufacturing method

Abstract

The application discloses a power supply circuit board with high-precision impedance control capability and a manufacturing method. The circuit board comprises a first outer signal layer and a first inner reference layer adjacent to the first outer signal layer. The first inner reference layer comprises a mixed pattern with uneven residual copper rate. A side surface of the first inner reference layer facing the first outer signal layer is a flat reference plane formed by copper lines, copper surfaces and solidified resin filled therebetween. An insulating medium layer is arranged above the flat reference plane and combined with the first outer signal layer to form a medium layer with uniform thickness. The manufacturing method comprises the following steps: after a mixed pattern is formed on the surface of an inner layer core plate, a planarization treatment is performed to form a flat reference plane; and then the surface after the planarization treatment is combined with an outer copper foil through an insulating medium layer. The application pre-planarizes the inner reference layer before pressing, and thus the thickness difference of the medium layer caused by uneven residual copper rate is eliminated from the root cause, the impedance control precision is significantly improved, and large-current current flow and high-precision impedance control can be considered at the same time within a limited number of layers.

Description

Technical Field

[0001] This invention relates to the field of printed circuit board technology, and more specifically, to a power circuit board with high-precision impedance control capability and its manufacturing method. Background Technology

[0002] With the rapid iteration and development of AI computing power, computing power boards need to carry larger currents, and the requirements for controlling signal transmission impedance are also becoming increasingly stringent. Traditional computing power boards typically adopt a multi-layer structure, using independent current-carrying modules and impedance control modules to achieve the functions of high-current transmission and high-precision signal transmission respectively.

[0003] In a typical eight-layer PCB design, the middle layer is usually designed as a large-area copper layer specifically for high current carrying; the outer or second-outer layer is designed as an impedance control layer, achieving specific impedance values ​​by controlling parameters such as line width and dielectric layer thickness. This design completely separates the current carrying function from the impedance control function, which can well meet conventional needs, but it occupies more board resources. Under the constraint of a limited total number of layers, it is difficult to simultaneously meet the ever-increasing current demand and signal integrity requirements.

[0004] When large copper surfaces for current carrying and fine circuitry for signal transmission need to be arranged simultaneously within the same layer, this layer becomes a hybrid layer, where the residual copper ratio (the proportion of copper area to the total area of ​​the layer) varies significantly across different regions. This non-uniformity in residual copper ratio can cause serious problems in subsequent lamination processes. Specifically, when using a prepreg to laminate this inner layer with uneven residual copper ratio to the outer copper foil, the resin in the prepreg preferentially flows and fills areas with low residual copper ratio and open spaces under high temperature and pressure. This causes the resin above densely copper areas to be squeezed out and become thinner, while the resin above open areas accumulates and becomes thicker, ultimately resulting in a significantly uneven dielectric layer thickness.

[0005] For impedance control, dielectric layer thickness is one of the key influencing factors. Local fluctuations in dielectric layer thickness can directly cause the impedance value to deviate from the design target. Traditional designs can typically only maintain impedance control accuracy at the ±10% level, which cannot meet the ±5% or even more stringent impedance control requirements of next-generation computing power boards. In addition, when using a thick copper design to improve current carrying capacity, the height difference of the copper pattern itself is greater, and the aforementioned problems of uneven resin flow and dielectric thickness differences will be more serious. It may even lead to voids at the bottom of the thick copper due to insufficient resin filling, resulting in reliability risks such as board delamination and blowout. Summary of the Invention

[0006] To achieve the above objectives, the present invention provides the following technical solution: This invention provides a power circuit board with high-precision impedance control capability, comprising a first outer signal layer and a first inner reference layer. The first outer signal layer includes signal lines with impedance control requirements. The first inner reference layer is disposed adjacent to the first outer signal layer and includes a hybrid pattern composed of copper lines and copper surfaces, the hybrid pattern having a non-uniform residual copper ratio. The surface of the first inner reference layer facing the first outer signal layer is a flat reference plane composed of copper lines, copper surfaces, and cured resin filling the space between them. An insulating dielectric layer is bonded to the first outer signal layer above this flat reference plane to form a dielectric layer of uniform thickness.

[0007] This solution eliminates the physical structural factor causing uneven dielectric layer thickness by constructing a flat reference plane formed by copper and resin on the surface of the first inner reference layer. This facilitates the formation of a dielectric layer with uniform thickness above the flat reference plane, significantly improving the impedance control accuracy of the impedance signal lines on the first outer signal layer. Simultaneously, since the reference plane is flattened, designers do not need to deliberately maintain a uniform residual copper ratio in the inner layers for impedance control, allowing for free arrangement of thick copper current-carrying within the same layer. This achieves both high current and high-precision impedance within a limited number of layers. The interlayer bonding utilizes a superstructured insulating dielectric layer, covering various bonding methods such as prepreg lamination, coating, and bonding, providing broader protection.

[0008] In a further embodiment, the insulating dielectric layer is formed by laminating prepreg. Prepreg lamination is the most mature and reliable interlayer bonding process in printed circuit board manufacturing, offering low cost and strong compatibility.

[0009] In a further embodiment, the flat reference plane is formed by covering the hybrid pattern of the first inner reference layer with resin filler material, followed by curing and polishing until the copper traces and copper surface are coplanar with the resin filler material. This process is mature, can reliably achieve the coplanar effect, and the copper surface is completely exposed after polishing, which is beneficial for enhancing interlayer adhesion.

[0010] In a further design, the copper thickness of the first inner reference layer is ≥2 oz; and / or the impedance linewidth of the first outer signal layer is ≥10 mil; and / or the thickness of the dielectric layer is ≥5 mil. Within this parameter range, the planarization process significantly improves the uniformity of the dielectric layer, and the design of a large linewidth and thick dielectric layer can significantly improve process tolerance and batch yield.

[0011] In a further design, the copper thickness of the first inner reference layer is 3 oz; the impedance linewidth of the first outer signal layer is 16 mil ± 0.8 mil; and the thickness of the dielectric layer is 9.5 ± 0.5 mil. This combination of parameters achieves an optimal balance between current carrying capacity, etching precision, and impedance control.

[0012] In a further design, the cured resin is compatible with the insulating dielectric layer, meeting requirements for interlayer adhesion, thermomechanical matching, and chemical stability. Compatibility is defined through testable performance indicators, ensuring clarity of the design and long-term product reliability.

[0013] In a further design, the circuit board also includes a second outer signal layer, a second inner reference layer, and multiple current-passing layers located between the first and second inner reference layers. These current-passing layers are large-area copper layers. This symmetrical structure facilitates dual-sided power supply and signal transmission, forming a complete product solution that can be directly applied to next-generation AI computing power supplies.

[0014] The present invention also provides a method for manufacturing a circuit board, comprising: providing an inner core board, forming a mixed pattern comprising copper lines and copper surfaces on its surface, the mixed pattern having a non-uniform residual copper ratio; performing planarization treatment on the surface of the inner core board to form a flat reference plane composed of copper lines, copper surfaces and cured resin filling therebetween; bonding the planarized surface of the inner core board to a first outer copper foil through an insulating dielectric layer to form a first dielectric layer of uniform thickness, the first outer copper foil being used to fabricate a first outer signal layer having impedance control requirements.

[0015] This method introduces planarization before the interlayer bonding step, breaking the causal chain from uneven residual copper content to uneven dielectric thickness at the manufacturing source. This ensures the stable formation of a dielectric layer with uniform thickness, significantly improving impedance control accuracy. Simultaneously, pre-filling with resin and planarization eliminates voids at the bottom of thick copper layers, enhancing interlayer reliability. The outer layer bonding process is achieved through bonding with an insulating dielectric layer, covering manufacturing processes that use any insulating dielectric to achieve interlayer bonding.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: First, by constructing a flat reference plane on the surface of the first inner reference layer where copper and resin are coplanar, the difference in dielectric layer thickness caused by uneven residual copper ratio is eliminated from the source, thereby improving the impedance control accuracy from the traditional ±10% to ±5% or even higher, meeting the stringent requirements of the new generation of computing power boards.

[0017] Secondly, planarization removes the design constraint that the inner reference layer must maintain a uniform residual copper ratio, allowing designers to freely deploy thick copper surfaces within the same layer for high current transmission. High current transmission and high-precision impedance control can be achieved simultaneously without adding extra layers, improving the integration and freedom of the design.

[0018] Third, when the scheme adopts thick copper, wide linewidth and thick dielectric layer design at the same time, since the absolute values ​​of key factors such as linewidth and dielectric layer thickness are much larger than those of traditional fine circuit design, the relative deviation caused by the same absolute process deviation is significantly reduced, the process window is wider, which is conducive to improving the consistency and yield of mass production.

[0019] Fourth, the height difference of the inner layer pattern is filled and cured with resin before pressing, so that the prepreg mainly plays the role of interlayer bonding rather than filling. This avoids the filling void problem caused by poor resin flow at the bottom of the thick copper pattern, and significantly improves the interlayer bonding reliability and anti-delamination ability of the circuit board. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a cross-sectional view of the circuit board in an embodiment of the present invention. The figure shows the arrangement of the eight conductive layers from top to bottom in cross-section, and highlights the surface of the first inner reference layer L2 facing the first outer signal layer L1. This surface is a flat reference plane composed of copper lines, copper surfaces and cured resin filling the space between them, and a dielectric layer of uniform thickness formed above this flat reference plane by an insulating dielectric layer.

[0022] Figure 2 This is a schematic diagram comparing the state of the inner core board before and after planarization treatment in an embodiment of the present invention. The upper part of the figure shows the state of the mixed pattern on the surface of the inner core board before treatment, which has undulations and uneven residual copper content; the lower part shows the state of the flat reference plane formed by the coplanarity of the copper surface and the resin surface after resin filling, baking and curing and polishing.

[0023] Figure 3 This is a flowchart illustrating the circuit board manufacturing method in an embodiment of the present invention. The flowchart shows, in sequence, the complete manufacturing steps of providing an inner core board and creating a hybrid pattern, performing planarization, bonding an outer copper foil through an insulating dielectric layer, creating impedance signal lines, repeating the symmetrical side processing, and completing subsequent processing.

[0024] The correspondence between the labels and component names in the diagram is as follows: L1 First outer signal layer, L2 First inner reference layer, L3 Third current-passing layer, L4 Fourth current-passing layer, L5 Fifth current-passing layer, L6 Sixth current-passing layer, L7 Second inner reference layer, L8 Second outer signal layer. Detailed Implementation

[0025] The present invention will be further described in detail below with reference to embodiments. It should be noted that the following embodiments are for illustrative purposes only and are not intended to limit the invention. Those skilled in the art, after reading this specification, will be able to make various changes and modifications to the embodiments without departing from the concept of the present invention, and such changes and modifications will also fall within the protection scope of the present invention.

[0026] This embodiment provides an eight-layer circuit board for AI computing power supply and its manufacturing method. (Refer to...) Figure 1 The circuit board in this embodiment includes eight conductive layers, arranged from top to bottom as follows: a first outer signal layer L1, a first inner reference layer L2, a third current-carrying layer L3, a fourth current-carrying layer L4, a fifth current-carrying layer L5, a sixth current-carrying layer L6, a second inner reference layer L7, and a second outer signal layer L8. The first outer signal layer L1 and the second outer signal layer L8 contain signal lines with impedance control requirements, such as an impedance control target of 45 ± 5% ohms. The first inner reference layer L2 and the second inner reference layer L7 serve as reference planes for adjacent signal layers and also carry some current-carrying functions. The third current-carrying layer L3, the fourth current-carrying layer L4, the fifth current-carrying layer L5, and the sixth current-carrying layer L6 are complete large-area copper layers specifically designed for high-current transmission.

[0027] The core problem to be solved in this embodiment lies in the first inner reference layer L2 and the second inner reference layer L7. Taking the first inner reference layer L2 as an example, its surface pattern simultaneously includes a wide copper surface for current flow and a fine copper line for signal reference, forming a mixed pattern with severely uneven residual copper content. For example, the residual copper content in some areas can reach over 80%, while the residual copper content in sparsely lined areas may be as low as below 20%. If L2 is directly laminated to the first outer signal layer L1 using a prepreg in the traditional process, the resin in the prepreg will preferentially flow to the empty areas with low residual copper content on the L2 layer under high temperature and pressure, resulting in a thinner dielectric layer above the dense copper areas and a thicker dielectric layer above the empty areas. Ultimately, this causes the actual impedance values ​​of each impedance line on the first outer signal layer L1 to deviate by more than ±5%. To solve the above problem, this embodiment adds a planarization process for the first inner reference layer L2 and the second inner reference layer L7 before the lamination process.

[0028] Reference Figure 3 The overall manufacturing process of this embodiment is as follows: Step S1: Provide an inner core board and fabricate a hybrid pattern containing copper lines and copper surfaces on its surface using conventional pattern transfer and etching processes. Taking the first inner reference layer L2 as an example, its initial copper thickness is designed to be 3OZ. The pattern includes a large area of ​​current-carrying copper surfaces and fine impedance reference lines, and the residual copper ratio varies significantly in different areas.

[0029] Step S2: Perform planarization treatment on the surface of the inner core board with uneven residual copper ratio. This planarization treatment specifically includes the following sub-steps: Step S2a: Select a resin filler material to cover the surface of the inner core board. This resin filler material can be, for example, a commercially available epoxy resin-based plugging resin, selected based on compatibility with the prepreg used in subsequent lamination. Compatibility here can be determined by the following verifiable standards: the interlayer bonding strength between the cured resin and the prepreg meets the relevant IPC-TM-650 test standards; the coefficient of thermal expansion is similar to that of the copper and the cured insulating layer of the prepreg, avoiding excessive stress during thermal shock; and it does not dissolve or severely degrade during subsequent wet process chemical immersion. Those skilled in the art can select suitable commercially available resin products based on the above standards through routine testing, without requiring creative effort. The resin filler material is then applied to the entire surface of the inner core board by printing or coating, ensuring that all copper-free areas are fully filled and the copper surface is completely covered.

[0030] Step S2b: Bake and cure the inner core board after covering with resin to completely cure the resin filler material and form a hard and stable filler.

[0031] Step S2c: Grind the cured surface. (Refer to...) Figure 2 The grinding process continues until the copper traces and the upper surface of the copper surface are fully exposed and aligned with the upper surface of the cured resin filler, forming a flat reference plane composed of copper and resin. Here, "flat" means that the surface undulations of this reference plane have been reduced to a level where the coefficient of variation of the dielectric layer thickness above it after subsequent lamination meets the target impedance accuracy requirements. In other words, the surface does not exhibit any graphic height differences at the microscale that would cause non-uniform resin flow. After grinding, the copper thickness will be reduced, for example, from approximately 4.2 mil initially to approximately 3.5 mil to 4.0 mil. The specific value can be adjusted according to impedance design requirements. In this embodiment, the copper thickness after grinding is controlled at approximately 3.8 mil. This flat reference plane is physically equivalent to a complete copper surface with 100% residual copper content, without any graphic height differences.

[0032] Step S3: The planarized inner core board surface is bonded to the first outer copper foil using an insulating dielectric layer. In this embodiment, the insulating dielectric layer is preferably a prepreg, and the bonding method is lamination. Specifically, a prepreg with tightly controlled adhesive content tolerance is selected, for example, the adhesive content tolerance is tightened from the conventional ±2% to ±1.5%. It is placed on the planarized surface of the first inner reference layer L2, and then covered with the outer copper foil used to form the first outer signal layer L1. Lamination is performed under high temperature and high pressure. Since the surface of the first inner reference layer L2 is already a flat reference plane, the resin in the prepreg does not need to fill the height difference of the pattern, but only needs to flow and cure uniformly, thereby forming a first dielectric layer with uniform thickness and height between the first inner reference layer L2 and the first outer signal layer L1. In this embodiment, the target thickness of the first dielectric layer after lamination is 9.5 mil, and the tolerance can be stably controlled within the range of ±0.5 mil. It should be noted that although this embodiment uses prepreg lamination as the bonding method, the present invention is not limited to this. Other insulating dielectric layer bonding methods can also be used in other possible embodiments. For example, a layer of liquid photosensitive resin can be screen-printed on a flat reference plane and then cured by light or heat to form an insulating dielectric layer; or a thermosetting adhesive film can be used, and interlayer bonding can be achieved through vacuum pressing. The key is to form a dielectric layer of uniform thickness above the flat reference plane.

[0033] Step S4: After lamination, signal lines with impedance control requirements are fabricated on the first outer copper foil using conventional drilling, electroplating, outer layer pattern transfer, and etching processes. In this embodiment, the first outer signal layer L1 uses a 2OZ base copper layer with a 1OZ electroplating layer to form a conductive layer with a total copper thickness of approximately 3.6mil. The impedance linewidth is designed to be 16mil ± 0.8mil. Due to the uniform dielectric layer thickness and large absolute linewidth, the impedance control accuracy can stably reach ±5% or even higher.

[0034] Step S5: Repeat the planarization, lamination and circuit fabrication processes of steps S1 to S4 above for the second inner reference layer L7 and the second outer signal layer L8 to form the other half of the symmetrical structure.

[0035] Step S6: Complete subsequent processing according to conventional multilayer board technology, which may include interlayer alignment, lamination, surface treatment, and molding, ultimately obtaining an eight-layer circuit board. During the manufacturing process described above, a database can be established to perform regression analysis on key parameters such as impedance, linewidth, dielectric layer thickness, and copper thickness of the semi-finished product, continuously optimizing process control standard values ​​and further improving mass production consistency.

[0036] Compared with the prior art, the beneficial effects of the present invention, as described in the beneficial effects section above, are mainly reflected in four aspects. By constructing a flat reference plane on the surface of the first inner reference layer where copper and resin are coplanar, the difference in dielectric layer thickness caused by uneven residual copper ratio is eliminated at its source, improving impedance control accuracy from the traditional ±10% to ±5% or even higher. The planarization process removes the design constraint that the inner reference layer must maintain a uniform residual copper ratio, allowing designers to freely deploy thick copper surfaces within the same layer for high current transmission, achieving both high current transmission and high-precision impedance control without adding extra layers. When the scheme simultaneously employs thick copper, wide linewidth, and thick dielectric layer designs, the relative deviation caused by the same absolute process deviation is significantly reduced because the absolute values ​​of key factors such as linewidth and dielectric layer thickness are much larger than in traditional fine-line designs, resulting in a wider process window. Pre-filling and curing the height difference of the inner layer pattern with resin before lamination allows the prepreg to primarily act as an interlayer adhesive rather than a filler, avoiding the filling voids caused by poor resin flow at the bottom of the thick copper pattern. The specific embodiments of the present invention have been described in detail above with reference to the examples, but the present invention is not limited to the specific solutions described in the above embodiments. Within the scope of the technical concept disclosed in the present invention, those skilled in the art can make equivalent substitutions or conventional adjustments to some features of the technical solutions, and these changes and adjustments all fall within the protection scope of the present invention.

Claims

1. A power supply circuit board with high-precision impedance control capability, comprising: The first outer signal layer contains signal lines with impedance control requirements; A first inner reference layer is disposed adjacent to the first outer signal layer. The first inner reference layer includes a hybrid pattern composed of copper lines and copper surfaces, and the hybrid pattern has a non-uniform residual copper ratio. Its features are, The surface of the first inner reference layer facing the first outer signal layer is a flat reference plane formed by the copper lines, the copper surface, and the cured resin filling the space between them. The flat reference plane is bonded to the first outer signal layer through an insulating dielectric layer to form a dielectric layer of uniform thickness.

2. The circuit board according to claim 1, characterized in that, The insulating dielectric layer is formed by pressing semi-cured sheets together.

3. The circuit board according to claim 1 or 2, characterized in that, The flat reference plane is formed by covering the hybrid pattern of the first inner reference layer with resin filler material, and then curing and grinding it until the copper lines and the copper surface are coplanar with the resin filler material.

4. The circuit board according to claim 1, characterized in that, The copper thickness of the first inner reference layer is ≥2OZ; and / or the impedance linewidth of the first outer signal layer is ≥10mil; and / or the thickness of the dielectric layer is ≥5mil.

5. The circuit board according to claim 4, characterized in that, The copper thickness of the first inner reference layer is 3 oz; the impedance linewidth of the first outer signal layer is 16 mil ± 0.8 mil; and the thickness of the dielectric layer is 9.5 ± 0.5 mil.

6. The circuit board according to claim 1, characterized in that, The cured resin is compatible with the insulating dielectric layer, satisfying the requirements for interlayer bonding strength, thermomechanical matching, and chemical stability.

7. The circuit board according to claim 1, characterized in that, The circuit board further includes: a second outer signal layer, a second inner reference layer, and a plurality of current-passing layers located between the first inner reference layer and the second inner reference layer, wherein the current-passing layers are large-area copper surface layers.

8. A method for manufacturing a circuit board, comprising: An inner core board is provided, on which a hybrid pattern comprising copper lines and copper surfaces is formed, the hybrid pattern having a non-uniform residual copper ratio; Its features are, The surface of the inner core board is planarized to form a flat reference plane composed of the copper lines, the copper surface, and the cured resin filling therebetween. The inner core board surface after planarization is bonded to the first outer copper foil through an insulating dielectric layer to form a first dielectric layer of uniform thickness. The first outer copper foil is used to fabricate a first outer signal layer with impedance control requirements.

9. The manufacturing method according to claim 8, characterized in that, The insulating dielectric layer is a semi-cured sheet, and the bonding is a pressing process.

10. The manufacturing method according to claim 8, characterized in that, The planarization process includes: covering the surface of the inner core board with a resin filler material; baking and curing the resin filler material; and grinding the cured surface until the copper lines and the copper surface are exposed and coplanar with the cured resin filler material.

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