Printed circuit board, package substrate including the same, and semiconductor package

Abstract

A printed circuit board, a package substrate including the same, and a semiconductor package are provided. The printed circuit board includes a first insulating layer, a first conductor pattern disposed on the first insulating layer, a first insulating film covering the first insulating layer and the first conductor pattern, and a second insulating layer disposed on the first insulating film. The first insulating film includes a first portion covering an upper surface of the first insulating layer on which the first conductor pattern is not formed and a second portion extending between the upper surface of the first insulating layer and a lower surface of the first conductor pattern. When a thickness of the first portion in a first direction of the printed circuit board is C and a thickness of the second portion in the first direction of the printed circuit board is E, a relationship C > E is satisfied, the first direction of the printed circuit board being a direction in which the first insulating layer and the second insulating layer are stacked.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2025-0043903, filed on April 4, 2025, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a printed circuit board, a packaging substrate including the printed circuit board, and a semiconductor package. Background Technology

[0003] Recently, photosensitive insulating materials have gained attention as an alternative to conventional insulating layers used in printed circuit boards and semiconductor packages. Their ability to be directly patterned using photolithography offers a significant advantage in forming fine micropatterns without the need for complex etching or additional masking steps. This approach improves manufacturing efficiency and design flexibility, especially when electronic devices require higher-density interconnects and miniaturization. However, despite these benefits, integrating photosensitive insulating materials into advanced packaging structures has presented persistent reliability issues.

[0004] Past attempts to achieve micropatterning using these materials have encountered critical issues that can compromise electrical performance and long-term stability, such as copper migration. Copper migration occurs when conductive paths are formed within or through insulating layers, leading to short circuits or signal degradation under thermal and electrical stress. Conventional mitigation strategies, including barrier layers and improved curing processes, have not fully addressed these issues, especially as feature sizes shrink and operating conditions become more demanding. Therefore, there is a need for new and improved printed circuit boards and packaging substrates capable of reliably achieving micropatterning. Summary of the Invention

[0005] One aspect of this disclosure is to provide a printed circuit board and packaging substrate capable of reliably implementing micropatterns.

[0006] One aspect of this disclosure is to provide a printed circuit board and packaging substrate that can improve reliability by suppressing copper migration.

[0007] According to one aspect of this disclosure, the upper, side, and lower surfaces of the conductor pattern are surrounded by an insulating film that satisfies a specific thickness relationship.

[0008] According to one aspect of this disclosure, a printed circuit board includes: a first insulating layer; a first conductor pattern disposed on the first insulating layer; a first insulating film covering at least a portion of an upper surface of the first insulating layer and at least a portion of each of a side surface and an upper surface of the first conductor pattern, and extending between the upper surface of the first insulating layer and a lower surface of the first conductor pattern; and a second insulating layer disposed on the first insulating film. When the thickness of the portion of the first insulating film covering the upper surface of the first insulating layer where the first conductor pattern is not formed is C in a first direction of the printed circuit board, and the thickness of the portion of the first insulating film extending between the upper surface of the first insulating layer and the lower surface of the first conductor pattern in the first direction of the printed circuit board is E, C>E, where the first direction of the printed circuit board is the direction along which the first insulating layer and the second insulating layer are stacked.

[0009] According to one aspect of this disclosure, a packaging substrate includes: a circuit board; and interconnecting members disposed in the circuit board, wherein the interconnecting members include the printed circuit board according to the above example.

[0010] According to one aspect of this disclosure, a packaging substrate includes a circuit substrate and interconnect members. The interconnect members are disposed on the outermost side of the circuit substrate and include a microcircuit redistribution layer. The microcircuit redistribution layer includes: a first insulating layer; a first conductor pattern disposed on the first insulating layer; a first insulating film covering the first insulating layer and the first conductor pattern, and extending between an upper surface of the first insulating layer and a lower surface of the first conductor pattern; and a second insulating layer disposed on the first insulating film. When the thickness of the portion of the first insulating film covering the upper surface of the first insulating layer where the first conductor pattern is not formed is C in a first direction of the microcircuit redistribution layer, and the thickness of the portion of the first insulating film extending between the upper surface of the first insulating layer and the lower surface of the first conductor pattern in the first direction of the microcircuit redistribution layer is E, C>E is satisfied, the first direction of the microcircuit redistribution layer is the direction along which the first insulating layer and the second insulating layer are stacked, and wherein both the first insulating layer and the second insulating layer comprise photosensitive organic insulating materials, and the first insulating film comprises an inorganic insulating material.

[0011] According to one aspect of this disclosure, a semiconductor package includes: a packaging substrate as described above; and a first semiconductor chip and a second semiconductor chip, mounted on the packaging substrate and interconnected via the interconnecting members. Attached Figure Description

[0012] The above and other aspects, features, and advantages of this disclosure will be more clearly understood through the following detailed embodiments, taken in conjunction with the accompanying drawings, in which: Figure 1 It is a block diagram that schematically illustrates an example of an electronic device system; Figure 2 This is a schematic cross-sectional view illustrating an example of a printed circuit board; Figure 3 yes Figure 2 A schematic enlarged cross-sectional view of the R1 region of the printed circuit board; Figure 4 yes Figure 2 A schematic enlarged cross-sectional view of the R2 region of a printed circuit board; Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Figure 5F , Figure 5G and Figure 5H It is a schematic representation of manufacturing. Figure 2 A cross-sectional view of an example of the R1 region of a printed circuit board; Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 6E , Figure 6F , Figure 6G and Figure 6H It is a schematic representation of manufacturing. Figure 2 A cross-sectional view of an example of the R2 region of a printed circuit board; Figure 7 This is a schematic cross-sectional view illustrating an example of a packaging substrate and a semiconductor package including the packaging substrate; and Figure 8 This is a cross-sectional view schematically showing another example of a packaging substrate and a semiconductor package including the packaging substrate. Detailed Implementation

[0013] In the following description, embodiments of the present disclosure will be illustrated with reference to the accompanying drawings. For clarity, the shapes and sizes of the elements in the drawings may be exaggerated or reduced.

[0014] Figure 1 This is a block diagram that schematically illustrates an example of an electronic device system.

[0015] Reference Figure 1The electronic device 1000 may house a motherboard 1010. Chip-related components 1020, network-related components 1030, and other components 1040 may be physically and / or electrically connected to the motherboard 1010. These components may be connected to other electronic components described below via various signal lines 1090.

[0016] Chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory), etc.; application processor chips, such as central processing units (e.g., central processing units (CPU)), graphics processing units (e.g., graphics processing units (GPUs)), digital signal processors, encryption processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific integrated circuits (ASICs), etc. However, chip-related components 1020 are not limited to these, and may also include other types of chip-related components. Furthermore, chip-related components 1020 may be combined with each other. Chip-related components 1020 may be in the form of a package.

[0017] Network-related components 1030 may include components compatible with or operating according to protocols such as: Wi-Fi (IEEE 802.11 series, etc.), WiMAX (IEEE 802.16 series, etc.), IEEE 802.20, LTE, Ev-DO, HSPA+, HSDPA+, HSUPA+, GSM+, EDGE+, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, WLAN, 3G, 4G, and 5G protocols, as well as any other wireless and wired protocols specified after the aforementioned protocols. However, network-related component 1030 is not limited to this, but may also include components that are compatible with or operate according to various other wireless or wired standards or protocols. Furthermore, network-related component 1030 may also be combined with chip-related component 1020.

[0018] Other components 1040 may include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, low-temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCCs), etc. However, other components 1040 are not limited to these, and may also include passive components in the form of chip modules for various other purposes. Furthermore, other components 1040 may also be combined with chip-related components 1020 and / or network-related components 1030.

[0019] Depending on the type of electronic device 1000, the electronic device 1000 may also include other electronic components that are physically and / or electrically connected to the motherboard 1010 or not physically and / or electrically connected to the motherboard 1010. These other electronic components may include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, etc., but are not limited to these. These other electronic components may be audio codecs, video codecs, power amplifiers, compasses, accelerometers, gyroscopes, speakers, mass storage units (e.g., hard disk drives), optical disc (CD) drives, digital versatile disc (DVD) drives, etc. Furthermore, depending on the type of electronic device 1000, the electronic device 1000 may also include other electronic components for various purposes.

[0020] Electronic device 1000 may be a smartphone, personal digital assistant (PDA), digital camera, digital camera, network system, computer, monitor, tablet PC, laptop PC, netbook PC, television, video game console, smartwatch, automotive component, artificial intelligence (AI) device (e.g., AI packaging substrate), server (e.g., server packaging substrate), etc. However, electronic device 1000 is not limited to these, and may be any other electronic device capable of processing data.

[0021] Figure 2 This is a schematic cross-sectional view of an example printed circuit board.

[0022] Figure 3 yes Figure 2 A schematic enlarged cross-sectional view of the R1 region of the printed circuit board.

[0023] Figure 4 yes Figure 2 A schematic enlarged cross-sectional view of the R2 region of the printed circuit board.

[0024] Reference Figures 2 to 4The printed circuit board 100 according to the example may include: a first insulating layer 111; a first conductor pattern 121 disposed on the first insulating layer 111; a first insulating film 131 covering at least a portion of the upper surface of the first insulating layer 111 and at least a portion of each of the side surface and the upper surface of the first conductor pattern 121, and extending between the upper surface of the first insulating layer 111 and the lower surface of the first conductor pattern 121; and a second insulating layer 112 disposed on the first insulating film 131. In this case, the printed circuit board 100 according to the example can satisfy the relationship C>E, where C is the thickness of the portion of the first insulating film 131 covering the upper surface of the first insulating layer 111, for example, the thickness of the first insulating film 131 in the portion where the first conductor pattern 121 is not disposed, and E is the thickness of the portion of the first insulating film 131 extending between the upper surface of the first insulating layer 111 and the lower surface of the first conductor pattern 121. Furthermore, when D is the thickness of the portion of the first insulating film 131 covering the upper surface of the first conductor pattern 121, D+E>C can be satisfied. Here, the thicknesses C, D and E mentioned above can be the thickness of the first insulating film 131 in the first direction of the printed circuit board 100 (i.e., the direction along which the first insulating layer 111 and the second insulating layer 112 are stacked).

[0025] Furthermore, Ajinomoto laminated film (ABF) has a significant surface roughness, making it difficult to achieve fine patterns with an L (linewidth) / S (pitch) ratio of 2μm / 2μm on printed circuit boards (PCBs) manufactured using ABF. Therefore, to achieve such fine patterns, insulating materials with good surface roughness and uniformity may be required. For example, photosensitive dielectrics (PIDs) could be used. However, PID materials may be more susceptible to copper migration than ABF materials.

[0026] In contrast, in the case of the printed circuit board 100 according to the example, the upper, side, and lower surfaces of the first conductor pattern 121 can be entirely surrounded by the first insulating film 131, thereby preventing copper migration. Therefore, even when the first conductor pattern 121 is implemented as a fine pattern using a PID material instead of ABF as the material for the first insulating layer 111 and the second insulating layer 112, reliability issues can be improved. For example, the first conductor pattern 121 can be a plurality of first conductor patterns 121, in which case each of the plurality of first conductor patterns 121 can have a linewidth of 1 μm to 3 μm, and the spacing between adjacent first conductor patterns 121 of the plurality of first conductor patterns 121 can be 1 μm to 3 μm.

[0027] Furthermore, in the printed circuit board 100 according to the example, the thickness of the first insulating film 131 can vary depending on its placement. For example, as described above, the thickness C of the portion of the first insulating film 131 covering the upper surface of the first insulating layer 111 can be greater than the thickness E of the portion of the first insulating film 131 extending between the upper surface of the first insulating layer 111 and the lower surface of the first conductor pattern 121. Additionally, the sum of the thickness D of the portion of the first insulating film 131 covering the upper surface of the first conductor pattern 121 and the aforementioned thickness E can be greater than the aforementioned thickness C. In this case, the first conductor pattern 121 can be implemented more precisely as a fine pattern. Furthermore, the first conductor pattern 121 can be more easily surrounded by the first insulating film 131, thus improving its reliability more effectively.

[0028] For example, the first insulating film 131 may include: an insulating film 131-1, disposed on the upper surface of the first insulating layer 111 and extending between the upper surface of the first insulating layer 111 and the lower surface of the first conductor pattern 121; and an insulating film 131-2, disposed on the upper surface of the insulating film 131-1 and covering at least a portion of each of the side and upper surfaces of the first conductor pattern 121 along the shape of the first conductor pattern 121. Therefore, the first insulating film 131 including the insulating film 131-1 and the insulating film 131-2 satisfies the aforementioned thickness relationship and can more easily surround the first conductor pattern 121. Furthermore, the insulating film 131-1 and the insulating film 131-2 may contain the same inorganic insulating material, and thus can be integral without a distinguishable boundary between them. However, if desired, the boundary between them may be distinguishable.

[0029] In this case, when the thickness of the portion of the 1-1 insulating film 131-1 disposed on the upper surface of the first insulating layer 111 (e.g., the thickness of the portion of the 1-1 insulating film 131-1 where the first conductor pattern 121 is not disposed) is defined as A, and the thickness of the portion of the 1-1 insulating film 131-1 extending between the upper surface of the first insulating layer 111 and the lower surface of the first conductor pattern 121 is defined as B, the relationship B>A can be satisfied. For example, in order to realize the first conductor pattern 121 as a fine pattern, dry etching may be required in the seed etching process, and in this process, the portion of the 1-1 insulating film 131-1 on which the first conductor pattern 121 is not disposed may be partially removed. Therefore, the 1-1 insulating film 131-1 can satisfy the above-described thickness relationship. Therefore, the first insulating film 131 can more easily satisfy the above-described thickness relationship. Here, the aforementioned thicknesses A and B can be the thickness of the insulating film 131-1 in the first direction of the printed circuit board 100 (i.e., the direction along which the first insulating layer 111 and the second insulating layer 112 are stacked).

[0030] Reference Figures 2 to 4 The printed circuit board 100 according to the example may further include: a second conductor pattern 122 disposed on a second insulating layer 112; a second insulating film 132 covering at least a portion of the upper surface of the second insulating layer 112 and at least a portion of each of the side surfaces and the upper surface of the second conductor pattern 122, and extending between the upper surface of the second insulating layer 112 and the lower surface of the second conductor pattern 122; and a third insulating layer 113 disposed on the second insulating film 132. For example, the printed circuit board 100 according to the example may have a multilayer printed circuit board structure.

[0031] Furthermore, the above description of the first conductor pattern 121 can be applied substantially similarly to the second conductor pattern 122. For example, the second conductor pattern 122 can be a plurality of second conductor patterns 122, and in this case, the linewidth of each of the plurality of second conductor patterns 122 can be 1 μm to 3 μm, and the spacing between adjacent second conductor patterns 122 of the plurality of second conductor patterns 122 can be 1 μm to 3 μm. Additionally, the above description of the first insulating film 131 can be applied substantially similarly to the second insulating film 132. For example, the second insulating film 132 may include: a 2-1 insulating film 132-1 disposed on the upper surface of the second insulating layer 112 and extending between the upper surface of the second insulating layer 112 and the lower surface of the second conductor pattern 122; and a 2-2 insulating film 132-2 disposed on the upper surface of the 2-1 insulating film 132-1 and covering at least a portion of each of the side surfaces and the upper surface of the second conductor pattern 122 along the shape of the second conductor pattern 122. At this point, the relationships relating to the thicknesses A, B, C, D, and E of the first insulating film 131-1 and the first insulating film 131 can be applied substantially in the same way to the second insulating film 132-1 and the second insulating film 132.

[0032] Reference Figures 2 to 4 The printed circuit board 100 according to the example may further include: a first pad pattern 123 disposed on a first insulating layer 111; a second pad pattern 124 disposed on a second insulating layer 112; and a via pattern 141 disposed between the first pad pattern 123 and the second pad pattern 124 and connecting the first pad pattern 123 and the second pad pattern 124 to each other. For example, the printed circuit board 100 according to the example may have a structure capable of vertical electrical connections.

[0033] Furthermore, the first insulating film 131 may cover at least a portion of each of the side and top surfaces of the first pad pattern 123, extend between the upper surface of the first insulating layer 111 and the lower surface of the first pad pattern 123, cover at least a portion of the side surface of the via pattern 141, and be in contact with at least a portion of the side surface of the via pattern 141. Similarly, the second insulating film 132 may cover at least a portion of each of the side and top surfaces of the second pad pattern 124, extend between the upper surface of the second insulating layer 112 and the lower surface of the second pad pattern 124, cover at least another portion of the side surface of the via pattern 141, and be in contact with at least another portion of the side surface of the via pattern 141. Moreover, the first insulating film 131 and the second insulating film 132 may be connected to each other. Therefore, the via pattern 141 can be more easily implemented as a microvia, and the aforementioned reliability improvement effect can be more easily achieved.

[0034] In this case, when the thickness of the portion of the second insulating film 132 covering the upper surface of the second insulating layer 112 (e.g., the thickness of the second insulating film 132 in the portion where the second pad pattern 124 is not provided) is F, the thickness of the portion of the second insulating film 132 covering the upper surface of the second pad pattern 124 is G, and the thickness of the portion of the second insulating film 132 extending between the upper surface of the second insulating layer 112 and the lower surface of the second pad pattern 124 is H, the conditions F>H and G+H>F can be satisfied. In this case, the aforementioned reliability improvement effect can be achieved more easily. Here, the aforementioned thicknesses F, G, and H can be the thickness of the second insulating film 132 in a first direction of the printed circuit board 100 (i.e., the direction along which the first insulating layer 111 and the second insulating layer 112 are stacked).

[0035] Furthermore, when the thickness of the portion of the second insulating film 132 covering and contacting the side surface of the via pattern 141 is J, the condition H>J can be satisfied. Here, the thickness J can be the thickness of the second insulating film 132 in the second direction of the printed circuit board 100 (i.e., parallel to the upper surface of the second insulating layer 112 and / or perpendicular to the first direction of the printed circuit board 100). For example, in order to make the via pattern 141 contact the first pad pattern 123, it may be necessary to remove at least a portion of the second insulating film 132 deposited on the bottom surface of the via hole vh in which the via pattern 141 will be formed. For example, the removal step described above can be performed using a trimming process utilizing an ion beam. During this process, a portion of the second insulating film 132 deposited on the wall surface of the via hole vh may also be removed, thereby allowing the second insulating film 132 to satisfy the aforementioned thickness relationship. For example, when this thickness relationship is satisfied, conductivity can be improved. Furthermore, reliability can be further improved.

[0036] Furthermore, when the thickness of the first portion of the first pad pattern 123 connected to the via pattern 141 (e.g., the central portion of the first pad pattern 123) is K, and the thickness of the second portion of the first pad pattern 123 surrounding at least a portion of the first portion (e.g., the outer peripheral portion of the first pad pattern 123) is L, L>K can be satisfied. For example, as described above, when at least a portion of the second insulating film 132 deposited on the bottom surface of the via vh is removed, at least a portion of the first pad pattern 123 exposed through the via vh may also be removed. Therefore, the thickness of the corresponding first portion (e.g., the central portion) can be reduced, and the above-described thickness relationship can be satisfied. For example, when this thickness relationship is satisfied, conductivity can be improved. In addition, reliability can be further improved. Here, the aforementioned thicknesses K and L can be the thickness of the first pad pattern 123 in a first direction of the printed circuit board 100 (i.e., the direction along which the first insulating layer 111 and the second insulating layer 112 are stacked).

[0037] Furthermore, the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 may all comprise a photosensitive organic insulating material, such as at least one of polyimide resins, phenolic resins, and polybenzoxazole resins, thereby further facilitating the realization of the first conductor pattern 121 and the second conductor pattern 122 as a fine pattern. Additionally, the first insulating film 131 and the second insulating film 132 (e.g., 1-1 insulating film 131-1 and 1-2 insulating film 131-2, and 2-1 insulating film 132-1 and 2-2 insulating film 132-2) may all be formed as thin film coatings using chemical vapor deposition (CVD) or atomic layer deposition (ALD), and therefore may all comprise an inorganic insulating material, such as at least one of Al2O3, SiO2, SiON, Si3N4, TiO2, TiON, and AlON. In this case, the first conductor pattern 121 and the second conductor pattern 122, the first pad pattern 123 and the second pad pattern 124, and the via pattern 141 can be more easily passivated.

[0038] Additionally, the first conductor pattern 121 and the first pad pattern 123 may each include a first seed metal layer sm1 and a first pattern metal layer pm1 disposed on the first seed metal layer sm1. Furthermore, the second conductor pattern 122, the second pad pattern 124, and the via pattern 141 may each include a second seed metal layer sm2 and a second pattern metal layer pm2 disposed on the second seed metal layer sm2. The first seed metal layer sm1 may include a first layer sm1-1 containing titanium and a second layer sm1-2 disposed on the first layer sm1-1 and containing copper. The second seed metal layer sm2 may include a first layer sm2-1 containing titanium and a second layer sm2-2 disposed on the first layer sm2-1 and containing copper. For example, the first seed metal layer sm1 and the second seed metal layer sm2 may both be formed by a sputtering process, and may both include, but are not limited to, sputtered titanium and sputtered copper layers. The first pattern metal layer pm1 and the second pattern metal layer pm2 may both include a third layer containing copper. For example, the first patterned metal layer pm1 and the second patterned metal layer pm2 can both be formed by an electrolytic plating process, and may include, but are not limited to, an electrolytic copper plating layer. The third layer may be thicker than each of the first layers sm1-1, sm2-1 and the second layers sm1-2, sm2-2.

[0039] In the following description, the components of the printed circuit board 100 according to the example will be described in more detail with reference to the accompanying drawings.

[0040] The first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 may all comprise an insulating material. The insulating material may include an organic insulating material. The organic insulating material may include thermosetting resins such as epoxy resins, thermoplastic resins such as polyimides, or materials comprising resins and inorganic fillers, organic fillers, and / or glass fibers (such as glass fabrics, for example, glass cloth). Specifically, the insulating material may include a photosensitive organic insulating material, and the photosensitive organic insulating material may include at least one of polyimide resins, phenolic resins, and polybenzoxazole resins. In this case, patterning processes, etc., may be simpler and more cost-effective than processes for forming silicon interposers or silicon bridges in related technologies. Furthermore, the first conductor pattern 121, the second conductor pattern 122, and the via pattern 141 can be easily formed into micropatterns and microvias. Therefore, a microcircuit substrate can be provided, and this microcircuit substrate can be easily applied as an interconnect bridge, a 2.1D redistribution layer (RDL), etc., to AI packaging substrates, server packaging substrates, etc.

[0041] The first conductor pattern 121 and the second conductor pattern 122, the first pad pattern 123 and the second pad pattern 124, and the via pattern 141 may all comprise a metallic material. The metallic material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. The first conductor pattern 121 and the second conductor pattern 122 may both comprise signal line patterns. The first pad pattern 123 and the second pad pattern 124 may both comprise signal pad patterns. If desired, power patterns and / or ground patterns may be further provided, and these patterns may each have line, pad, and / or planar shapes. The via pattern 141 may comprise a signal via pattern. If desired, power via patterns and / or ground via patterns may be further provided. The via pattern 141 may be integrated with the second pad pattern 124 without a boundary therebetween. The via pattern 141 may have a tapered shape in cross-section where the width at the upper end is greater than the width at the lower end. The first conductor pattern 121 and the first pad pattern 123 may each include a first seed metal layer sm1 and a first pattern metal layer pm1. The second conductor pattern 122, the second pad pattern 124, and the via pattern 141 may each include a second seed metal layer sm2 and a second pattern metal layer pm2. The first seed metal layer sm1 may include a first layer sm1-1 containing titanium and a second layer sm1-2 containing copper disposed on the first layer sm1-1. The second seed metal layer sm2 may include a first layer sm2-1 containing titanium and a second layer sm2-2 containing copper disposed on the first layer sm2-1. The first pattern metal layer pm1 and the second pattern metal layer pm2 may each include a third layer containing copper. In this case, it is more advantageous to form the above-mentioned micropatterns and microvias.

[0042] The first insulating film 131 and the second insulating film 132 may both comprise inorganic insulating materials. For example, the first insulating film 131 and the second insulating film 132 (more specifically, 1-1 insulating film 131-1 and 1-2 insulating film 131-2 and 2-1 insulating film 132-1 and 2-2 insulating film 132-2) may both comprise at least one of Al2O3, SiO2, SiON, Si3N4, TiO2, TiON, and AlON. In this case, the first conductor pattern 121 and the second conductor pattern 122, the first pad pattern 123 and the second pad pattern 124, and the via pattern 141 can be more easily passivated. Therefore, even in high-temperature and high-humidity environments such as unbiased high accelerated stress testing (uHAST) and biased high accelerated stress testing (bHAST), moisture penetration can be easily prevented. Therefore, stable electrical performance can be maintained without micropattern migration (e.g., copper migration), and thus, it can be easily applied to various types of packaged microcircuit boards requiring high reliability.

[0043] Additionally, additional conductor patterns, pad patterns, via patterns, insulating films, and insulating layers can be formed on the third insulating layer 113 as needed. The above can be applied substantially similarly to the additional conductor patterns, pad patterns, via patterns, insulating films, and insulating layers. Furthermore, a substrate layer 110 can be disposed beneath the first insulating layer 111. The substrate layer 110 can be a substrate made of various materials (such as organic insulating layers, inorganic insulating layers (e.g., ceramic layers, glass layers, etc.)). The substrate layer 110 may also be omitted.

[0044] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Figure 5F , Figure 5G and Figure 5H It shows the manufacturing process. Figure 2 A schematic cross-sectional view of an example of the R1 region of a printed circuit board.

[0045] Reference Figure 5A The substrate layer 110 can be prepared. The substrate layer 110 can be a substrate made of various materials as described above.

[0046] Reference Figure 5B A first insulating layer 111 can be formed on the substrate layer 110. The first insulating layer 111 can be formed by coating the substrate layer 110 with a PID material and curing it, or by laminating a film containing a PID material on the substrate layer 110 and curing it.

[0047] Reference Figure 5C An insulating film 131-1 can be formed on the first insulating layer 111. The insulating film 131-1 can be formed by depositing an inorganic insulating material using an ALD or CVD process.

[0048] Reference Figure 5D A first seed metal layer sm1 can be formed on the 1-1 insulating film 131-1. For example, a first layer sm1-1 containing titanium and a second layer sm1-2 containing copper can be sequentially formed on the 1-1 insulating film 131-1 using a sputtering process.

[0049] Reference Figure 5E A first patterned metal layer pm1 can be formed on a first seed metal layer sm1. The first patterned metal layer pm1 can be formed by the following steps: forming a photoresist coating on the first seed metal layer sm1, forming openings in the photoresist coating using a photolithography process, filling the openings using an electroplating process, and then removing the photoresist coating. For example, a first patterned metal layer pm1 including copper can be formed.

[0050] Reference Figure 5FThe portion of the first seed metal layer sm1 on which the first patterned metal layer pm1 is not formed can be removed using dry etching or the like. Therefore, the first conductor pattern 121 can be formed, and the first pad pattern 123 (not shown) can be formed. Additionally, during the dry etching process, portions of the 1-1 insulating film 131-1 in areas where the first patterned metal layer pm1 is not formed may be removed, thereby reducing the thickness of the 1-1 insulating film 131-1 in the corresponding areas.

[0051] Reference Figure 5G An insulating film 131-2 covering the first conductor pattern 121 can be formed on the insulating film 131-1. The insulating film 131-2 can also cover the first pad pattern 123. This enables the formation of a first insulating film 131 that passivates the first conductor pattern 121 and the first pad pattern 123. The insulating film 131-2 can be formed by depositing an inorganic insulating material using an ALD or CVD process.

[0052] Reference Figure 5H A second insulating layer 112 can be formed on the first insulating film 131. The second insulating layer 112 can be formed by coating the first insulating film 131 with PID material and curing it, or by laminating a film containing PID material on the first insulating film 131 and curing it.

[0053] The R1 area of ​​the printed circuit board according to the example can be manufactured through a series of processes, and other details can be substantially the same as those described above.

[0054] Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 6E , Figure 6F , Figure 6G and Figure 6H It shows the manufacturing process. Figure 2 A schematic cross-sectional view of an example of the R2 region of a printed circuit board.

[0055] Reference Figure 6A A substrate layer 110 can be prepared. Furthermore, a first insulating layer 111, an insulating film 131-1, a first pad pattern 123, an insulating film 131-2, and a second insulating layer 112 can be sequentially formed on the substrate layer 110. Specific details can be found in… Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Figure 5F , Figure 5G and Figure 5HThe descriptions are essentially the same. Subsequently, vias vh can be formed on the second insulating layer 112 to expose a portion of the upper surface of the insulating films 1-2 131-2 covering the first pad pattern 123. The vias vh can be formed using a photolithography process.

[0056] Reference Figure 6B An insulating film 132-1 (2-1) can be formed on the second insulating layer 112 and within the via hole vh. The insulating film 132-1 (2-1) can be formed by depositing an inorganic insulating material using an ALD or CVD process. The insulating film 132-1 (2-1) can be in contact with the insulating film 131-2 (1-2) at the bottom surface of the via hole vh.

[0057] Reference Figure 6C The 2-1 insulating film 132-1 and the 1-2 insulating film 131-2 disposed on the bottom surface of the via hole vh can be removed. For example, via photoresist can be formed in the hole formed by the 2-1 insulating film 132-1. An opening exposing the bottom surface of the hole formed by the 2-1 insulating film 132-1 can be formed in the via photoresist by a photolithography process, and the 2-1 insulating film 132-1 and the 1-2 insulating film 131-2 disposed on the bottom surface of the via hole vh can be removed by a dry etching process (e.g., using an ion beam trimming process). During this process, a portion of the 2-1 insulating film 132-1 disposed on the wall surface of the via hole vh may be removed, thereby reducing the thickness of the corresponding portion. In addition, the portion of the first pad pattern 123 exposed through the via hole vh may be removed, thereby reducing the thickness of the corresponding portion. The via photoresist can be removed after the trimming process.

[0058] Reference Figure 6D The second seed metal layer sm2 can be formed on the 2-1 insulating film 132-1 (including the portion located on the wall surface of the via hole vh) and the portions of the first pad pattern 123 and the 1-2 insulating film 131-2 exposed through the via hole vh. For example, the second seed metal layer sm2 can be formed by sequentially forming a first layer sm2-1 containing titanium and a second layer sm2-2 containing copper on the 2-1 insulating film 132-1 (including the portion located on the wall surface of the via hole vh) and the portions of the first pad pattern 123 and the 1-2 insulating film 131-2 exposed through the via hole vh using a sputtering process.

[0059] Reference Figure 6E A second patterned metal layer pm2 can be formed on the second seed metal layer sm2. The second patterned metal layer pm2 can be formed by forming a coated photoresist on the second seed metal layer sm2, forming openings in the coated photoresist using a photolithography process, filling the openings using an electroplating process, and then removing the coated photoresist. For example, a second patterned metal layer pm2 containing copper can be formed.

[0060] Reference Figure 6F The portion of the second seed metal layer sm2 on which the second patterned metal layer pm2 is not formed can be removed using dry etching or similar methods. Therefore, the second pad pattern 124 can be formed. Furthermore, the second conductor pattern 122 (not shown) can also be formed. Additionally, during the dry etching process, portions of the 2-1 insulating film 132-1 in the areas where the second patterned metal layer pm2 is not formed may be removed, thereby reducing the thickness of the 2-1 insulating film 132-1 in the corresponding portions.

[0061] Reference Figure 6G A 2-2 insulating film 132-2 covering the second pad pattern 124 can be formed on the second insulating film 132-1. The 2-2 insulating film 132-2 can also cover the second conductor pattern 122. Therefore, a second insulating film 132 can be formed to passivate the second conductor pattern 122 and the second pad pattern 124. The 2-2 insulating film 132-2 can be formed by depositing an inorganic insulating material using an ALD or CVD process.

[0062] Reference Figure 6H A third insulating layer 113 can be formed on the second insulating film 132. The third insulating layer 113 can be formed by coating the second insulating film 132 with PID material and curing it, or by laminating a film containing PID material on the second insulating film 132 and curing it.

[0063] The R2 area of ​​the printed circuit board according to the example can be manufactured through a series of processes, and other details can be substantially the same as those described above.

[0064] Figure 7 This is a cross-sectional view schematically showing an example of a packaging substrate and a semiconductor package including the packaging substrate.

[0065] Reference Figure 7 The package substrate 200 according to the example may include a circuit substrate 210 and interconnect members 220 disposed within the circuit substrate 210. Furthermore, the semiconductor package 500 according to the example may include the package substrate 200 and a first semiconductor chip 410 and a second semiconductor chip 420 mounted on the package substrate 200. The circuit substrate 210 may be a conventional multilayer printed circuit board, and its specific structure is not particularly limited. The interconnect member 220 may be a bridging substrate 220 including micropatterns interconnecting the first semiconductor chip 410 and the second semiconductor chip 420. The bridging substrate 220 may be embedded within the circuit substrate 210. The bridging substrate 220 may include the printed circuit board 100 according to the example described above. Each of the first semiconductor chip 410 and the second semiconductor chip 420 may be a memory chip, an application processor chip, or a logic chip. The first semiconductor chip 410 and the second semiconductor chip 420 may be the same type of chip or different types of chips.

[0066] Figure 8 This is a cross-sectional view schematically showing another example of a packaging substrate and a semiconductor package including the packaging substrate.

[0067] Reference Figure 8According to another example, the package substrate 300 may include a circuit substrate 310 and interconnect members 320 disposed on the circuit substrate 310. Furthermore, according to another example, the semiconductor package 600 may include a package substrate 300 and a first semiconductor chip 410 and a second semiconductor chip 420 mounted on the package substrate 300. The circuit substrate 310 may be a conventional multilayer printed circuit board, and its specific structure is not particularly limited. The interconnect members 320 may be disposed at the outermost edge of the circuit substrate 310 and may be a microcircuit redistribution layer 320 including micropatterns interconnecting the first semiconductor chip 410 and the second semiconductor chip 420. The microcircuit redistribution layer 320 may be a 2.1D RDL. The microcircuit redistribution layer 320 may include the printed circuit board 100 according to the above example. For example, the microcircuit redistribution layer 320 may include: a first insulating layer 111; a first conductor pattern 121 disposed on the first insulating layer 111; a first insulating film 131 covering the first insulating layer 111 and the first conductor pattern 121, and extending between the upper surface of the first insulating layer 111 and the lower surface of the first conductor pattern 121; and a second insulating layer 112 disposed on the first insulating film 131; wherein, when the first insulating film 131 covers the upper surface of the first insulating layer 111 and the first conductor pattern 121 is not formed thereon... When the thickness of the portion of the microcircuit redistribution layer 320 in the first direction is C, and the thickness of the portion of the first insulating film 131 extending between the upper surface of the first insulating layer 111 and the lower surface of the first conductor pattern 121 in the first direction of the microcircuit redistribution layer 320 is E, C>E, the first direction is the direction along which the first insulating layer 111 and the second insulating layer 112 are stacked, and wherein both the first insulating layer 111 and the second insulating layer 112 comprise photosensitive organic insulating material, and the first insulating film 131 comprises inorganic insulating material. The first insulating film 131 may include: 1-1 insulating film 131-1, disposed on the upper surface of the first insulating layer 111 and extending between the upper surface of the first insulating layer 111 and the lower surface of the first conductor pattern 121; and 1-2 insulating film 131-2, disposed on the upper surface of 1-1 insulating film 131-1 and covering at least a portion of each of the side surfaces and the upper surface of the first conductor pattern 121 along the shape of the first conductor pattern 121. The thickness D of the portion of the first insulating film 131 covering the upper surface of the first conductor pattern 121 in the first direction of the microcircuit redistribution layer 320 satisfies D+E>C, and wherein the first insulating film 131 is formed by atomic layer deposition or chemical vapor deposition, and includes at least one of Al2O3, SiO2, SiON, Si3N4, TiO2, TiON, and AlON. Each of the first semiconductor chip 410 and the second semiconductor chip 420 may be a memory chip, an application processor chip, or a logic chip.The first semiconductor chip 410 and the second semiconductor chip 420 can be the same type of chip or different types of chips.

[0068] As described above, according to embodiments, printed circuit boards and packaging substrates in which micropatterns can be reliably implemented can be provided.

[0069] According to an embodiment, a printed circuit board and packaging substrate may be provided that can improve reliability by suppressing copper migration.

[0070] In this disclosure, the term "cover" can include covering a portion or the entirety of a component, and can also include direct or indirect coverage. Furthermore, the term "fill" can include not only complete filling but also partial filling and approximate filling. Similarly, the term "surround" can include not only complete surrounding but also partial and approximate surrounding. Moreover, "expose" can include not only complete exposure but also partial exposure, and can refer to a component being exposed from another component it is embedded in.

[0071] In this disclosure, the term "section" can refer to the cross-sectional shape when an object is cut vertically, or the cross-sectional shape when the object is viewed from a side view. Furthermore, the term "plane" can refer to the planar shape when an object is cut horizontally, or the planar shape when the object is viewed from a top or bottom view.

[0072] In this disclosure, for convenience, the term "lower" in terms such as "lower side," "lower part," and "lower surface" is used to indicate a downward direction based on the cross-section in the accompanying drawings, and the term "upper side," "upper part," and "upper surface" is used to indicate the opposite direction. However, these directions are defined for ease of description, and the scope of the claims is not particularly limited by the description of these directions; of course, the concepts of "upper" and "lower" can be changed at any time.

[0073] In this disclosure, "connection" is defined not only as a direct connection but also as an indirect connection, such as through an adhesive layer. Furthermore, "electrical connection" encompasses both physical and non-physical connections. Additionally, expressions such as "first," "second," etc., are used to distinguish one component from another and do not limit the order and / or importance of the components. In some cases, without departing from the scope of the claims, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0074] In this disclosure, thickness, width, linewidth, spacing, etc., can be measured using a scanning electron microscope or an optical microscope based on a cross-section obtained by polishing or cutting a printed circuit board. The cross-section can be a vertical or horizontal cross-section, and each value can be measured based on the desired cross-section. For example, the width of the upper and / or lower ends of a via can be measured on a cross-section obtained by cutting the via along its central axis. In this case, if the value is not constant, it can be determined as the average of values ​​measured at five arbitrary points.

[0075] The expression "(a) example" as used in this disclosure does not imply the same embodiment, but is provided to emphasize and describe different and unique characteristics. However, the examples presented above do not preclude implementation by combining features with other examples. For example, unless a contrary or contradictory description exists in another example, the content described in a particular example may be understood to be related to the other example even if it is not described in another example.

[0076] The terminology used in this disclosure is for illustrative purposes only and is not intended to limit the disclosure. In this context, unless the context clearly indicates otherwise, the singular expressions also include their plural meanings.

[0077] While exemplary embodiments have been shown and described above, it will be readily understood by those skilled in the art that modifications and variations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A printed circuit board, comprising: First insulating layer; A first conductor pattern is disposed on the first insulating layer; A first insulating film covers at least a portion of the upper surface of the first insulating layer and at least a portion of each of the side and upper surfaces of the first conductor pattern, and extends between the upper surface of the first insulating layer and the lower surface of the first conductor pattern. as well as The second insulating layer is disposed on the first insulating film. Wherein, when the thickness of the portion of the first insulating film covering the upper surface of the first insulating layer and on which the first conductor pattern is not formed is C in the first direction of the printed circuit board, and the thickness of the portion of the first insulating film extending between the upper surface of the first insulating layer and the lower surface of the first conductor pattern in the first direction of the printed circuit board is E, C>E is satisfied, and the first direction of the printed circuit board is the direction along which the first insulating layer and the second insulating layer are stacked.

2. The printed circuit board according to claim 1, wherein, When the thickness of the portion of the first insulating film covering the upper surface of the first conductor pattern in the first direction of the printed circuit board is D, D+E>C is satisfied.

3. The printed circuit board according to claim 1, wherein, The first insulating film includes: 1-1 insulating film disposed on the upper surface of the first insulating layer and extending between the upper surface of the first insulating layer and the lower surface of the first conductor pattern; and 1-2 insulating film disposed on the upper surface of the 1-1 insulating film and covering at least a portion of each of the upper surface and the side surface of the first conductor pattern along the shape of the first conductor pattern.

4. The printed circuit board according to claim 3, wherein, When the thickness of the portion of the 1-1 insulating film disposed on the upper surface of the first insulating layer without the first conductor pattern formed thereon is A in the first direction of the printed circuit board, and the thickness of the portion of the 1-1 insulating film extending between the upper surface of the first insulating layer and the lower surface of the first conductor pattern in the first direction of the printed circuit board is B, then B>A is satisfied.

5. The printed circuit board according to claim 3, wherein, The 1-1 insulating film and the 1-2 insulating film comprise the same inorganic insulating material.

6. The printed circuit board according to claim 1, wherein, Both the first insulating layer and the second insulating layer comprise photosensitive organic insulating material, and The first insulating film comprises an inorganic insulating material.

7. The printed circuit board according to claim 6, wherein, The photosensitive organic insulating material includes at least one of polyimide resin, phenolic resin, and polybenzoxazole resin, and The inorganic insulating material includes at least one of Al2O3, SiO2, SiON, Si3N4, TiO2, TiON and AlON.

8. The printed circuit board according to claim 1, wherein, The first conductor pattern is configured as multiple first conductor patterns. Each of the plurality of first conductor patterns has a linewidth of 1 μm to 3 μm, and The spacing between adjacent first conductor patterns in the plurality of first conductor patterns is 1 μm to 3 μm.

9. The printed circuit board according to claim 1, further comprising: A second conductor pattern is disposed on the second insulating layer; A second insulating film covers at least a portion of the upper surface of the second insulating layer and at least a portion of each of the side and upper surfaces of the second conductor pattern, and extends between the upper surface of the second insulating layer and the lower surface of the second conductor pattern; as well as The third insulating layer is disposed on the second insulating film.

10. The printed circuit board according to claim 9, wherein, The second insulating film includes: an insulating film 2-1 disposed on the upper surface of the second insulating layer and extending between the upper surface of the second insulating layer and the lower surface of the second conductor pattern; and an insulating film 2-2 disposed on the upper surface of the insulating film 2-1 and covering at least a portion of each of the upper surface and the side surface of the second conductor pattern along the shape of the second conductor pattern.

11. The printed circuit board according to claim 9, further comprising: The first pad pattern is set on the first insulating layer; The second pad pattern is set on the second insulating layer; as well as A via pattern is disposed between the first pad pattern and the second pad pattern, and connects the first pad pattern and the second pad pattern to each other. The first insulating film also covers at least a portion of each of the side and top surfaces of the first pad pattern, extends between the top surface of the first insulating layer and the bottom surface of the first pad pattern, and also covers at least a portion of the side surface of the via pattern. The second insulating film also covers at least a portion of each of the side and top surfaces of the second pad pattern, extends between the top surface of the second insulating layer and the bottom surface of the second pad pattern, and also covers at least another portion of the side surface of the via pattern; and The first insulating film and the second insulating film are connected to each other.

12. The printed circuit board according to claim 11, wherein, When the thickness of the portion of the second insulating film covering the upper surface of the second insulating layer where the second pad pattern is not formed is F in the first direction of the printed circuit board, the thickness of the portion of the second insulating film covering the upper surface of the second pad pattern in the first direction of the printed circuit board is G, and the thickness of the portion of the second insulating film extending between the upper surface of the second insulating layer and the lower surface of the second pad pattern in the first direction of the printed circuit board is H, G+H>F is satisfied.

13. The printed circuit board according to claim 12, wherein, When the thickness of the portion of the second insulating film covering the side surface of the via pattern is J in the second direction of the printed circuit board, H>J is satisfied, and the second direction of the printed circuit board is parallel to the upper surface of the second insulating layer and / or perpendicular to the first direction of the printed circuit board.

14. The printed circuit board according to claim 12, wherein, When the thickness of the first portion of the first pad pattern connected to the via pattern in the first direction of the printed circuit board is K, and the thickness of the second portion of the first pad pattern surrounding at least a portion of the first portion in the first direction of the printed circuit board is L, L>K is satisfied.

15. The printed circuit board according to claim 11, wherein, Both the first conductor pattern and the first pad pattern include a first seed metal layer and a first pattern metal layer disposed on the first seed metal layer. The second conductor pattern, the second pad pattern, and the via pattern all include a second seed metal layer and a second pattern metal layer disposed on the second seed metal layer. Both the first seed metal layer and the second seed metal layer include a first layer containing titanium and a second layer disposed on the first layer and containing copper. Both the first patterned metal layer and the second patterned metal layer include a third layer containing copper, and The third layer is thicker than each of the first and second layers.

16. A packaging substrate, comprising: Circuit board; and Interconnecting components are disposed in the circuit board. The interconnecting components include printed circuit boards according to any one of claims 1 to 15.

17. A packaging substrate, comprising: Circuit board; and An interconnect component is disposed on the outermost side of the circuit substrate, the interconnect component including a microcircuit redistribution layer, the microcircuit redistribution layer comprising: First insulating layer; A first conductor pattern is disposed on the first insulating layer; A first insulating film covers the first insulating layer and the first conductor pattern, and extends between the upper surface of the first insulating layer and the lower surface of the first conductor pattern; and A second insulating layer is disposed on the first insulating film; Wherein, when the thickness of the portion of the first insulating film covering the upper surface of the first insulating layer on which the first conductor pattern is not formed is C in the first direction of the microcircuit redistribution layer, and the thickness of the portion of the first insulating film extending between the upper surface of the first insulating layer and the lower surface of the first conductor pattern in the first direction of the microcircuit redistribution layer is E, C>E is satisfied, and the first direction of the microcircuit redistribution layer is the direction along which the first insulating layer and the second insulating layer are stacked, and The first insulating layer and the second insulating layer both include photosensitive organic insulating materials, and the first insulating film includes inorganic insulating materials.

18. The packaging substrate according to claim 17, wherein, The first insulating film includes: 1-1 insulating film disposed on the upper surface of the first insulating layer and extending between the upper surface of the first insulating layer and the lower surface of the first conductor pattern; and 1-2 insulating film disposed on the upper surface of the 1-1 insulating film and covering at least a portion of each of the side surface and the upper surface of the first conductor pattern along the shape of the first conductor pattern.

19. The packaging substrate according to claim 17, wherein, The thickness D of the portion of the first insulating film covering the upper surface of the first conductor pattern in the first direction of the microcircuit redistribution layer satisfies D+E>C, and wherein the first insulating film is formed by atomic layer deposition or chemical vapor deposition, and includes at least one of Al2O3, SiO2, SiON, Si3N4, TiO2, TiON and AlON.

20. A semiconductor package, comprising: The packaging substrate according to any one of claims 16 to 19; as well as A first semiconductor chip and a second semiconductor chip are mounted on the packaging substrate and interconnected by the interconnecting member.

21. The semiconductor package of claim 20, wherein, Each of the first semiconductor chip and the second semiconductor chip is a memory chip, an application processor chip, or a logic chip, and the first semiconductor chip and the second semiconductor chip are of the same type or different types of chips.

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