PCB manufacturing method and device for improving via signal integrity

Abstract

The application relates to a PCB manufacturing method and device for improving via hole signal integrity, which comprises the following steps: performing first drilling processing on a first multilayer board to manufacture a first drilled hole, performing first copper plating processing on the hole wall of the first drilled hole to manufacture a first copper plating layer, and performing first resin hole filling processing on the first drilled hole; pressing a first outer layer board on the first surface and / or the second surface of the first multilayer board to form a second multilayer board; performing second drilling processing on the second multilayer board to manufacture a second drilled hole, wherein the second drilled hole is located in the first drilled hole, performing second copper plating processing on the hole wall of the first drilled hole to manufacture a second copper plating layer, and performing second resin hole filling processing on the second drilled hole; the application optimizes the via hole structure through double drilling, copper plating and resin hole filling processing, reduces impedance discontinuity and parasitic parameters, effectively reduces signal reflection and parasitic effects caused by the via hole, and improves the integrity and reliability of high-speed signal transmission.

Description

Technical Field

[0001] This invention relates to the field of PCB manufacturing technology, specifically to a PCB manufacturing method and apparatus for improving the signal integrity of vias. Background Technology

[0002] In high-speed digital circuits and high-frequency microwave systems, the physical structure of PCB vias transforms them from mere electrical connection points into distributed components with parasitic parameters, posing significant challenges to signal integrity and electromagnetic compatibility. The geometric characteristics of via pads, apertures, and anti-pads typically result in characteristic impedances that are approximately 6%–12% lower than conventional transmission lines, creating impedance abrupt changes and triggering signal reflections. While the amount of a single reflection is limited, the cumulative effect of reflections in cascaded vias or high-speed serial links can significantly degrade the receiver's eye diagram. Simultaneously, the inherent parasitic capacitance (approximately 0.5 pF) and parasitic inductance (approximately 1 nH) of vias prolong signal rise time, reduce bandwidth, and exhibit considerable inductive reactance at high frequencies (e.g., inductive reactance exceeding 3 Ω at a 1 ns rise time). The superposition of multiple vias leads to transmission delay deviations and jitter. When signals change layers and the reference plane is discontinuous, the return current is forced to detour, forming a large current loop, inducing ground bounce noise and enhancing differential-mode radiation, significantly increasing the risk of electromagnetic interference, especially in the GHz band. In addition, under high-density wiring conditions, coupling between adjacent vias can cause crosstalk, and asymmetric structures can easily convert differential-mode signals into common-mode noise, further degrading common-mode rejection capability and aggravating EMI radiation.

[0003] The aforementioned problems make it difficult for traditional ideal interconnect design methods to meet the ever-increasing speed requirements, and there is an urgent need for accurate modeling and optimization design of vias. Summary of the Invention

[0004] In view of the above problems, embodiments of the present invention provide a PCB manufacturing method and apparatus for improving the signal integrity of vias, which is used to solve the problem that traditional ideal interconnect design methods are difficult to meet the ever-increasing speed requirements.

[0005] According to one aspect of the present invention, a PCB fabrication method for improving via signal integrity is provided, the method comprising: Fabricate the first multilayer board; The first multilayer board is drilled to create a first hole, the hole wall of the first hole is copper plated to create a first copper plating layer, and the first hole is filled with resin plugging. A first outer layer is pressed onto the first surface and / or the second surface of the first multilayer board to form a second multilayer board; The second multilayer board is subjected to a second drilling process to create a second hole, and the second hole is located inside the first hole. A second copper plating layer is created on the hole wall of the first hole through a second copper plating process, and the second hole is filled with a second resin plugging process. The second multilayer board is then processed in subsequent steps to produce the target PCB board.

[0006] In some embodiments, both the first drilling process and the second drilling process are performed by mechanical drilling, wherein the first drilling is a through hole penetrating the first multilayer board, and the second drilling is a through hole penetrating the second multilayer board.

[0007] In some embodiments, the first copper plating layer on the borehole wall of the first drilled hole is connected to the power ground to form a grounded GND layer.

[0008] In some embodiments, during the first resin plugging process, the first drilled hole is plugged at least once from the first surface of the first multilayer board, the first drilled hole is plugged at least once from the second surface of the first multilayer board, and the first multilayer board is subjected to baking and resin grinding processes to complete the filling of the first drilled hole. In the second resin plugging process, the second drilled hole is plugged at least once from the first surface of the second multilayer board, the second drilled hole is plugged at least once from the second surface of the first multilayer board, and the second multilayer board is baked and resin polished to fill the second drilled hole.

[0009] In some embodiments, both the first copper plating process and the second copper plating process include: The first multilayer board or the second multilayer board is immersed in an activation solution for activation treatment to form an activation layer on the hole wall of the first drilled hole or the second drilled hole. The first multilayer board or the second multilayer board is immersed in a copper plating solution to allow the activation layer to undergo a displacement reaction with the copper ions in the copper plating solution, so as to form a thin copper layer in the first drilled hole or the second drilled hole. The first and second drilled holes are subjected to pattern electroplating to thicken the thin copper layer, thereby forming a first copper plating layer or a second copper plating layer.

[0010] In some embodiments, during the second drilling process, a third hole is also formed in the second multilayer board, and the third hole is located outside the first hole; during the second copper plating process, a third copper plating layer is formed on the hole wall of the third hole, and the third hole is filled by a second resin plugging process; the third copper plating layer of the third hole enables communication connection between the core boards of the second multilayer board.

[0011] In some implementations, fabricating the first multilayer board specifically includes: The raw material board is cut into core boards using a slitting device; The core board is processed to create inner layer circuitry, and the inner layer circuitry is then subjected to inner layer AOI inspection. Multiple core boards are pressed together using a pressing device to form a first multilayer board.

[0012] In some embodiments, after the first drilling process is performed on the first multilayer board to create the first hole, and before the first copper plating process is performed on the hole wall of the first hole to create the first copper plating layer, the method further includes: The first multilayer board is subjected to plasma adhesive removal treatment using a plasma device.

[0013] In some embodiments, the second multilayer board undergoes post-processing to fabricate the target PCB board, specifically including: The second multilayer board is subjected to cap electroplating to form a third copper plating layer at the second drilled location of the second multilayer board. The second multilayer board is processed to create outer layer circuitry, and the outer layer circuitry is then subjected to outer layer AOI inspection. The second multilayer board is subjected to solder resist treatment to create a solder resist layer on the outer surface of the second multilayer board; Text processing is performed on the second multilayer board to form a text layer in the solder resist layer of the second multilayer board; The second multilayer board is subjected to molding process to produce the target PCB board.

[0014] According to another aspect of the present invention, a PCB fabrication apparatus for improving via signal integrity is provided, the apparatus being used to perform the above-described PCB fabrication method for improving via signal integrity.

[0015] The PCB manufacturing method and apparatus for improving via signal integrity of the present invention have the following advantages: The present invention includes: manufacturing a first multilayer board; performing a first drilling process on the first multilayer board to create a first drilled hole, performing a first copper plating process on the hole wall of the first drilled hole to create a first copper plating layer, and performing a first resin plugging process to fill the first drilled hole; pressing a first outer layer board onto a first surface and / or a second surface of the first multilayer board to form a second multilayer board; performing a second drilling process on the second multilayer board to create a second drilled hole, wherein the second drilled hole is located inside the first drilled hole, performing a second copper plating process on the hole wall of the first drilled hole to create a second copper plating layer, and performing a second resin plugging process to fill the second drilled hole; performing post-processing on the second multilayer board to manufacture a target PCB board. By optimizing the via structure through double drilling, copper plating, and resin plugging, impedance discontinuities and parasitic parameters are reduced, effectively reducing signal reflection and parasitic effects caused by vias, and improving the integrity and reliability of high-speed signal transmission.

[0016] The above description is merely an overview of the technical solutions of the embodiments of the present invention. In order to better understand the technical means of the embodiments of the present invention and to implement them in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the embodiments of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description

[0017] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings: Figure 1 A flowchart illustrating a PCB fabrication method for improving via signal integrity according to an embodiment of the present invention is shown. Figure 2 A flowchart illustrating step S1 of an embodiment provided by the present invention is shown; Figure 3 A flowchart illustrating step S5 of an embodiment provided by the present invention is shown; Figure 4 A schematic diagram of the first drilling process of a first multilayer board according to an embodiment of the present invention is shown. Figure 5 This diagram illustrates the structure of a first multilayer board undergoing a first copper plating process and a first resin plugging process, according to an embodiment of the present invention. Figure 6 This diagram illustrates a structure provided by an embodiment of the present invention, showing the bonding of a first outer layer to a first multilayer board. Figure 7 This diagram illustrates a structure for a second drilling process in a second multilayer board according to an embodiment of the present invention. Figure 8This diagram illustrates the structure of the target PCB board according to an embodiment of the present invention. Figure 9 The diagram shows a first borehole and a second borehole according to an embodiment of the present invention.

[0018] Figure descriptions: 1. First multilayer board; 2. First drilled hole; 3. First copper plating layer; 4. Resin filling; 5. First outer layer board; 6. Second multilayer board; 7. Second drilled hole; 8. Third drilled hole; 9. Second copper plating layer; 10. Third copper plating layer; 11. Outer layer circuit; L2-L7, First multilayer board; L1 / L8, First outer layer board. Detailed Implementation

[0019] Exemplary embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0020] Example 1, Figure 1 This illustration shows a first embodiment of a PCB fabrication method for improving via signal integrity, addressing the problem that traditional ideal interconnect design methods struggle to meet ever-increasing speed requirements. The method includes: S1, Fabrication of the first multilayer board; In step S1, the first multilayer board is fabricated. The first multilayer board can be formed by laminating multiple core boards and dielectric layers, and contains a pre-defined conductive layer and insulating layer. For example, conventional lamination technology can be used to laminate prepreg and copper foil layers to form a substrate with a specific number of layers.

[0021] S2, the first multilayer board is drilled to create a first hole, the hole wall is copper-plated to create a first copper layer, and the first hole is filled with resin. In step S2, see... Figure 4 The first drilling process can be performed using laser drilling equipment or mechanical drilling equipment. A laser beam or mechanical drill bit is used to create through-holes or non-through-holes in the first multilayer board. For example, laser parameters can be set to create a first hole with a diameter of X micrometers at a specified location. The first copper plating process can include two stages: chemical copper plating and electroplating. For example, the first multilayer board after drilling is first immersed in a chemical copper plating solution to form a thin layer of chemical copper on the hole wall surface, followed by electroplating to thicken the copper layer to a preset thickness. The first resin plugging process can be performed by filling the first drilled hole with liquid resin using a scraper or spraying method, followed by curing. For example, epoxy resin can be evenly filled into the first drilled hole using a scraper, and then baked to cure. A cross-sectional diagram of the first multilayer board undergoing the first copper plating and first resin plugging processes is shown below. Figure 5As shown.

[0022] S3, pressing the first outer layer onto the first surface and / or the second surface of the first multilayer board to form the second multilayer board; in step S3, see [link to step S3] Figure 6 The lamination process can employ vacuum lamination equipment to tightly bond the first outer layer to the first multilayer board under high temperature and high pressure conditions. For example, prepreg and copper foil can be used as the first outer layer and laminated with the first multilayer board that has already been plugged to form a new multilayer structure.

[0023] S4, a second drilling process is performed on the second multilayer board to create a second hole, which is located inside the first hole. A second copper plating layer is created on the hole wall of the first hole through a second copper plating process, and the second hole is filled with resin through a second resin plugging process. In step S4, see... Figure 7 The second drilling process can be performed using high-precision laser drilling equipment or mechanical drilling equipment to ensure that the second hole is precisely located in the center area of ​​the resin-filled first hole. For example, using a vision positioning system, a second hole with a diameter of Y micrometers can be precisely drilled within the resin-filled area of ​​the first hole, where Y is less than X. The second copper plating process is similar to the first copper plating process and can include chemical copper plating and electroplating. For example, the second multilayer board after drilling is immersed in a chemical copper plating solution to form a thin copper layer on the hole wall of the second hole, followed by electroplating to thicken the copper layer to a predetermined thickness. The second resin plugging process can be performed using a method similar to the first plugging process, filling the second hole with resin material and curing it. For example, a scraper is used to fill the second hole with resin and then baked to cure it, ensuring the smoothness and insulation of the interior of the second hole.

[0024] S5, perform post-processing on the second multilayer board to manufacture the target PCB board. In step S5, post-processing may include conventional PCB manufacturing steps such as outer layer circuitry fabrication, solder mask fabrication, text printing, and shaping. For example, outer layer circuitry is fabricated using processes such as photolithography and etching, then solder mask ink is applied, text is printed, and finally, the board is cut into the shape of the target PCB board using milling or stamping processes. See [link to target PCB board structure] for details. Figure 8 To create the first and second drilling lines, as shown below. Figure 9 As shown.

[0025] This invention effectively improves the signal integrity degradation caused by impedance discontinuities, parasitic effects, and return current path problems in traditional vias by creating a second drilled hole inside the first drilled hole and performing copper plating and resin plugging on both holes. The method optimizes the via structure, reduces signal reflection, and decreases parasitic capacitance and inductance, thereby improving signal transmission bandwidth and stability. It also helps suppress ground bounce noise and electromagnetic interference, enhancing the overall performance of PCBs in high-frequency, high-speed applications.

[0026] Example 2: Based on Embodiment 1, the present invention provides a first embodiment of a PCB fabrication method for improving via signal integrity, to further describe steps S1-S5 in Embodiment 1.

[0027] In some implementations, both the first and second drilling processes are performed using mechanical drilling. The first hole is a through hole penetrating the first multilayer board, and the second hole is a through hole penetrating the second multilayer board.

[0028] The above technical solution, employing mechanical drilling for both the first and second drilling processes, ensures the stability and controllability of the drilling process, resulting in more precise hole diameters and smooth hole walls, providing a solid foundation for subsequent copper plating. Furthermore, designing both the first and second drilled holes as through-holes simplifies the drilling process, avoiding the additional processing steps and costs associated with blind or buried vias. This through-hole structure, in nested via designs, provides a direct and low-impedance signal transmission path, helping to reduce signal reflection and loss, thereby effectively improving the signal integrity of the vias. This design not only ensures manufacturing feasibility and economy but also optimizes signal transmission performance.

[0029] In some implementations, the first copper plating layer on the wall of the first drilled hole is connected to the power ground to form a grounding GND layer. Specifically, connecting the first copper plating layer on the wall of the first drilled hole to the power ground means that during PCB manufacturing, the first copper plating layer, formed after the first copper plating process, is electrically connected to the power ground (GND) plane on the PCB board through a conductive path. This can be achieved in several ways: for example, when manufacturing the first multilayer board, its inner layers can be designed with dedicated grounding layers. When the first drilled hole is a through-hole penetrating the first multilayer board and passing through these grounding layers, the first copper plating layer can form a reliable electrical connection with these grounding layers through subsequent copper plating processes. Alternatively, grounding rings or grounding pads can be designed on the outer or inner layers of the first multilayer board, and the first copper plating layer can be connected to these grounding rings or grounding pads through conductive traces, thereby connecting to the power ground of the entire system. This connection ensures that the first copper plating layer is in a stable low potential state.

[0030] Forming a grounding GND layer refers to connecting the first copper plating layer on the wall of the first drilled via to the power ground, so that the copper plating layer functionally acts as or becomes an effective grounding shield structure. In PCB design, the grounding GND layer is typically one or more large-area copper foil layers used to provide a common potential reference point and serve as a signal return path and electromagnetic shielding. In this embodiment, the first copper plating layer is effectively integrated into the PCB's grounding system, forming a grounding cylinder surrounding the via. This grounding cylinder provides effective electromagnetic shielding for the internal second drilled via and the signals it carries, thereby isolating internal signals from the external environment and reducing the coupling of electromagnetic radiation and external interference.

[0031] The above technical solution connects the first copper plating layer on the wall of the first drilled hole to the power ground, forming an effective grounding GND layer. This grounding GND layer acts as an electromagnetic shield, effectively isolating the second drilled hole and its signal lines from the external environment. This grounding shielding structure significantly reduces electromagnetic radiation generated by the via during high-speed signal transmission and effectively suppresses the coupling of external electromagnetic interference to internal signals, thereby greatly reducing signal crosstalk and reflection, ensuring the integrity and stability of signal transmission. Compared to vias that only undergo copper plating, the introduction of this grounding GND layer provides a low-impedance return path for internal signals, further optimizing the signal loop. Especially for high-frequency signals, it effectively avoids ground bounce noise and common-mode noise, thus improving the overall signal integrity of the PCB board.

[0032] In some embodiments, during the first resin plugging process, the first drilled hole is plugged at least once from the first surface of the first multilayer board, the first drilled hole is plugged at least once from the second surface of the first multilayer board, and the first multilayer board is subjected to baking and resin grinding processes to complete the filling of the first drilled hole. In the second resin plugging process, the second hole is plugged at least once from the first surface of the second multilayer board, the second hole is plugged at least once from the second surface of the first multilayer board, and the second multilayer board is baked and resin polished to fill the second hole.

[0033] By employing the above technical solution, when performing resin plugging on the first and second drilled holes, a plugging process is applied at least once from both sides of the board. This significantly improves the filling rate and uniformity of the resin material within the drilled holes, effectively avoiding defects such as voids and bubbles that may occur with traditional single-sided plugging. The subsequent baking process ensures complete curing of the resin material, imparting stable mechanical properties to the filler. Furthermore, the resin grinding process precisely removes excess resin from the surface, ensuring the plugged area is flush with the board surface. This provides a flat and precise base for subsequent lamination, nested drilling, and outer layer circuitry. This refined plugging, curing, and grinding process not only ensures the structural integrity and reliability of the vias but also effectively reduces impedance discontinuities in the signal transmission path by eliminating surface unevenness, thereby significantly improving the signal integrity of the vias. This is particularly crucial for ensuring the transmission performance of high-frequency and high-speed signals.

[0034] In some embodiments, both the first and second copper plating processes include: The first or second multilayer board is immersed in an activation solution to form an activation layer on the hole wall of the first or second drilled hole. The first or second multilayer board is immersed in a copper plating solution to allow the activation layer to undergo a displacement reaction with the copper ions in the copper plating solution, thereby forming a thin copper layer in the first or second drilled hole. The first and second drilled holes are subjected to patterned electroplating to thicken the thin copper layer, forming a first or second copper plating layer.

[0035] Specifically, activation treatment is a crucial pretreatment step before electroless copper plating. Its purpose is to deposit a catalytically active substance, or activation layer, onto the non-conductive borehole wall surface, allowing the subsequent electroless copper plating reaction to proceed uniformly on its surface. This solves the problem that the resin material itself is non-conductive and cannot be directly electroplated. Activation treatment is typically achieved by immersing the first or second multilayer board in an activation solution containing noble metal (such as palladium) ions. Palladium ions are reduced to palladium nuclei on the borehole wall surface, forming a thin and uniform catalytic activation layer. The concentration, temperature, and immersion time of the activation solution affect the quality and uniformity of the activation layer.

[0036] After the activation layer is formed, a thin and uniform copper layer is deposited on the surface of the activation layer through electroless copper plating (also known as electroless copper plating). This thin copper layer is conductive, providing a basis for subsequent electroplating. The principle of electroless copper plating is to utilize the copper ions in the plating solution to undergo a redox reaction with a reducing agent under the catalysis of the activation layer, thereby depositing copper metal on the hole walls. The activated first or second multilayer board is immersed in a copper plating solution containing copper salts (such as copper sulfate), reducing agents (such as formaldehyde), complexing agents, stabilizers, and pH adjusters. Under the catalysis of the activation layer, copper ions are reduced to copper atoms and deposited on the hole walls, forming a thin copper layer with a thickness typically between 0.5 micrometers and several micrometers.

[0037] While electroless copper plating creates a thin copper layer that is conductive, its thickness is insufficient to meet the electrical performance and mechanical strength requirements of a PCB. Pattern plating (also known as electrolytic copper plating) thickens the copper layer using electrochemical methods to achieve the desired thickness. Pattern plating allows for selective copper plating in specific areas (such as inside drilled holes), forming a first or second copper plating layer. After electroless copper plating forms a thin copper layer, pattern transfer (such as photolithography) is typically performed to define the areas where the copper layer needs to be thickened. Then, the first or second multilayer board is used as the cathode and immersed in an electroplating solution containing copper sulfate, sulfuric acid, chloride ions, and various additives (such as brighteners and leveling agents). By applying an external DC power supply, copper ions move towards the cathode under the influence of the electric field and are reduced and deposited on the thin copper layer, thus gradually thickening the copper layer. Electroplating current density, time, solution composition, and temperature are key parameters affecting the plating quality and thickness.

[0038] Through the above technical solution, firstly, the activation treatment ensures that the non-conductive hole walls can uniformly adsorb the catalyst, laying a good foundation for subsequent metal deposition. Secondly, electroless copper plating forms a uniform and well-adhered conductive thin copper layer on the activation layer, effectively solving the problem of non-conductivity of the hole wall material. Based on this, patterned electroplating can precisely control the thickness of the copper layer to meet design requirements and significantly enhance the bonding strength and conductivity between the copper layer and the hole walls. This step-by-step and refined copper plating process effectively avoids defects such as poor copper layer adhesion, uneven thickness, and voids that may occur with traditional single copper plating methods. This ensures that the conductive paths inside the first and second drilled holes have excellent signal transmission integrity, lower resistance, and higher reliability, making it particularly suitable for high-frequency, high-speed PCB designs with stringent signal quality requirements.

[0039] In some embodiments, during the second drilling process, a third hole is also formed on the second multilayer board, and the third hole is located outside the first hole; during the second copper plating process, a third copper plating layer is formed on the hole wall of the third hole, and the third hole is filled by a second resin plugging process; the third copper plating layer of the third hole enables communication connection between the core boards of the second multilayer board.

[0040] The above technical solution introduces a third drilled hole located outside the first drilled hole in the second multilayer board. This third hole is then copper-plated and resin-filled, forming an independent conductive channel with a third copper plating layer. This enables communication connections between the core boards of the second multilayer board. This design solves the problem that relying solely on main signal vias cannot meet the needs of complex communication connections. Specifically, the third drilled hole can be flexibly used as an additional grounding via, power via, or auxiliary signal via. When used as a grounding via, it forms an effective grounding shielding ring around the main signal vias (the first and second drilled holes), significantly reducing electromagnetic interference and crosstalk, thereby further improving the signal integrity of the main signal vias. Simultaneously, when used as a power via or auxiliary signal via, it greatly increases the routing flexibility and functional expandability within the PCB. The resin-filled via treatment ensures the mechanical stability and long-term reliability of these additional connections. Overall, the solution provides superior electrical performance and greater design flexibility for high-density, high-frequency, and high-speed PCB designs without affecting the performance of the main signal vias, effectively suppressing noise and ensuring the stability and reliability of signal transmission.

[0041] In some implementations, a first multilayer board is fabricated, see [link to relevant documentation]. Figure 2 Specifically, it includes: S11, The raw material board is cut into core board by a slitting device; S12, Perform inner layer circuit processing on the core board to create inner layer circuits, and perform inner layer AOI inspection on the inner layer circuits; S13, multiple core boards are pressed together using a pressing device to form the first multilayer board.

[0042] In steps S11-S13, through the above technical solution, every step in the fabrication of the first multilayer board, from the raw material board cutting, the fabrication of the inner layer circuitry of the core board, the rigorous testing of the inner layer circuitry, to the final precise lamination of multiple core boards, is meticulously controlled. This refined manufacturing process ensures that the first multilayer board has high-precision, high-reliability inner layer circuitry and a stable interlayer structure. This provides a solid foundation for subsequent key steps such as the first drilling process to create the first drilled hole, the first copper plating process to create the first copper plating layer on the hole wall of the first drilled hole, and the first resin plugging process to fill the hole, effectively avoiding the decline in via signal integrity caused by substrate quality issues. For example, precise inner layer circuitry and a stable lamination structure help ensure accurate hole positioning during drilling, uniform hole wall during copper plating, and sufficient filling during plugging, thereby guaranteeing the overall performance and reliability of the final PCB board from the source and significantly improving the signal integrity of the vias.

[0043] In some embodiments, after the first drilling process is performed on the first multilayer board to create the first hole, and before the first copper plating process is performed on the hole wall to create the first copper plating layer, the method further includes: performing a plasma desmearing treatment on the first multilayer board using a plasma device. Through the above technical solution, introducing a plasma desmearing treatment after the first drilling process on the first multilayer board and before the first copper plating process can thoroughly remove adhesive residue, resin coating, and drilling debris generated during drilling from the hole wall. This not only provides a clean and activated hole wall surface for the subsequent first copper plating process, but also greatly enhances the bonding strength and uniformity between the first copper plating layer and the hole wall, effectively avoiding defects such as plating voids and delamination, thereby ensuring the conductivity and mechanical reliability of the first hole. Ultimately, by optimizing the copper plating quality of the first hole, the signal integrity of the vias on the entire PCB board is significantly improved, especially in high-frequency and high-speed applications, effectively suppressing signal attenuation and reflection, and ensuring the stability and reliability of signal transmission.

[0044] In some implementations, the second multilayer board undergoes post-processing to fabricate the target PCB board, see [link to relevant documentation]. Figure 3 Specifically, it includes: S51, capping electroplating is performed on the second multilayer board to form a third copper plating layer at the second drilled position of the second multilayer board. S52, perform outer layer circuit processing on the second multilayer board to create outer layer circuits, and perform outer layer AOI inspection on the outer layer circuits; S53, Solder resist treatment is applied to the second multilayer board to create a solder resist layer on the outer surface of the second multilayer board. S54, perform text processing on the second multilayer board to form a text layer in the solder resist layer of the second multilayer board; S55, the second multilayer board is shaped to produce the target PCB board.

[0045] In steps S51-S55, after completing the second drilling, second copper plating, and second resin plugging of the second multilayer board, a capping electroplating process is required to ensure effective protection of the hole openings and provide flat pads for subsequent surface mount technology. This process aims to form a third copper plating layer at the second drilled location on the second multilayer board. Capping electroplating typically involves applying a layer of photoresist or dry film to the hole opening area, followed by electroplating, allowing a copper layer to grow above the hole opening and cover the plugging resin, forming a flat copper cap. This effectively prevents internal copper layer oxidation or environmental corrosion, while also improving soldering reliability.

[0046] Building upon this foundation, to achieve electrical connections and signal transmission between components, the second multilayer board requires outer layer circuitry processing to create the outer layer wiring. Outer layer circuitry processing is a crucial step in creating conductive patterns on the PCB surface, typically involving steps such as film application, exposure, development, and etching. Through photosensitive materials and chemical etching processes, precise conductive patterns are formed on the board surface. Simultaneously, to ensure the quality and reliability of the outer layer wiring, external AOI inspection is necessary. External AOI inspection utilizes a high-resolution camera and image processing algorithms to scan the completed outer layer wiring, compare it with design data, and automatically identify and mark any defects that do not conform to design specifications, such as short circuits, open circuits, uneven line widths, or residual copper, thereby ensuring the electrical performance of the wiring.

[0047] Subsequently, to protect the outer layer circuitry from environmental influences and prevent solder smearing during the soldering process, the second multilayer board needs to undergo a solder resist treatment to create a solder resist layer on its outer surface. The solder resist layer typically uses liquid photosensitive solder resist ink or dry film solder resist ink. Through steps such as coating, exposure, development, and curing, an insulating protective layer is formed in the non-pad areas, precisely defining the soldering area, preventing solder bridging, and improving the PCB's electrical insulation performance and environmental tolerance.

[0048] To facilitate component installation, PCB identification, and maintenance, text processing is required on the second multilayer board to create a text layer on the solder mask. Text processing typically employs screen printing or inkjet printing techniques to print component reference numbers, polarity indicators, company logos, version information, and other characters and symbols onto the solder mask, providing clear guidance for subsequent assembly, testing, and repair.

[0049] Finally, in order to process the large-sized second multilayer board into the final product form, it needs to undergo a shaping process to create the target PCB board. The shaping process can be carried out using CNC milling, laser cutting, or die stamping, etc., to accurately cut out the outline and internal slots of the PCB according to the design requirements, so that it can be smoothly integrated into the final product.

[0050] Through the aforementioned series of meticulous post-processing steps, the second-layer multilayer board, after completing the core nested via structure fabrication, is transformed into a fully functional, highly reliable target PCB board that meets the requirements of practical applications. Capping plating effectively protects the openings of the second drilled holes, preventing oxidation and corrosion, and providing a smooth surface for subsequent component soldering, thereby improving soldering quality and signal transmission stability. Outer layer circuit processing and outer layer AOI inspection ensure the accuracy of the conductive patterns on the PCB surface and the reliability of electrical connections, avoiding defects such as open circuits and short circuits. Solder masking protects the circuitry while precisely defining the soldering area, preventing solder bridging, and significantly improving the PCB's electrical insulation performance and environmental tolerance. Text processing provides clear identification information for the PCB, facilitating assembly, testing, and maintenance. The final molding process gives the PCB board precise physical dimensions and shape, allowing for smooth integration into the final product. These steps work together to ensure that the PCB board manufactured using nested via technology not only possesses excellent signal integrity but also the comprehensive functionality and reliability required for practical applications.

[0051] Example 3: Based on Embodiment 1 or Embodiment 2, the present invention provides an embodiment of a PCB fabrication apparatus for improving via signal integrity. This apparatus is used to execute the PCB fabrication method for improving via signal integrity according to Embodiment 1 or Embodiment 2.

[0052] The device achieves a nested double-drilled structure, combining the first and second drilled holes in an internally nested manner, and employs a step-by-step resin filling process to effectively eliminate via impedance discontinuities and reduce parasitic capacitance and inductance effects. Specifically, the device ensures that the second drilled hole is precisely located inside the first drilled hole, forming a continuous current path, avoiding return current detours, and significantly suppressing ground bounce noise and electromagnetic radiation. Due to the step-by-step drilling and plugging process, the device performs multiple plugging processes on the first drilled hole from the first and second surfaces of the first multilayer board during the first resin plugging process, and implements baking and resin grinding processes to ensure hole wall flatness. In the second drilling process, the device further controls the positioning accuracy of the second drilled hole, ensuring that it is strictly located in the center area of ​​the resin-filled first drilled hole, thereby optimizing the geometry of the via to match the characteristic impedance of the transmission line.

[0053] Through the above technical solutions, the PCB manufacturing equipment can produce circuit boards with improved via structures, effectively reducing signal reflection accumulation effects, shortening signal rise time, and improving high-frequency bandwidth performance. Simultaneously, by ensuring the second drilled hole is located inside the first drilled hole through process control, the equipment maintains a continuous return current path, reduces the current loop area, and thus significantly suppresses differential-mode radiation and common-mode noise conversion, ultimately meeting the signal integrity requirements of 56Gbps and above high-speed serial links.

[0054] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of the invention may be practiced without these specific details. Similarly, for the sake of brevity and to aid in understanding one or more aspects of the invention, in the description of exemplary embodiments of the invention above, various features of the embodiments are sometimes grouped together in a single embodiment, figure, or description thereof. The claims, which follow the detailed description, are hereby expressly incorporated into the detailed description, wherein each claim itself is a separate embodiment of the invention.

[0055] Those skilled in the art will understand that the modules in the devices of the embodiments can be adaptively changed and placed in one or more devices different from those in the embodiments. Modules, units, or components in the embodiments can be combined into a single module, unit, or component, and further, they can be divided into multiple sub-modules, sub-units, or sub-components, except that at least some of such features and / or processes or units are mutually exclusive.

[0056] It should be noted that the above embodiments are illustrative of the invention and not restrictive, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims enumerating several systems, several of these systems may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names. The steps in the above embodiments, unless otherwise specified, should not be construed as limiting the order of execution.

Claims

1. A PCB fabrication method for improving via signal integrity, characterized in that, The method includes: Fabricate the first multilayer board; The first multilayer board is drilled to create a first hole, the hole wall of the first hole is copper plated to create a first copper plating layer, and the first hole is filled with resin plugging. A first outer layer is pressed onto the first surface and / or the second surface of the first multilayer board to form a second multilayer board; The second multilayer board is subjected to a second drilling process to create a second hole, and the second hole is located inside the first hole. A second copper plating layer is created on the hole wall of the first hole through a second copper plating process, and the second hole is filled with a second resin plugging process. The second multilayer board is then processed in subsequent steps to produce the target PCB board.

2. The PCB fabrication method for improving via signal integrity according to claim 1, characterized in that, Both the first and second drilling processes are performed using mechanical drilling. The first hole is a through hole that penetrates the first multilayer board, and the second hole is a through hole that penetrates the second multilayer board.

3. The PCB fabrication method for improving via signal integrity according to claim 2, characterized in that, The first copper plating layer on the wall of the first drilled hole is connected to the power ground to form a grounded GND layer.

4. The PCB fabrication method for improving via signal integrity according to claim 1, characterized in that, In the first resin plugging process, the first drilled hole is plugged at least once from the first surface of the first multilayer board, the first drilled hole is plugged at least once from the second surface of the first multilayer board, and the first multilayer board is baked and resin polished to fill the first drilled hole. In the second resin plugging process, the second drilled hole is plugged at least once from the first surface of the second multilayer board, the second drilled hole is plugged at least once from the second surface of the first multilayer board, and the second multilayer board is baked and resin polished to fill the second drilled hole.

5. The PCB fabrication method for improving via signal integrity according to claim 1, characterized in that, Both the first and second copper plating processes include: The first multilayer board or the second multilayer board is immersed in an activation solution for activation treatment to form an activation layer on the hole wall of the first drilled hole or the second drilled hole. The first multilayer board or the second multilayer board is immersed in a copper plating solution to allow the activation layer to undergo a displacement reaction with the copper ions in the copper plating solution, so as to form a thin copper layer in the first drilled hole or the second drilled hole. The first and second drilled holes are subjected to pattern electroplating to thicken the thin copper layer, thereby forming a first copper plating layer or a second copper plating layer.

6. The PCB fabrication method for improving via signal integrity according to claim 1, characterized in that, In the second drilling process, a third hole is also made in the second multilayer board, and the third hole is located outside the first hole; in the second copper plating process, a third copper plating layer is formed on the hole wall of the third hole, and the third hole is filled by a second resin plugging process; the third copper plating layer of the third hole enables communication connection between the core boards of the second multilayer board.

7. The PCB fabrication method for improving via signal integrity according to claim 1, characterized in that, The fabrication of the first multilayer board specifically includes: The raw material board is cut into core boards using a slitting device; The core board is processed to create inner layer circuitry, and the inner layer circuitry is then subjected to inner layer AOI inspection. Multiple core boards are pressed together using a pressing device to form a first multilayer board.

8. The PCB fabrication method for improving via signal integrity according to claim 1, characterized in that, After the first drilling process is performed on the first multilayer board to create the first hole, and before the first copper plating process is performed on the hole wall of the first hole to create the first copper plating layer, the process further includes: The first multilayer board is subjected to plasma adhesive removal treatment using a plasma device.

9. The PCB fabrication method for improving via signal integrity according to claim 1, characterized in that, The second multilayer board undergoes post-processing to fabricate the target PCB board, specifically including: The second multilayer board is subjected to cap electroplating to form a third copper plating layer at the second drilled location of the second multilayer board. The second multilayer board is processed to create outer layer circuitry, and the outer layer circuitry is then subjected to outer layer AOI inspection. The second multilayer board is subjected to solder resist treatment to create a solder resist layer on the outer surface of the second multilayer board; Text processing is performed on the second multilayer board to form a text layer in the solder resist layer of the second multilayer board; The second multilayer board is subjected to molding process to produce the target PCB board.

10. A PCB fabrication apparatus for improving via signal integrity, characterized in that, The apparatus is used to perform the PCB fabrication method for improving via signal integrity as described in any one of claims 1-9.

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