Method for manufacturing a circuit board and circuit board

Abstract

The application discloses a circuit board preparation method and a circuit board. The preparation method comprises the following steps: obtaining a to-be-processed plate; wherein the to-be-processed plate comprises a first surface and a second surface arranged oppositely, the first surface comprises at least one first pad, and the second surface comprises a conductive network; forming at least one conductive connecting hole at a preset position of the second surface corresponding to each first pad; forming a corresponding conductive lead between each conductive connecting hole and the conductive network; and electrifying the conductive network on the second surface to electroplate gold on each first pad based on the conductive network, the conductive lead and the conductive connecting hole. The application can realize the electroplating of the first pad through the reverse electroplating mode, thereby solving the problem that the electroplating of hard gold needs to be realized by arranging the conductive lead on the surface where the pad is located in the electroplating hard gold process.

Description

Technical Field

[0001] This application relates to the field of circuit board processing technology, and in particular to methods for preparing circuit boards and circuit boards themselves. Background Technology

[0002] A printed circuit board (PCB) is a carrier that holds electronic components and provides electrical connections for them.

[0003] In related technologies, to improve signal transmission quality and speed, a gold plating process is typically used to plate a gold layer onto the pads of a PCB board. This ensures good connection reliability and electrical transmission performance between the PCB board and components. Specifically, the PCB surface treatment requires setting gold-plated leads on the surface where the pads are located to electroplate them.

[0004] However, since the PCB surface needs to be coated with an OSP layer (Organic solderability preservative) at the factory, and some pads are located in the middle of the PCB board rather than the edge area, when using the OSP process on the same side, the gold-plated leads cannot be pulled into the board, thus making it impossible to plate the pads with gold effectively. Summary of the Invention

[0005] The main technical problem addressed by this application is to provide a method for manufacturing a circuit board and the circuit board itself, which solves the problem in related technologies that requires conductive leads to be set on the surface of the pads in order to achieve electroplating.

[0006] To solve the above-mentioned technical problems, the first technical solution adopted in this application is to provide a method for manufacturing a circuit board, comprising: obtaining a board material to be processed; wherein the board material to be processed includes a first surface and a second surface disposed opposite to each other, the first surface including at least one first pad; the second surface including a conductive network; forming at least one conductive connection hole at a preset position corresponding to each first pad on the second surface; forming a corresponding conductive lead between each conductive connection hole and the conductive network; and energizing the conductive network on the second surface to electroplate gold onto each first pad based on the conductive network, the conductive lead, and the conductive connection hole.

[0007] The step of electroplating gold on each first pad based on the conductive network, conductive leads, and conductive connecting holes by energizing the conductive network on the second surface includes: energizing the conductive network on the second surface based on preset electroplating parameters to electroplat gold on each first pad based on the conductive network, conductive leads, and conductive connecting holes; and controlling the thickness of the gold plating layer formed on each first pad to be 15 to 30 microinches.

[0008] Before the step of energizing the conductive network on the second surface to electroplate gold onto each first pad based on the conductive network, conductive leads, and conductive connection holes, the process includes: attaching a dry film to the first and second surfaces; exposing and developing the substrate with the attached dry film to remove the dry film corresponding to each first pad; after the step of energizing the conductive network on the second surface to electroplate gold onto each first pad based on the conductive network, conductive leads, and conductive connection holes, the process includes: removing the remaining dry film.

[0009] The step of forming at least one conductive connection hole at a preset position corresponding to each first pad on the second surface includes: drilling at the preset position corresponding to each first pad on the second surface to form at least one connection hole; wherein the bottom of the connection hole is the first pad; and performing a hole-forming process on the connection hole to form a conductive connection layer on the hole wall of the connection hole.

[0010] The step of drilling at a preset position corresponding to each first pad on the second surface to form at least one connection hole includes: drilling at each preset position by mechanical drilling, and controlling the diameter of each connection hole to be 0.2 to 0.25 mm.

[0011] The step of obtaining the substrate to be processed includes: obtaining a copper-clad laminate, the copper-clad laminate including a first copper layer and a second copper layer disposed opposite to each other; wherein the first copper layer is disposed on a first surface and the second copper layer is disposed on a second surface; attaching dry films to the surfaces of the first copper layer and the second copper layer respectively; sequentially exposing and developing the copper-clad laminate with the attached dry films to form at least one first pad on the first copper layer and a conductive network on the second copper layer; and removing the remaining dry film to obtain the substrate to be processed.

[0012] The process includes, after energizing the conductive network on the second surface to electroplate gold onto each first pad based on the conductive network, conductive leads, and conductive connection holes, removing the conductive leads to obtain a circuit board.

[0013] The first pad includes an independent pad.

[0014] To solve the above-mentioned technical problems, the second technical solution adopted in this application is to provide a circuit board, which includes a first surface and a second surface disposed opposite to each other. The first surface includes at least one first pad, and the second surface includes a conductive network. At least one conductive connection hole is formed on the second surface at a preset position corresponding to each first pad. A gold plating layer is formed on each first pad.

[0015] The thickness of the gold plating layer is 15 to 30 microinches.

[0016] The beneficial effects of this application are as follows: Unlike existing technologies, this application provides a method for fabricating a circuit board and the circuit board itself. By providing conductive connection holes communicating with first pads on a second surface, and conductive leads connecting the conductive connection holes and the conductive network, gold plating can be performed on each first pad located on the first surface based on the conductive network, conductive leads, and conductive connection holes when the conductive network on the second surface is energized. This achieves the plating of the first pads through reverse plating, thus solving the problem that conductive leads need to be provided on the surface where the pads are located in the hard gold plating process. Furthermore, since the gold plating leads (i.e., conductive leads) required for the hard gold plating process are located on the second surface, the fabrication of the OSP layer on the first surface will not affect the plating of the first pads. This allows the hard gold plating process and the OSP process to be fabricated on the same surface, thereby reducing the fabrication difficulty and cost of the circuit board. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the example description will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic flowchart of the first embodiment of the method for manufacturing the circuit board of this application;

[0019] Figure 2 This is a schematic flowchart of the first embodiment of the method for manufacturing the circuit board of this application;

[0020] Figure 3 This is a flowchart illustrating the third embodiment of the circuit board fabrication method of this application;

[0021] Figure 4 This is a schematic diagram of the structure of the plate material to be processed obtained in S309 according to one embodiment;

[0022] Figure 5 This is a schematic diagram of one embodiment of the circuit board of this application. Detailed Implementation

[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0024] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to limit the application. The singular forms “a,” “said,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms, unless otherwise clearly indicated above. “Multiple” generally includes at least two, but does not exclude the inclusion of at least one.

[0025] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0026] It should be understood that the terms "comprising," "including," or any other variations used herein are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0027] In related technologies, to improve signal transmission quality and speed, a gold plating process is typically used to plate a gold layer onto the pads of the PCB board. This ensures good connection reliability and electrical transmission performance between the PCB board and components. Specifically, the PCB surface treatment requires setting gold-plated leads on the surface where the pads are located to electroplate the pads.

[0028] However, since the PCB surface needs to be coated with an OSP layer (Organic solderability preservative) at the factory, and some pads are located in the middle of the PCB board rather than the edge area, when using the OSP process on the same side, the gold-plated leads cannot be pulled into the board, thus making it impossible to plate the pads with gold effectively.

[0029] Based on the above, this application provides a method for manufacturing a circuit board and a circuit board that can solve the problem that related technologies cannot effectively plate gold on solder pads.

[0030] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0031] Please see Figure 1 , Figure 1This is a schematic flowchart of the first embodiment of the circuit board fabrication method of this application. In this embodiment, the fabrication method includes:

[0032] S11: Obtain the board material to be processed; wherein the board material to be processed includes a first surface and a second surface disposed opposite to each other, the first surface includes at least one first pad; the second surface includes a conductive network.

[0033] In this embodiment, the substrate to be processed includes a single-layer core board or a multi-layer core board obtained through lamination. Lamination refers to a method of bonding two or more layers of the same or different materials into a whole by heating and pressurizing, with or without adhesive. The core board is a copper-clad laminate, which includes a dielectric layer and a copper layer. The dielectric layer can cover the copper layer on one side or both sides.

[0034] In this embodiment, the first pad can be connected to external components via board-to-board connection or lamination connection.

[0035] In this embodiment, the first pad includes an independent pad. An independent pad is a pad that is not connected to the circuit pattern on the first surface.

[0036] In some implementations, the first pad refers to a separate pad designed for a connector or module interface. This separate pad is electrically and physically isolated from other circuitry to meet specific signal integrity, impedance matching, or mechanical fixation requirements.

[0037] Independent pads can be matched with a variety of connectors in PCB design, and the specific choice depends on electrical requirements, mechanical fixing method and signal type.

[0038] In some implementations, the connector type includes a press-fit connector, which forms a solderless connection with an independent pad through pressure, avoiding the effects of high temperatures and suitable for high-frequency or high-reliability applications. In some specific implementations, the first pad refers to an independent pad designed at the CAMM2 (Compression Attached Memory Module 2) connector location. CAMM2 is characterized by achieving high-density, high-speed signal transmission through a compression connection (non-slotted), requiring direct pressing between the PCB pads and module contacts.

[0039] In other embodiments, the connector type may also include spring pin connectors, flexible circuit connectors, magnetic adsorption connectors, high-frequency coaxial connectors, etc., which are not limited in this application.

[0040] Specifically, in this embodiment, the independent pads are not directly connected to surrounding traces to avoid signal crosstalk (especially high-frequency signals). Furthermore, the independent pads are independently designed to facilitate precise impedance calculation and adjustment; for example, the high-speed DDR signals corresponding to the DDR (Double Data Rate) chips on the CAMM2 require differential impedance matching. Simultaneously, as press-fit contact points, the independent pads possess flatness and wear resistance.

[0041] In this embodiment, the shape and size of the first pad are set based on the module contacts to be connected, and the number of the first pads is also consistent with the number of module contacts to ensure matching with the module contacts.

[0042] In other embodiments, the first pad may also be a regular network pad that requires lead wires to be plated, and this application does not limit this to that.

[0043] In this embodiment, the conductive network on the second surface includes a circuit pattern and a clamping process border connecting the circuit pattern.

[0044] In the gold plating process of circuit boards, the clamping process frame is an additional extension structure designed on the edge of the PCB board. It is mainly used for fixing, transporting, and processing during the production process, and provides a current path for electroplating. For example, it can evenly distribute the current when plating the entire board to ensure uniform plating. After electroplating is completed, the frame can be removed by cutting to retain clean functional circuitry.

[0045] In some embodiments, the first surface also includes a conductive network, and the second surface may also be provided with independent pads or other ordinary network pads that require lead wires for electroplating, so as to supply power to the second surface through the first surface, thereby plating the pads located on the second surface with gold. This application does not limit this.

[0046] S12: At least one conductive connection hole is formed on the second surface at a preset position corresponding to each first pad.

[0047] In this embodiment, the bottom of each conductive connection hole corresponds to a first pad.

[0048] S13: A corresponding conductive lead is formed between each conductive connection hole and the conductive network.

[0049] In this embodiment, a conductive lead is provided between each conductive connection hole and the nearest circuit pattern to connect the conductive connection hole to the conductive network of the second surface.

[0050] Understandably, placing a conductive lead between each conductive connection hole and the nearest circuit pattern can not only reduce the difficulty of fabricating the conductive lead, but also reduce the probability of signal crosstalk.

[0051] S14: Apply current to the conductive network on the second surface to electroplate gold onto each first pad based on the conductive network, conductive leads, and conductive connection holes.

[0052] In this embodiment, a process frame for clamping is energized on the second surface to provide a current path for electroplating gold to each first pad located on the first surface based on the circuit pattern, conductive leads, and conductive connection holes, thereby plating a gold layer on each first pad.

[0053] Specifically, gold electroplating utilizes the principle of electrolysis to reduce gold ions from the electroplating solution and deposit them on the surface of a substrate. In this process, the substrate acts as the cathode, and gold acts as the anode. By applying an external current, the gold ions are reduced to metallic gold on the substrate surface, forming a plating layer.

[0054] In this embodiment, the thickness of the gold plating layer on the first pad can be adjusted based on the magnitude of the electroplating current and the time.

[0055] In this embodiment, after electroplating is completed, the conductive leads are removed to obtain a circuit board.

[0056] In some implementations, a dry film is attached to both sides of the board to be treated after electroplating, and the board is subjected to at least exposure, development, etching, and film removal steps in sequence to completely cover the first pad on the first surface, the circuit pattern on the second surface, and the process border, leaving only the conductive leads exposed. The conductive leads are then etched away to obtain the circuit board.

[0057] Unlike related technologies, this embodiment, by providing conductive connection holes communicating with the first pads on the second surface and conductive leads connecting the conductive connection holes and the conductive network, enables gold plating on each first pad located on the first surface based on the conductive network, conductive leads, and conductive connection holes when the conductive network on the second surface is energized. This achieves the plating of the first pads through reverse plating, thus solving the problem of requiring conductive leads on the surface of the pads in the hard gold plating process. Furthermore, since the gold plating leads (i.e., conductive leads) required for the hard gold plating process are located on the second surface, the preparation of the OSP layer on the first surface does not affect the plating of the first pads. This allows the hard gold plating process and the OSP process to be fabricated on the same surface, thereby reducing the difficulty and cost of circuit board fabrication.

[0058] Please see Figure 2 , Figure 2 This is a schematic flowchart of the first embodiment of the circuit board fabrication method of this application. In this embodiment, the fabrication method includes:

[0059] S21: Obtain the board material to be processed; wherein the board material to be processed includes a first surface and a second surface disposed opposite to each other, the first surface includes at least one first pad; the second surface includes a conductive network.

[0060] Please refer to the description in S11 for the specific process, which will not be repeated here.

[0061] S22: At least one conductive connection hole is formed on the second surface at a preset position corresponding to each first pad.

[0062] Please refer to the description in S12 for the specific process, which will not be repeated here.

[0063] S23: A corresponding conductive lead is formed between each conductive connection hole and the conductive network.

[0064] Please refer to the description in S13 for the specific process, which will not be repeated here.

[0065] S24: Based on preset electroplating parameters, current is applied to the conductive network on the second surface to electroplat gold onto each first pad based on the conductive network, conductive leads, and conductive connection holes.

[0066] In this embodiment, the preset electroplating parameters include current density, gold bath solution concentration, and electroplating time.

[0067] The greater the current density, the higher the concentration of the gold plating solution, and the longer the electroplating time, the thicker the gold plating layer formed on the first pad.

[0068] S25: Control the thickness of the gold plating layer formed on each first pad to be 15 to 30 microinches.

[0069] In related technologies, because the independent pads in the CAMM2 connector are located at non-edge positions on the PCB, gold layers can typically only be deposited on these independent pads using chemical gold plating. The core of chemical gold plating is a redox reaction, where gold ions (Au) react with each other in the chemical plating solution. 3+ The gold is reduced to elemental gold (Au) by a reducing agent and deposited on the substrate surface. This process does not require an external power source and is a spontaneous reduction reaction. However, the coating formed by chemical gold plating is a thin gold layer, with a maximum thickness of 3 to 5 microinches. It cannot pass salt spray and MFG (Mixed Flowing Gas) tests and cannot ensure a stable connection with CAMM2.

[0070] Unlike related technologies, this embodiment forms a gold plating layer on the first pad by electroplating gold. By controlling the electroplating parameters, the thickness of the gold plating layer formed on each first pad can be no less than 15 microinches. This not only allows the gold plating layer to pass salt spray and MFG tests, but also reduces the probability of oxidation of the gold plating layer, thereby improving the reliability of the connection between the first pad and the external module, and thus improving the product yield of the PCB.

[0071] Please see Figure 3 , Figure 3 This is a schematic flowchart of a third embodiment of the circuit board fabrication method of this application. In this embodiment, the fabrication method includes:

[0072] S301: Obtain a copper-clad laminate, which includes a first copper layer and a second copper layer disposed opposite to each other; wherein the first copper layer is disposed on a first surface and the second copper layer is disposed on a second surface.

[0073] S302: Dry films are attached to the surfaces of the first copper layer and the second copper layer, respectively.

[0074] S303: The copper-clad laminate with dry film attached is exposed and developed sequentially to form at least one first pad on the first copper layer and a conductive network on the second copper layer.

[0075] In some implementations, a circuit pattern that is not connected to the first pad can also be formed on the first copper layer.

[0076] S304: Remove the remaining dry film to obtain the board to be treated.

[0077] S305: Drilling is performed on the second surface at a preset position corresponding to each first pad to form at least one connection hole; wherein the bottom of the connection hole is the first pad.

[0078] In this embodiment, holes are drilled at each preset position by mechanical drilling, and the diameter of each connecting hole is controlled to be 0.2 to 0.25 mm.

[0079] In other embodiments, holes can be drilled at each preset position by laser drilling, and the diameter of each connecting hole can be controlled to be 0.15 to 0.2 mm.

[0080] S306: The connection hole is perforated to form a conductive connection layer on the hole wall.

[0081] In this embodiment, after mechanical drilling or laser drilling is performed on the plate to be treated, and at least one connecting hole is drilled at a preset position on the plate to be treated, there may be residual drilling debris such as resin residue and copper residue in the hole of the plate to be treated. Therefore, it is necessary to perform drilling debris removal treatment on the connecting hole to clean it.

[0082] Furthermore, the connecting holes on the substrate to be processed undergo a hole-forming treatment. This hole-forming treatment includes copper plating, black hole treatment, or shadow plating. By metallizing the holes on the substrate, a conductive material is coated onto the hole walls and / or bottom, facilitating subsequent electroplating. Specifically, black hole treatment involves immersing a fine graphite or carbon black coating (black hole solution) onto the hole walls and / or bottom to form a conductive layer; shadow plating involves immersing a shadow solution containing unique additives and conductive gel-like substances onto the hole walls and / or bottom to form a conductive layer; and copper plating involves chemically depositing a thin layer of electroless copper onto the hole walls and / or bottom as a substrate for electroplating.

[0083] Furthermore, the substrate to be treated is electroplated to form a conductive bonding layer on the wall of the connecting hole.

[0084] S307: A corresponding conductive lead is formed between each conductive connection hole and the conductive network.

[0085] Please refer to the description in S13 for the specific process, which will not be repeated here.

[0086] S308: Dry film is attached to the first surface and the second surface.

[0087] S309: Expose and develop the substrate to be processed with dry film attached to remove the dry film corresponding to each first pad.

[0088] Specifically, please refer to Figure 4 , Figure 4 This is a schematic diagram of the structure of the material to be processed obtained in S309 according to one embodiment.

[0089] In this embodiment, the substrate 100 to be processed includes a first surface 101 and a second surface 102 disposed opposite to each other. The first surface 101 includes a plurality of first pads 20, and the second surface 102 includes a conductive network 30. A plurality of conductive connection holes 40 are formed on the second surface 102 at a preset position corresponding to each first pad 20, and each conductive connection hole 40 is electrically connected to the conductive network through a corresponding conductive lead 50.

[0090] S310: Power is applied to the conductive network on the second surface to electroplate gold onto each first pad based on the conductive network, conductive leads, and conductive connection holes.

[0091] For details, please refer to the descriptions in S14 and S24-S25, which will not be repeated here.

[0092] S311: Remove any remaining dry film.

[0093] S312: Remove the conductive leads to obtain the circuit board.

[0094] Specifically, please refer to Figure 5 , Figure 5 This is a schematic diagram of one embodiment of the circuit board of this application.

[0095] In this embodiment, the circuit board 200 includes a first surface 101 and a second surface 102 disposed opposite to each other. The first surface 101 includes a plurality of first pads 20, and the second surface 102 includes a conductive network 30. A plurality of conductive connection holes 40 are formed on the second surface 102 at preset positions corresponding to each first pad 20, and a gold plating layer 21 is formed on each first pad 20.

[0096] The thickness of the gold plating layer is 15 to 30 microinches.

[0097] Understandably, by making the thickness of the gold plating layer 21 on the first pad 20 15 to 30 microinches, not only can the gold plating layer 21 pass the salt spray and MFG tests, but the probability of the gold plating layer 21 being oxidized can also be reduced, thereby improving the reliability of the connection between the first pad 20 and the external module, and thus improving the product yield of the circuit board 200.

[0098] Unlike related technologies, this application, by providing conductive connection holes communicating with the first pads on the second surface and providing conductive leads connecting the conductive connection holes and the conductive network, enables gold plating of each first pad located on the first surface based on the conductive network, conductive leads, and conductive connection holes when the conductive network on the second surface is energized. This achieves the plating of the first pads through reverse plating, thereby solving the problem that the hard gold plating process requires conductive leads on the surface where the pads are located to achieve plating. Furthermore, since the gold plating leads (i.e., conductive leads) required for the hard gold plating process are located on the second surface, the preparation of the OSP layer on the first surface will not affect the plating of the first pads. This allows the hard gold plating process and the OSP process to be fabricated on the same surface, thereby reducing the difficulty and cost of circuit board fabrication.

[0099] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A method for manufacturing a circuit board, characterized in that, include: A substrate to be processed is obtained; wherein the substrate to be processed includes a first surface and a second surface disposed opposite to each other, the first surface includes at least one first pad; the second surface includes a conductive network; At least one conductive connection hole is formed on the second surface at a predetermined position corresponding to each of the first pads; A corresponding conductive lead is formed between each of the conductive connection holes and the conductive network; A current is applied to the conductive network on the second surface to electroplate gold onto each of the first pads based on the conductive network, the conductive leads, and the conductive connection holes.

2. The preparation method according to claim 1, characterized in that, The step of energizing the conductive network on the second surface to electroplate gold onto each of the first pads based on the conductive network, the conductive leads, and the conductive vias includes: Based on preset electroplating parameters, an electric current is applied to the conductive network on the second surface to electroplat gold onto each of the first pads based on the conductive network, the conductive leads, and the conductive connection holes. The thickness of the gold plating layer formed on each of the first pads is controlled to be 15 to 30 microinches.

3. The preparation method according to claim 2, characterized in that, Prior to the step of energizing the conductive network on the second surface to electroplate gold onto each of the first pads based on the conductive network, the conductive leads, and the conductive vias, the method includes: A dry film is attached to the first surface and the second surface; The substrate to be processed, to which the dry film is attached, is exposed and developed to remove the dry film corresponding to each of the first pads; After the step of energizing the conductive network on the second surface to electroplate gold onto each of the first pads based on the conductive network, the conductive leads, and the conductive connection holes, the method includes: Remove the remaining dry film.

4. The preparation method according to claim 1, characterized in that, The step of forming at least one conductive connection hole at a predetermined position corresponding to each of the first pads on the second surface includes: Drilling is performed on the second surface at the preset position corresponding to each of the first pads to form at least one connection hole; wherein the bottom of the connection hole is the first pad; The connection hole is subjected to a perforation treatment to form a conductive connection layer on the hole wall.

5. The preparation method according to claim 4, characterized in that, The step of drilling holes at the preset positions corresponding to each of the first pads on the second surface to form at least one connection hole includes: Holes are drilled at each of the preset positions using mechanical drilling, and the diameter of each connecting hole is controlled to be 0.2 to 0.25 mm.

6. The preparation method according to claim 1, characterized in that, The step of obtaining the material to be processed includes: A copper-clad laminate is obtained, the copper-clad laminate comprising a first copper layer and a second copper layer disposed opposite to each other; wherein, the first copper layer is disposed on the first surface, and the second copper layer is disposed on the second surface; Dry films are attached to the surfaces of the first copper layer and the second copper layer, respectively. The copper-clad laminate with the dry film attached is exposed and developed sequentially to form at least one first pad on the first copper layer and the conductive network on the second copper layer. Remove the remaining dry film to obtain the substrate to be processed.

7. The preparation method according to claim 1, characterized in that, After the step of energizing the conductive network on the second surface to electroplate gold onto each of the first pads based on the conductive network, the conductive leads, and the conductive connection holes, the method includes: Remove the conductive leads to obtain the circuit board.

8. The preparation method according to claim 1, characterized in that, The first pad includes an independent pad.

9. A circuit board, characterized in that, The circuit board includes a first surface and a second surface disposed opposite to each other. The first surface includes at least one first pad, and the second surface includes a conductive network. At least one conductive connection hole is formed on the second surface at a preset position corresponding to each of the first pads. A gold plating layer is formed on each of the first pads.

10. The circuit board according to claim 9, characterized in that, The thickness of the gold plating layer is 15 to 30 microinches.

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