A method for manufacturing and processing an odd-layer carrier plate and an odd-layer carrier plate

Abstract

The application relates to the technical field of manufacturing and processing of odd-layer carrier plates, in particular to a manufacturing and processing method of odd-layer carrier plates and an odd-layer carrier plate. The application directly adopts a commercial thin double-sided copper-clad plate with a peelable protective copper foil as a starting material, and an inner-layer circuit pattern is directly formed on an original conductive layer (namely a second conductive layer) of the copper-clad plate. The conductive layer is extremely thin with a thickness of 2-5 microns and a smooth surface, and solves the problem that the inner-layer conductor material is too thick to be applied to high-precision circuit processing in the prior art.

Description

Technical Field

[0001] This application relates to the field of fabrication technology for odd-layer substrates, and more particularly to a method for fabricating odd-layer substrates and an odd-layer substrate. Background Technology

[0002] The statements in this section are merely background information related to this application and do not necessarily constitute prior art.

[0003] As electronic products evolve towards thinner, smaller, higher-performance, and higher-density interconnects, IC packaging substrates, as key connectors between chips and motherboards, face increasingly stringent requirements for circuit precision, interlayer alignment, and reliability. To achieve higher-density wiring within limited space, 3D packaging and system-in-package (SIIP) have become mainstream, giving rise to the demand for coreless substrates with odd-numbered layers, such as 3-layer and 5-layer substrates.

[0004] Traditional multilayer circuit board fabrication is mostly based on a double-layer core board, adding layers by successively and symmetrically laminating prepreg (PP) and copper foil to ultimately form an even-layer structure. To obtain an odd-layer carrier board, several existing technologies exist, but all have significant drawbacks: ① Asymmetric pressing method: Odd-layer plates are directly prepared by asymmetric pressing. However, due to the severe asymmetry in material properties and thermal expansion coefficients of the laminated structure, the finished plates suffer from severe warping problems, which cannot meet the requirements of subsequent high-precision assembly and reliability. Therefore, this method lacks practical application value.

[0005] ② Two-layer lamination method: As disclosed in invention patent CN104066281B, this method involves low-temperature lamination of copper foil on both sides of a first prepreg to form a double-sided board, followed by lamination of a second prepreg and copper foil on one side to form a three-layer board, and finally a high-temperature lamination to completely cure the resin. Because this method involves two laminations, in the field of substrate manufacturing, especially when processing high-precision circuits, multiple thermal processes can exacerbate dimensional expansion and contraction, increase interlayer alignment deviations, and potentially introduce additional reliability risks. In contrast, this application avoids the cumulative errors and reliability risks associated with two-layer lamination through a single process.

[0006] ③ Inner layer conductor patterning method: As disclosed in invention patent CN113645773A, this method first uses a conductor material of a certain thickness as the inner layer, and forms a single-layer pattern on it. Then, a prepreg and an outer copper foil are laminated to both sides of the inner layer. Its limitation is that the inner layer conductor material must have sufficient thickness to support the pattern processing and subsequent lamination, which cannot meet the current demand for thinner and finer circuits with line width / spacing <10μm.

[0007] Therefore, how to provide a method for fabricating odd-layer substrates that can avoid warping, reduce process risks, and is suitable for high-precision circuit processing is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0008] Based on this, and in response to the aforementioned technical problems, this application provides a method for manufacturing an odd-layer carrier plate and an odd-layer carrier plate.

[0009] The technical solution adopted in this application to solve the problems existing in the prior art is: This application proposes a method for manufacturing an odd-layer carrier plate, comprising the following steps: S1: A double-sided copper-clad laminate is provided, the double-sided copper-clad laminate includes an insulating dielectric layer, and a first conductive layer and a second conductive layer respectively bonded to opposite sides of the insulating dielectric layer; wherein, a protective copper foil is peelably bonded to the surface of the first conductive layer and the second conductive layer away from the insulating dielectric layer through an adhesive layer. S2: Remove the protective copper foil located outside the second conductive layer to expose the second conductive layer; S3: Perform laser drilling from the first side to the second side of the double-sided copper-clad laminate, wherein the first side is the side where the first conductive layer is located, and the second side is the side where the second conductive layer is located; The desired laser hole pattern is formed on the second conductive layer by laser drilling, and at the same time a continuous fused copper edge is formed around the protective copper foil outside the first conductive layer. The fused copper edge closes the boundary between the protective copper foil outside the first conductive layer and the adhesive layer. S4: A first inner layer circuit pattern is formed on the exposed second conductive layer, the first inner layer circuit pattern serving as the intermediate layer circuit of the odd-numbered layer carrier. S5: At least one layer of prepreg and an outer copper foil are laminated on one side of the second conductive layer on which the first inner layer circuit pattern is formed; S6: Remove the fused copper edge located on the first side formed in step S3; S7: Peel the protective copper foil and the adhesive layer bonded to it from the first conductive layer on the first side to obtain an intermediate substrate with a three-layer conductive structure. The three-layer conductive structure includes a first inner layer circuit pattern in the intermediate layer, and a first conductive layer and an outer copper foil on opposite sides of the middle layer. S8: The desired second outer layer circuit pattern and third outer layer circuit pattern are formed on opposite sides of the intermediate substrate, respectively.

[0010] Preferably, In step S5, the lamination is a single-sided lamination, where the prepreg and the outer copper foil are laminated only on the side of the second conductive layer where the first inner layer circuit pattern is formed.

[0011] Preferably, In step S5, the pressing is a double-sided pressing. While pressing the prepreg and the outer copper foil on the side of the second conductive layer where the first inner layer circuit pattern is formed, a useless prepreg and / or copper foil is pressed on the protective copper foil on the first side to balance the thermal stress during the pressing process.

[0012] Preferably, The thickness of the first conductive layer and the second conductive layer is 2μm to 5μm, and the thickness of the protective copper foil is 18μm to 35μm.

[0013] Preferably, In step S3, the laser drilling uses an ultraviolet laser; the width of the fused copper edge is 0.1mm to 0.3mm.

[0014] Preferably, The protective copper foil and adhesive layer peeled off in step S7, after adhesive layer removal treatment, form a thin copper-clad laminate material for experimental testing.

[0015] Preferably, In step S8, the formation of the second outer layer circuit pattern and the third outer layer circuit pattern includes: laser drilling, desmearing, chemical copper plating, electroplating to fill holes, and circuit pattern formation.

[0016] Preferably, The method further includes: S9: After completing step S8, printing solder resist ink on both sides of the substrate to form a solder resist layer.

[0017] An odd-numbered layer carrier plate is manufactured using the manufacturing and processing method for odd-numbered layer carrier plates as described in any one of claims 1 to 8.

[0018] Compared with the prior art, the beneficial effects of this application are as follows: 1. Wide applicability, meeting the needs of fine circuits: This application directly uses commercially available thin double-sided copper-clad laminate with peelable protective copper foil as the starting material. The inner layer circuit pattern is directly formed on the original conductive layer (i.e. the second conductive layer) of the copper-clad laminate. The conductive layer is extremely thin, with a thickness of 2-5μm and a smooth surface, which solves the problem in the prior art that the inner conductor material is too thick to be applied to high-precision circuit processing.

[0019] 2. Effective Prevention of Chemical Penetration and Interlayer Separation: In the laser drilling step, this application innovatively utilizes a laser to form a continuous fused copper edge on the protective copper foil on the non-processed surface (i.e., the first side). This fused copper edge acts as an effective physical barrier in subsequent wet patterning and lamination processes, preventing chemical solutions or flowing prepreg resin from penetrating between the protective copper foil and the adhesive layer. This technique is not disclosed in existing technologies and brings unexpected technical effects, significantly improving product yield and avoiding interlayer reliability problems caused by adhesive layer separation.

[0020] 3. Flexible control of warpage and improved product flatness: This application provides two options for the lamination process: single-sided or double-sided lamination. This application allows for flexible selection of the lamination scheme based on product requirements and cost considerations. Especially in the double-sided lamination scheme, by laminating a useless material on the other side for symmetrical lamination, thermal stress can be actively balanced, thereby flexibly controlling or even eliminating warpage. This "on-demand selection" flexibility is a significant advancement of this application compared to existing technologies.

[0021] 4. Simplified process and reduced costs: All key steps in this application—inner layer patterning, outer layer lamination, and outer layer patterning—are completed in a single process flow, eliminating the need for secondary lamination or multiple transfers. This avoids dimensional expansion and contraction and alignment accuracy issues caused by multiple high-temperature processes. Furthermore, the unusable material removed can be recycled as a test board, reducing material waste.

[0022] 5. Improve product reliability: Through the protection mechanism of "fused copper edge" and the stress management mechanism of "selective pressing", this application effectively avoids the potential defects caused by chemical penetration, uneven stress and secondary pressing in the prior art, thereby improving the long-term reliability of the final product. Attached Figure Description

[0023] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments of this application and their descriptions are used to explain this application and do not constitute an undue limitation of this application.

[0024] Figure 1 This is a schematic diagram of the overall structure of a double-sided copper-clad laminate; Figure 2 for Figure 1 A schematic diagram showing the removal of the protective copper foil on the bottom surface; Figure 3 A schematic diagram showing the laser hole pattern required to form the L2 layer on the bottom surface for laser drilling, and the fusion layer burned out around the front surface. Figure 4 The bottom surface forms the first inner layer circuit pattern of layer L2; Figure 5For lamination, the bottom surface is laminated to form the copper foil used for L3 layer pattern formation; Figure 6 To cut the edge, the top surface fused layer formed in step 3 is removed; Figure 7 To peel off the ineffective layer on the top surface and form the required 3-layer substrate, at this time the upper and lower L1 / L3 of the substrate are exactly in the state of copper foil; Figure 8 To process the L3 layer laser, the L1 / L3 layer pattern is then formed; Figure 9 The solder resist pattern is formed by printing ink, and the production of the 3-layer board is completed. Detailed Implementation

[0025] The present application will be further described below with reference to the accompanying drawings and embodiments.

[0026] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this disclosure. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms “comprising” and / or “including” are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0027] In this disclosure, terms such as "upper," "lower," "left," "right," "front," "back," "vertical," "horizontal," "side," and "bottom" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are merely relational terms determined for the convenience of describing the structural relationship of the various components or elements in this disclosure, and do not specifically refer to any component or element in this disclosure, nor should they be construed as limiting this disclosure.

[0028] This application provides a method for manufacturing an odd-layer carrier board, comprising the following steps: S1: A double-sided copper-clad laminate is provided, the double-sided copper-clad laminate includes an insulating dielectric layer, and a first conductive layer and a second conductive layer respectively bonded to opposite sides of the insulating dielectric layer; wherein, a protective copper foil is peelably bonded to the surface of the first conductive layer and the second conductive layer away from the insulating dielectric layer through an adhesive layer. S2: Remove the protective copper foil located outside the second conductive layer to expose the second conductive layer; S3: Perform laser drilling from the first side to the second side of the double-sided copper-clad laminate, wherein the first side is the side where the first conductive layer is located, and the second side is the side where the second conductive layer is located; The desired laser hole pattern is formed on the second conductive layer by laser drilling, and at the same time a continuous fused copper edge is formed around the protective copper foil outside the first conductive layer. The fused copper edge closes the boundary between the protective copper foil outside the first conductive layer and the adhesive layer. S4: A first inner layer circuit pattern is formed on the exposed second conductive layer, the first inner layer circuit pattern serving as the intermediate layer circuit of the odd-numbered layer carrier. S5: At least one layer of prepreg and an outer copper foil are laminated on one side of the second conductive layer on which the first inner layer circuit pattern is formed; S6: Remove the fused copper edge located on the first side formed in step S3; S7: Peel the protective copper foil and the adhesive layer bonded to it from the first conductive layer on the first side to obtain an intermediate substrate with a three-layer conductive structure. The three-layer conductive structure includes a first inner layer circuit pattern in the intermediate layer, and a first conductive layer and an outer copper foil on opposite sides of the middle layer. S8: The desired second outer layer circuit pattern and third outer layer circuit pattern are formed on opposite sides of the intermediate substrate, respectively.

[0029] In some embodiments, in step S5, the pressing is a single-sided pressing, where the prepreg and the outer copper foil are pressed only on the side of the second conductive layer on which the first inner layer circuit pattern is formed.

[0030] In some embodiments, in step S5, the pressing is double-sided pressing. While pressing a prepreg and an outer copper foil on one side of the second conductive layer where the first inner layer circuit pattern is formed, a useless prepreg and / or copper foil is pressed on the protective copper foil on the first side to balance the thermal stress during the pressing process.

[0031] In some embodiments, the thickness of both the first conductive layer and the second conductive layer is 2μm to 5μm, and the thickness of the protective copper foil is 18μm to 35μm.

[0032] In step S3, the laser drilling uses an ultraviolet laser; the width of the fused copper edge is 0.1mm to 0.3mm.

[0033] By controlling the laser power and pulse width, the laser energy is reduced to the point that it can only melt the edge material of the protective copper foil when processing the area around the protective copper foil on the first side, forming the fused copper edge with a width of 0.1 mm to 0.3 mm.

[0034] The protective copper foil and adhesive layer peeled off in step S7, after adhesive layer removal treatment, form a thin copper-clad laminate material for experimental testing.

[0035] In some embodiments, step S8, the formation of the second outer layer circuit pattern and the third outer layer circuit pattern includes: laser drilling, desmearing, chemical copper plating, electroplating to fill holes, and circuit pattern formation.

[0036] In some embodiments, the method for manufacturing the odd-numbered layer substrate of this application further includes: S9: after completing step S8, printing solder resist ink on both sides of the substrate to form a solder resist layer.

[0037] This application provides an odd-layer carrier plate, which is manufactured using the above-described method for manufacturing odd-layer carrier plates.

[0038] To make the objectives, technical solutions, and advantages of this application clearer, embodiments and comparative examples are provided below to demonstrate the advantages of this application in warp control, circuit accuracy, yield, etc. It is understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0039] Example 1 Step 1: Material Collection A double-sided copper-clad laminate 100 is provided, with the following structure: Insulating dielectric layer 101: Glass fiber reinforced epoxy resin FR-4 or BT resin, with a thickness ranging from 60 μm to 200 μm, preferably 100 μm in this embodiment. First conductive layer 102 and second conductive layer 103 are both electrolytic copper foil or rolled copper foil, with a thickness ranging from 2 μm to 5 μm, preferably 3 μm in this embodiment. Adhesive layer 104: Thermally peelable or mechanically peelable adhesive material, with a thickness ranging from 5 μm to 15 μm, preferably 8 μm in this embodiment. Protective copper foil 105: Electrolytic copper foil, with a thickness ranging from 18 μm to 35 μm, preferably 25 μm in this embodiment.

[0040] Step 2: Remove the single-sided protective copper foil The protective copper foil 105 located outside the second conductive layer 103 is removed using a mechanical peeling method, exposing the second conductive layer 103. The peeling force is controlled within the range of 0.05 N / mm to 0.15 N / mm to ensure that the second conductive layer 103 is not damaged during the peeling process. The protective copper foil 105 on the first side is retained.

[0041] Step 3: Laser drilling The process is performed using a 355nm wavelength laser drilling machine, with the following parameters: laser power: 3W~8W; pulse frequency: 50kHz~100kHz; pulse width: 10ns~30ns; spot diameter: 20μm~30μm; processing method: forming the required laser hole pattern on the second conductive layer 103, with a hole diameter of 50μm~80μm. Simultaneously, when processing the peripheral area of ​​the first protective copper foil 105, the laser power is reduced to 2W~4W, so that the laser only melts the edge material of the protective copper foil 105, forming a continuous fused copper edge 106 with a width of 0.1mm~0.3mm.

[0042] In low-power mode, the laser energy is only sufficient to melt the surface of the copper foil without penetrating it. The molten copper forms a continuous molten ring under surface tension, which, upon cooling, forms a dense metallic seal. The sealing effect of this structure can be confirmed by microscopic observation, with no visible gaps.

[0043] Step 4: Graphic Formation A dry film with a thickness of 15μm to 25μm is laminated onto the second conductive layer 103. After exposure at an energy of 40mJ / cm² to 80mJ / cm², followed by development and etching (using acidic copper chloride or alkaline etching solution) at a temperature of 45℃ to 55℃, the first inner layer circuit pattern 107 is formed. The line width / spacing ranges from 8μm / 8μm to 15μm / 15μm, with 10μm / 10μm being preferred in this embodiment.

[0044] Step 5: Pressing Option A (single-sided lamination): A prepreg 108 with a thickness of 40μm to 100μm (preferably 60μm in this embodiment) and an outer copper foil 109 with a thickness of 12μm to 18μm (preferably 12μm in this embodiment) are sequentially stacked on the side of the second conductive layer 103. Vacuum pressing conditions: vacuum degree ≤10mmHg, temperature 180℃ to 220℃, pressure 2.5MPa to 3.5MPa, time 60min to 90min.

[0045] Option B (double-sided lamination): While stacking the prepreg 108 and the outer copper foil 109 on the second conductive layer 103 side, a useless prepreg 108' with the same thickness as the prepreg 108 and a useless copper foil 109' with a thickness of 12μm is stacked on the protective copper foil 105 on the first side. The lamination conditions are the same as in scheme A.

[0046] Step 6: Trim the edges Using a mechanical milling machine or an ultraviolet laser cutting machine, cut along the inner side of the fused copper edge 106 with a cutting width of 0.2mm to 0.5mm to expose the boundary between the protective copper foil 105 and the adhesive layer 104.

[0047] Step 7: Remove useless materials The protective copper foil 105 and adhesive layer 104 on the first side are peeled off using a mechanical peeling method. The peeling force is controlled between 0.05 N / mm and 0.15 N / mm. After peeling, the protective copper foil and adhesive layer are immersed in acetone or a special peeling solution at a temperature of 50℃ to 70℃ for 5 min to 15 min to remove the adhesive layer, resulting in a thin copper-clad laminate that can be used for experimental testing.

[0048] Step 8: Subsequent graphic processing Laser drilling: Laser drilling is performed on the first conductive layer 102 and the outer copper foil 109 to form blind vias to the first inner layer circuit pattern 107. The laser parameters are the same as in step 3.

[0049] Removal of adhesive residue: Plasma cleaning or potassium permanganate chemical removal process is used, with a treatment time of 10 to 20 minutes, to ensure the cleanliness of the inner wall of the blind hole.

[0050] Chemical copper plating: depositing a chemical copper layer with a thickness of 0.5μm to 1.5μm on the hole walls and surface.

[0051] Electroplating for hole filling: DC electroplating or pulse electroplating is used, with a copper plating thickness of 10μm to 25μm, to completely fill the blind holes.

[0052] Circuit pattern formation: The first conductive layer 102 is processed into the second outer circuit pattern (L1 layer) by film application, exposure, development and etching, and the outer copper foil 109 is processed into the third outer circuit pattern (L3 layer), with line width / line spacing of 8μm / 8μm to 15μm / 15μm.

[0053] Step 9: Solder resist formation Solder resist ink (thickness 15μm~25μm) is printed on both sides of the substrate, and then exposed (exposure energy 300mJ / cm²~500mJ / cm²), developed (developer concentration 0.8%~1.2% Na2CO3), and heat-cured (150℃~170℃, 30min~60min) to form a solder resist layer.

[0054] Example 2 This embodiment uses the three-layer carrier plate obtained in Embodiment 1 as a basis and adds layers on both sides, as detailed below: Step 10: Double-sided layering On both sides of the three-layer carrier board, a prepreg with a thickness of 40μm to 60μm and an outer copper foil with a thickness of 12μm are stacked on the surfaces of the L1 and L3 layers, respectively.

[0055] Vacuum pressing was used, under the same conditions as step 5, scheme B in Example 1, to form a five-layer structure after pressing.

[0056] Step 11: Repeat subsequent processing Repeat step 8 of Example 1, laser drilling, descaling, chemical copper plating, electroplating for filling holes, circuit pattern formation, and step 9 for solder resist formation to obtain a five-layer carrier board product.

[0057] Step 12: Adding layers multiple times As needed, steps 10 and 11 can be repeated to prepare carrier plates with seven, nine, or more odd-numbered layers. Each additional layer can be laminated on one or both sides to balance warping.

[0058] Comparative Example 1: Using the method described in prior art CN104066281B, a three-layer carrier board was fabricated using a two-stage lamination scheme, with a linewidth / spacing of 10μm / 10μm. Its structure includes: ① a first copper circuit and copper electrode (intermediate layer) embedded between the first and second prepregs; ② second copper circuits (outer layer circuits) on both sides of the substrate; ③ conductive vias penetrating the two prepregs (composed of back-to-back blind vias).

[0059] The specific steps are as follows: ① First lamination: Low-temperature lamination of a 2μm first copper foil and a 12μm second copper foil on both sides of the first semi-cured sheet to form a double-sided panel.

[0060] ②Inner layer pattern: The first copper line and copper electrode (intermediate layer) are formed by photolithography on the second copper foil.

[0061] ③ Second lamination: The second prepreg and the third copper foil are stacked sequentially on the inner layer pattern side, and the resin is cured by high temperature lamination, and the inner layer circuit is embedded between the two prepregs.

[0062] ④ Laser drilling: Laser drilling is performed from both sides to the copper electrode to form back-to-back blind holes.

[0063] ⑤ Remove adhesive residue and outer copper foil: Etch away the first and third copper foils.

[0064] ⑥ Chemical copper plating, electroplating for hole filling, and circuit formation: The outer layer circuit is formed through a semi-additive process.

[0065] Comparative Example 2: The starting material described in this application is used, but the step of forming the fused copper edge in step S3 is omitted. No fused copper edge is formed during laser drilling. The remaining steps are the same as in Example 1.

[0066] Comparative Example 3: Using the traditional asymmetric pressing method, the three-layer structure is directly pressed together without any intermediate pattern formation steps.

[0067] Test methods and results: Results analysis: ① Warpage Comparison: Example 2 (double-sided pressing) showed the lowest warpage at 0.08 mm, indicating that the selective double-sided pressing of this application can effectively balance thermal stress, significantly better than Comparative Example 1 (two-stage pressing) and Comparative Example 3 (asymmetric pressing). The warpage of Example 1 (single-sided pressing) was 0.25 mm, still better than the 0.35 mm of Comparative Example 1, indicating that the single-stage pressing process of this application itself helps to reduce warpage.

[0068] ② Sealing effect of fused copper edge: No chemical leakage was observed in Examples 1 and 2, while Comparative Example 2, which omitted the fused copper edge, showed significant leakage, resulting in a high adhesive layer separation defect rate of 5.2% during subsequent peeling, compared to only 0.3% to 0.5% in Examples 1 and 2. This demonstrates that the sealing effect of the fused copper edge is crucial for protecting the adhesive layer and improving yield.

[0069] ③ Line Accuracy and Yield: The interlayer alignment accuracy of Examples 1 and 2 (±10μm to ±12μm) is better than that of Comparative Example 1 (±18μm). This is because the single-pressing process of this application reduces the cumulative expansion and contraction caused by multiple presses. Examples 1 and 2 can achieve fine lines of 8μm / 8μm, while Comparative Example 1, limited by the expansion and contraction control of the secondary press, can only achieve 12μm / 12μm; Comparative Example 3 has the lowest line accuracy due to severe warpage. This indicates that this application is more suitable for the field of high-precision substrates.

[0070] ④ Overall yield: Example 2 had the highest yield of 96%, Comparative Example 1 had a yield of 88%, Comparative Example 2 had a yield of 82% due to the lack of edge protection of fused copper, and Comparative Example 3 had a yield of only 65%. This fully demonstrates the significant advantages of the technical solution of this application in improving product yield.

[0071] The above are merely preferred embodiments of this application and are not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0072] The contents not described in detail in this specification are existing technologies known to those skilled in the art.

[0073] While the specific embodiments of this application have been described above in conjunction with the accompanying drawings, this is not intended to limit the scope of protection of this application. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art without creative effort based on the technical solutions of this application are still within the scope of protection of this application.

Claims

1. A method for manufacturing an odd-numbered layer carrier plate, characterized in that, Includes the following steps: S1: A double-sided copper-clad laminate is provided, the double-sided copper-clad laminate includes an insulating dielectric layer, and a first conductive layer and a second conductive layer respectively bonded to opposite sides of the insulating dielectric layer; wherein, a protective copper foil is peelably bonded to the surface of the first conductive layer and the second conductive layer away from the insulating dielectric layer through an adhesive layer. S2: Remove the protective copper foil located outside the second conductive layer to expose the second conductive layer; S3: Perform laser drilling from the first side to the second side of the double-sided copper-clad laminate, wherein the first side is the side where the first conductive layer is located, and the second side is the side where the second conductive layer is located; The desired laser hole pattern is formed on the second conductive layer by laser drilling, and at the same time a continuous fused copper edge is formed around the protective copper foil outside the first conductive layer. The fused copper edge closes the boundary between the protective copper foil outside the first conductive layer and the adhesive layer. S4: A first inner layer circuit pattern is formed on the exposed second conductive layer, the first inner layer circuit pattern serving as the intermediate layer circuit of the odd-numbered layer carrier. S5: At least one layer of prepreg and an outer copper foil are laminated on one side of the second conductive layer on which the first inner layer circuit pattern is formed; S6: Remove the fused copper edge located on the first side formed in step S3; S7: Peel the protective copper foil and the adhesive layer bonded to it from the first conductive layer on the first side to obtain an intermediate substrate with a three-layer conductive structure. The three-layer conductive structure includes a first inner layer circuit pattern in the intermediate layer, and a first conductive layer and an outer copper foil on opposite sides of the middle layer. S8: The desired second outer layer circuit pattern and third outer layer circuit pattern are formed on opposite sides of the intermediate substrate, respectively.

2. The method for manufacturing an odd-numbered layer carrier plate according to claim 1, characterized in that: In step S5, the lamination is a single-sided lamination, where the prepreg and the outer copper foil are laminated only on the side of the second conductive layer where the first inner layer circuit pattern is formed.

3. The method for manufacturing and processing an odd-numbered layer carrier plate according to claim 1, characterized in that: In step S5, the pressing is a double-sided pressing. While pressing the prepreg and the outer copper foil on the side of the second conductive layer where the first inner layer circuit pattern is formed, a useless prepreg and / or copper foil is pressed on the protective copper foil on the first side to balance the thermal stress during the pressing process.

4. The method for manufacturing an odd-numbered layer carrier plate according to claim 1, characterized in that: The thickness of the first conductive layer and the second conductive layer is 2μm to 5μm, and the thickness of the protective copper foil is 18μm to 35μm.

5. The method for manufacturing an odd-numbered layer carrier plate according to claim 1, characterized in that: In step S3, the laser drilling uses an ultraviolet laser; the width of the fused copper edge is 0.1mm to 0.3mm.

6. The method for manufacturing an odd-numbered layer carrier plate according to claim 1, characterized in that: The protective copper foil and adhesive layer peeled off in step S7, after adhesive layer removal treatment, form a thin copper-clad laminate material for experimental testing.

7. The method for manufacturing an odd-numbered layer carrier plate according to claim 1, characterized in that: In step S8, the formation of the second outer layer circuit pattern and the third outer layer circuit pattern includes: laser drilling, desmearing, chemical copper plating, electroplating to fill holes, and circuit pattern formation.

8. The method for manufacturing an odd-numbered layer carrier plate according to claim 1, characterized in that: The method further includes: S9: After completing step S8, printing solder resist ink on both sides of the substrate to form a solder resist layer.

9. An odd-layer carrier plate, characterized in that: It is manufactured using the manufacturing and processing method of any one of claims 1 to 8 for an odd-numbered layer carrier plate.

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