Processing method of high-order impedance controllable multi-layer interconnection FPC

Abstract

The application discloses a processing method of high-order impedance controllable multilayer interconnection FPC and belongs to the technical field of flexible printed circuit boards. The method selects double-sided glue-free calendering base material as a main base material, completes core layer impedance control line etching, implements selective plasma activation in the impedance control line area, coats ultrathin low dielectric constant modified glue, forms a dielectric compensation layer through pre-curing, prepares a jig alignment hole and an optical identification point on the main base material, symmetrically attaches pure glue to the main base material as a center and upwards and downwards through the jig sleeve alignment hole to attach and press the outer layer base material, forms a divergent laminated structure, fills the step height difference formed by the dielectric compensation layer in the pre-pressing stage, discharges low pressure, and then rises to the main pressing stage to complete lamination. The application locks the tolerance in the core impedance layer, realizes active regulation and control of the impedance in advance, greatly narrows the impedance window of the finished product, eliminates micro-bubbles, and improves the alignment tolerance and reliability.

Description

Technical Field

[0001] This invention belongs to the field of flexible printed circuit board (FPC) technology, specifically relating to a processing method for a high-order impedance controllable multilayer interconnect FPC. Background Technology

[0002] High-order multilayer interconnect HDI-FPCs (typically 7 layers or more) are widely used in high-end consumer electronics and automotive electronics. One of their core performance requirements is the precise and controllable impedance of high-frequency differential circuits and precision single-ended circuits. However, existing technologies have the following drawbacks in the fabrication of high-order HDI-FPCs: 1. Traditional processes typically employ a sequential layer-by-layer stacking method from the bottom layer to the top layer, resulting in a continuous accumulation of alignment misalignment with each layer. Flexible PI substrates have a high coefficient of thermal expansion and are sensitive to temperature and humidity. The inconsistent expansion and contraction after etching and browning of each core layer, coupled with the high temperature during lamination, can easily cause interlayer slippage due to resin flow. The final layer may deviate from the IPC Level 3 standard by ±30 μm, leading to blind via interconnect failure and geometric alignment distortion.

[0003] 2. Impedance control mainly relies on post-production measurement and trial-and-error rework of the first piece, lacking proactive means to control the dielectric constant and residual stress of the core impedance layer in advance. Summary of the Invention

[0004] A method for fabricating a high-order impedance-controllable multilayer interconnect FPC includes the following steps: S1. Select double-sided adhesive-free calendered substrate as the main substrate, complete the core layer circuit etching, and form an impedance control circuit including high-frequency differential circuit and single-ended impedance circuit. S2. Selective plasma activation is performed on the impedance control circuit region, followed by coating with a low dielectric constant modified adhesive and B-stage pre-curing to form a dielectric compensation layer with the modified adhesive. S3. Prepare fixture alignment holes and optical identification points on the main substrate; S4. With the main substrate as the center, pure adhesive is symmetrically attached upwards and downwards through the alignment holes of the fixture and the outer substrate is superimposed to form a stacked structure that radiates from the middle to both ends.

[0005] Preferably, step S2 further includes preparing shallow grooves with a width of 50~100 μm on both sides of the impedance control line as a flow barrier structure before the selective plasma activation.

[0006] Preferably, in step S2, the selective plasma activation employs a dry film mask combined with laser windowing to expose the impedance control circuit region; the activation gas used is... and The mixture of gases and The volume ratio is 3:1 to 5:1, and the power density is 0.1 to 0.3. The processing time is 30~90 seconds.

[0007] Preferably, in step S2, the dielectric constant Dk of the low dielectric constant modified adhesive after curing is 2.8~3.2, and the coating thickness is 5~8 μm; the B-stage pre-curing temperature is 120~140℃, the curing time is 5~15 min, and the degree of curing is controlled at 30~50%.

[0008] Preferably, the low dielectric constant modified adhesive comprises the following components: fluorinated bisphenol A diglycidyl ether, bisphenol F diglycidyl ether, linear phenolic resin, latent imidazole accelerator, and surface-hydrophobic treated vapor phase. and solvents.

[0009] Preferably, the mass fractions of each component in the low dielectric constant modified adhesive are as follows: 40-55 parts of fluorinated bisphenol A diglycidyl ether, 20-30 parts of bisphenol F diglycidyl ether, 15-25 parts of linear phenolic resin, 0.8-1.5 parts of latent imidazole accelerator, and surface hydrophobic treated vapor phase. 3 to 6 servings.

[0010] Preferably, the low dielectric constant modified adhesive is prepared by the following steps: S10. Fluorinated bisphenol A diglycidyl ether and bisphenol F diglycidyl ether are mixed at 80~90°C; S20. Add linear phenolic resin, heat to 100~110℃ and stir to dissolve for pre-reaction to form a prepolymer, wherein the epoxy conversion rate of the prepolymer is controlled at 10~15%; S30. Cool to below 60°C, then add the latent imidazole promoter and the surface-hydrophobic treated gas phase. Dispersed to a thixotropic index TI ≥ 3.5; S40. Add the solvent to adjust the solid content to 35-45%.

[0011] Preferably, in step S4, the main substrate is an L3 / L4 core board, and the order of the divergent stacking is as follows: first, pure adhesive is applied to the L3 and L4 surfaces respectively, and L2 and L5 layers of single-sided adhesive-free substrate are stacked on top; then, pure adhesive is applied outwards and L1 and L6 layers of single-sided adhesive-free substrate are stacked on top; finally, pure adhesive is applied and L7 layer of single-sided adhesive-free substrate is stacked on top; each applied pure adhesive layer is separated by laser to create windows to avoid gaps in the layered areas.

[0012] Preferably, the lamination process in step S4 includes a pre-pressing stage and a main pressing stage, wherein the pressure in the pre-pressing stage is ≤0.5 MPa and the temperature is controlled at 120~140℃; the pressure in the main pressing stage is 2.0~3.0 MPa; and after the outer layer circuit is processed, a second drilling is performed in the drilling process using solid copper grippers punched out by laser as a positioning reference.

[0013] Preferably, step S1 further includes pre-compensating for the pattern expansion and contraction in the X and Y directions based on the anisotropic thermal shrinkage coefficient of the main substrate.

[0014] The fabrication method for high-order impedance-controllable multilayer interconnect FPC provided by this invention has the following beneficial effects: 1. By using a process timing sequence that "diversifies from the middle to both ends", the alignment tolerance of high-frequency differential and precision single-ended circuits is firmly locked on the main substrate of the core impedance layer. Combined with the closed-loop measurement of layer expansion and contraction, the problem of layer misalignment accumulation caused by traditional unidirectional stacking is overcome. The stacking alignment tolerance can be stably controlled within ±15 μm, which greatly reduces blind via misalignment and open / short circuit defects.

[0015] 2. By selectively activating plasma and pre-coating with low dielectric constant modified adhesive and B-stage pre-curing, the dielectric constant and thickness of the core impedance layer can be actively controlled in advance. This effectively resists the compression of the impedance line geometry by subsequent high voltage stacking, significantly narrows the differential impedance and single-ended impedance windows of the finished product, and can effectively solve the problem of high impedance deviation rate. Detailed Implementation

[0016] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be described in detail below. The description in this part is only exemplary and explanatory, and should not be used to limit the scope of protection of the present invention in any way.

[0017] This embodiment provides a method for fabricating a high-order impedance-controllable multilayer interconnect FPC, including the following steps: (1) Preparation of double-sided core in the middle: Double-sided adhesive-free calendered substrate is selected as the main substrate, and the core layer circuit is etched to form an impedance control circuit including high-frequency differential circuit and single-ended impedance circuit.

[0018] (2) Core layer dielectric pre-compensation: Selective plasma activation is performed in the impedance control circuit area, followed by coating with ultra-thin low dielectric constant modified adhesive, and B-stage pre-curing is performed to form a dielectric compensation layer.

[0019] (3) Fixture alignment reference preparation: Fixture alignment holes and optical identification points are prepared on the main substrate.

[0020] (4) Diverging from the middle to both ends of the laminate: Taking the main substrate as the center, pure adhesive is symmetrically attached upwards and downwards through the alignment holes of the fixture, and the outer substrate is then laminated to form a laminated structure that diverges from the middle to both ends. During the lamination process, in the pre-pressing stage, the secondary flow of pure adhesive in the molten state is used to fill the step height difference formed by the medium compensation layer and low-pressure venting is performed. After venting is completed, the pressure is increased to the main pressing stage to complete the lamination. After each lamination, the expansion and contraction data are measured, and the subsequent lamination parameters are corrected in a closed loop based on the measured data.

[0021] In step (1), the double-sided adhesive-free calendered substrate is composed of an upper copper foil (12 μm), a middle polyimide PI insulating layer (25 μm) and a lower copper foil (12 μm); the impedance control circuit includes a high-frequency differential circuit (target linewidth / spacing of 50 / 50 μm) opened by microstrip line topology extension and a single-ended impedance circuit (target linewidth of 60 μm).

[0022] In step (2), selective plasma activation is performed only on the local copper surface and surrounding PI substrate where the impedance control circuit is located. High-energy active particles are generated by gas ionization to attack the substrate surface, cut the molecular chains and introduce polar functional groups (such as hydroxyl and carboxyl groups), and increase the surface tension of the treated area to more than 55 mN / m, while the untreated area remains in its original hydrophobic state. Subsequently, an ultra-thin low dielectric constant modified adhesive is coated and locked into a semi-cured state by B-stage pre-curing to form a dielectric compensation layer that works in synergy with the upper dielectric.

[0023] In step (3), fixture alignment holes (such as D holes with a diameter of 2.0 mm) and optical identification points (including LDI positioning points and PTH monitoring rings) are prepared in the non-patterned area of ​​the main substrate board edge.

[0024] In step (4), "diffusion from the middle to both ends" refers to symmetrically and synchronously laying pure adhesive and single-sided unadhesive substrates upwards (L2, L1) and downwards (L5, L6, L7) with the L3 / L4 core board as the center; in the pre-pressing stage of the initial rapid lamination, the temperature is controlled at the 120~140℃ window, which is the lowest point of the pure adhesive (AD) resin melt viscosity (below 100 Pa·s), and a lower pressure (≤0.5MPa) is used to induce the pure adhesive resin to generate controlled secondary lateral melt flow, fill the small step height difference formed at the edge of the ultra-thin modified adhesive layer, and expel the residual micro-traces of gas between layers; after the steps are filled and the gas is expelled, the pressure is quickly increased to the main pressure stage (2.0~3.0). High-temperature curing and pressing are completed at MPa. After each lamination, the actual spatial displacement of the D-hole and diagonal reference point on the main substrate is measured using a CCD image measuring instrument. The measured expansion and contraction is compared with the theoretical shrinkage rate to generate a dynamic scaling factor, which is input into the engineering CAM system to correct the size of the next layer of outer film / LDI exposure pattern and the coordinates of the second drill target in real time, forming a full displacement closed loop.

[0025] The fabrication method for high-order impedance-controllable multilayer interconnect FPC provided in this embodiment has the following beneficial effects: 1. By using a process timing sequence that "diversifies from the middle to both ends", the alignment tolerance of high-frequency differential and precision single-ended circuits is firmly locked on the main substrate of the core impedance layer. Combined with the closed-loop measurement of layer expansion and contraction, the problem of layer misalignment accumulation caused by traditional unidirectional stacking is overcome. The stacking alignment tolerance can be stably controlled within ±15 μm, which greatly reduces blind via misalignment and open / short circuit defects.

[0026] 2. By selectively activating plasma and pre-coating with low dielectric constant modified adhesive and B-stage pre-curing, the dielectric constant and thickness of the core impedance layer can be actively controlled in advance. This effectively resists the compression of the impedance line geometry by subsequent high voltage stacking, significantly narrows the differential impedance and single-ended impedance windows of the finished product, and can effectively solve the problem of high impedance deviation rate.

[0027] Furthermore, in step (2), before selective plasma activation, shallow grooves with a width of 50~100 μm are prepared on both sides of the impedance control circuit as flow barrier structures.

[0028] Furthermore, in step (2), selective plasma activation employs a dry film mask combined with laser windowing to expose the impedance control circuit area. The activation gas used is... and The mixture of gases and The volume ratio is 3:1 to 5:1, and the power density is 0.1 to 0.3. The processing time is 30~90 seconds.

[0029] Furthermore, in step (2), the dielectric constant Dk of the low dielectric constant modified adhesive after curing is 2.8~3.2, and the coating thickness is 5~8 μm. The B-stage pre-curing temperature is 120~140℃, the curing time is 5~15 min, and the degree of curing is controlled at 30~50%.

[0030] Prior to selective plasma activation, shallow grooves with a width of 50–100 μm and a depth of 5–8 μm are created in parallel on both sides of the impedance control line using laser ablation or micro-etching processes. The edges of these shallow grooves are spaced 10–20 μm apart from the edges of the impedance lines, forming a physical microgroove barrier.

[0031] Plasma activation employs dry film lamination combined with laser windowing masking to precisely expose only impedance lines and shallow groove areas. In the mixed gas... and The air is introduced into the vacuum chamber at a volume ratio of 3:1 to 5:1, and the pressure is maintained at 0.1 to 0.3... Ionization at power density. Free radicals provide hydroxylation and roughening, improving interfacial adhesion, while The fluorine free radicals generated by ionization are used for gentle micro-etching and cleaning of residues. The processing time is controlled at 30~90 s, so that the water droplet contact angle in the activated area is reduced to below 20°.

[0032] After curing, the coating of ultrathin low-Dk modified adhesive resulted in a Dk value ranging from 2.8 to 3.2, with a dry film thickness of 5 to 8 μm. B-stage pre-curing involved baking at 120 to 140°C for 5 to 15 minutes, and the modified adhesive was brought to a semi-cured B-stage state by controlling the heat integration process.

[0033] Furthermore, the low dielectric constant modified adhesive comprises the following material components: fluorinated bisphenol A diglycidyl ether, bisphenol F diglycidyl ether, linear phenolic resin, latent imidazole accelerator, and surface-hydrophobic treated vapor phase. and solvents.

[0034] Furthermore, the mass fractions of each component in the low dielectric constant modified adhesive are as follows: 40-55 parts of fluorinated bisphenol A diglycidyl ether, 20-30 parts of bisphenol F diglycidyl ether, 15-25 parts of linear phenolic resin, 0.8-1.5 parts of latent imidazole accelerator, and surface hydrophobic treated vapor phase. 3 to 6 servings.

[0035] Furthermore, the low dielectric constant modified adhesive is prepared through the following steps: a. Mix fluorinated bisphenol A diglycidyl ether and bisphenol F diglycidyl ether at 80~90°C.

[0036] b. Add linear phenolic resin, heat to 100~110℃, stir to dissolve and carry out pre-reaction, control the epoxy conversion rate to 10~15%, and form a prepolymer.

[0037] c. Cool to below 60℃, add latent imidazole accelerator and surface-hydrophobic treated gas phase Dispersed to a thixotropic index TI≥3.5.

[0038] d. Add solvent to adjust the solid content to 35-45%.

[0039] Fluorinated bisphenol A diglycidyl ether (40-55 parts) serves as the main resin, utilizing the low polarizability and large volume of fluorine atoms in the molecule to reduce the dielectric constant of the adhesive layer; bisphenol F diglycidyl ether (20-30 parts) possesses low viscosity characteristics, used to adjust the rheological properties of the system and improve the smoothness of ultra-thin coatings; linear phenolic resin (15-25 parts, softening point 80-100℃) provides a rigid skeleton, enhancing the shear modulus in the B-stage state; latent imidazole accelerators (0.8-1.5 parts, such as microencapsulated 2-ethyl-4-methylimidazolium) are activated at 120-140℃, precisely controlling the degree of semi-curing; and surface hydrophobic treatment vapor phase... (3-6 portions, specific surface area 150-200) A thixotropic network was constructed; the solid content was adjusted to 35-45% using diethylene glycol monobutyl ether acetate, a high-boiling-point solvent.

[0040] In the preparation process, fluorinated epoxy and bisphenol F epoxy are first premixed at 80-90℃; phenolic resin is added and the temperature is raised to 100-110℃ for a mild pre-reaction. The unreacted epoxy groups are determined by hydrochloric acid-acetone titration. When the epoxy conversion rate reaches 10-15%, the temperature is immediately lowered to below 60℃ to terminate the reaction, forming a prepolymer; subsequently, a latent accelerator and a hydrophobic polymer are added. High-speed dispersion achieves a thixotropic index (TI) of over 3.5. During the pre-reaction process (stirring at 100-110℃), samples are taken every 10 minutes. Unreacted epoxy groups in the sample are reacted with excess hydrochloric acid-acetone solution, and then the excess hydrochloric acid is back-titrated with sodium hydroxide (NaOH) standard solution to calculate the current epoxy value of the sample. ).

[0041] The formula for calculating conversion rate is:

[0042] in, This represents the initial epoxy value of the mixed resin before the reaction. The measured epoxy value at reaction time t.

[0043] Further, in step (4), the main substrate is an L3 / L4 core board, and the order of divergent stacking is as follows: first, pure adhesive is applied to the L3 and L4 surfaces respectively, and then L2 and L5 layers of single-sided adhesive-free substrate are stacked on top. Then, pure adhesive is applied outwards and L1 and L6 layers of single-sided adhesive-free substrate are stacked on top. Finally, pure adhesive is applied and L7 layer of single-sided adhesive-free substrate is stacked on top. Each applied pure adhesive layer is separated by laser-assisted window opening to avoid gaps in the layered areas.

[0044] Furthermore, in step (4), the pressure during the pre-pressing stage is ≤0.5 MPa, and the temperature is controlled at 120~140℃. The pressure during the main pressing stage is 2.0~3.0 MPa. After the outer layer circuitry is processed, solid copper grippers punched out by laser are used as positioning references for secondary drilling during the drilling process.

[0045] Furthermore, in step (1), based on the anisotropic thermal shrinkage coefficient of the main substrate, the pattern expansion and contraction in the X and Y directions are pre-compensated during the pattern design stage. The high-frequency differential impedance of the finished product is controlled within ±5Ω of the design value, the single-ended impedance is controlled within ±3Ω of the design value, and the lamination alignment tolerance is controlled within ±15 μm.

[0046] The divergent lamination process strictly follows a symmetrical sequence: L3 / L4 core board, AD2~3 / AD3~4 pure adhesive, L2 / L5 single-sided adhesive-free substrate, AD1~2 / AD5~6 pure adhesive, L1 / L6 single-sided adhesive-free substrate, AD6~7 pure adhesive, and L7 substrate. Before lamination, all pure adhesives are used to cut and open windows in the delaminated areas using ultraviolet laser.

[0047] After the pre-pressure low-pressure exhaust (≤0.5 MPa, 120~140℃) and main pressure high-temperature and high-pressure curing (2.0~3.0 MPa, 160~180℃) are completed, the outer layer second drilling process uses solid copper gripping points (P holes) punched on the edge of the board by laser for photoelectric sensing gripping point positioning to remove the outer layer waste copper obstruction.

[0048] Considering the inconsistency in thermal shrinkage rates between the longitudinal (MD) and transverse (TD) directions of the rolled copper foil PI substrate (e.g., MD = -0.05%, TD = -0.12%), the X / Y axis graphics can be pre-amplified according to the anisotropic inverse coefficient during the engineering graphic design stage. This ultimately ensures that the differential impedance of the finished product is controlled within ±5Ω of the design value, the single-ended impedance within ±3Ω, and the lamination alignment tolerance ≤ ±15μm.

[0049] Specific embodiments are provided below. These embodiments are intended to enable those skilled in the art to more fully understand the present invention, but do not limit the present invention in any way.

[0050] Example 1

[0051] In this embodiment, double-sided adhesive-free rolled copper foil substrate (copper thickness 12 μm, polyimide PI thickness 25 μm) is selected as the main substrate of L3 / L4 core board. Circuit pattern transfer and etching are completed to form a red high-frequency differential impedance line with a target linewidth / spacing of 50 / 50 μm and a green single-ended impedance line with a target linewidth of 60 μm. Based on the anisotropic shrinkage rate of the rolled copper foil PI substrate (longitudinal MD -0.05%, transverse TD -0.12%), the pattern is pre-compensated for scaling in reverse proportion during the CAM engineering drawing stage. Next, shallow grooves with a width of 80 μm and a depth of 6 μm are created on both sides of the impedance control line using ultraviolet laser ablation as physical flow barrier walls, with a 15 μm gap between the groove edge and the line edge. Subsequently, a photosensitive dry film is laminated onto the L3 / L4 surface, and laser windowing exposes the impedance line and shallow groove area, allowing a 4:1 volume ratio of [unspecified material] to be introduced. The mixed gas is at 0.2 Vacuum plasma activation treatment at power density for 60 s reduced the water droplet contact angle in the activation zone to 18°.

[0052] Weigh 48.0 g of fluorinated bisphenol A diglycidyl ether and 25.0 g of bisphenol F diglycidyl ether and premix them at 85℃; add 20.0 g of linear phenolic resin with a softening point of 90℃, heat to 105℃ and stir to pre-react, and determine the epoxy value of the system every 10 min using the hydrochloric acid-acetone titration method (GB / T 1677). When the initial epoxy value decreases from 0.45 mol / 100g to 0.39 mol / 100g (epoxy conversion rate reaches about 12%), immediately cool down to 55℃; add 1.2 g of microencapsulated 2-ethyl-4-methylimidazolium accelerator and surface hydrophobic gas phase. (Specific surface area 180) 4.5 g of diethylene glycol monobutyl ether acetate was dispersed at high speed until the thixotropic index (TI) reached 3.8; finally, 60.0 g of diethylene glycol monobutyl ether acetate was added to adjust the solid content, and the mixture was filtered to obtain a low-Dk modified adhesive.

[0053] The initial gel time of the modified collagen solution was measured to be 360 ​​s at 130℃ using a plate gel time tester according to GB / T 4722 standard. The modified adhesive was coated onto a plasma-activated zone, and the dry film thickness after drying was controlled to be 6 μm (Dk = 3.0). Pre-curing was performed by baking in a 130℃ oven for 6 min (including time for solvent evaporation and temperature rise). After baking, samples were taken for retesting, and the residual gel time of the semi-cured film at 130℃ was shortened to 200 s. The dry film mask was removed and the film was cleaned.

[0054] D-holes with a diameter of 2.0 mm, LDI positioning points, and PTH monitoring holes were prepared on the edge of the main substrate board. Centered on the L3 / L4 core board, 15 μm thick epoxy resin halogen-free pure adhesive P15-250E(F), after laser-layered windowing, was symmetrically attached through the D-holes using a fixture. Then, L2 / L5 single-sided adhesive-free substrates, AD1~2 / AD5~6 pure adhesive, L1 / L6 substrates, and AD6~7 pure adhesive and L7 substrates were sequentially laminated. The rapid lamination process employed a vacuum stepped pressurization process: the pre-pressing stage was set at 130℃ and 0.4 MPa for 4 min; subsequently, the pressure was increased to the main press stage at 2.5 MPa and 170℃ to complete high-temperature curing. After each lamination, the actual displacement of the D-hole spacing was measured using a CCD image measuring instrument, and the dimensions of the next layer's LDI film pattern were dynamically corrected after comparison with the theoretical shrinkage rate. After lamination, the outer layer is drilled twice (using laser P-hole solid copper gripping for positioning), VCP copper plating is performed, the circuit is exposed and etched, solder resist is applied, and the shielding film steel sheet is bonded to complete the finished product manufacturing.

[0055] Example 2

[0056] In this embodiment, the main substrate and pattern pre-compensation are the same as in Embodiment 1, but the width of the shallow groove is adjusted to 50 μm and the depth to 5 μm. Plasma activation is performed using... Volume ratio 3:1, power density 0.1 After 90 seconds of treatment, the contact angle of the water droplets in the activated zone decreased to 19°.

[0057] Weigh 42.0 g of fluorinated bisphenol A diglycidyl ether and 28.0 g of bisphenol F diglycidyl ether, premix them at 80℃, add 22.0 g of linear phenolic resin, heat to 100℃ for pre-reaction, and when the epoxy conversion rate reaches about 10%, cool down to 50℃; add 0.9 g of microencapsulated imidazole promoter and hydrophobic gas phase. 3.5 g of the solution was dispersed until the thixotropic index (TI) was 3.5, and 65.0 g of diethylene glycol monobutyl ether acetate was added to adjust the solid content. The initial gel time of the original solution was measured at 120℃ according to GB / T 4722 standard and was 480 s. The solution was coated onto the activation area and baked at 120℃ for 8 min. The residual gel time at 120℃ was measured again and was 240 s (Dk = 2.8, dry film thickness 5 μm).

[0058] The divergent lamination and alignment reference preparation were the same as in Example 1. During the rapid pressing pre-pressing stage, the temperature was set at 120 ℃ and the pressure at 0.3 MPa for 5 min. During the main pressing stage, the pressure was increased to 2.0 MPa and pressed at 165 ℃ for curing. After each lamination, the displacement of the D-hole was measured, and the exposure pattern for the next layer was corrected using a closed-loop method. Finally, the second drilling and outer layer processes were completed.

[0059] Example 3

[0060] In this embodiment, the main substrate and pattern pre-compensation are the same as in Embodiment 1, but the width of the shallow groove is adjusted to 100 μm and the depth to 8 μm. Plasma activation is performed using... Volume ratio 5:1, power density 0.3 After 30 seconds of treatment, the contact angle of water droplets in the activated zone decreased to 17°.

[0061] Weigh 54.0 g of fluorinated bisphenol A diglycidyl ether and 21.0 g of bisphenol F diglycidyl ether, premix them at 90℃, add 16.0 g of linear phenolic resin, raise the temperature to 110℃ for pre-reaction, and when the epoxy conversion rate reaches about 15%, lower the temperature to 50℃; add 1.4 g of microencapsulated imidazole accelerator and hydrophobic gas phase. 5.5 g of the solution was dispersed until the thixotropic index (TI) was 4.1, and 55.0 g of diethylene glycol monobutyl ether acetate was added to adjust the solid content. The initial gel time of the original solution was measured at 140℃ according to GB / T 4722 standard and was found to be 300 s. After baking at 140℃ for 5 min, the residual gel time at 140℃ was measured again and found to be 180 s (Dk = 3.2, dry film thickness 8 μm).

[0062] The divergent lamination process is the same as in Example 1. During the rapid pressing pre-pressing stage, the temperature is set at 140°C and the pressure at 0.5 MPa, maintained for 3 minutes. During the main pressing stage, the pressure is increased to 3.0 MPa and the temperature is 175°C to complete curing. After each lamination, the displacement of the D-hole is measured for closed-loop correction, followed by selective plating and conventional outer layer processing.

[0063] Comparative Example 1 In this comparative example, the same L3 / L4 core board substrate as in Example 1 was used. Differential and single-ended impedance lines were etched, but shallow grooves were not created on both sides of the impedance lines, selective plasma activation was not performed, and low-Dk modified adhesive was not applied. D-holes were directly prepared on the L3 / L4 core board, and pure adhesive was bonded and the outer substrate was stacked in a diverging sequence from the center to both ends. During lamination, vacuum step pressure was not used; instead, conventional single-stage high-pressure lamination and curing were performed at 2.5 MPa and 170°C. The lamination process did not undergo layer-by-layer expansion and contraction measurement closed-loop correction; only front-end fixing pre-compensation was used, followed by outer layer processing and testing.

[0064] Comparative Example 2 In this comparative example, the etching and plasma activation parameters of the L3 / L4 main substrate circuits are completely consistent with those in Example 1, but shallow grooves are not created on both sides of the circuits. A low-Dk modified adhesive with the same formulation as in Example 1 (target thickness 6 μm after wet film drying) is applied, but no pre-curing at 130°C is performed after coating. Pure adhesive is then directly attached and the outer substrate is laminated. The fast lamination process also skips the low-pressure pre-pressure venting section, directly applying pressure to 2.5 MPa and pressing at 170°C for curing. Subsequent outer layer processes are then completed.

[0065] Comparative Example 3 In this comparative example, the etching of the L3 / L4 main substrate circuitry, the creation of shallow grooves, plasma activation, the application of low-Dk modified adhesive, and the B-stage pre-curing at 130℃ for 6 min were all exactly the same as in Example 1. However, during the subsequent divergent lamination and rapid pressing, the pre-pressurized low-pressure secondary flow section was omitted (0.4 MPa low-pressure venting was not set), and the pressure was directly increased to the 2.5 MPa main pressure section and rapidly heated to 170℃ for pressing and curing. The outer layer processing was completed as usual.

[0066] The 7-layer HDI-FPC products prepared in Examples 1-3 and Comparative Examples 1-3 were subjected to various core performance tests. The test methods and judgment criteria are as follows: 1. Lamination alignment tolerance deviation test: The relative concentric deviation displacement between the main substrate D hole and the outer layer PTH through hole / second drill hole center is measured using an automatic image measuring instrument (CCD, accuracy ±0.5 μm). 20 blind hole test points are randomly selected and the maximum offset value is taken.

[0067] 2. Finished Product Differential and Single-Ended Impedance Window Test: A time domain reflectometer (TDR) is used to measure the high-frequency differential impedance (target value 100Ω) and single-ended impedance (target value 50Ω) of the test code on the finished PCB, and the impedance distribution range of 100 sampling lines on each board is recorded.

[0068] 3. 180° peel strength test: Cut the finished product into strips 10 mm wide and use a universal tensile testing machine to perform a 180° peel test on the modified rubber / pure rubber step bonding area at a tensile speed of 50 mm / min. Record the peel force value (N / mm).

[0069] 4. Thermal shock cycling test: Place the sample in a thermal shock test chamber and keep it at -40℃ and 125℃ for 15 min each, with a transition time of <10 s. Repeat this cycle 100 times. Remove the sample afterward. Visually inspect and peel to determine the percentage of blistering and delamination between the layers within the plate.

[0070] 5. Measurement of modified adhesive layer thickness deviation: The difference in dry film thickness before and after coating the top of the impedance line with low Dk modified adhesive was measured using a digital film thickness gauge (accuracy 0.1 μm), and the maximum absolute value of the deviation from the target dry film thickness was calculated.

[0071] The test data is shown in Table 1 below:

[0072] The data above shows that: In Examples 1-3, the differential impedance of the finished products was within ±5Ω of the target value, the single-ended impedance was within ±3Ω, and the interfacial peel strength was high. The thermal shock delamination rate was 0%, and the thickness deviation of the modified adhesive was extremely small.

[0073] Comparative Example 1 shows a severely scattered impedance window, proving that relying solely on physical alignment cannot solve the problems of electromagnetic interference and impedance deviation in high-frequency dielectrics; Comparative Example 2 shows a thickness deviation of ±2.85 μm and low interface peel strength, resulting in severe impedance distortion; Comparative Example 3 shows a peel strength of only 0.58 N / mm, attributed to the inability to fill the micro-steps, resulting in inadequate coverage of the step edges; and a thermal shock burst rate as high as 18.40%.

[0074] This article uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. The above are merely preferred embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the technical scope disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be within the scope of protection of the present invention.

Claims

1. A method for fabricating a high-order impedance-controllable multilayer interconnect FPC, characterized in that, Includes the following steps: S1. Select double-sided adhesive-free calendered substrate as the main substrate, complete the core layer circuit etching, and form an impedance control circuit including high-frequency differential circuit and single-ended impedance circuit. S2. Selective plasma activation is performed on the impedance control circuit region, followed by coating with a low dielectric constant modified adhesive and B-stage pre-curing to form a dielectric compensation layer with the modified adhesive. S3. Prepare fixture alignment holes and optical identification points on the main substrate; S4. With the main substrate as the center, pure adhesive is symmetrically attached upwards and downwards through the alignment holes of the fixture and the outer substrate is superimposed to form a stacked structure that radiates from the middle to both ends.

2. The processing method according to claim 1, characterized in that, Step S2 further includes preparing shallow grooves with a width of 50~100 μm on both sides of the impedance control line as a flow barrier structure before the selective plasma activation.

3. The processing method according to claim 1, characterized in that, In step S2, the selective plasma activation employs a dry film mask combined with laser windowing to expose the impedance control circuit region; the activation gas used is... and The mixture of gases and The volume ratio is 3:1 to 5:1, and the power density is 0.1 to 0.

3. The processing time is 30~90 seconds.

4. The processing method according to claim 1, characterized in that, In step S2, the dielectric constant Dk of the low dielectric constant modified adhesive after curing is 2.8~3.2, and the coating thickness is 5~8 μm; the B-stage pre-curing temperature is 120~140℃, the curing time is 5~15 min, and the degree of curing is controlled at 30~50%.

5. The processing method according to claim 1, characterized in that, The low dielectric constant modified adhesive comprises the following components: fluorinated bisphenol A diglycidyl ether, bisphenol F diglycidyl ether, linear phenolic resin, latent imidazole accelerator, and surface-hydrophobic treated vapor phase. and solvents.

6. The processing method according to claim 5, characterized in that, The mass fractions of each component in the low dielectric constant modified adhesive are as follows: 40-55 parts of fluorinated bisphenol A diglycidyl ether, 20-30 parts of bisphenol F diglycidyl ether, 15-25 parts of linear phenolic resin, 0.8-1.5 parts of latent imidazole accelerator, and surface hydrophobic treated vapor phase. 3 to 6 servings.

7. The processing method according to claim 5, characterized in that, The low dielectric constant modified adhesive is prepared by the following steps: S10. Fluorinated bisphenol A diglycidyl ether and bisphenol F diglycidyl ether are mixed at 80~90°C; S20. Add linear phenolic resin, heat to 100~110℃ and stir to dissolve and carry out pre-reaction to form a prepolymer, wherein the epoxy conversion rate of the prepolymer is controlled at 10~15%; S30. Cool to below 60°C, then add the latent imidazole promoter and the surface-hydrophobic treated gas phase. Dispersed to a thixotropic index TI ≥ 3.5; S40. Add the solvent to adjust the solid content to 35-45%.

8. The processing method according to claim 1, characterized in that, In step S4, the main substrate is an L3 / L4 core board, and the divergent stacking sequence is as follows: first, pure adhesive is applied to the L3 and L4 surfaces respectively, and L2 and L5 layers of single-sided adhesive-free substrate are stacked on top; then, pure adhesive is applied outwards and L1 and L6 layers of single-sided adhesive-free substrate are stacked on top; finally, pure adhesive is applied and L7 layer of single-sided adhesive-free substrate is stacked on top; each applied pure adhesive layer is separated by laser to create windows to avoid gaps in the layered areas.

9. The processing method according to claim 1, characterized in that, The stacking process in step S4 includes a pre-pressing stage and a main pressing stage. The pressure in the pre-pressing stage is ≤0.5 MPa and the temperature is controlled at 120~140℃. The pressure in the main pressing stage is 2.0~3.0 MPa. After the outer layer circuit is processed, a second drilling is performed in the drilling process using solid copper grippers punched out by laser as a positioning reference.

10. The processing method according to claim 1, characterized in that, Step S1 also includes pre-compensating for the pattern expansion and contraction in the X and Y directions based on the anisotropic thermal shrinkage coefficient of the main substrate.

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