High speed printed circuit board impedance compensation method

Abstract

The application relates to a high-speed printed circuit board impedance compensation method, which comprises the following steps: forming an impedance test strip and a sampling piece of a plurality of impedance measurement point areas on an inner layer core board; obtaining characteristic impedance measured values and corresponding plane coordinates; measuring medium layer thickness, copper thickness and line width of a corresponding area of the sampling piece, and constructing a multivariate parameter vector of each measurement point; calculating medium thickness compensation amounts of each measurement point, and generating a resin coating compensation graph; preparing a coating screen with differentiated openings, and transferring resin paint on the screen to corresponding areas of a prepreg; placing the printed prepreg in a pre-baking device for baking; laminating the prepreg with the compensation after pre-baking, the inner layer core board and copper foil according to a designed lamination sequence, and placing the lamination structure in a vacuum laminating machine for pressing. The compensation method completes impedance and geometric parameter collection of each measurement point after first pressing, and reduces product scrap rate from a process source.

Description

Technical Field

[0001] This application relates to printed circuit board processing technology, specifically to a method for impedance compensation of high-speed printed circuit boards. Background Technology

[0002] With the explosive growth in computing power demand for large AI models, AI servers have become a core infrastructure of data centers. The high-speed interconnects within AI servers (such as PCIe Gen6, NVLink 5.0, and 800G / 1.6T optical module ports) place extremely high demands on signal integrity, with single-channel speeds climbing to 64 GT / s and even exceeding 200 Gb / s. One of the key physical carriers supporting these high-speed signals is the printed circuit board (commonly known as connector PCB or gold finger PCB) mounted at the high-speed connector plug. These PCBs are typically manufactured using low-loss, high-speed materials of M6, M7, and M8 grades, with material suppliers including industry leaders such as Panasonic, Doosan, TUC, and EMC. As a large-scale manufacturer of these high-speed connector PCBs, our company faces a significant process bottleneck: a high internal scrap rate due to impedance control yield issues. The current average impedance yield of the production line is about 85%, which means that about 15 out of every 100 boards put into production are scrapped or reworked in the electrical testing or final inspection stages due to impedance deviation, directly affecting production costs and delivery cycle.

[0003] Key factors affecting PCB impedance include: dielectric constant (Dk value), dielectric layer thickness, copper thickness, line width, and solder mask thickness. Among these factors:

[0004] Material Dk value: M6 / M7 / M8 high-speed materials are supplied by leading suppliers, and the Dk value is relatively stable between batches. Incoming material inspection has been strictly controlled, and it is not the main reason for the current yield fluctuation.

[0005] Copper thickness and linewidth: Through horizontal electroplating uniformity control, LDI direct imaging and online etching factor monitoring, copper thickness and linewidth have been controlled at a high level, and the impact of spatial fluctuations on impedance has become acceptable.

[0006] Dielectric layer thickness: This is the primary source of current low impedance yield fluctuations. The dielectric layer thickness is jointly determined by the core and prepreg / PP in the lamination process. In AI server connector PCBs with significant differences in inner layer pattern density, the residual copper ratio varies significantly in different areas, resulting in strong regional unevenness in the flow and filling behavior of the prepreg resin during lamination. Specifically, areas with dense inner layer circuitry (high residual copper ratio) have insufficient resin filling, resulting in a thinner dielectric thickness after lamination; while areas with sparse inner layers (low residual copper ratio) have resin accumulation, resulting in a thicker dielectric thickness after lamination. This chain reaction of inner layer pattern differences → uneven resin filling → regional dielectric thickness fluctuations causes discrete impedance distributions at different locations on the same board, which is difficult to correct through traditional global etching compensation or layer stack design.

[0007] Currently, the main technical approaches for impedance uniformity control in the industry include: static compensation at the design stage, closed-loop adjustment of process parameters after finished product inspection, flatness correction after lamination, and pure resin filling. However, none of the existing technologies can perform targeted pre-compensation for the dielectric layer thickness before the lamination process. Summary of the Invention

[0008] To overcome the above-mentioned defects, this application provides a high-speed printed circuit board impedance compensation method. This compensation method completes the acquisition of impedance and geometric parameters of each measuring point after the first pressing, and directly obtains the regional compensation amount of the prepreg through inverse kinematics, thereby reducing the scrap rate of the product from the source of the process.

[0009] The technical solution adopted by this application to solve its technical problem is:

[0010] A method for impedance compensation of high-speed printed circuit boards includes the following steps:

[0011] Fabrication of inner core board: Impedance test strips with multiple impedance measurement point areas are formed on the inner core board, and sampling elements are formed at corresponding positions of each impedance test strip. The sampling elements are electrically isolated from the electrical functional area of ​​the motherboard.

[0012] Impedance measurement: After the inner core board and the prepreg are first pressed together, the measured characteristic impedance values ​​and corresponding plane coordinates of each impedance test strip are obtained to obtain the impedance distribution dataset.

[0013] Parameter correlation: After separating the sample, the dielectric layer thickness, copper thickness and line width of the corresponding area of ​​the sample are measured. The measured geometric parameters are correlated with the corresponding data in the impedance distribution dataset to construct a multivariate parameter vector for each measurement point.

[0014] Compensation calculation: Based on the multivariate parameter vector and combined with the preset impedance analysis model, the measured copper thickness and line width are used as fixed parameters, and the preset target impedance is used as input. The ideal dielectric layer thickness corresponding to each measurement point is solved in reverse, and the dielectric thickness compensation amount of each measurement point is calculated. The corresponding plane coordinates are then associated to generate a resin coating compensation diagram.

[0015] Differentiated coating: Prepare a coating screen with differentiated openings, and based on the resin coating compensation map, transfer the resin coating on the screen to the corresponding area of ​​the prepreg to achieve differentiated resin coating;

[0016] Pre-baking semi-curing: The printed semi-cured sheet is placed in a pre-baking device for baking, so that the coated resin layer reaches a semi-cured state.

[0017] Lamination, thermal riveting and pressing: The pre-baked pre-cured sheet with compensation is laminated with the inner core board and copper foil according to the designed lamination sequence, and the laminated structure is pre-fixed by thermal riveting. Then the laminated structure is placed in a vacuum laminator for pressing to obtain a printed circuit board with uniform impedance.

[0018] Optionally, the sampling element is formed on the folded extension of the impedance test strip and is connected to the impedance test strip through a micro-connection bridge. Each impedance measurement point area covers a high residual copper ratio area, a low residual copper ratio area, and a transition area. The high residual copper ratio area includes the BGA package projection area and the connector pin area.

[0019] Optionally, the impedance measurement uses a 10~40GHz vector network analyzer to obtain the measured value of characteristic impedance through time-domain reflection function or frequency-domain-time conversion function, and records the plane coordinates through the precision positioning system of the test fixture.

[0020] Optionally, each sample is circumferentially cut and separated along a preset circumferential contour. During the separation process, the motherboard body remains intact and can continue to be transferred. Cross-sectional samples are prepared and microscopic measurements are performed on each separated sample to obtain the dielectric layer thickness Hi, copper thickness Ti, and test line width Wi of the corresponding area of ​​each sample. For the measurement points of the differential structure, the line spacing Si of the corresponding test line segment is also measured.

[0021] Optionally, the circumferential separation is achieved using a precision milling cutter or laser cutting method. The cross-sectional sample preparation and microscopic measurement specifically include: preparing the sample by slicing, and measuring the dielectric layer thickness H, copper thickness T, test line width W, and line spacing S using a metallographic microscope or scanning electron microscope.

[0022] Optionally, the impedance analysis model is a two-dimensional boundary element field solver model or a two-dimensional / three-dimensional quasi-static electromagnetic field solver model, wherein the dielectric constant εr in the model is the nominal value of the batch of prepreg material or the measured effective dielectric constant.

[0023] Optionally, the calculation of the medium thickness compensation amount also incorporates the flow compensation coefficient α_flow of the prepreg, where α_flow ranges from 1.1 to 1.3, and the specific value is positively correlated with the prepreg model and pressing parameters.

[0024] Optionally, the coating screen is a wire mesh screen, made of 200-500 mesh high-tensile stainless steel wire mesh or composite wire mesh, and the proportion of the opening area or the emulsion thickness in different regions is positively correlated with the compensation amount of the medium thickness at the corresponding measuring point.

[0025] Optionally, the resin coating is an epoxy resin or polyphenylene ether-based resin coating compatible with the prepreg resin system, with a viscosity of 30~80 Pa·s at a temperature of 25°C. It is printed by a doctor blade at a speed of 50~150 mm / s and a pressure of 0.2~0.5 MPa, with a single wet film thickness of 5~25 μm. Areas with a compensation amount greater than 25 μm are printed by multiple overprints.

[0026] Optionally, the coated semi-cured sheet is pre-baked at 80~120℃ for 5~20 minutes to allow the resin layer to reach a semi-cured state; after pre-fixing by hot riveting, it is pressed in a laminator with a vacuum degree ≤2mbar according to the gradient temperature and segmented pressure curve of M6 / M7 / M8 grade high-speed materials.

[0027] The beneficial effects of this application are:

[0028] (1) Compared with the traditional process, impedance judgment is performed only after the final pressing is completed and defective products are directly scrapped. This solution completes the acquisition of impedance and geometric parameters of each measuring point after the first pressing. The area compensation amount of the prepreg is obtained directly through inverse kinematics. The compensation adjustment is completed before the final pressing, changing the post-screening to pre-compensation. There is no need to wait for the final pressing to judge the yield. The scrap rate is reduced from the source of the process. The impedance yield rate of the traditional process can be increased from 85% to more than 93%.

[0029] (2) This application obtains the true structural parameters without damaging the electrical function and mechanical integrity of the motherboard by attaching a sampling component to the folded edge of the impedance test strip, thus solving the pain points of traditional slice sampling, which is destructive and cannot be multi-point. The high-density impedance test strip arrangement characteristics of the small board connector provide a feasible space for this multi-point non-destructive sampling; the resin coating control of point-to-point or partition surface is achieved by screen printing on the prepreg, and the compensation spatial resolution depends on the screen pattern design, which can accurately match the complex changes of the inner layer pattern.

[0030] (3) Since screen printing, pre-baking, and lamination are all standard processes and equipment in PCB factories, there is no need to introduce expensive new processes such as laser ablation and chemical vapor deposition. Only a high-precision screen printing station and a matching VNA high-speed measurement system are needed. The existing process personnel's skills can be quickly adapted; the impedance, dielectric thickness, and compensation data obtained from each production cycle can be continuously accumulated, and the accuracy of the back-inference model and the flow coefficient can be continuously optimized through machine learning or statistical regression methods to form a knowledge base for the company's own high-speed connector PP compensation process; the resin system of M6 / M7 / M8 materials has good compatibility with the additional coating resin, and the compensation amount of this application is in the micron level, which will not damage the original dielectric loss (Df) characteristics. The pre-baking semi-curing process ensures the synchronous rheology and cross-linking of the compensation resin and the substrate PP sheet, avoiding interface delamination. Detailed Implementation

[0031] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the embodiments of this application. Obviously, the embodiments described in this application are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0032] A method for impedance compensation of high-speed printed circuit boards includes the following steps:

[0033] Fabrication of inner core board: Impedance test strips with multiple impedance measurement point areas are formed on the inner core board, and sampling elements are formed at corresponding positions of each impedance test strip. The sampling elements are electrically isolated from the electrical functional area of ​​the motherboard.

[0034] Impedance measurement: After the inner core board and the prepreg are first pressed together, the measured characteristic impedance values ​​and corresponding plane coordinates of each impedance test strip are obtained to obtain the impedance distribution dataset.

[0035] Parameter correlation: After separating the sample, the dielectric layer thickness, copper thickness and line width of the corresponding area of ​​the sample are measured. The measured geometric parameters are correlated with the corresponding data in the impedance distribution dataset to construct a multivariate parameter vector for each measurement point.

[0036] Compensation calculation: Based on the multivariate parameter vector and combined with the preset impedance analysis model, the measured copper thickness and line width are used as fixed parameters, and the preset target impedance is used as input. The ideal dielectric layer thickness corresponding to each measurement point is solved in reverse, and the dielectric thickness compensation amount of each measurement point is calculated. The corresponding plane coordinates are then associated to generate a resin coating compensation diagram.

[0037] Differentiated coating: Prepare a coating screen with differentiated openings, and based on the resin coating compensation map, transfer the resin coating on the screen to the corresponding area of ​​the prepreg to achieve differentiated resin coating;

[0038] Pre-baking semi-curing: The printed semi-cured sheet is placed in a pre-baking device for baking, so that the coated resin layer reaches a semi-cured state.

[0039] Lamination, thermal riveting, and pressing: The pre-baked compensated prepreg is laminated with the inner core board and copper foil according to the designed lamination sequence. Thermal riveting is used to pre-fix the laminated structure. Then, the laminated structure is placed in a vacuum laminator for pressing to obtain a printed circuit board with uniform impedance. In traditional PCB manufacturing, once the lamination process parameters such as temperature, pressure, time, and PP sheet selection are set, uniform conditions are applied to the entire board surface. However, the non-uniformity of the inner layer pattern inevitably leads to regional differences in dielectric thickness, which ultimately manifests as uneven impedance distribution.

[0040] This application breaks this passive situation. Before the prepreg enters the lamination process, based on the measured impedance distribution data of the previous batch or the same batch of samples, a different amount of resin coating is applied to different areas of the prepreg in advance. This ensures that the actual dielectric thickness of each area after lamination just offsets the fluctuations caused by the differences in the inner layer pattern, thereby achieving high uniformity of the board surface impedance.

[0041] Compared to the traditional process where impedance judgment is only performed after final lamination and defective products are directly scrapped, this solution completes the acquisition of impedance and geometric parameters at each measuring point after the first lamination. The regional compensation amount of the prepreg is directly obtained through inverse kinematics, and the compensation adjustment is completed before final lamination. This transforms post-screening into pre-compensation, eliminating the need to wait for final lamination to determine the yield. This reduces scrap from the source of the process and can increase the impedance yield of the traditional process from 85% to over 93%.

[0042] This application obtains true structural parameters without damaging the electrical function and mechanical integrity of the motherboard by attaching a sampling component to the folded edge of the impedance test strip. This solves the pain points of traditional slice sampling, which is destructive and unable to perform multi-point sampling. The high-density impedance test strip arrangement characteristics of small board connectors provide a feasible space for this multi-point non-destructive sampling. By screen printing on the prepreg, point-to-point or partitioned resin coating can be controlled, and the spatial resolution compensation depends on the screen pattern design, which can accurately match the complex changes in the inner layer pattern.

[0043] Since screen printing, pre-baking, and lamination are all standard processes and equipment in PCB factories, there is no need to introduce expensive new processes such as laser ablation or chemical vapor deposition. Only a high-precision screen printing station and a matching VNA high-speed measurement system are required. Existing process personnel can quickly adapt their skills; the impedance, dielectric thickness, and compensation data obtained from each production cycle can be continuously accumulated, and the accuracy of the back-calculation model and the flow coefficient can be continuously optimized through machine learning or statistical regression methods, forming a company-specific knowledge base for high-speed connector PP compensation processes; the resin system of M6 / M7 / M8 materials has good compatibility with additional resin coatings, and the compensation amount in this application is at the micron level, which will not damage the original dielectric loss (Df) characteristics. The pre-baking semi-curing process ensures synchronous rheological and cross-linking between the compensation resin and the substrate PP sheet, avoiding interface delamination.

[0044] The sampling element is formed on the folded extension of the impedance test strip and is connected to the impedance test strip through a micro-connection bridge. Each impedance measurement point area covers a high residual copper ratio area, a low residual copper ratio area, and a transition area. Typical areas include the board edge, center, high-speed signal area, connector pin area, BGA area, etc. The high residual copper ratio area includes the BGA package projection area and the connector pin area.

[0045] The impedance measurement employs a 10-40 GHz vector network analyzer, acquiring the measured characteristic impedance value through time-domain reflection or frequency-domain-time conversion, and recording the planar coordinates using a precision positioning system of the test fixture. A 20 GHz vector network analyzer is preferred.

[0046] Optionally, each sample is circumferentially cut and separated along a preset circumferential contour. During the separation process, the motherboard body remains intact and can continue to be transferred. Cross-sectional samples are prepared and microscopic measurements are performed on each separated sample to obtain the dielectric layer thickness Hi, copper thickness Ti, and test line width Wi of the corresponding area of ​​each sample. For the measurement points of the differential structure, the line spacing Si of the corresponding test line segment is also measured.

[0047] The circumferential separation is achieved using a precision milling cutter or laser cutting method. The cross-sectional sample preparation and microscopic measurement specifically include: slicing the sample and measuring the dielectric layer thickness H, copper thickness T, test line width W, and line spacing S using a metallographic microscope or scanning electron microscope. The micro-connector bridge is severed during circumferential separation without damaging the electrical function or structural integrity of the motherboard.

[0048] The impedance analytical model is a two-dimensional boundary element field solver model or a two-dimensional / three-dimensional quasi-static electromagnetic field solver model. The dielectric constant εr in the model is the nominal value or the measured effective dielectric constant of the prepreg material batch. The measured effective dielectric constant can be obtained by substituting the measured impedance value Zi of the sample and the corresponding geometric parameters Hi, Ti, and Wi into the impedance analytical model, thus eliminating the inverse solution error caused by dielectric constant fluctuations between prepreg batches and further improving compensation accuracy.

[0049] The two-dimensional boundary element field solver model referred to in this application can typically be implemented using Polar Instruments Si9000 software; the two-dimensional / three-dimensional quasi-static electromagnetic field solver model can typically be implemented using Ansys Q2D (two-dimensional quasi-static finite element) or Ansys Q3D (three-dimensional quasi-static finite element).

[0050] The calculation of the medium thickness compensation also introduces the flow compensation coefficient α_flow of the prepreg, with the value ranging from 1.1 to 1.3. The specific value is positively correlated with the prepreg model and pressing parameters.

[0051] The coated screen is a wire mesh screen, made of 200~500 mesh high-tensile stainless steel wire mesh or composite wire mesh. The proportion of the opening area or the emulsion thickness in different regions is positively correlated with the compensation amount of the medium thickness at the corresponding measuring point.

[0052] The resin coating is an epoxy resin or polyphenylene ether-based resin coating compatible with the prepreg resin system. Its viscosity at 25°C is 30-80 Pa·s. It is printed using a doctor blade at a speed of 50-150 mm / s and a pressure of 0.2-0.5 MPa, with a single wet film thickness of 5-25 μm. Areas with a compensation amount greater than 25 μm require multiple overprints. The coated prepreg is pre-baked at 80-120°C for 5-20 minutes to achieve a semi-cured resin layer. After pre-fixing with thermal riveting, it is laminated in a laminator with a vacuum degree ≤2 mbar according to the gradient temperature and segmented pressure curve of M6 / M7 / M8 grade high-speed materials.

[0053] Example 1: A method for impedance compensation of high-speed printed circuit boards, comprising the following steps:

[0054] S1 Inner Layer Core Board Fabrication: Impedance test strips are formed in each impedance measurement point area of ​​the inner layer core board, and sampling components are formed at the folded edges of the impedance test strips. The sampling components are connected to the impedance test strips through micro-connection bridges. The sampling components are electrically isolated from the electrical functional areas of the motherboard. Each sampling component is arranged one-to-one in each impedance measurement point area. The impedance measurement point areas cover high residual copper ratio areas, low residual copper ratio areas, and transition areas; typical areas include the board edge, center, high-speed signal area, connector pin area, BGA area, etc.

[0055] S2 Impedance Value Acquisition: After the inner core board and prepreg are initially laminated, a 20GHz vector network analyzer is used to perform full-scale measurement of the impedance test strips in each impedance measurement area. The characteristic impedance of each test strip is obtained through the time-domain reflection function or frequency-domain-time conversion function of the vector network analyzer. The coordinate values ​​(Xi, Yi) of each impedance test strip in the planar coordinate system are recorded through the precision positioning system of the test fixture, resulting in a full-board impedance distribution dataset. This dataset includes the characteristic impedance measurement value Zi and its coordinate values ​​(Xi, Yi) corresponding to each impedance test strip. By performing full-scale measurement of the impedance test strips in all areas, high-density board surface impedance distribution data can be obtained, providing sufficient data support for subsequent inverse dielectric thickness analysis. Unlike the traditional TDR single-point probe moving scan method, the high-frequency accuracy and multi-port or switch matrix expansion capability of the VNA allow for one-time or rapid polling to complete the measurement of all impedance test strips on the board, significantly improving efficiency and data density. Because the layout size of AI server connector PCBs is relatively small, multiple impedance test strips can be densely distributed on each board. These impedance test strips cover different areas of the board, such as the edge, center, high-speed signal area, connector pin area, BGA area, etc.

[0056] S3 Sampling Analysis: After completing the impedance measurement, each sampling component is separated by circumferential cutting along the preset circumferential cutting contour. That is, a precision milling cutter or laser is used to separate each sampling component from the folded edge of the impedance test strip along the preset circumferential cutting path. During the separation process, the main board body remains intact and can continue to be transferred.

[0057] Cross-sectional samples and microscopic measurements were performed on each separated sample. The dielectric layer thickness Hi, copper thickness Ti, test line width Wi, and line spacing Si suitable for differential structures in the corresponding regions of each sample were measured using a metallographic microscope or SEM. The geometric parameters of each sample were correlated with the corresponding measured characteristic impedance values ​​Zi and coordinates (Xi,Yi) to construct a multivariate parameter vector {Zi,Hi,Ti,Wi,Si,Xi,Yi} for each measurement point.

[0058] S4 Reverse Compensation Calculation: Based on the constructed multivariate parameter vectors of each measurement point, combined with the preset stripline or microstrip line impedance analytical model, the measured copper thickness Ti, linewidth Wi, optional line spacing Si, and known dielectric constant εr of the corresponding measurement point are used as fixed parameters. The preset target impedance value is used as input to solve the ideal dielectric layer thickness H0,i corresponding to each measurement point in reverse. The difference between the ideal dielectric layer thickness H0,i and the measured dielectric layer thickness Hi at each measurement point is calculated to obtain the initial dielectric thickness compensation amount ΔHi. Based on the compression flow characteristics of the prepreg, ΔHi is corrected to obtain the final dielectric thickness compensation amount ΔHcompensated,i. The final dielectric thickness compensation amount ΔHcompensated,i of each measurement point is associated with the corresponding plane coordinates (Xi,Yi) to generate a prepreg partitioned resin coating compensation map.

[0059] Specifically, for the stripline or microstrip structure commonly found in high-speed connector PCBs, the analytical or simulation model of its characteristic impedance can be expressed as: Z = f(H, T, W, S, εr), where εr is the dielectric constant (determined by the material batch and considered known; or calculated by substituting the measured impedance value into the model).

[0060] On the same board, the copper thickness T, line width W, and line spacing S have already been formed through electroplating and etching processes, and their distribution within this batch can be considered predetermined (i.e., the measured spatial distribution of T, W, and S remains unchanged). If the measured impedance Z in a certain region deviates from the target impedance Z0, then in the model, with Z0 as input and T / W / S / εr fixed as known conditions, the required ideal dielectric layer thickness H0 for that region is calculated in reverse: H0 = f^(-1)(Z0 | T, W, S, εr)

[0061] Furthermore, the difference between the ideal dielectric thickness H0 and the measured dielectric thickness H in this region, ΔH = H0 - H, is used as the resin thickness compensation amount for this region on the prepreg. If ΔH > 0, it indicates that the resin thickness in this region needs to be increased; if ΔH < 0, it indicates that the resin thickness in this region needs to be reduced (this can be achieved by using a thinner base PP sheet or reducing the amount of local coating).

[0062] Because resin flows during the pressing process of the prepreg, the compensation amount needs to be corrected based on flow simulation or empirical flow coefficient:

[0063] ΔH_compensated = ΔH × α_flow

[0064] Where α_flow is the flow compensation coefficient (usually 1.1~1.3, depending on the PP type and pressing parameters).

[0065] By correlating the ΔH_compensated values ​​of each region of the entire board with their spatial coordinates, a prepreg partition resin coating compensation map is generated.

[0066] S5 screen printing pattern production: The prepreg is cut to size to match the lamination requirements; positioning holes are machined on the cut prepreg, i.e., mechanical drilling; positioning holes such as riveting holes and pin holes are drilled to match the inner core board and lamination fixture.

[0067] Based on the generated partitioned resin coating compensation map, a screen printing stencil is prepared: the compensation map is converted into a film graphic for screen printing, and a screen substrate such as high-tensile stainless steel wire mesh (200~500 mesh) or composite wire mesh is used to make the stencil in combination with photosensitive emulsion. Different areas of the screen printing stencil correspond to different positions of the prepreg and have differentiated opening area (opening ratio) or emulsion thickness to achieve differentiated resin coating amount in the corresponding areas in subsequent printing processes.

[0068] S6 graphic screen printing resin coating: The prepared screen printing plate is installed at the printing station of the screen printing machine, the prepreg to be printed is fixed on the printing platform, the prepreg and the screen printing plate are precisely aligned through the positioning structure, and the positional accuracy is ensured to be within ±0.05mm through vacuum adsorption or positioning pin.

[0069] A resin coating compatible with the prepreg resin system is selected, and screen-printed using a squeegee according to preset process parameters. The resin coating is transferred to the corresponding areas of the prepreg according to the differentiated openings of the screen pattern, achieving differentiated resin coating amounts in each area. Specifically, an epoxy resin or polyphenylene ether-based resin coating (depending on the specific high-speed material system) compatible with the prepreg substrate resin system is selected, and the coating viscosity (typically 30~80 Pa·s, 25℃) and thixotropy are controlled. Screen printing is performed using a squeegee at a constant speed (e.g., 50~150 mm / s) and pressure (e.g., 0.2~0.5 MPa), precisely transferring the resin coating to the designated areas on the surface of the prepreg according to the openings of the screen pattern.

[0070] The wet film thickness of a single print can be adjusted by the screen mesh count, emulsion thickness, and squeegee parameters, typically within the range of 5–25 μm. For areas with a large compensation amount (>25 μm), multiple overprints can be used to accumulate the film layer by layer. After each print, the need for surface drying depends on the rheological properties of the coating.

[0071] S7 Pre-baked Semi-cured: The printed semi-cured sheet is placed in a hot air circulating oven or infrared pre-baking equipment for baking at a temperature of 80℃~120℃ (time 5~20 minutes, depending on the resin coating formula) to make the coated resin layer reach a semi-cured state; after pre-baking, the resin layer has lost its fluidity but still has the ability to re-level and cross-link in subsequent hot pressing, which not only prevents resin migration during transportation and stacking, but also ensures wetting and bonding with the core board surface during pressing.

[0072] S8 Lamination, Hot Riveting, and Pressing: The pre-baked compensated prepreg, inner core board, and copper foil are laminated according to the designed lamination sequence. Hot riveting is used to pre-fix the laminated structure, which is then pressed in a vacuum laminator to obtain a printed circuit board with uniform impedance. Pressing is performed according to the standard pressing curves (gradient temperature rise, segmented pressurization) for M6 / M7 / M8 materials. Because different areas of the prepreg have pre-set differentiated resin amounts, after pressing, areas with initially thinner dielectric thickness (high residual copper areas) will thicken due to additional resin supplementation, while areas with initially thicker dielectric thickness (low residual copper areas) will have their dielectric thickness reduced and matched by the reduction in the base PP sheet. This results in the final actual dielectric thickness of each area approaching H0, thus significantly improving impedance uniformity.

[0073] Because the prepreg already has a zoned resin thickness compensation layer, special care must be taken when stacking the sheets:

[0074] Ensure the prepreg compensation surface faces the correct core board surface;

[0075] High-precision alignment is achieved through positioning holes to prevent relative misalignment between the screen-printed pattern and the inner layer pattern of the core board;

[0076] Hot riveting is used to pre-fix the four corners or edges of the laminated structure to prevent interlayer slippage.

[0077] The process parameters used in the compensation method are shown in Table 1:

[0078] Table 1: Summary of Process Parameters

[0079]

[0080] Practical applications:

[0081] 1. Application Scenario: A backplane connector PCB for an AI server, using M7 grade high-speed material. The layer stack-up structure is as follows: L1-L2 are signal-to-ground microstrip lines, and L3-L4 are inner striplines (the layers containing the high-speed differential pairs of the connector). The customer requires a differential impedance of 100Ω ±7%. The board size is 26mm × 139mm, with 36 boards shipped per board. Each board is designed with 10 connector units, and each board comes with one impedance test strip (Coupon), totaling 36 strips. The 36 impedance test strips cover different locations such as the edges, center, connector pad area, and finger insertion / removal area.

[0082] 2. Implementation process

[0083] (1) Full-page measurement

[0084] A 20GHz VNA with a multiplexer matrix was used to perform TDR impedance testing on the differential pairs of 36 impedance test strips. The measured impedance distribution is shown in Table 2 below:

[0085] Table 2: Impedance Distribution Diagram

[0086]

[0087] (2) Non-destructive circumferential sampling and sectioning

[0088] The coupon folded sample modules at the corresponding positions of CP-01, CP-05, CP-12, CP-18, and CP-23 were circumferentially cut off and metallographic sections were prepared. The interlayer dielectric thickness (H), copper thickness (T), and linewidth (W) of L3-L4 were measured as shown in Table 3 below:

[0089] Table 3: Test Results

[0090]

[0091] (3) Impedance back-calculation and compensation calculation

[0092] Based on the stripline impedance model (Simplified IPC-2141 formula combined with HFSS verification), under the condition of fixed T, W, εr=3.5 (typical value of M7), the ideal dielectric thickness H0 corresponding to the target impedance of 100Ω is estimated to be approximately 102μm.

[0093] The compensation amount for each region (ΔH = H0 - H, without multiplication of the adhesive coefficient) is calculated, as shown in Table 4:

[0094] Table 4: Compensation Amounts for Each Region

[0095]

[0096] The flow coefficient α_flow was calibrated to 1.2 by DOE, and the corrected compensation amount is shown in Table 5 below:

[0097] Table 5: Corrected Compensation Amount

[0098]

[0099] Spatial interpolation is used to generate a resin coating compensation map for the prepreg in an 80mm x 60mm area across the entire board.

[0100] (4) Screen printing and lamination

[0101] Based on the compensation diagram, the screen printing stencil is made as follows: a thicker emulsion layer and a larger aperture ratio are designed for the corresponding areas of CP-01 / CP-23, and the wet film transfer is about 45μm; a medium aperture ratio is designed for the corresponding areas of CP-05 / CP-18, and the wet film transfer is about 20μm; no additional resin is printed for the corresponding area of ​​CP-12, and the base PP sheet is selected as a model that is 12μm thinner than the conventional one.

[0102] After printing, pre-bake (100℃ / 12min), stack, heat-rivet, and press according to the M7 standard pressing curve. Measure the impedance again after pressing, as shown in Table 6 below:

[0103] Table 6: Impedance Improvement

[0104] .

[0105] It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the scope of protection of this application. Therefore, the scope of protection of this patent application shall be determined by the appended claims.

Claims

1. A method for impedance compensation of high-speed printed circuit boards, characterized in that: Includes the following steps: Fabrication of inner core board: Impedance test strips with multiple impedance measurement point areas are formed on the inner core board, and sampling elements are formed at corresponding positions of each impedance test strip. The sampling elements are electrically isolated from the electrical functional area of ​​the motherboard. Impedance measurement: After the inner core board and the prepreg are first pressed together, the measured characteristic impedance values ​​and corresponding plane coordinates of each impedance test strip are obtained to obtain the impedance distribution dataset. Parameter correlation: After separating the sample, the dielectric layer thickness, copper thickness and line width of the corresponding area of ​​the sample are measured. The measured geometric parameters are correlated with the corresponding data in the impedance distribution dataset to construct a multivariate parameter vector for each measurement point. Compensation calculation: Based on the multivariate parameter vector and combined with the preset impedance analysis model, the measured copper thickness and line width are used as fixed parameters, and the preset target impedance is used as input. The ideal dielectric layer thickness corresponding to each measurement point is solved in reverse, and the dielectric thickness compensation amount of each measurement point is calculated. The corresponding plane coordinates are then associated to generate a resin coating compensation diagram. Differentiated coating: Prepare a coating screen with differentiated openings, and based on the resin coating compensation map, transfer the resin coating on the screen to the corresponding area of ​​the prepreg to achieve differentiated resin coating; Pre-baking semi-curing: The printed semi-cured sheet is placed in a pre-baking device for baking, so that the coated resin layer reaches a semi-cured state. Lamination, thermal riveting and pressing: The pre-baked pre-cured sheet with compensation is laminated with the inner core board and copper foil according to the designed lamination sequence, and the laminated structure is pre-fixed by thermal riveting. Then the laminated structure is placed in a vacuum laminator for pressing to obtain a printed circuit board with uniform impedance.

2. The high-speed printed circuit board impedance compensation method according to claim 1, characterized in that: The sampling element is formed on the folded extension of the impedance test strip and is connected to the impedance test strip through a micro-connection bridge. Each impedance measurement point area covers a high residual copper ratio area, a low residual copper ratio area, and a transition area. The high residual copper ratio area includes the BGA package projection area and the connector pin area.

3. The high-speed printed circuit board impedance compensation method according to claim 1, characterized in that: The impedance measurement is performed using a 10~40GHz vector network analyzer. The measured value of the characteristic impedance is obtained through the time domain reflection function or the frequency domain-time domain conversion function, and the plane coordinates are recorded through the precision positioning system of the test fixture.

4. The high-speed printed circuit board impedance compensation method according to claim 1, characterized in that: The sampled parts are separated by circumferential cutting along the preset circumferential contour. During the separation process, the motherboard body remains intact and can continue to be transferred. The separated sampled parts are cross-sectionally sampled and microscopically measured to obtain the dielectric layer thickness Hi, copper thickness Ti, and test line width Wi of the corresponding area of ​​each sampled part. For the measurement points of the differential structure, the line spacing Si of the corresponding test line segment is also measured.

5. The high-speed printed circuit board impedance compensation method according to claim 4, characterized in that: The circumferential separation is achieved using a precision milling cutter or laser cutting method. The cross-sectional sample preparation and microscopic measurement specifically include: preparing the sample by slicing, and measuring the dielectric layer thickness H, copper thickness T, test line width W, and line spacing S using a metallographic microscope or scanning electron microscope.

6. The high-speed printed circuit board impedance compensation method according to claim 1, characterized in that: The impedance analysis model is a two-dimensional boundary element field solver model or a two-dimensional / three-dimensional quasi-static electromagnetic field solver model, wherein the dielectric constant εr in the model is the nominal value of the batch of prepreg material or the measured effective dielectric constant.

7. The high-speed printed circuit board impedance compensation method according to claim 1, characterized in that: The calculation of the medium thickness compensation also introduces the flow compensation coefficient α_flow of the prepreg, with the value ranging from 1.1 to 1.

3. The specific value is positively correlated with the prepreg model and pressing parameters.

8. The high-speed printed circuit board impedance compensation method according to claim 1, characterized in that: The coated screen is a wire mesh screen, made of 200~500 mesh high-tensile stainless steel wire mesh or composite wire mesh. The proportion of the opening area or the emulsion thickness in different regions is positively correlated with the compensation amount of the medium thickness at the corresponding measuring point.

9. The high-speed printed circuit board impedance compensation method according to claim 1, characterized in that: The resin coating is an epoxy resin or polyphenylene ether-based resin coating compatible with the prepreg resin system. The viscosity at 25°C is 30~80 Pa·s. It is printed by a doctor blade at a speed of 50~150 mm / s and a pressure of 0.2~0.5 MPa. The thickness of a single wet film is 5~25 μm. Areas with a compensation amount greater than 25 μm are printed by multiple overprints.

10. The high-speed printed circuit board impedance compensation method according to claim 1, characterized in that: The coated semi-cured sheet is pre-baked at 80~120℃ for 5~20 minutes to allow the resin layer to reach a semi-cured state; after pre-fixing by hot riveting, it is pressed in a laminator with a vacuum degree ≤2mbar according to the gradient temperature and segmented pressure curve of M6 / M7 / M8 grade high-speed materials.

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