A method of manufacturing a printed circuit board cavity and a printed circuit board

Abstract

The application provides a printed circuit board cavity manufacturing method and a printed circuit board, and comprises the following steps: providing an inner layer substrate, manufacturing an inner layer circuit pattern on the surface of the inner layer substrate; sequentially placing an insulating medium layer and an outer layer conductive layer on the inner layer substrate, and forming a multi-layer laminated plate through lamination; manufacturing an outer layer circuit pattern on the multi-layer laminated plate, and etching and removing the outer layer conductive layer outside a predetermined cavity processing area during the manufacturing of the outer layer circuit pattern; and scanning and irradiating the predetermined cavity processing area by using an ultrashort pulse laser, so that the ultrashort pulse laser penetrates the outer layer conductive layer and removes at least part of the insulating medium layer below the outer layer conductive layer until the surface of the inner layer circuit pattern is exposed, thereby forming a cavity structure. The problems of long process, additional protective layer or functional layer, pre-chemical etching to remove the surface copper, limited alignment accuracy between processes, laser thermal effect damage to the inner layer circuit, and limited material adaptability are solved.

Description

Technical Field

[0001] This invention relates to the field of laser processing technology, specifically to a method for manufacturing a printed circuit board cavity and a printed circuit board. Background Technology

[0002] Printed Circuit Boards (PCBs) are the fundamental carriers for the electrical interconnection and mechanical support of electronic components. Currently, electronic products are trending towards thinner, lighter, smaller, and more highly integrated designs. This necessitates the fabrication of cavity structures within or on the surface of PCBs for purposes such as embedding chips, constructing antenna resonant cavities, forming acoustic cavities, or waveguide structures. In many applications, it is required to expose the inner layer circuitry at the bottom of the cavity to enable direct electrical connection between the chip and the inner layer circuitry, signal testing, or functional debugging.

[0003] Currently, existing technologies for exposing inner layer circuitry at the bottom of the cavity mainly include the following types: (1) First, chemically etch to remove copper, then laser ablate the dielectric. First, the circuit pattern is made on the inner layer substrate by photolithography and etching process, and then laminated to form a multilayer board structure. Then, an etching protective layer is formed in the cavity area to be processed by pattern transfer process. The surface conductive layer of this area is completely removed by chemical etching solution to expose the unprocessed window of the insulating dielectric layer. The insulating dielectric layer is ablated layer by layer by carbon dioxide laser or nanosecond ultraviolet laser with the same long pulse laser until the bottom inner layer circuit is exposed. Finally, the residual adhesive and slag are removed by post-processing processes such as plasma cleaning and chemical cleaning.

[0004] (2) Pre-installed functional protective or barrier layers assist laser processing. Some technical solutions protect the inner circuitry at the bottom of the cavity by gold plating before lamination, utilizing the laser-resistant properties of the precious metal layer as a laser barrier layer to protect the bottom circuitry from laser energy damage. Other solutions employ a layer-by-layer stacking method, first creating raised pads on the substrate surface, then sequentially stacking a peelable second insulating layer and a copper foil barrier layer, and finally stacking a third insulating layer and an outer copper foil layer on top of the copper foil barrier layer. A cavity is formed by laser drilling, with the copper foil barrier layer used to prevent laser damage to the raised pads below. Some solutions also use a release layer to assist subsequent separation.

[0005] (3) First, leave the inner copper layer, then remove it by etching. By pre-reserving a copper layer at the bottom of the tank, the copper layer is ablated by laser, and then the reserved copper layer is removed by wet etching to form the tank structure.

[0006] (4) Lid-off process. Some solutions use the lid-off method, first covering the inner layer circuit area to be exposed with a peelable protective layer (such as polyimide film), then pressing it together and cutting out the cavity outline with a laser, and then physically removing the cover to expose the inner layer circuit underneath.

[0007] However, current existing technologies have significant technical drawbacks in engineering practice. Specifically, firstly, the engineering chain is lengthy and manufacturing efficiency is low. Existing solutions generally involve multiple independent process modules, such as inner layer circuit fabrication, lamination, photolithography patterning, wet etching, laser ablation, and plasma cleaning. Each process requires multiple board turnovers, repositioning, and reference conversions, resulting in a long overall production cycle time, which is difficult to meet the efficiency requirements of large-scale mass production. Secondly, additional functional layers are required, leading to a significant increase in material costs and process complexity. Existing solutions use precious metal protection for inner layer circuits, or set up multi-layer heterogeneous structures, or use additional processes such as cover film windowing. These additional functional layers not only increase the bill of materials (BOM) cost but also introduce new alignment tolerances and interface reliability risks, and increase the complexity of process control. Thirdly, chemical etching is required to remove the surface copper layer beforehand, leading to environmental compliance pressures and loss of pattern accuracy. Limited by the high reflectivity and low absorptivity of long-pulse lasers on copper layers, existing solutions cannot directly penetrate the copper layer to process the underlying insulating medium. Chemical etching is required to remove the surface copper in the cavity area beforehand, adding wet processing steps such as pattern transfer, chemical etching, and film removal. This necessitates the use of various chemical solutions, including etching and film removal solutions, resulting in wastewater treatment and discharge burdens, increasing environmental costs. Furthermore, the isotropic etching effect during chemical etching can lead to lateral etching, causing dimensional deviations and affecting processing accuracy. Fourthly, the alignment accuracy between multiple processes is limited. Chemical etching for windowing and laser drilling are performed by different equipment, requiring a conversion of positioning references between the two processes, which easily leads to cumulative alignment errors. Some solutions require an additional alignment copper layer on the core layer for positioning assistance, increasing alignment complexity and affecting cavity position accuracy and dimensional consistency, especially in fine-pitch, high-density products. Fifthly, the laser thermal effect affects the quality of the cavity and inner layer circuitry. The carbon dioxide laser and nanosecond laser thermal processing methods generate a significant heat-affected zone (Heat) during processing. The Affected Zone (HAZ) leads to defects such as molten material accumulation on the sidewalls, increased surface roughness, dielectric layer delamination, and even resin pyrolysis and carbonization, affecting the conductivity reliability of the inner layer circuits and subsequent soldering performance. Furthermore, improper laser energy control poses a risk of over-ablation damage to the inner layer circuits. Sixthly, material adaptability is limited, and some solutions have specific requirements for the material system. For example, in the layer-by-layer stacking solution, the second insulating layer needs to be made of a special material that can be etched by the sandblasting process (such as resin without glass fiber reinforcement), which severely limits the range of substrate material selection.

[0008] Therefore, there is an urgent need for a printed circuit board structure and its manufacturing method that can directly achieve cavity forming and expose inner layer circuitry through one-step ultrashort pulse laser processing. Summary of the Invention

[0009] The present invention provides a method for manufacturing a cavity of a printed circuit board and a printed circuit board, which at least solves the problems of lengthy processes, additional protective or functional layers, pre-chemical etching to remove surface copper, limited alignment accuracy between processes, damage to inner circuitry by laser thermal effects, and limited material adaptability.

[0010] According to one aspect of the present invention, a method for manufacturing a printed circuit board cavity is provided, comprising: An inner layer substrate is provided, and an inner layer circuit pattern is formed on the surface of the inner layer substrate. An insulating dielectric layer and an outer conductive layer are sequentially placed on the inner substrate and then laminated to form a multilayer laminate; wherein the insulating dielectric layer covers the inner circuit pattern and the outer conductive layer covers the insulating dielectric layer. An outer layer circuit pattern is formed on the multilayer laminate, and during the process of forming the outer layer circuit pattern, the outer conductive layer outside the predetermined cavity processing area is etched away. The predetermined cavity processing area is scanned and irradiated using an ultrashort pulse laser. The ultrashort pulse laser penetrates the outer conductive layer and removes at least a portion of the insulating dielectric layer below the outer conductive layer until the surface of the inner circuit pattern is exposed, thus forming a cavity structure.

[0011] As an optional approach, an inner layer circuit pattern is formed on the surface of the inner layer substrate, including: A first photoresist layer is applied to the surface of the inner substrate. The first photoresist layer is exposed and developed to form a first resist mask with a circuit pattern. Using the first resist mask as a protective layer, the surface of the inner substrate is etched; Remove the first resist mask to obtain the inner layer circuit pattern.

[0012] As an optional approach, an outer layer circuit pattern is fabricated on the multilayer laminate, and during the fabrication of the outer layer circuit pattern, the outer conductive layer outside the predetermined cavity processing area is etched away, including: A second photoresist layer is applied to the surface of the outer conductive layer of the multilayer laminate. The second photoresist layer is exposed and developed to form a second photoresist mask with a circuit pattern; wherein the second photoresist mask covers the outer conductive layer corresponding to the predetermined cavity processing area; Using the second resist mask as a protective layer, the uncovered outer conductive layer is etched. Remove the second resist mask to form an outer circuit pattern, so that the outer conductive layer corresponding to the predetermined cavity processing area remains intact.

[0013] As an optional approach, during the scanning irradiation process of the ultrashort pulse laser, the outer conductive layer corresponding to the predetermined cavity processing area is used as the starting surface for the ultrashort pulse laser ablation.

[0014] As an alternative, during the short-pulse laser processing, the ultrashort-pulse laser stops ablation when it reaches the surface of the inner layer circuit pattern.

[0015] As an alternative, the pulse width of the ultrashort pulse laser is less than 20 ps.

[0016] As an optional option, the wavelength of the ultrashort pulse laser is in the ultraviolet band or the green light band.

[0017] As an alternative approach, during the ultrashort pulse laser scanning irradiation process, the energy parameters and number of scans of the ultrashort pulse laser are controlled so that the ultrashort pulse laser removes the exposed inner layer circuit pattern surface at a preset removal depth.

[0018] As an optional approach, the preset removal depth is 1~2μm.

[0019] As an alternative, the insulating dielectric layer comprises FR4, polyimide, or liquid crystal polymer.

[0020] As an alternative, the outer conductive layer is a copper layer.

[0021] According to another aspect of the present invention, a printed circuit board is also provided, manufactured using the printed circuit board cavity manufacturing method described above, comprising: Inner circuit layer; wherein, the surface of the inner circuit layer is formed with an inner circuit pattern; An insulating dielectric layer covers the inner circuit layer. An outer conductive layer covers the insulating dielectric layer; an outer circuit pattern is formed on the surface of the outer conductive layer. A cavity structure extending through the outer conductive layer and at least a portion of the insulating dielectric layer, with at least a portion of the inner layer circuit pattern exposed at the bottom of the cavity structure.

[0022] As an optional solution, the angle between the sidewall and the bottom surface of the cavity structure is 88°~92°.

[0023] The beneficial effects of this invention are as follows: This invention, in the process of fabricating the outer layer circuit pattern, only etches and removes the outer conductive layer outside the predetermined cavity processing area, keeping the outer conductive layer in the predetermined cavity processing area intact. An ultrashort pulse laser directly penetrates this outer conductive layer and the underlying insulating dielectric layer until the surface of the inner layer circuit pattern is exposed, forming a cavity structure. This eliminates multiple processes such as pre-chemical etching to remove copper, pattern transfer, film removal, and subsequent cleaning, shortening the production cycle and avoiding the use of chemical solutions and loss of lateral etching accuracy. No additional gold-plated protective layer, barrier layer, or release layer is required, reducing material costs and process complexity. The fabrication of the outer layer circuit pattern and laser processing are performed continuously on the same laminating plate, eliminating alignment errors between different devices. Simultaneously, the cold processing characteristics of the ultrashort pulse laser minimize the heat-affected zone, ensuring that the exposed inner layer circuit surface is free from carbonization, oxidation, or molten spatter. Furthermore, this method does not rely on the specific physical properties of the dielectric layer material and is applicable to various material systems, thus effectively solving the problems of lengthy processes, high costs, poor alignment accuracy, severe thermal damage, and limited material adaptability in existing technologies. Attached Figure Description

[0024] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of the present invention, and those skilled in the art can obtain other embodiments based on these drawings without creative effort.

[0025] Figure 1 This is a flowchart of a printed circuit board cavity manufacturing method according to an embodiment of the present invention.

[0026] Figure 2 This is a schematic front view of the structure of the four-layer laminated plate in an embodiment of the present invention.

[0027] Figure 3 This is a top view schematic diagram of the structure of the four-layer laminated plate in an embodiment of the present invention.

[0028] Figure 4 This is a schematic diagram of the front cross-section of the four-layer laminated plate after the cavity structure is formed in an embodiment of the present invention.

[0029] Figure 5 This is a top view cross-sectional schematic diagram of the four-layer laminated plate after the cavity structure is formed in an embodiment of the present invention.

[0030] Figure 6 This is a schematic diagram of the front cross-section of a four-layer IC substrate after the cavity structure is formed in an embodiment of the present invention.

[0031] The labels in the above figures are as follows: 1. Inner substrate; 2. Insulating dielectric layer; 3. Outer conductive layer; 4. Cavity structure; 41. Pre-defined cavity processing area; L1~L4: Conductive layers; J12, J23, J34: Insulating dielectric layers. Detailed Implementation

[0032] Embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. While some embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present invention. It should be understood that the drawings and embodiments of the present invention are for illustrative purposes only and are not intended to limit the scope of protection of the present invention.

[0033] Example 1 Figure 1 The diagram shows a method for manufacturing a printed circuit board cavity, including: Step S11: Provide an inner layer substrate 1 and fabricate an inner layer circuit pattern on the surface of the inner layer substrate 1.

[0034] The aforementioned inner substrate 1 is an insulating support inside the printed circuit board used to carry the inner layer circuitry.

[0035] The aforementioned inner layer circuit pattern is a conductive pattern formed on the surface of the inner layer substrate 1 through photolithography and etching processes. Its local area serves as the electrical connection interface to be exposed at the bottom of the subsequent cavity structure 4.

[0036] By pre-completing the inner layer circuit pattern on the inner layer substrate 1, the inability to form fine circuits at the bottom due to the covering of the insulating dielectric layer 2 after lamination is avoided, thus providing an inner layer electrical connection interface that can be directly exposed at the bottom of the cavity structure 4.

[0037] In step S12, an insulating dielectric layer 2 and an outer conductive layer 3 are sequentially placed on the inner substrate 1 and then laminated to form a multilayer laminate; wherein the insulating dielectric layer 2 covers the inner circuit pattern and the outer conductive layer 3 covers the insulating dielectric layer 2.

[0038] The aforementioned multilayer laminate is a structure formed by stacking the inner substrate 1, the insulating dielectric layer 2, and the outer conductive layer 3 in a preset stacking order and then pressing them together to form a multilayer laminate structure with tight interlayer bonding.

[0039] By laminating to form a multilayer laminate, the inner circuit pattern is completely covered and protected by the insulating dielectric layer 2, and the outer conductive layer 3 is placed on the outermost side as the starting surface for subsequent laser processing, providing a complete starting surface for direct penetration by ultrashort pulse laser.

[0040] Step S13: Create an outer layer circuit pattern on the multilayer laminate, and during the process of creating the outer layer circuit pattern, etch away the outer conductive layer 3 outside the predetermined cavity processing area 41.

[0041] The aforementioned outer circuit pattern is a conductive pattern formed on the outer conductive layer 3 through photolithography and etching processes.

[0042] The aforementioned predetermined cavity processing area 41 refers to the area that is designed and will require the opening of cavities later.

[0043] The aforementioned etching removal refers to using a chemical etching solution to dissolve and remove the outer conductive layer 3 that is not protected by the second resist mask.

[0044] By etching away only the outer conductive layer 3 outside the predetermined cavity processing area 41, the outer conductive layer 3 corresponding to the predetermined cavity processing area 41 remains intact. This eliminates the need for separate pre-processing steps such as pattern transfer, chemical etching to remove copper, and film removal, which are required in the prior art. At the same time, it avoids the impact of chemical etching on pattern accuracy.

[0045] Step S14: The predetermined cavity processing area 41 is scanned and irradiated with an ultrashort pulse laser. The ultrashort pulse laser penetrates the outer conductive layer 3 and removes at least part of the insulating dielectric layer 2 below the outer conductive layer 3 until the surface of the inner circuit pattern is exposed, forming the cavity structure 4.

[0046] The aforementioned ultrashort pulse lasers refer to pulse lasers with a pulse width of less than 20 ps, ​​including picosecond or femtosecond lasers. They have extremely high peak power density and extremely short action time, which can vaporize and remove materials before heat conduction occurs, thus achieving a cold processing effect.

[0047] The cavity structure 4 mentioned above refers to a concave cavity that penetrates the outer conductive layer 3 and at least part of the insulating dielectric layer 2.

[0048] The ultrashort pulse laser takes the outer conductive layer 3 corresponding to the predetermined cavity processing area 41 as the starting surface, directly penetrates the outer conductive layer 3 and at least part of the underlying insulating dielectric layer, and completes the cavity structure 4 at the same time as stopping at the surface of the inner circuit pattern. Due to the cold processing characteristics of the ultrashort pulse laser, the heat-affected zone is extremely small, and there is no carbonization, oxidation or molten spatter on the surface of the inner circuit. The cleanliness meets the requirements for direct welding and no subsequent plasma cleaning or chemical cleaning is required.

[0049] Specifically, in step S11, an inner layer circuit pattern is formed on the surface of the inner layer substrate 1, including: Step S111: Cover the surface of the inner substrate 1 with a first photoresist layer.

[0050] Step S112: Expose and develop the first photoresist layer to form a first resist mask with a circuit pattern.

[0051] Step S113: Using the first resist mask as a protective layer, the surface of the inner substrate 1 is etched.

[0052] Step S114: Remove the first resist mask to obtain the inner layer circuit pattern.

[0053] It should be noted that the fabrication of the inner layer circuit pattern is not limited to the tenting process described above. Those skilled in the art can employ any suitable circuit pattern fabrication process known in the art, including but not limited to subtractive processing, semi-additive processing (SAP), or modified semi-additive processing (mSAP), depending on the circuit accuracy requirements and application scenario. Regardless of the process used to fabricate the inner layer circuit pattern, it does not affect the implementation of subsequent steps in this invention. That is, after the inner layer circuit pattern is fabricated, lamination, outer layer circuit pattern fabrication, and ultrashort pulse laser cavity processing are performed sequentially. This invention does not limit the specific fabrication method of the inner layer circuit pattern, as long as the required circuit pattern can be formed on the surface of the inner layer substrate.

[0054] Specifically, in step S12, an insulating dielectric layer 2 and an outer conductive layer 3 are sequentially placed on the inner substrate 1 and then pressed together to form a multilayer press plate.

[0055] In this embodiment, the insulating dielectric layer 2 covers the inner circuit pattern, and the outer conductive layer 3 covers the insulating dielectric layer 2.

[0056] In this embodiment, the insulating dielectric layer 2 includes at least one of FR4, polyimide, or liquid crystal polymer; the outer conductive layer 3 is a copper layer.

[0057] It should be noted that the insulating dielectric layer 2 can be made of various insulating materials known in the art, including but not limited to polymer materials, ceramic materials, or glass materials. Among them, polymer materials can be epoxy resin, phenolic resin, polyimide, polytetrafluoroethylene, BT resin, liquid crystal polymer, polyphenylene ether, etc.; ceramic materials can be alumina, aluminum nitride, etc. The outer conductive layer 3 can also be made of various conductive materials known in the art, including but not limited to copper, copper alloys, aluminum, gold, silver, nickel, and other metallic materials. Furthermore, since this invention uses ultrashort pulse lasers as a processing method, its removal mechanism depends on the ablation threshold of the material rather than its specific chemical composition or physical morphology. Moreover, ultrashort pulse lasers have direct absorption characteristics for metallic materials. Therefore, this invention has good process adaptability to insulating dielectric layer materials with different compositions, different reinforcement forms, or different filler systems, as well as various conductive layer materials, and is not limited to a specific material system.

[0058] It should be noted that the multilayer laminate includes at least one inner substrate 1, one insulating dielectric layer 2, and one outer conductive layer 3. However, the present invention is not limited to this, and in practical applications, multiple insulating dielectric layers 2 and corresponding outer conductive layers 3 can be alternately arranged according to actual needs.

[0059] Specifically, in step S13, an outer layer circuit pattern is formed on the multilayer laminate, and during the formation of the outer layer circuit pattern, the outer conductive layer 3 outside the predetermined cavity processing area 41 is etched away, including: Step S131: Cover the surface of the outer conductive layer 3 of the multilayer laminate with a second photoresist layer.

[0060] Step S132 involves exposing and developing the second photoresist layer to form a second photoresist mask with a circuit pattern. In this embodiment, the second photoresist mask covers the outer conductive layer 3 corresponding to the predetermined cavity processing area 41.

[0061] Step S133: Using the second resist mask as a protective layer, the uncovered outer conductive layer 3 is etched.

[0062] Step S134: Remove the second resist mask to form an outer circuit pattern, so that the outer conductive layer 3 corresponding to the predetermined cavity processing area 41 is retained intact.

[0063] Step S14: The predetermined cavity processing area 41 is scanned and irradiated with an ultrashort pulse laser. The ultrashort pulse laser penetrates the outer conductive layer 3 and removes at least part of the insulating dielectric layer 2 below the outer conductive layer 3 until the surface of the inner circuit pattern is exposed, forming the cavity structure 4.

[0064] In this embodiment, during the scanning irradiation process of the ultrashort pulse laser, the outer conductive layer 3 corresponding to the predetermined cavity processing area 41 is used as the starting surface for ultrashort pulse laser ablation.

[0065] In this embodiment, during the short-pulse laser processing, the ultrashort-pulse laser stops ablation when it reaches the surface of the inner layer circuit pattern.

[0066] In this embodiment, the pulse width of the ultrashort pulse laser is less than 20 ps, ​​preferably a picosecond laser or a femtosecond laser.

[0067] In this embodiment, the wavelength of the ultrashort pulse laser is in the ultraviolet or green light band, which has a high absorption rate. Specifically, the wavelength in the ultraviolet band is 355 nm, and the wavelength in the green light band is 532 nm.

[0068] In this embodiment, controlling the energy parameters and number of scans of the ultrashort pulse laser can precisely control the removal depth of the cavity structure 4. Specifically, since there is a difference in the ablation threshold between the insulating dielectric layer 2 and the outer conductive layer 3 materials caused by the ultrashort pulse laser, and the energy of the ultrashort pulse laser decreases after penetrating the outer conductive layer 3, when processing the inner circuit pattern surface, the laser energy density is lower than the ablation threshold of the inner circuit pattern surface, thus automatically stopping at the inner circuit pattern surface, achieving zero-damage exposure of the inner circuit.

[0069] As another implementation method, controlling the energy parameters and number of scans of the ultrashort pulse laser can also enable the ultrashort pulse laser to remove the exposed inner layer circuit pattern surface at a preset removal depth. The preset removal depth is 1~2 μm.

[0070] In practical applications, the removal depth of the cavity structure 4 using ultrashort pulse laser can be controlled by the energy parameters and number of scans of the ultrashort pulse laser in this embodiment, or by controlling parameters such as the filling spacing and laser power density of the ultrashort pulse laser, thereby forming the cavity structure 4. The cavity structure 4 can be formed in one step or multiple times.

[0071] It should be noted that due to the cold processing characteristics of ultrashort pulse lasers—that is, the laser pulse width is shorter than the material's thermal diffusion characteristic time—energy is used for material vaporization and removal before heat conduction occurs. The bottom and sidewalls of cavity structure 4 are essentially free of residual adhesive and carbonized residues. The exposed inner layer circuit pattern surface is clean, free of oxidation and molten spatter, typically eliminating the need for plasma or chemical cleaning steps. Furthermore, when the ultrashort pulse laser penetrates the outer conductive layer 3, it achieves rapid vaporization and removal of the outer conductive layer 3 through the high peak power density of the ultrashort pulse, rather than thermal melting. Therefore, no molten conductive material spatter is generated during processing, contaminating the cavity sidewalls, bottom, or the surface of the completed outer layer circuit pattern.

[0072] Example 2 In this embodiment, a method for manufacturing a printed circuit board cavity is provided. Unlike embodiment 1, the number of layers in the multilayer lamination board is set differently in this embodiment.

[0073] by Figure 2 and Figure 3Taking the four-layer laminated board structure shown as an example, from top to bottom, it includes a conductive layer L1, an insulating dielectric layer J12, a conductive layer L2, an insulating dielectric layer J23, a conductive layer L3, an insulating dielectric layer J34, and a conductive layer L4, which are laminated to form a multilayer laminated board. Among them, the inner substrate 1 is a core board structure composed of conductive layer L2, insulating dielectric layer J23, and conductive layer L3, with conductive layers on both sides. An inner layer circuit pattern is formed on the upper surface of the conductive layer L2, which is in contact with the insulating dielectric layer J12. The outer conductive layer 3 is the conductive layer L1, and an outer layer circuit pattern is formed on the upper surface away from the insulating dielectric layer J12. The outer conductive layer 3 corresponding to the predetermined cavity processing area 41 is configured as a pad or circuit area to be exposed.

[0074] The predetermined cavity processing area 41 is scanned and irradiated using an ultrashort pulse laser to remove the conductive layer L1 and the insulating dielectric layer J12, forming the cavity structure 4 and exposing the inner layer circuit pattern on the inner substrate 1 (conductive layer L2). Figure 4 The diagram shown is a front cross-sectional view of the four-layer laminated plate after the cavity structure 4 is formed; Figure 5 The diagram shown is a top view of the cross-section of the four-layer laminated plate after the cavity structure 4 is formed.

[0075] Specifically, in the case of a four-layer BT resin-based IC carrier board, the total thickness is 200 μm. The top-to-bottom structural configuration of the four-layer BT resin-based IC carrier board is shown in Table 1.

[0076] Table 1. Structural composition of a four-layer BT resin-based IC substrate

[0077] As shown in Table 1, conductive layer L1 serves as the starting surface of the cavity to be processed, insulating dielectric layer J12 serves as the secondary surface dielectric layer, conductive layer L2 serves as the bottom stop layer of cavity structure 4, insulating dielectric layer J23 serves as the core dielectric layer, conductive layer L3 serves as the inner circuit layer, insulating dielectric layer J34 serves as the secondary surface dielectric layer, and conductive layer L4 serves as the bottom conductive layer. The conductive layer L2, insulating dielectric layer J23, and conductive layer L3 together form the inner substrate 1.

[0078] In this embodiment, the target depth of cavity structure 4 is 30μm. It is designed to start from the surface of conductive layer L1, penetrate 12μm of conductive layer L1 and 18μm of insulating dielectric layer J12, and finally expose the surface of copper layer of conductive layer L2. Then, 1~2μm of the inner layer circuit pattern on the surface of conductive layer L2 is removed by controllable micro-removal to ensure that the copper layer is completely free of resin residue.

[0079] Based on the above, when the multilayer laminate is a four-layer BT resin-based IC carrier board, the process of manufacturing the printed circuit board cavity specifically includes the following steps: Step S21: An inner layer circuit pattern is fabricated on the surface of the conductive layer L2 using a conventional pattern transfer process. After fabrication, the inner layer substrate 1 is cleaned and dried. The inner layer circuit pattern on the surface of the conductive layer L2 corresponding to the predetermined cavity processing area 41 is configured as pads or circuit areas to be exposed.

[0080] Step S22: The inner layer substrate 1 with the inner layer circuit pattern, the insulating dielectric layer J12 and the conductive layer L1, and the insulating dielectric layer J34 and the conductive layer L4 are stacked and pressed together at high temperature to form a four-layer BT resin-based IC carrier board.

[0081] Step S23: On the surface of the conductive layer L1, an outer layer circuit pattern is made by conventional pattern transfer process, and during the process of making the outer layer circuit pattern, the conductive layer L1 outside the predetermined cavity processing area 41 is etched away.

[0082] Step S24: A laser beam is emitted using an ultrashort pulse laser processing device, and after the laser beam is shaped by a mask, it is projected onto the surface of the four-layer BT resin-based IC substrate to be processed for laser removal to obtain cavity structure 4.

[0083] In this embodiment, the wavelength of the ultrashort pulse laser is 355μm or 532μm, and the pulse width is less than 20ps.

[0084] For ultrashort pulse lasers, the laser parameter setting range is shown in Table 2.

[0085] Table 2. Laser parameter setting range for ultrashort pulse lasers

[0086] Two processing methods are used in combination during ultrashort pulse laser scanning irradiation. The specific range of ultrashort pulse laser parameter settings under different processing methods includes: (1) Process the outer frame first and then the interior in sequence.

[0087] For the first tool set used for rough cutting of the outer frame, the average output power is set to 4KW~6KW, the cutting scanning speed is set to 2800mm / s~3200mm / s, the path spacing is set to 8μm~12μm, the number of cuts is 1, and the processing mode is pulse train mode.

[0088] For the second tool set used for internal precision cutting, the average output power is set to 1KW~3KW, the cutting scanning speed is set to 2500mm / s~3500mm / s, the path spacing is set to 8μm~12μm, the number of cuts is 1, and the processing mode is a cycle mode.

[0089] (2) The internal area is processed by multiple cutting.

[0090] For the first cut, the average output power is set to 4KW~6KW, and the cutting scanning speed is set to 2800mm / s~3200mm / s.

[0091] For the second cut, the average output power is reduced by 20% to 40% compared to the first cut, the cutting scanning speed is reduced by 5% to 15% compared to the first cut, the path spacing is set to 8μm to 12μm, the number of cuts is 2, and the processing mode adopts a loop mode.

[0092] The position of cavity structure 4 is determined according to the design coordinates of the predetermined cavity processing area 41. An ultrashort pulse laser is activated and scanned along a preset scanning path to irradiate the cavity structure 4 area. It first penetrates the 12μm conductive layer L1 and the 18μm insulating dielectric layer J12. By precisely controlling the energy parameters and the number of scans, the surface of the copper layer of conductive layer L2 is exposed, and 1-2μm of the inner layer circuit pattern is removed before the scan stops. Figure 6 The diagram shown is a front cross-sectional view of the four-layer IC carrier after the cavity structure 4 is formed.

[0093] Based on the above, the resulting cavity structure 4 has excellent processing effects in many aspects, specifically including: Regarding the morphology and dimensional accuracy of cavity structure 4, the depth of cavity structure 4 is within the error range of 30μm±1.5μm; the bottom of cavity structure 4 is flat, with no obvious overcut or undercut phenomenon; the angle between the sidewall and the bottom surface of cavity structure 4 is 88°~92°, and the sidewall has no obvious taper or step; the pads / lines of the inner layer circuit pattern on the conductive layer L2 exposed at the bottom of cavity structure 4 have no resin residue after micro-controllable removal.

[0094] Regarding the quality of the bottom and sidewalls of cavity structure 4, the width of the heat-affected zone (HAZ) on the sidewalls of cavity structure 4 is controlled within 2μm, with no carbonization or resin melting and resolidification marks; the conductive layer L1 around cavity structure 4 is free from warping and delamination, and the bonding between the insulating dielectric layer J12 and the conductive layers L1 and L2 remains intact; the surface of the completed outer circuit pattern is free from laser spatter contamination.

[0095] In terms of processing consistency, the depth deviation between different cavity structures of the same batch of four-layer BT resin-based IC carriers is less than or equal to ±2μm; under multiple scanning cutting processes, the transition area between the first and second cuts is smooth, without boundary steps or grooves.

[0096] Regarding the stop-loss layer effect, scanning electron microscopy (SEM) observation and depth measurement show that when the laser penetrates the insulating dielectric layer J12 and reaches the surface of the conductive copper layer L2, the laser energy is effectively absorbed by the conductive copper layer L2 due to the direct absorption characteristics of the ultrashort pulse laser on copper, achieving micro-vaporization removal. By precisely controlling the number of laser scans and energy parameters, approximately 1–2 μm of the conductive layer L2 surface is controllably removed. This removal amount is uniform and controllable, eliminating any potentially residual extremely thin resin layer and ensuring complete removal of the insulating dielectric layer J12, resulting in 100% cleanliness of the conductive copper layer L2. The surface of the conductive copper layer L2 is smooth, without unexpected over-ablation, molten spatter, or thermal damage, and the resistivity change of the copper layer is ≤ 5%. This micro-removal does not affect the electrical performance of the L2 layer circuitry or the reliability of subsequent bonding / soldering, while ensuring excellent adhesion between the copper surface at the bottom of the cavity and the subsequently deposited material.

[0097] Example 3 Based on the same design concept, this embodiment provides a printed circuit board, manufactured using a printed circuit board cavity manufacturing method, including: Inner circuit layer; wherein, the surface of the inner circuit layer is made with an inner circuit pattern.

[0098] Insulating dielectric layer 2 covers the inner circuit layer.

[0099] An outer conductive layer 3 covers the insulating dielectric layer 2; an outer circuit pattern is formed on the surface of the outer conductive layer 3.

[0100] The cavity structure 4 penetrates the outer conductive layer 3 and at least part of the insulating dielectric layer 2, and the bottom of the cavity structure 4 exposes at least part of the inner layer circuit pattern in the inner layer circuit layer.

[0101] In this embodiment, the angle between the sidewall and the bottom surface of the cavity structure 4 is 88°~92°.

[0102] In this embodiment, the depth of cavity structure 4 is 30μm, the error range is 1.5μm, and the depth deviation range between different cavity structures 4 in the same batch is 2μm.

[0103] It should be noted that the term "comprising" and its variations used in the embodiments of this invention are open-ended, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The modifications of "one" and "a plurality" mentioned in the embodiments of this invention are illustrative and not restrictive, and those skilled in the art should understand that unless explicitly indicated otherwise in the context, they should be understood as "one or more".

[0104] The user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in the embodiments of this invention are subject to strict compliance with relevant laws, regulations, and regulatory requirements in their collection, storage, use, processing, transmission, provision, and disclosure, and adhere to the principles of legality, legitimacy, necessity, and good faith. The acquisition of relevant information and data is premised on the user's explicit consent or other legitimate reasons, and a clear and convenient authorization management approach is provided to the user, allowing the user to independently choose to consent, withdraw consent, or refuse to provide relevant information. For functions that rely on user information, if the user does not authorize or withdraws authorization, the corresponding technical function cannot be implemented, and the technical solution of this invention is not applicable in this scenario. The steps described in the method implementation embodiments provided by the embodiments of this invention can be executed in different orders and / or in parallel. Furthermore, the method implementation embodiments may include additional steps and / or omit the steps shown. The scope of protection of this invention is not limited in this respect.

[0105] The term "embodiment" in this specification refers to a specific feature, structure, or characteristic described in connection with an embodiment that may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily imply the same embodiment, nor does it imply independence or alternativeity from other embodiments. The various embodiments in this specification are described in a related manner, with reference to each other for similar or identical parts. In particular, for apparatus, device, and system embodiments, since they are substantially similar to method embodiments, the description is relatively simple, and relevant details are referred to in the description of the method embodiments.

[0106] The above-described embodiments are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of protection. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. A method for manufacturing a printed circuit board cavity, characterized in that, include: An inner layer substrate is provided, and an inner layer circuit pattern is formed on the surface of the inner layer substrate. An insulating dielectric layer and an outer conductive layer are sequentially placed on the inner substrate and then laminated to form a multilayer laminate; wherein the insulating dielectric layer covers the inner circuit pattern and the outer conductive layer covers the insulating dielectric layer. An outer layer circuit pattern is formed on the multilayer laminate, and during the process of forming the outer layer circuit pattern, the outer conductive layer outside the predetermined cavity processing area is etched away. The predetermined cavity processing area is scanned and irradiated using an ultrashort pulse laser. The ultrashort pulse laser penetrates the outer conductive layer and removes at least a portion of the insulating dielectric layer below the outer conductive layer until the surface of the inner circuit pattern is exposed, thus forming a cavity structure.

2. The method for manufacturing a printed circuit board cavity according to claim 1, characterized in that, Fabricating an inner layer circuit pattern on the surface of the inner layer substrate includes: A first photoresist layer is applied to the surface of the inner substrate. The first photoresist layer is exposed and developed to form a first resist mask with a circuit pattern. Using the first resist mask as a protective layer, the surface of the inner substrate is etched; Remove the first resist mask to obtain the inner layer circuit pattern.

3. The method for manufacturing a printed circuit board cavity according to claim 1, characterized in that, An outer layer circuit pattern is formed on the multilayer laminate, and during the formation of the outer layer circuit pattern, the outer conductive layer outside the predetermined cavity processing area is etched away, including: A second photoresist layer is applied to the surface of the outer conductive layer of the multilayer laminate. The second photoresist layer is exposed and developed to form a second photoresist mask with a circuit pattern; wherein the second photoresist mask covers the outer conductive layer corresponding to the predetermined cavity processing area; Using the second resist mask as a protective layer, the uncovered outer conductive layer is etched. Remove the second resist mask to form an outer circuit pattern, so that the outer conductive layer corresponding to the predetermined cavity processing area remains intact.

4. The method for manufacturing a printed circuit board cavity according to claim 1, characterized in that, During the scanning irradiation process of the ultrashort pulse laser, the outer conductive layer corresponding to the predetermined cavity processing area is used as the starting surface for the ultrashort pulse laser ablation.

5. The method for manufacturing a printed circuit board cavity according to claim 1, characterized in that, During the short-pulse laser processing, the ultra-short pulse laser stops ablation when it reaches the surface of the inner layer circuit pattern.

6. The method for manufacturing a printed circuit board cavity according to claim 1, characterized in that, The pulse width of the ultrashort pulse laser is less than 20 ps.

7. The method for manufacturing a printed circuit board cavity according to claim 1, characterized in that, The wavelength of the ultrashort pulse laser is in the ultraviolet band or the green light band.

8. The method for manufacturing a printed circuit board cavity according to claim 1, characterized in that, During the ultrashort pulse laser scanning irradiation process, the energy parameters and number of scans of the ultrashort pulse laser are controlled so that the ultrashort pulse laser removes the exposed inner layer circuit pattern surface at a preset removal depth.

9. The method for manufacturing a printed circuit board cavity according to claim 8, characterized in that, The preset removal depth is 1~2μm.

10. The method for manufacturing a printed circuit board cavity according to claim 1, characterized in that, The insulating dielectric layer includes FR4, polyimide, or liquid crystal polymer.

11. The method for manufacturing a printed circuit board cavity according to claim 1, characterized in that, The outer conductive layer is a copper layer.

12. A printed circuit board, characterized in that, The printed circuit board cavity is manufactured using the method for manufacturing a printed circuit board cavity according to any one of claims 1 to 11, comprising: Inner circuit layer; wherein, the surface of the inner circuit layer is formed with an inner circuit pattern; An insulating dielectric layer covers the inner circuit layer. An outer conductive layer covers the insulating dielectric layer; an outer circuit pattern is formed on the surface of the outer conductive layer. A cavity structure extending through the outer conductive layer and at least a portion of the insulating dielectric layer, with at least a portion of the inner layer circuit pattern exposed at the bottom of the cavity structure.

13. The printed circuit board according to claim 12, characterized in that, The angle between the sidewall and the bottom surface of the cavity structure is 88°~92°.

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