Semiconductor device and method of forming the same, memory system

Abstract

The embodiments of the present disclosure provide a semiconductor device and a forming method thereof, a storage system, the semiconductor device comprising: a first semiconductor structure comprising a plurality of capacitor structures, at least one first plate and a first contact structure, the first plate being coupled with the plurality of capacitor structures; a second semiconductor structure being bonded with the first semiconductor structure; a plurality of conductive structures extending along a first direction and being spaced apart along a second direction, the plurality of conductive structures being located on a side of the first semiconductor structure away from the second semiconductor structure; the plurality of conductive structures comprising a plurality of first conductive structures coupled with the second semiconductor structure and a plurality of second conductive structures located between adjacent first conductive structures and coupled with the first plate; the first plate being located between the plurality of second conductive structures and the plurality of capacitor structures; the first contact structure extending along a third direction and being located on a side of the first plate along the first direction, opposite first and second ends of the first contact structure along the third direction being coupled with the plurality of second conductive structures and the second semiconductor structure respectively.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device, a method for forming the same, and a memory system. Background Technology

[0002] With the development of semiconductor technology, the feature size of semiconductor devices is shrinking and the integration density is increasing. However, as the feature size of semiconductor devices approaches the lower limit of the process, planar processes and manufacturing technologies become challenging and costly, making it difficult to further increase the density of memory cells in semiconductor devices, posing a serious challenge to the semiconductor memory industry. Summary of the Invention

[0003] In view of the above, embodiments of the present disclosure provide a semiconductor device and a method for forming the same, as well as a memory system.

[0004] According to a first aspect of the present disclosure, a semiconductor device is provided, comprising: a first semiconductor structure, the first semiconductor structure including a plurality of capacitor structures, at least one first electrode plate, and a first contact structure, the first electrode plate being coupled to the plurality of capacitor structures; a second semiconductor structure bonded to the first semiconductor structure; conductive structures extending along a first direction and spaced apart along a second direction, located on the side of the first semiconductor structure away from the second semiconductor structure; the conductive structures including a plurality of first conductive structures at least coupled to the second semiconductor structure and second conductive structures located between adjacent first conductive structures and coupled to the first electrode plate; the first electrode plate being located between the second conductive structures and the plurality of capacitor structures; the first contact structure extending along a third direction and located on the side of the first electrode plate along the first direction, the first end and second end of the first contact structure opposite each other along the third direction being coupled to the second conductive structure and the second semiconductor structure, respectively; wherein the first direction and the second direction are both parallel to the surface of the first electrode plate, the third direction is perpendicular to the surface of the first electrode plate, and the first direction intersects the second direction.

[0005] In one alternative implementation, along the second direction, the sum of the dimensions of the plurality of first conductive structures is greater than or equal to the sum of the dimensions of all second conductive structures.

[0006] In one alternative implementation, along the second direction, the ratio of the sum of the dimensions of the plurality of first conductive structures to the sum of the dimensions of all second conductive structures ranges from 1 to 2.

[0007] In one alternative embodiment, the spacing between the second conductive structure and the two first conductive structures adjacent to the second conductive structure is equal.

[0008] In one alternative embodiment, along the second direction, adjacent first conductive structures are symmetrically distributed with respect to the second conductive structures located between adjacent first conductive structures.

[0009] In one alternative implementation, the number of the first conductive structures is greater than the number of the second conductive structures.

[0010] In one alternative embodiment, the ratio between the number of the first conductive structures and the number of the second conductive structures ranges from 1.5 to 2.

[0011] In one optional embodiment, the second conductive structure includes a plurality of conductive pillars spaced apart along the first direction and a first conductive layer located on the plurality of conductive pillars and extending along the first direction; the plurality of conductive pillars are located between the first electrode plate and the first conductive layer.

[0012] In one alternative embodiment, along the third direction, the ratio between the size of the first conductive layer and the size of the conductive post ranges from 7 to 8; along the third direction, the ratio between the size of the first conductive layer and the size of the first electrode plate ranges from 30 to 45.

[0013] In one optional embodiment, the first semiconductor structure further includes: a second contact structure extending along a third direction, the second contact structure being located on one side of the first electrode plate along the first direction, and the first end and the second end of the second contact structure being coupled to the first conductive structure and the second semiconductor structure respectively along the third direction.

[0014] In one optional embodiment, the second semiconductor structure includes a peripheral circuit; the semiconductor device further includes a bonding interface located between the first semiconductor structure and the second semiconductor structure; the first conductive structure is coupled to the peripheral circuit at least through the second contact structure and the bonding interface; the second conductive structure is coupled to the peripheral circuit through the first contact structure and the bonding interface.

[0015] In one optional embodiment, the capacitor structure includes a first electrode, a dielectric layer, and a second electrode; the dielectric layer covers the surface of the first electrode, and the second electrode covers the surface of the dielectric layer; the first semiconductor structure further includes a vertical transistor, the vertical transistor including: a vertical channel structure; a gate structure located on at least one side of the vertical channel structure; a source and a drain, the source and drain being located on opposite sides of the vertical channel structure along the third direction; the first electrode of the capacitor structure is connected to one of the source or the drain; and the second electrodes of a plurality of capacitor structures are coupled to the first electrode plate.

[0016] According to a second aspect of the present disclosure, a storage system is provided, comprising: at least one semiconductor device as described in any of the first aspects; and a controller configured to control the semiconductor device.

[0017] According to a third aspect of the present disclosure, a method for forming a semiconductor device is provided, comprising: forming a first semiconductor structure, the first semiconductor structure including a plurality of capacitor structures, at least one first electrode plate, and a first contact structure, the first electrode plate being coupled to the plurality of capacitor structures; forming a second semiconductor structure; bonding the first semiconductor structure and the second semiconductor structure; forming conductive structures extending along a first direction and spaced apart along a second direction, the conductive structures being located on the side of the first semiconductor structure away from the second semiconductor structure; the conductive structures including a plurality of first conductive structures at least coupled to the second semiconductor structure and second conductive structures located between adjacent first conductive structures and coupled to the first electrode plate; the first electrode plate being located between the second conductive structure and the plurality of capacitor structures; the first contact structure extending along a third direction and located on the side of the first electrode plate along the first direction, the first end and second end of the first contact structure being coupled to the second conductive structure and the second semiconductor structure respectively along the third direction; wherein the first direction and the second direction are both parallel to the surface of the first electrode plate, the third direction is perpendicular to the surface of the first electrode plate, and the first direction intersects the second direction.

[0018] In one alternative implementation, along the second direction, the sum of the dimensions of the plurality of first conductive structures is greater than or equal to the sum of the dimensions of all second conductive structures.

[0019] In one optional embodiment, forming a conductive structure extending along a first direction and spaced apart along a second direction includes: forming a plurality of through holes on the side of the first semiconductor structure away from the second semiconductor structure, exposing a portion of the first electrode plate; the plurality of through holes being spaced apart along the first direction; filling the plurality of through holes with a first conductive material to form a plurality of conductive pillars; forming a plurality of first trenches spaced apart along the second direction and second trenches located between adjacent first trenches on the side of the first semiconductor structure away from the second semiconductor structure; both the first trenches and the second trenches extending along the first direction, with the second trenches exposing the surface of the conductive pillars; and filling the plurality of first trenches and the second trenches with a second conductive material to form a second conductive layer of the first conductive structure and a first conductive layer of the second conductive structure, respectively.

[0020] In one alternative implementation, along the second direction, the sum of the dimensions of the plurality of first trenches is greater than or equal to the sum of the dimensions of all second trenches.

[0021] In one alternative implementation, along the second direction, the ratio of the sum of the dimensions of the plurality of first trenches to the sum of the dimensions of all second trenches ranges from 1 to 2.

[0022] In one alternative embodiment, along the third direction, the ratio between the size of the second trench and the size of the through hole ranges from 7 to 8; along the third direction, the ratio between the size of the second trench and the size of the first electrode plate ranges from 30 to 45.

[0023] In one alternative embodiment, forming the first semiconductor structure further includes: forming a vertical channel structure; forming a gate structure on at least one side of the vertical channel structure; forming a source and a drain, the source and drain being located on opposite sides of the vertical channel structure along the thickness direction of the first electrode; and forming the capacitor structure, the capacitor structure being connected to one of the source or the drain.

[0024] The technical solution provided in this disclosure provides a semiconductor device. The first semiconductor structure in this device includes multiple capacitor structures and a first electrode. Coupling between the second semiconductor structure and the capacitor structures is achieved through a first contact structure, the first electrode, and a second conductive structure. Furthermore, a first conductive structure coupled to the second semiconductor structure is provided for other structures in the semiconductor device besides the capacitor structures. This disclosure sets the conductive structures as alternating first and second conductive structures along a second direction. This effectively reduces electric field interference and provides a conductive path for the capacitor structures formed by the first contact structure, the second conductive structure, and the first electrode. It also provides first conductive structures coupled to the second semiconductor structure for other structures in the semiconductor device besides the capacitor structures. This increases wiring density, reduces the overall resistance of the conductive structures, optimizes the power distribution network of the semiconductor device, and achieves efficient voltage distribution to the capacitor structures and other structures, thereby improving the integration and performance of the semiconductor device. Attached Figure Description

[0025] Figure 1 A schematic cross-sectional view of a semiconductor device provided in an embodiment of this disclosure;

[0026] Figure 2 This is a circuit connection diagram of a 1T1C architecture provided in an embodiment of this disclosure;

[0027] Figure 3 A cross-sectional schematic diagram of a semiconductor device provided in an embodiment of this disclosure;

[0028] Figure 4A One of the schematic diagrams of the structural form of the capacitor structure provided in the embodiments of this disclosure;

[0029] Figure 4B This is a second schematic diagram of the structural form of the capacitor structure provided in the embodiments of this disclosure;

[0030] Figure 5 A three-dimensional schematic diagram of a semiconductor device provided in this disclosure embodiment;

[0031] Figure 6 One of the top views of a semiconductor device provided in this disclosure embodiment;

[0032] Figure 7 This is a second top view schematic diagram of a semiconductor device provided in an embodiment of this disclosure;

[0033] Figure 8 for Figure 6 A schematic diagram of the cross section along the AA' direction;

[0034] Figure 9A third top view schematic diagram of a semiconductor device provided in an embodiment of this disclosure;

[0035] Figure 10 A schematic diagram illustrating the specific implementation flow of a method for forming a semiconductor device according to an embodiment of this disclosure;

[0036] Figure 11 This is one of the top view schematic diagrams provided in the embodiments of the present disclosure of a process for forming a semiconductor device;

[0037] Figure 12 for Figure 11 A schematic diagram of the cross section along the AA' direction;

[0038] Figure 13 This is a second top view schematic diagram of a semiconductor device forming process provided in an embodiment of the present disclosure;

[0039] Figure 14 for Figure 13 A schematic diagram of the cross section along the AA' direction;

[0040] Figure 15 This is the third top view schematic diagram of a semiconductor device forming process provided in an embodiment of the present disclosure;

[0041] Figure 16 for Figure 15 A schematic diagram of the cross section along the AA' direction;

[0042] Figure 17A This is a schematic block diagram of an exemplary system according to an embodiment of the present disclosure;

[0043] Figure 17B A schematic diagram of the composition of an exemplary system provided in an embodiment of this disclosure;

[0044] Figure 18A This is a schematic block diagram of an exemplary solid-state drive (SSD) according to an embodiment of the present disclosure;

[0045] Figure 18B This is a schematic block diagram illustrating the composition of an exemplary memory according to an embodiment of the present disclosure.

[0046] In the above figures (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The figures illustrate, by way of example and not limitation, the various embodiments discussed herein. Detailed Implementation

[0047] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0048] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise scale, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0049] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “below” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0050] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0051] To gain a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this disclosure.

[0052] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0053] To further improve storage density, three-dimensional (3D) semiconductor device architectures can address some of the density limitations in planar semiconductor devices. Figure 1 A schematic cross-sectional view of a semiconductor device provided in an embodiment of this disclosure, such as... Figure 1 As shown, the semiconductor device 100 includes a first semiconductor structure 102 and a second semiconductor structure 104. Exemplarily, the first semiconductor structure 102 includes a memory array, and the second semiconductor structure 104 includes peripheral circuitry.

[0054] In some embodiments, during the fabrication process of a semiconductor device, a first semiconductor structure 102 and a second semiconductor structure 104 are bonded together to obtain a semiconductor device. The memory array of the first semiconductor structure 102 includes multiple memory cells. Exemplarily, each memory cell is mainly composed of a transistor and a capacitor structure controlled by the transistor, i.e., Dynamic Random Access Memory (DRAM) includes an architecture of one transistor (T) and one capacitor structure (C) (1T1C); its main operating principle is to use the amount of charge stored in the capacitor structure to represent whether a binary bit is 1 or 0.

[0055] Figure 2 This is a circuit connection diagram of a 1T1C architecture provided in an embodiment of this disclosure, as shown below. Figure 2 As shown, the drain of transistor T is electrically connected to the bit line (BL), the source of transistor T is electrically connected to the first electrode of capacitor structure C, the second electrode of capacitor structure C is used to receive voltage Vcp, and the gate of transistor T is connected to the word line (WL). The voltage applied through word line WL controls the transistor T to be turned on or off. Bit line BL is used to perform read or write operations on transistor T when it is turned on.

[0056] In some implementations, the memory cell in the first semiconductor structure includes a planar transistor. However, since the source and drain of the planar transistor are laterally positioned at different locations, this increases the transistor's footprint. The design of the planar transistor also complicates the arrangement of word lines or bit lines coupled to the memory cell, for example, by limiting the spacing between word lines or bit lines, thereby increasing manufacturing complexity and reducing product yield.

[0057] In some embodiments, in order to further reduce the overall size of the semiconductor device, the transistors of the memory cell are configured as vertical transistors with a vertical channel structure to reduce the planar size of the first semiconductor structure, thereby increasing the density of the semiconductor device.

[0058] In some implementations, a voltage Vcp needs to be applied to the second electrode of the capacitor structure when performing a read or write operation on the memory cell. Exemplarily, when transistor T is turned on by word line voltage Vg, capacitor structure C charges or discharges in response to bit line voltage Vbl. When bit line voltage Vbl is at a logic high level (e.g., Vcc), capacitor structure C is charged, i.e., storing a "1". Otherwise, capacitor structure C discharges, i.e., storing a "0". Here, the second electrode of capacitor structure C receives voltage Vcp. Exemplarily, voltage Vcp is 0V or half the supply voltage (e.g., 1 / 2 Vcc). Exemplarily, during a write operation, voltage Vcp can be adjusted to 1 / 2 Vcc to optimize charging and discharging speed. During a read operation, voltage Vcp can be adjusted to 0V to improve sensing sensitivity. The specific value of voltage Vcp is chosen depending on the design and operational requirements of the semiconductor device.

[0059] In the above embodiments, the voltage Vcp is used to provide a stable reference voltage to ensure the stability of the charging and discharging process of the capacitor structure, and the voltage Vcp affects the charging / discharging speed and efficiency of the capacitor structure. However, in the process of applying voltage Vcp to the capacitor structure, it occupies the wiring space of the conductive paths of other structures (such as word lines or bit lines), which reduces the width and increases the resistance of the wiring (e.g., conductive structures) on the conductive paths of other structures (such as word lines or bit lines), resulting in a large voltage drop (IR Drop). This affects the voltage received by other structures during read or write operations, thereby reducing the overall performance of the semiconductor device. Therefore, improving the power delivery networks (PDNs) of semiconductor devices to improve their performance has become an urgent technical problem to be solved.

[0060] In view of this, embodiments of this disclosure provide a semiconductor device, such as... Figure 3 and Figure 5As shown, the semiconductor device 100 includes: a first semiconductor structure 102, which includes a plurality of capacitor structures 108, at least one first electrode 110, and a first contact structure 112, wherein the first electrode 110 is coupled to the plurality of capacitor structures 108; a second semiconductor structure 104, which is bonded to the first semiconductor structure 102; and conductive structures 118 extending along a first direction and spaced apart along a second direction, located on the side of the first semiconductor structure 102 away from the second semiconductor structure 104; the conductive structures 118 include a plurality of first conductive structures 114 at least coupled to the second semiconductor structure 104 and second conductive structures 116 located between adjacent first conductive structures 114 and coupled to the first electrode 110; the first electrode 110 is located between the second conductive structures 116 and the plurality of capacitor structures 108; and a first contact structure 112 extending along a third direction and located on the side of the first electrode 110 along the first direction, wherein a first end and a second end of the first contact structure 112 opposite to each other along the third direction are coupled to the second conductive structure 116 and the second semiconductor structure 104, respectively.

[0061] The first and second directions are both parallel to the surface of the first electrode plate, the third direction is perpendicular to the surface of the first electrode plate, and the first and second directions intersect.

[0062] It should be noted that, here and below, the first direction can be the direction in which the conductive structure extends, the second direction can be the direction in which the conductive structures are spaced apart, and the third direction can be the direction in which the first contact structure extends. Both the first and second directions are perpendicular to the third direction, and the first and second directions intersect each other. In some specific embodiments, the first direction is perpendicular to the second direction. For example, the first direction can be the extension direction of the X-axis shown in the figures, the second direction can be the extension direction of the Y-axis shown in the figures, and the third direction can be the extension direction of the Z-axis shown in the figures.

[0063] In this embodiment, the conductive structure is configured as a first conductive structure and a second conductive structure arranged alternately along a second direction. On the one hand, this can effectively reduce electric field interference. On the other hand, it provides a conductive path composed of a first contact structure, a second conductive structure, and a first electrode for the capacitor structure. It also provides a first conductive structure coupled to the second semiconductor structure for other structures in the semiconductor device besides the capacitor structure. This improves wiring density, reduces the overall resistance of the conductive structure, optimizes the power distribution network of the semiconductor device, and achieves efficient voltage distribution to the capacitor structure and other structures, which is beneficial to improving the integration and performance of the semiconductor device.

[0064] In some embodiments, the capacitor structure 108 includes a first electrode 1081, a dielectric layer 1082, and a second electrode 1083; the dielectric layer 1082 covers the surface of the first electrode 1081, and the second electrode 1083 covers the surface of the dielectric layer 1082.

[0065] In some embodiments, the capacitor structure 108 can be Figure 4A The cylindrical shape shown can also be... Figure 4B The diagram shows a pillar-shaped structure. The semiconductor devices provided in this disclosure do not specifically limit the type of capacitor structure.

[0066] In some embodiments, the dielectric layer 1082 is made of high-k materials including, but not limited to, hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), etc. The first electrode 1081 and the second electrode 1083 are made of materials including, but not limited to, tungsten (W), cobalt (Co), nickel (Ni), or other conductive materials.

[0067] In some embodiments, such as Figure 3 As shown, when performing read or write operations on the memory cell, the second semiconductor structure... Figure 3 The dummy line radial capacitor structure 108 shown provides a voltage Vcp. Exemplarily, the second semiconductor structure 104 applies the voltage Vcp to the second electrode 1083 of the capacitor structure 108 via the first contact structure 112, the first contact 113, the second conductive structure 116, and the second contact 122.

[0068] In some embodiments, the materials of the first contact 113 and the second contact 122 include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), or other conductive materials. The arrangement of the first contact 113 facilitates more uniform voltage transmission.

[0069] It should be noted that, Figure 3 To illustrate the positional relationship between the first and second conductive structures and the first electrode and capacitor structure, the surfaces of the first conductive structure 114 and the second conductive structure 116 that are furthest from the second semiconductor structure are offset in a third-order orientation. In actual semiconductor devices, such as... Figure 5 As shown, along a third direction, the surfaces of the first conductive structure 114 and the second conductive structure 116 that are furthest from the second semiconductor structure are flush. Furthermore, Figure 5 To and Figure 3 The corresponding 3D diagram is shown, but for simplicity, Figure 5 Only the first semiconductor structure 102, the second semiconductor structure 104, and the conductive structure 118 are shown; the rest are omitted. Figure 3 Other structures within.

[0070] In some embodiments, along the second direction, the sum of the dimensions of the plurality of first conductive structures is greater than or equal to the sum of the dimensions of all second conductive structures. For example, as... Figure 6 As shown, D1 is the dimension of the first conductive structure 114 along the second direction, and D2 is the dimension of the second conductive structure 116 along the second direction. Figure 6 The sum of the dimensions of the three first conductive structures 114 shown is greater than or equal to the sum of the dimensions of the two second conductive structures 116.

[0071] In some embodiments, since the first conductive structure is used to provide a conductive path for the capacitor structure, the second conductive structure is used to provide a conductive path for other structures in the semiconductor device besides the capacitor structure (e.g., word lines or...). Figure 3 The bit line 134 shown provides a conductive path. The voltage transmitted to the capacitor structure via the second conductive structure is typically less than or equal to the voltage transmitted to other structures (e.g., word lines or bit lines) via the first conductive structure. Therefore, by setting the sum of the dimensions of the multiple first conductive structures along the second direction to be greater than or equal to the sum of the dimensions of all second conductive structures along the second direction according to the actual transmitted voltage, the resistance of the first conductive structure can be reduced without increasing the overall resistance of the conductive structure, and the transmission requirements of different voltage magnitudes in different structures of the semiconductor device can be met, thereby improving the performance of the semiconductor device.

[0072] In some embodiments, along the second direction, the ratio of the sum of the dimensions of the plurality of first conductive structures 114 to the sum of the dimensions of all second conductive structures 116 ranges from 1 to 2. More specifically, the ratio of the sum of the dimensions D1 of the plurality of first conductive structures 114 to the sum of the dimensions D2 of all second conductive structures 116 is 1, 1.5, or 2.

[0073] In some embodiments, the size D1 of the first conductive structure 114 is equal to the size D2 of the second conductive structure 116.

[0074] For example, Figure 6 The dimensions D1 of the first conductive structure 114 and the dimension D2 of the second conductive structure 116 shown both range from 5 micrometers to 10 micrometers.

[0075] In some embodiments, the spacing between the second conductive structure 116 and the two first conductive structures 114 adjacent to the second conductive structure 116 is equal.

[0076] For example, such as Figure 6 As shown, the spacing between the second conductive structure 116 and the two first conductive structures 114 adjacent to the second conductive structure 116 is L1. For example, the value of L1 ranges from 5 micrometers to 10 micrometers. It should be noted that... Figure 6The diagram illustrates that within the coverage area of ​​a first electrode plate 110, along the second direction, the sum of the dimensions of a plurality of first conductive structures 114 is greater than or equal to the sum of the dimensions of all second conductive structures 116.

[0077] In other embodiments, such as Figure 7 As shown, the number of first electrode plates 110 can be multiple (e.g., two), and the orthographic projection of at least one first conductive structure 114 (e.g., first conductive structure 114-1) can simultaneously intersect with the orthographic projections of two first electrode plates 110. Figure 7 As shown, along the second direction, within the coverage area of ​​each first electrode 110, the effective size of the first conductive structure 114-1 is D3, and the effective size of the first conductive structure 114-2 is D1. Figure 7 In the example, the sum of the dimensions of the multiple first conductive structures being greater than or equal to the sum of the dimensions of all second conductive structures can be understood as the sum of the effective dimensions of the multiple first conductive structures being greater than or equal to the sum of the dimensions of all second conductive structures. In other words, twice D3 plus D1 is greater than twice D2.

[0078] Thus, when there are multiple first electrode plates, the dimensions of the first conductive structure and the second conductive structure set on each first electrode plate along the second direction are such that the sum of the dimensions of the multiple first conductive structures is greater than or equal to the sum of the dimensions of all second conductive structures, thereby satisfying the transmission requirements of different voltages in different regions of the semiconductor device and improving the overall performance of the semiconductor device.

[0079] In some embodiments, the dimensions D1 of the first conductive structure 114, the dimension D2 of the second conductive structure 116, and the spacing L1 are equal.

[0080] In some embodiments, such as Figure 6 As shown, along the second direction, adjacent first conductive structures 114 are symmetrically distributed with respect to the second conductive structures 116 located between adjacent first conductive structures 114. This reduces wiring path conflicts between the first and second conductive structures, reduces electric field interference, increases the density of the first and second conductive structures, and also helps to improve the integration density of semiconductor devices.

[0081] In some embodiments, the number of first conductive structures 114 is greater than the number of second conductive structures 116.

[0082] In some embodiments, the ratio between the number of first conductive structures 114 and the number of second conductive structures 116 ranges from 1.25 to 2. More specifically, the ratio between the number of first conductive structures 114 and the number of second conductive structures 116 can be 1.25, 1.5, or 2.

[0083] In some embodiments, the number of first conductive structures is 5, and the number of second conductive structures is 4.

[0084] In some implementations, such as Figure 6 As shown, the number of first conductive structures is 3, and the number of second conductive structures is 2.

[0085] In some implementations, such as Figure 9 As shown, the number of first conductive structures is 2, and the number of second conductive structures is 1. Exemplarily, along the second direction, the size of the first conductive structure 114 is D1; ​​within the coverage area of ​​the first electrode plate 110, the effective size of the first conductive structure 114 is D3, and the effective size of the second conductive structure 116 is D2. Figure 9 In the example, the sum of the dimensions of the multiple first conductive structures being greater than or equal to the sum of the dimensions of all second conductive structures can be understood as the sum of the effective dimensions of the multiple first conductive structures being greater than or equal to the sum of the effective dimensions of all second conductive structures. In other words, twice D3 is greater than or equal to D2.

[0086] exist Figure 9 In this instance, D1 is greater than D2; for example, D1 is equal to twice D2. For example, Figure 9 The dimensions D1 of the first conductive structure 114 shown range from 10 micrometers to 20 micrometers, and the dimensions D2 of the second conductive structure 116 range from 5 micrometers to 10 micrometers.

[0087] In some embodiments, the number of first electrode plates 110 can be one (see reference). Figure 6 (This can also be multiple (see reference)) Figure 7 ).

[0088] It should be noted that the specific number of the first conductive structure, the second conductive structure, and the first electrode plate in the above embodiments is only an illustrative example and is not a limitation on the number of the first conductive structure, the second conductive structure, and the first electrode plate of this disclosure. In practical applications, the number of the first conductive structure, the second conductive structure, and the first electrode plate can be set according to actual needs.

[0089] In some embodiments, such as Figure 3 , Figure 6 , Figure 7 and Figure 8 As shown, the second conductive structure 116 includes a plurality of conductive pillars 1162 arranged at intervals along a first direction and a first conductive layer 1161 located on the plurality of conductive pillars 1162 and extending along the first direction; the plurality of conductive pillars 1162 are located between the first electrode plate 110 and the first conductive layer 1161.

[0090] In some embodiments, the materials of the first conductive layer 1161 and the conductive pillar 1162 may be the same or different. For example, the materials of the first conductive layer 1161 and the conductive pillar 1162 include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), or other conductive materials.

[0091] It should be noted that, Figure 6 , Figure 7 as well as Figure 9 In order to clearly show the positional relationship between the first conductive layer 1161, the conductive pillar 1162 and the first conductive structure 114, a perspective view is used to illustrate the first conductive layer 1161.

[0092] In some embodiments, such as Figure 8 As shown, along the third direction, the ratio between the size h2 of the first conductive layer 1161 and the size h1 of the conductive post 1162 ranges from 7 to 8; along the third direction, the ratio between the size h2 of the first conductive layer 1161 and the size h3 of the first electrode plate 110 ranges from 30 to 45.

[0093] For example, the ratio between the size h2 of the first conductive layer 1161 and the size h1 of the conductive post 1162 can be 7, 7.5 or 8, and the ratio between the size h2 of the first conductive layer 1161 and the size h3 of the first electrode plate 110 can be 30, 40 or 45.

[0094] In some embodiments, such as Figure 8 As shown, the first electrode 110 includes a first sub-layer 1101 and a second sub-layer 1102, wherein the material of the first sub-layer 1101 includes, but is not limited to, silicon germanium, and the material of the second sub-layer 1102 includes, but is not limited to, metallic tungsten (W) or tungsten nitride (WN).

[0095] In this embodiment of the present disclosure, by setting the first conductive structure as a plurality of conductive pillars spaced apart along the first direction and a first conductive layer located on the plurality of conductive pillars and extending along the first direction, a uniform voltage distribution can be achieved when the voltage is transmitted to the first electrode through the first conductive structure, thereby reducing the fluctuation between the voltages received by the capacitor structures of the multiple memory cells, which is beneficial to improving the performance of the semiconductor device.

[0096] In some embodiments, such as Figure 3 As shown, the first semiconductor structure 102 further includes a second contact structure 120 extending along a third direction. The second contact structure 120 is located on one side of the first electrode plate 110 along the first direction, and the first end and the second end of the second contact structure 120, which are opposite each other along the third direction, are coupled to the first conductive structure 114 and the second semiconductor structure 104, respectively.

[0097] In some embodiments, such as Figure 3 As shown, the second contact structure 120 and the first contact structure 112 are located on different sides of the first electrode plate along the first direction. This reduces mutual interference between the first conductive structure and the second conductive structure during voltage transmission.

[0098] In other embodiments, the second contact structure 120 and the first contact structure 112 may also be located on the same side of the first electrode plate along the first direction. This simplifies wiring design, reduces wiring space requirements, improves wiring efficiency, and thus optimizes the integration density of the semiconductor device.

[0099] In some embodiments, such as Figure 1 and Figure 3 As shown, the second semiconductor structure 104 includes peripheral circuitry; the semiconductor device further includes a bonding interface 106 located between the first semiconductor structure 102 and the second semiconductor structure 104; the first conductive structure 114 is coupled to the peripheral circuitry at least through the second contact structure 120 and the bonding interface 106; the second conductive structure 116 is coupled to the peripheral circuitry through the first contact structure 112 and the bonding interface 106.

[0100] In some embodiments, the first semiconductor structure further includes a vertical transistor 132, which includes: a vertical channel structure 126; a gate structure 128 located on at least one side of the vertical channel structure 126; a source 124 and a drain 130, which are respectively located on opposite sides of the vertical channel structure 126 along a third direction; a first electrode 1081 of a capacitor structure 108 connected to one of the source 124 or the drain 130; and second electrodes 1083 of a plurality of capacitor structures 108 coupled to a first electrode plate 110.

[0101] In some embodiments, such as Figure 3 As shown, the first semiconductor structure 102 also includes a shielding layer 136. The shielding layer 136 is located on the side of the vertical channel structure 126 of the two adjacent vertical transistors 132 where the gate structure 128 is not provided.

[0102] In some embodiments, the material of the vertical channel structure 126 includes at least one selected from indium gallium zinc oxide (IGZO), indium tungsten oxide (IWO), indium tin oxide (ITO), and indium zinc oxide (IZO). When the material of the vertical channel structure 126 is IGZO, the leakage current of the vertical transistor is relatively small (leakage current less than or equal to 10). -15A), thereby ensuring a low refresh rate for the dynamic random access memory. Exemplarily, the material of the shielding layer 136 includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), or other conductive materials. In some embodiments, the material of the shielding layer 136 is tungsten.

[0103] As the density of semiconductor devices continues to increase, the gate structures of memory cells become physically closer, leading to increased capacitive coupling between adjacent cells. By incorporating a shielding layer between the vertical transistors of adjacent memory cells, the coupling capacitance between them can be effectively reduced, mitigating the row hammer effect.

[0104] This disclosure also provides a method for forming a semiconductor device. Figure 10 This is a schematic diagram illustrating a specific implementation flow of a method for forming a semiconductor device according to an embodiment of this disclosure, as shown below. Figure 10 As shown, the method for forming the semiconductor device specifically includes the following steps:

[0105] Step S10: Form a first semiconductor structure, the first semiconductor structure including multiple capacitor structures, at least one first electrode plate and a first contact structure, the first electrode plate being coupled to the multiple capacitor structures;

[0106] Step S20: Forming a second semiconductor structure;

[0107] Step S30: Bond the first semiconductor structure and the second semiconductor structure;

[0108] Step S40: Form conductive structures extending along a first direction and spaced apart along a second direction, the conductive structures being located on the side of the first semiconductor structure away from the second semiconductor structure; the conductive structures include a plurality of first conductive structures coupled to at least the second semiconductor structure and second conductive structures located between adjacent first conductive structures and coupled to a first electrode plate; the first electrode plate is located between the second conductive structures and a plurality of capacitor structures; a first contact structure extends along a third direction and is located on the side of the first electrode plate along the first direction, the first end and the second end of the first contact structure opposite each other along the third direction are coupled to the second conductive structure and the second semiconductor structure, respectively.

[0109] The first and second directions are both parallel to the surface of the first electrode plate, the third direction is perpendicular to the surface of the first electrode plate, and the first and second directions intersect.

[0110] It should be understood that Figure 10 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 10 The steps shown can be adjusted in order according to actual needs.

[0111] In some embodiments, along the second direction, the sum of the dimensions of the plurality of first conductive structures is greater than or equal to the sum of the dimensions of all second conductive structures.

[0112] The voltage transmitted to the capacitor structure via the second conductive structure is usually less than or equal to the voltage transmitted to other structures (such as word lines or bit lines) via the first conductive structure. Therefore, by setting the sum of the dimensions of multiple first conductive structures along the second direction to be greater than or equal to the sum of the dimensions of all second conductive structures along the second direction according to the actual transmitted voltage, the resistance of the first conductive structure can be reduced without increasing the overall resistance of the conductive structure, and the transmission requirements of different voltages in different structures of the semiconductor device can be met, thereby improving the performance of the semiconductor device.

[0113] Next, combine Figure 3 , Figure 6 , Figure 8 as well as Figure 11 Figure 16 The process of forming semiconductor devices is described in detail.

[0114] Step S10 is executed to form the first semiconductor structure 102.

[0115] In some embodiments, such as Figure 3 As shown, forming a first semiconductor structure 102 further includes: forming a vertical channel structure 126; forming a gate structure 128 on at least one side of the vertical channel structure 126; forming a source 124 and a drain 130, the source 124 and the drain 130 being located on opposite sides of the vertical channel structure 126 along the thickness direction of the first electrode 110, the vertical channel structure 126, the gate structure 128, the source 124, and the drain 130 constituting a vertical transistor 132; and forming a capacitor structure 108, the capacitor structure 108 being connected to one of the source 124 or the drain 130.

[0116] refer to Figure 3 The capacitor structure 108 includes a first electrode 1081, a dielectric layer 1082, and a second electrode 1083. The dielectric layer 1082 covers the surface of the first electrode 1081, and the second electrode 1083 covers the surface of the dielectric layer 1082. The first electrode 1081 of the capacitor structure 108 is connected to the source 124, the second electrodes 1083 of the plurality of capacitor structures 108 are coupled to the first electrode plate 110, and the bit line 134 is coupled to the drain 130.

[0117] In some embodiments, the extension direction of the word line is perpendicular to the extension direction of the bit line. In some embodiments, the gate structure surrounds two sides of the vertical channel structure (one side of the vertical channel structure along a first direction and one side of the vertical channel structure along a second direction), and the word line ( Figure 3 (Not shown) Extends along a first direction and is connected to the gate structure of a plurality of vertical transistors arranged along the first direction, and the bit line extends along a second direction and is connected to the drain of a plurality of vertical transistors arranged along the second direction.

[0118] Step S20 is performed to form the second semiconductor structure 104.

[0119] In step S30, the first semiconductor structure 102 and the second semiconductor structure 104 are bonded. The first semiconductor structure 102 and the second semiconductor structure 104 are connected through a bonding interface 106; the first semiconductor structure 102 and the second semiconductor structure 104 can be connected by a hybrid bonding method or the like. In some embodiments, the first semiconductor structure 102 can be bonded to the top of the second semiconductor structure 104 at the bonding interface 106 in a face-to-face manner.

[0120] Step S40 is performed to form a conductive structure 118 that extends along a first direction and is spaced apart along a second direction.

[0121] like Figure 11 and Figure 12 As shown, a plurality of vias 140 are formed on the side of the first semiconductor structure away from the second semiconductor structure to expose a portion of the first electrode 110; the plurality of vias 140 are spaced apart along a first direction. Exemplarily, a first dielectric layer 138 is formed on the side of the first semiconductor structure away from the second semiconductor structure to cover the first electrode 110, and a portion of the first dielectric layer 138 is removed to form a plurality of vias 140 exposing a portion of the first electrode 110.

[0122] In some embodiments, the methods for forming the first dielectric layer 138 include, but are not limited to, processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD).

[0123] In some embodiments, the method for forming the via 140 includes, but is not limited to, dry etching or wet etching.

[0124] In some implementations, the dimension of the through hole 140 in the third direction is equal to h1.

[0125] like Figure 13 and Figure 14 As shown, a plurality of through holes are filled with a first conductive material to form a plurality of conductive pillars 1162. Exemplarily, the first conductive material includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), or aluminum (Al).

[0126] like Figure 15 and Figure 16 As shown, a plurality of first trenches 142 and second trenches 144 are formed on the side of the first semiconductor structure away from the second semiconductor structure, which are spaced apart along the second direction; the first trenches 142 and the second trenches 144 both extend along the first direction, and the second trenches 144 expose the surface of the conductive pillars 1162.

[0127] For example, a second dielectric layer 139 covering a plurality of conductive pillars 1162 is formed on the side of the first semiconductor structure away from the second semiconductor structure. A portion of the second dielectric layer 139 is removed to form a plurality of first trenches 142 and a second trench 144 exposing the surface of the conductive pillars 1162.

[0128] In some embodiments, the spacing between the second trench 144 and the two first trenches 142 adjacent to the second trench 144 is equal.

[0129] For example, such as Figure 15 and Figure 16 As shown, the interval between the second groove 144 and the two first grooves 142 adjacent to the second groove 144 is L1.

[0130] It should be noted that, in order to illustrate the positional relationship between the first trench, the second trench, and the conductive post, Figure 15 The first dielectric layer, second dielectric layer, and other structures are omitted.

[0131] In some embodiments, along the second direction, the sum of the dimensions of the plurality of first grooves 142 is greater than or equal to the sum of the dimensions of all second grooves 144. Exemplarily, along the second direction, the dimension of the first groove 142 is equal to D1, and the dimension of the second groove 144 is equal to D2, such as... Figure 15 and Figure 16 As shown, along the second direction, the sum of the dimensions of the three first grooves 142 is greater than or equal to the sum of the dimensions of the two second grooves 144.

[0132] In some embodiments, along the second direction, the ratio of the sum of the dimensions of the plurality of first trenches 142 to the sum of the dimensions of all second trenches 144 ranges from 1 to 2. More specifically, the ratio of the sum of the dimensions of the plurality of first conductive structures 114 to the sum of the dimensions of all second conductive structures 116 is 1, 1.5, or 2.

[0133] In some embodiments, along a third direction, the ratio between the size of the second trench and the size of the through hole ranges from 7 to 8; along a third direction, the ratio between the size of the second trench and the size of the first electrode plate ranges from 30 to 45. For example, along a third direction, the size of the second trench 144 is equal to h2, the size of the first electrode plate is equal to h3, the ratio between h2 and h1 ranges from 7 to 8, and the ratio between h2 and h3 ranges from 30 to 45. More specifically, the ratio between h2 and h1 is 7, 7.5, or 8, and the ratio between h2 and h3 is 30, 40, or 45.

[0134] like Figure 6 and Figure 8 As shown, a second conductive material is filled in a plurality of first trenches 142 and second trenches 144 to form a second conductive layer of a first conductive structure 114 and a first conductive layer 1161 of a second conductive structure 116, respectively.

[0135] In some implementations, the second conductive material may be the same as the first conductive material.

[0136] This disclosure also provides a storage system comprising: at least one semiconductor device as described in any of the first aspects; and a controller configured to control the semiconductor device.

[0137] Here, a semiconductor device can be a memory or a part of a memory.

[0138] Figure 17A A schematic block diagram of an exemplary system according to an embodiment of the present disclosure is shown. Figure 17A As shown, system 1 may include a host and a storage system 30, the storage system 30 including a controller 10 and one or more memories 20. The host may be a processor of an electronic device (e.g., a central processing unit (CPU) or a graphics processing unit (GPU)). The host may be configured to send data to or receive data from the memory 20. The controller 10 is coupled to the memory 20 and the host and is configured to control the memory 20. The controller 10 may manage the data stored in the memory 20 and communicate with the host.

[0139] Controller 10 can be configured to control the operation of memory 20, such as read, write, and refresh operations. In some embodiments, controller 10 is also configured to process error correction codes (ECCs) regarding data read from or written to memory 20. Controller 10 can also perform any other suitable functions, such as formatting memory 20.

[0140] In some specific embodiments, the controller 10 and one or more memories 20 can be integrated into various types of electronic devices. For example, the controller 10 can be integrated into the northbridge of a computer motherboard or directly into the computer CPU, and multiple memories 20 can be integrated into a memory module. In other words, the storage system 30 can be implemented and packaged into different types of terminal electronic products.

[0141] Controller 10 can send data to / receive data from the host (HOST) and can send commands (CMD) and addresses (ADDR) to the memory 20. Controller 10 may include a command generator 11, an address generator 12, a device interface 13, and a host interface 14. The host interface 14 can receive commands (CMD) and addresses (ADDR) from the host (HOST). The command generator 11 can generate access commands, row hammer refresh commands, etc., by decoding the commands (CMD) received from the host (HOST), and can provide access commands and row hammer refresh commands to the memory 20 through the device interface 13. An access command may be a signal instructing the memory 20 to write or read data by accessing a row of the memory cell array 220 corresponding to address ADDR. A row hammer refresh command may be a signal instructing the memory 20 to perform an additional refresh operation on word lines adjacent to word lines that are frequently accessed in a short period. In other words, an additional refresh operation can be performed on word lines adjacent to word lines that are accessed multiple times in a short period.

[0142] The address generator 12 in the controller 10 can generate the row and column addresses to be accessed in the memory cell array 220 by decoding the address ADDR received from the host interface 14. Furthermore, the memory 20 can generate addresses of the memory banks to be accessed when the memory cell array 220 comprises multiple banks.

[0143] Furthermore, the controller 10 can control memory operations such as writing and reading by providing various signals to the memory 20 via the device interface 13. For example, the controller 10 can provide a write command to the memory 20. The write command is used to instruct the memory 20 to perform a write operation to store data in the memory 20.

[0144] In some embodiments, the memory 20 includes a memory cell array 220 and peripheral circuitry 210. The memory cell array 220 includes multiple banks, each bank includes multiple blocks, each block includes multiple rows and columns of memory cells, each row is coupled to a corresponding word line, and each column is coupled to a corresponding bit line. The peripheral circuitry 210 can write data to or read data from the memory cell array 220 based on commands CMD and addresses ADDR received from the controller 10, or it can provide control signals CTRL to the row decoding and column decoding circuits for refreshing the memory cells included in the memory cell array 220. In other words, the peripheral circuitry 210 can perform all operations to process the data in the memory cell array 220. The peripheral circuit 210 may include: control circuits corresponding to each memory block, such as sensing amplifier (SA) circuits and word-line driver (WLD) circuits; control circuits corresponding to each memory bank, such as row decoding circuits and column decoding circuits; and control circuits corresponding to all memory banks, such as command buffers, command decoders, address buffers, data input / output buffers, and mode registers.

[0145] The memory 20 can be random access memory (RAM), such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), static RAM (SRAM), double data rate SDRAM (DDR SDRAM), DDR2 SDRAM, DDR3 SDRAM, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), etc. The following explanation uses DRAM as an example only.

[0146] Figure 17BA schematic diagram of the composition of an exemplary system according to an embodiment of the present disclosure is shown. In some embodiments, DRAM may be a structure outside of storage system 30, which may be directly connected to the host as main memory during host operation, or DRAM may be embedded in the host. In some embodiments, DRAM may be a structure outside of storage system 30, which may be coupled to storage system 30 for use as buffer memory, for example, for storing a mapping table. In some embodiments, DRAM as buffer memory may also be embedded in controller 10. In other embodiments, DRAM may also be part of controller 10, for example, DRAM as buffer memory is embedded in controller 10. In some embodiments, DRAM may also be part of controller 10, for example, part of a DRAM controller, for controlling memory 20 to perform operations such as write and read. In other embodiments, a plurality of DRAM stacks may be applied to a high-bandwidth memory (HBM) architecture for use as storage media.

[0147] Figure 18A This is a schematic block diagram illustrating the composition of an exemplary SSD according to an embodiment of this disclosure. Here, SSD can be understood as the aforementioned... Figure 17A as well as Figure 17B In this example, DRAM can be used as a buffer memory, representing one type of storage system.

[0148] like Figure 18AAs shown, SSD 30' may include SSD controller 10', buffer memory 20', and non-volatile memory 40. SSD controller 10' provides the physical connection between the host and SSD 30'. That is, SSD controller 10' can provide an interface between the host and SSD 30' according to the host's bus format. SSD controller 10' can decode instructions provided by the host. SSD controller 10' can access non-volatile memory 40 based on the decoding result. Buffer memory 20' can temporarily store write data provided by the host or data read from non-volatile memory 40. When the host issues a read request, if the data present in non-volatile memory 40 is cached, buffer memory 20' can support caching functionality for directly providing cached data to the host. The data transfer rate through the host's bus format (e.g., SATA or SAS) is much higher than the data transfer rate of the SSD 30's memory channel. That is, when the host interface speed is significantly higher, the performance degradation caused by the speed difference can be minimized by providing a high-capacity buffer memory 20'. Additionally, the buffer memory 20' can store the address mapping table of the non-volatile memory 40. The buffer memory 20' can be, but is not limited to, DRAM. The non-volatile memory 40 can be configured as a storage medium for an SSD 30'. The non-volatile memory 40 can be, but is not limited to, NAND flash memory.

[0149] Figure 18B This is a schematic block diagram illustrating the composition of an exemplary memory according to an embodiment of this disclosure; here, memory can be understood as the aforementioned Figure 17A One type of storage system in this example uses DRAM as a storage medium.

[0150] like Figure 18B As shown, memory 30” can be easily attached to or installed into or removed from system 1 via the illustrated interface. Memory 30” may include a plurality of volatile memories 20” (e.g., DRAM) and a memory controller 10”. Memory 30” can be used to write data, store data, retrieve (or read) data, and / or erase data under the control of the computer’s processor. In some embodiments, memory controller 10” can communicate with DRAM using at least one communication protocol or technology standard typically associated with, for example, dual in-line memory modules (DIMMs), register-based DIMMs (RDIMMs), low-load DIMMs (LRDIMMs), registerless DIMMs (UDIMMs), etc.

[0151] It should be noted that, Figure 18A Buffer memory 20' and Figure 18B Medium volatile memory 20” are all Figure 17AOne application scenario of the memory 20.

[0152] It should be understood that the phrases "an embodiment" or "some embodiments" throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this disclosure. Therefore, "in an embodiment" or "in some embodiments" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0153] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: A first semiconductor structure, comprising a plurality of capacitor structures, at least one first electrode plate, and a first contact structure, wherein the first electrode plate is coupled to the plurality of capacitor structures; A second semiconductor structure is bonded to the first semiconductor structure; Conductive structures extending along a first direction and spaced apart along a second direction are located on the side of the first semiconductor structure away from the second semiconductor structure; the conductive structures include a plurality of first conductive structures at least coupled to the second semiconductor structure and second conductive structures located between adjacent first conductive structures and coupled to the first electrode. The first electrode plate is located between the second conductive structure and the plurality of capacitor structures; the first contact structure extends along a third direction and is located on one side of the first electrode plate along the first direction, and the first end and the second end of the first contact structure opposite each other along the third direction are coupled to the second conductive structure and the second semiconductor structure, respectively; wherein the first direction and the second direction are both parallel to the surface of the first electrode plate, the third direction is perpendicular to the surface of the first electrode plate, and the first direction intersects the second direction.

2. The semiconductor device according to claim 1, characterized in that, Along the second direction, the sum of the dimensions of the plurality of first conductive structures is greater than or equal to the sum of the dimensions of all second conductive structures.

3. The semiconductor device according to claim 2, characterized in that, Along the second direction, the ratio of the sum of the dimensions of the plurality of first conductive structures to the sum of the dimensions of all second conductive structures ranges from 1 to 2.

4. The semiconductor device according to claim 2, characterized in that, The spacing between the second conductive structure and the two first conductive structures adjacent to the second conductive structure is equal.

5. The semiconductor device according to claim 2, characterized in that, Along the second direction, adjacent first conductive structures are symmetrically distributed with respect to the second conductive structures located between adjacent first conductive structures.

6. The semiconductor device according to claim 1, characterized in that, The number of the first conductive structure is greater than the number of the second conductive structure.

7. The semiconductor device according to claim 6, characterized in that, The ratio between the number of the first conductive structure and the number of the second conductive structure ranges from 1.5 to 2.

8. The semiconductor device according to claim 1, characterized in that, The second conductive structure includes a plurality of conductive pillars spaced apart along the first direction and a first conductive layer located on the plurality of conductive pillars and extending along the first direction; The plurality of conductive pillars are located between the first electrode plate and the first conductive layer.

9. The semiconductor device according to claim 8, characterized in that, Along the third direction, the ratio between the size of the first conductive layer and the size of the conductive pillar ranges from 7 to 8; Along the third direction, the ratio between the size of the first conductive layer and the size of the first electrode plate ranges from 30 to 45.

10. The semiconductor device according to claim 1, characterized in that, The first semiconductor structure further includes: A second contact structure extending along a third direction is located on one side of the first electrode plate along the first direction, and the first end and the second end of the second contact structure opposite each other along the third direction are coupled to the first conductive structure and the second semiconductor structure, respectively.

11. The semiconductor device according to claim 10, characterized in that, The second semiconductor structure includes peripheral circuitry; the semiconductor device further includes: A bonding interface is located between the first semiconductor structure and the second semiconductor structure; The first conductive structure is coupled to the peripheral circuit at least through the second contact structure and the bonding interface; the second conductive structure is coupled to the peripheral circuit through the first contact structure and the bonding interface.

12. The semiconductor device according to claim 1, characterized in that, The capacitor structure includes a first electrode, a dielectric layer, and a second electrode; the dielectric layer covers the surface of the first electrode, and the second electrode covers the surface of the dielectric layer. The first semiconductor structure further includes a vertical transistor, the vertical transistor comprising: Vertical channel structure; A gate structure is located on at least one side of the vertical channel structure; The source and drain are located on opposite sides of the vertical channel structure along the third direction. The first electrode of the capacitor structure is connected to either the source or the drain; the second electrodes of the plurality of capacitor structures are coupled to the first plate.

13. A storage system, characterized in that, include: At least one semiconductor device as described in any one of claims 1 to 12; as well as A controller configured to control the semiconductor device.

14. A method for forming a semiconductor device, characterized in that, include: A first semiconductor structure is formed, the first semiconductor structure including a plurality of capacitor structures, at least one first electrode plate and a first contact structure, wherein the first electrode plate is coupled to the plurality of capacitor structures; Forming a second semiconductor structure; Bonding the first semiconductor structure and the second semiconductor structure; A conductive structure is formed extending along a first direction and spaced apart along a second direction, the conductive structure being located on the side of the first semiconductor structure away from the second semiconductor structure; the conductive structure includes a plurality of first conductive structures at least coupled to the second semiconductor structure and second conductive structures located between adjacent first conductive structures and coupled to the first electrode plate; The first electrode plate is located between the second conductive structure and the plurality of capacitor structures; the first contact structure extends along a third direction and is located on one side of the first electrode plate along the first direction, and the first end and the second end of the first contact structure opposite each other along the third direction are respectively coupled to the second conductive structure and the second semiconductor structure; Wherein, the first direction and the second direction are both parallel to the surface of the first electrode plate, the third direction is perpendicular to the surface of the first electrode plate, and the first direction intersects the second direction.

15. The method according to claim 14, characterized in that, Along the second direction, the sum of the dimensions of the plurality of first conductive structures is greater than or equal to the sum of the dimensions of all second conductive structures.

16. The method according to claim 14, characterized in that, The formation of the conductive structure extending along a first direction and spaced apart along a second direction includes: A plurality of through holes are formed on the side of the first semiconductor structure away from the second semiconductor structure, exposing a portion of the first electrode plate; the plurality of through holes are arranged at intervals along the first direction; The plurality of through holes are filled with a first conductive material to form a plurality of conductive pillars; A plurality of first trenches and a second trench located between adjacent first trenches are formed on the side of the first semiconductor structure away from the second semiconductor structure, which are spaced apart along the second direction; both the first trenches and the second trenches extend along the first direction, and the second trenches expose the surface of the conductive pillars; A second conductive material is filled into the plurality of first trenches and second trenches to form a second conductive layer of the first conductive structure and a first conductive layer of the second conductive structure, respectively.

17. The method according to claim 16, characterized in that, Along the second direction, the sum of the dimensions of the plurality of first trenches is greater than or equal to the sum of the dimensions of all second trenches.

18. The method according to claim 17, characterized in that, Along the second direction, the ratio of the sum of the dimensions of the plurality of first grooves to the sum of the dimensions of all second grooves ranges from 1 to 2.

19. The method according to claim 16, characterized in that, Along the third direction, the ratio between the size of the second trench and the size of the through hole ranges from 7 to 8; Along the third direction, the ratio between the size of the second trench and the size of the first electrode plate ranges from 30 to 45.

20. The method according to claim 14, characterized in that, The formation of the first semiconductor structure further includes: Forming a vertical channel structure; A gate structure is formed on at least one side of the vertical channel structure; A source and a drain are formed, the source and the drain being located on opposite sides of the vertical channel structure along the thickness direction of the first electrode plate; The capacitor structure is formed and connected to one of the source or the drain.

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