A semiconductor device, a manufacturing method thereof, and an electronic device

Abstract

Embodiments of the present disclosure provide a semiconductor device and a preparation method thereof, and an electronic device. The semiconductor device comprises a plurality of memory cells distributed in different layers and stacked along a first direction, wherein each memory cell comprises a transistor comprising a semiconductor layer, the semiconductor layer forms a first ring along a second direction and forms a second ring along a third direction, the second direction and the third direction are perpendicular to the first direction, and a word line extending along the third direction and surrounding the second ring of the semiconductor layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method, and an electronic device. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that small differences in the manufacturing process may affect the performance of the devices.

[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0004] In view of the above, this disclosure provides a semiconductor device and a method for fabricating the same, as well as an electronic device.

[0005] To achieve the above objectives, the technical solution disclosed herein is implemented as follows:

[0006] In a first aspect, embodiments of this disclosure provide a semiconductor device, comprising: a plurality of memory cells distributed on different layers and stacked along a first direction; each memory cell including a transistor, the transistor including a semiconductor layer; the semiconductor layer forming a first ring along a second direction, and the semiconductor layer forming a second ring along a third direction; the second direction and the third direction intersect and are both perpendicular to the first direction; word lines extending along the third direction; the word lines surrounding the second ring of the semiconductor layer.

[0007] In some embodiments, the system further includes: a bit line and a memory structure; one end of the first ring of the semiconductor layer is connected to the bit line, and the other end is connected to the memory structure.

[0008] In some embodiments, the system further includes: an isolation structure located between two adjacent bit lines along the third direction and between the word line and the memory structure; a fourth fill layer within the first and second rings of the semiconductor layer, the semiconductor layer having an opening, the fourth fill layer being connected to the isolation structure via the opening.

[0009] In some embodiments, the word line includes a gate surrounding a channel region of the semiconductor layer and a connection electrode between adjacent gates along the third direction.

[0010] In some embodiments, the semiconductor layer has a recessed region in the third direction that is recessed toward the interior of the semiconductor layer, and the gate has a protruding region in the third direction that is protruding toward the semiconductor layer, wherein the protruding region of the gate is fitted with the recessed region of the semiconductor layer.

[0011] In some embodiments, the device further includes: a gate dielectric layer located between the semiconductor layer and the gate; the gate dielectric layer surrounding the second ring of the semiconductor layer.

[0012] In some embodiments, the bit line extends along the first direction; a plurality of memory cells arranged along the first direction are connected to the same bit line, and two adjacent memory cells along the second direction are connected to the same bit line.

[0013] In some embodiments, the memory structure includes: a first electrode, a dielectric layer, and a second electrode; the first electrodes in the memory structures of different layers are spaced apart in a first direction; the first electrode includes a recess away from the semiconductor layer, and two adjacent first electrodes along the first direction have a first gap, the dielectric layer and the second electrode are formed in the recess and the first gap; the dielectric layer covers two surfaces of the first electrode opposite to each other along the first direction; the first electrode is connected to the first annular connection of the semiconductor layer; the second electrodes of the plurality of memory structures arranged along the first direction are connected to form an integral structure.

[0014] In some embodiments, the second electrode includes a first conductive layer and a second conductive layer, wherein the first conductive layer and the second conductive layer are made of different materials.

[0015] In some embodiments, the semiconductor layer has a dimension in the third direction that is larger than the bit line has a dimension in the third direction.

[0016] In some embodiments, the size of the semiconductor layer in the third direction is greater than the size of the semiconductor layer in the second direction.

[0017] In a second aspect, embodiments of this disclosure provide a method for fabricating a semiconductor device, comprising: providing a substrate, the substrate including a substrate and a stacked structure formed on the substrate, the stacked structure including a first insulating layer and a second insulating layer alternately disposed along a first direction; forming a first trench penetrating the stacked structure and extending along a third direction; laterally etching the first insulating layer based on the first trench to form a plurality of first lateral grooves extending along the third direction and spaced apart along the first direction; forming an initial word line structure within the first lateral grooves; forming a capacitor hole penetrating the stacked structure on one side of the first trench along a second direction, and transmitting the first insulating layer through the capacitor hole. The edge layer is laterally etched to form first capacitor grooves on both sides of the capacitor hole. The initial word line structure is etched through the first capacitor grooves to form a double-layer word line structure. An isolation hole is formed through the stacked structure. The double-layer word line structure is partially etched through the isolation hole to form a word line groove. A connecting word line structure is formed in the word line groove. The connecting word line structure and the remaining double-layer word line structure constitute a word line. A semiconductor layer is formed in the remaining space of the first lateral groove. The semiconductor layer forms a first ring along a second direction and a second ring along a third direction. The word line surrounds the second ring of the semiconductor layer.

[0018] In some embodiments, forming an initial word line structure within the first lateral groove includes: sequentially forming a gate structure layer and a first fill layer within the first lateral groove, wherein the gate structure layer and the first fill layer constitute the initial word line structure.

[0019] In some embodiments, before forming a capacitor hole penetrating the stacked structure on one side of the first trench along the second direction, the method further includes: forming a second filling layer in the first trench; forming a plurality of first etch holes extending along a first direction and spaced apart along a third direction in the second filling layer; and laterally etching the first filling layer in the initial gate structure through the first etch holes to form a second lateral groove located on both sides of the first etch holes.

[0020] In some embodiments, the method further includes: filling the first etched hole and the second lateral groove to form a third filler layer; removing the third filler layer in the first etched hole and forming a bit line in the first etched hole.

[0021] In some embodiments, before forming a capacitor via through the stacked structure on one side of the first trench along the second direction, the method further includes: forming an isolation via through the stacked structure; etching the gate structure layer in the exposed initial gate structure through the isolation via; and forming a first sacrificial structure within the isolation via.

[0022] In some embodiments, etching the initial word line structure through the first capacitor groove to form a double-layer word line structure includes: etching the gate structure layer in the initial word line structure through the first capacitor groove, such that the gate structure layers covering the sidewalls of the first fill layer are disconnected from each other to form a first gate structure layer and a second gate structure layer, wherein the first gate structure layer, the second gate structure layer and the remaining first fill layer constitute the double-layer word line structure.

[0023] In some embodiments, before forming an isolation hole through the stacked structure, the method further includes: etching the exposed first filling layer through the first capacitor groove to expose the third filling layer to form a fourth lateral groove; forming a seventh filling layer in the fourth lateral groove; and forming a first electrode in the first capacitor groove.

[0024] In some embodiments, forming an isolation hole through the stacked structure includes removing the first sacrificial structure within the isolation hole.

[0025] In some embodiments, partially etching the dual-layer word line structure through the isolation via to form a word line groove includes: removing the remaining first filler layer in the dual-layer word line structure through the isolation via, and etching away a portion of the first gate structure layer and the second gate structure layer to form a word line groove; the first gate structure layer includes a first gate layer and a first gate dielectric layer, and the second gate structure layer includes a second gate layer and a second gate dielectric layer; forming a connecting word line structure within the word line groove includes: filling the word line groove with a gate dielectric material to form a third gate dielectric layer, etching the gate dielectric material to expose the first gate layer and the second gate layer, filling with gate material to form a third gate layer, and the third gate layer and the remaining third gate dielectric layer constituting the connecting word line structure.

[0026] In some embodiments, forming a semiconductor layer in the remaining space of the first transverse groove includes: removing the third filler layer and the seventh filler layer through the isolation hole to form a third transverse groove; forming a semiconductor layer on the inner wall of the third transverse groove and filling it to form a fourth filler layer; connecting one end of the first annulus of the semiconductor layer to the bit line and the other end to the first electrode; and forming an isolation structure in the isolation hole.

[0027] In some embodiments, forming a first electrode within the first capacitor recess includes: forming a first electrode in the capacitor hole and the inner wall of the first capacitor recess and filling it to form a fifth filling layer; removing the first electrode and the fifth filling layer from the capacitor hole; and forming a second sacrificial structure within the capacitor hole.

[0028] In some embodiments, the method further includes: removing the second sacrificial structure within the capacitor hole; removing the fifth filling layer within the first capacitor groove through the capacitor hole to form a second capacitor groove; partially etching the exposed isolation structure through the capacitor hole to form a third capacitor groove; and sequentially forming a dielectric layer and a second electrode within the capacitor hole, the second capacitor groove, and the third capacitor groove; wherein the first electrode, the dielectric layer, and the second electrode constitute a storage structure.

[0029] Thirdly, embodiments of this disclosure provide an electronic device, including any of the semiconductor devices described in the first aspect, or a semiconductor device manufactured according to the method for manufacturing a semiconductor device described in any of the second aspects.

[0030] This disclosure provides a semiconductor device and its fabrication method, as well as an electronic device. The semiconductor device includes: a plurality of memory cells distributed in different layers and stacked along a first direction; each memory cell includes a transistor, and each transistor includes a semiconductor layer; the semiconductor layer forms a first ring along a second direction, and the semiconductor layer forms a second ring along a third direction; the second direction and the third direction intersect and are both perpendicular to the first direction; word lines extend along the third direction, and the word lines surround the second ring of the semiconductor layer. In the semiconductor device provided by this disclosure, the semiconductor layer forms ring structures along the second direction and the third direction, respectively, thereby increasing the contact area with the bit lines and the memory structure, reducing contact resistance, and improving the performance of the memory structure and the transistor. Furthermore, in this embodiment, the transistor adopts a ring gate structure (word lines are arranged around the semiconductor layer), which enhances the gate control capability to achieve better switching control of the channel. Attached Figure Description

[0031] Figure 1 A schematic diagram illustrating the steps of a method for fabricating a semiconductor device according to an embodiment of this disclosure;

[0032] Figure 2A and Figure 2B Schematic diagram of the structure in the process of fabricating the semiconductor device provided in the embodiments of this disclosure. Figure 1 ;

[0033] Figure 3A and Figure 3B Schematic diagram 2 of the process for fabricating a semiconductor device according to an embodiment of this disclosure;

[0034] Figure 4A and Figure 4B Schematic diagram three showing the structure of the semiconductor device fabrication method provided in this embodiment of the disclosure;

[0035] Figure 5A and Figure 5B Schematic diagram four illustrating the structure of the semiconductor device fabrication method provided in this embodiment of the disclosure;

[0036] Figure 6A and Figure 6B Five are schematic diagrams illustrating the structure of the semiconductor device fabrication method provided in this embodiment of the disclosure.

[0037] Figure 7A and Figure 7B Sixth schematic diagram of the structure in the process of fabricating the semiconductor device provided in the embodiments of this disclosure;

[0038] Figure 8A and Figure 8B Schematic diagram seven showing the structure of the semiconductor device fabrication method provided in this embodiment of the disclosure;

[0039] Figure 9A and Figure 9B Eight is a schematic diagram of the structure in the process of fabricating a semiconductor device according to an embodiment of this disclosure;

[0040] Figure 10A and Figure 10B Schematic diagram nine illustrating the structure of the semiconductor device fabrication method provided in this embodiment of the disclosure;

[0041] Figure 11A and Figure 11B A schematic diagram of the structure in the process of fabricating the semiconductor device provided in the embodiments of this disclosure;

[0042] Figure 12A and Figure 12B 11. Schematic diagram of the structure in the process of fabricating the semiconductor device provided in the embodiments of this disclosure;

[0043] Figure 13A and Figure 13B Schematic diagram twelve illustrating the structure of the semiconductor device fabrication method provided in this embodiment of the disclosure; Figures 2A to 13B In Figure B, (a) is a cross-sectional view of the structure shown in Figure A along line AA', (b) is a cross-sectional view of the structure shown in Figure A along line BB', (c) is a cross-sectional view of the structure shown in Figure A along line CC', (d) is a cross-sectional view of the structure shown in Figure A along line DD', (e) is a cross-sectional view of the structure shown in Figure A along line EE', and (f) is a cross-sectional view of the structure shown in Figure A along line FF'.

[0044] Figure 14 This is a three-dimensional schematic diagram of a semiconductor device provided in an embodiment of this disclosure. Detailed Implementation

[0045] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0046] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0047] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0048] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0049] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0050] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0051] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0052] This disclosure provides a semiconductor device, including: a plurality of memory cells distributed on different layers and stacked along a first direction; each memory cell including a transistor, the transistor including a semiconductor layer; the semiconductor layer forming a first ring along a second direction, and the semiconductor layer forming a second ring along a third direction; the second direction and the third direction intersect and are both perpendicular to the first direction; a word line extending along the third direction; the word line surrounding the second ring of the semiconductor layer.

[0053] In this embodiment, the semiconductor layer forms a ring structure along the second direction and the third direction, respectively, thereby increasing the contact area with the bit line and the memory structure, reducing the contact resistance, and improving the performance of the memory structure and the transistor.

[0054] In this embodiment, the word line serves as the gate of the transistor, surrounding the semiconductor layer. This means the transistor gate has a ring-gate structure. The ring-gate structure effectively surrounds the channel region of the semiconductor layer on all four sides, significantly mitigating issues such as leakage current, capacitance effects, and short-channel effects caused by reduced gate pitch, thus enhancing gate control performance. Furthermore, the ring-gate structure reduces the word line resistance of each memory cell and greatly shields interference from adjacent memory cells, reducing or eliminating parasitic MOS capacitance. In other words, this embodiment eliminates the need for additional parasitic MOS removal steps, thereby significantly reducing process complexity.

[0055] In this embodiment of the disclosure, multiple storage cells can be arranged in a single layer or stacked in multiple layers along a first direction. The storage cells in each layer can be distributed in an array along a second direction and a third direction.

[0056] The memory cells in the semiconductor device provided in this disclosure can not only be stacked in a direction perpendicular to the substrate, but also arranged in an array in a plane parallel to the substrate, which is beneficial to improving the integration density of the memory cells.

[0057] Figure 1 This is a schematic diagram illustrating the steps of a method for fabricating a semiconductor device according to an embodiment of this disclosure. Figure 1 As shown, the preparation method includes the following steps:

[0058] Step S101: Provide a substrate, the substrate including a substrate and a stacked structure formed on the substrate, the stacked structure including an alternately arranged first insulating layer and a second insulating layer.

[0059] Step S102: Form a first trench that penetrates the stacked structure and extends along a third direction.

[0060] Step S103: Based on the first trench, the first insulating layer is etched laterally to form a plurality of first transverse grooves that extend along a third direction and are spaced apart along the first direction.

[0061] Step S104: Form the initial letter line structure within the first horizontal groove.

[0062] Step S105: A capacitor hole is formed through the stacked structure on one side of the first trench along the second direction. The first insulating layer is laterally etched through the capacitor hole to form a first capacitor groove located on both sides of the capacitor hole. The initial word line structure is etched through the first capacitor groove to form a double-layer word line structure.

[0063] Step S106: Form an isolation hole through the stacked structure, and partially etch the double-layer word line structure through the isolation hole to form word line grooves.

[0064] Step S107: A connecting character line structure is formed in the character line groove. The connecting character line structure and the remaining double-layer character line structure constitute the character line.

[0065] Step S108: A semiconductor layer is formed in the remaining space of the first transverse groove. The semiconductor layer forms a first ring along the second direction and a second ring along the third direction. Word lines surround the second ring of the semiconductor layer.

[0066] It should be understood that Figure 1 The steps shown are not exclusive, and other steps may be performed before, after, or between any of the steps shown.

[0067] In some embodiments, step S104 includes: sequentially forming a gate structure layer and a first fill layer in the first lateral groove, wherein the gate structure layer and the first fill layer constitute the initial word line structure.

[0068] In some embodiments, prior to step S105, the method further includes: forming a second filling layer in the first trench; forming a plurality of first etching holes extending along a first direction and spaced apart along a third direction in the second filling layer; and laterally etching the first filling layer in the initial gate structure through the first etching holes to form a second lateral groove located on both sides of the first etching holes.

[0069] In some embodiments, the method further includes: filling the first etched hole and the second lateral groove to form a third filler layer; removing the third filler layer in the first etched hole and forming a bit line in the first etched hole.

[0070] In some embodiments, prior to step S105, the method further includes: forming an isolation via through the stacked structure; etching the gate structure layer in the exposed initial gate structure through the isolation via; and forming a first sacrificial structure within the isolation via.

[0071] In some embodiments, step S105 includes: etching the gate structure layer in the initial word line structure through the first capacitor groove, such that the gate structure layers covering the sidewalls of the first fill layer are disconnected from each other to form a first gate structure layer and a second gate structure layer, wherein the first gate structure layer, the second gate structure layer and the remaining first fill layer constitute the dual-layer word line structure.

[0072] In some embodiments, before forming an isolation hole through the stacked structure, the method further includes: etching the exposed first filling layer through the first capacitor groove to expose the third filling layer to form a fourth lateral groove; forming a seventh filling layer in the fourth lateral groove; and forming a first electrode in the first capacitor groove.

[0073] In some embodiments, forming an isolation hole through the stacked structure includes removing the first sacrificial structure within the isolation hole.

[0074] In some embodiments, step S106 includes: removing the remaining first fill layer in the dual-layer word line structure through the isolation via, and etching away a portion of the first gate structure layer and the second gate structure layer to form a word line groove; the first gate structure layer includes a first gate layer and a first gate dielectric layer, and the second gate structure layer includes a second gate layer and a second gate dielectric layer.

[0075] In some embodiments, step S107 includes: filling the word line groove with gate dielectric material to form a third gate dielectric layer, etching the gate dielectric material to expose the first gate layer and the second gate layer, filling the gate material to form a third gate layer, wherein the third gate layer and the remaining third gate dielectric layer constitute the connection word line structure.

[0076] In some embodiments, step S108 includes: removing the remaining third filler layer and the seventh filler layer through the isolation hole to form a third lateral groove; forming a semiconductor layer on the inner wall of the third lateral groove and filling it to form a fourth filler layer; connecting one end of the first annulus of the semiconductor layer to the bit line and the other end to the first electrode; and forming an isolation structure in the isolation hole.

[0077] In some embodiments, forming a first electrode within the first capacitor recess includes: forming a first electrode in the capacitor hole and the inner wall of the first capacitor recess and filling it to form a fifth filling layer; removing the first electrode and the fifth filling layer from the capacitor hole; and forming a second sacrificial structure within the capacitor hole.

[0078] In some embodiments, the method further includes: removing the second sacrificial structure within the capacitor hole; removing the fifth filling layer within the first capacitor groove through the capacitor hole to form a second capacitor groove; partially etching the exposed isolation structure through the capacitor hole to form a third capacitor groove; and sequentially forming a dielectric layer and a second electrode within the capacitor hole, the second capacitor groove, and the third capacitor groove; wherein the first electrode, the dielectric layer, and the second electrode constitute a storage structure.

[0079] In some embodiments, the material of the semiconductor layer includes a metal oxide semiconductor, wherein the metal oxide semiconductor includes at least one element selected from indium, gallium, zinc, tin, and tungsten.

[0080] It should be noted that in the above embodiments, the execution order of the steps in the method is not strictly limited. These steps may not necessarily be executed in the described order, and may be executed in other ways. Moreover, at least a portion of any step may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but may be executed alternately or in turn with other steps or at least a portion of the sub-steps or stages of other steps. The method is limited to the ability to fabricate the corresponding semiconductor device.

[0081] Figures 2A to 13A This is a three-dimensional structural schematic diagram of the semiconductor device fabrication method provided in the embodiments of this disclosure. Figures 2B to 13B This is a schematic cross-sectional view of the semiconductor device fabrication method provided in this embodiment of the disclosure. Figures 2B to 13B Figure (a) shows a cross-sectional view of the structure shown in the three-dimensional schematic diagram along line AA'; Figure (b) shows a cross-sectional view of the structure shown in the three-dimensional schematic diagram along line BB'; Figure (c) shows a cross-sectional view of the structure shown in the three-dimensional schematic diagram along line CC'; Figure (d) shows a cross-sectional view of the structure shown in the three-dimensional schematic diagram along line DD'; Figure (e) shows a cross-sectional view of the structure shown in the three-dimensional schematic diagram along line EE'; and Figure (f) shows a cross-sectional view of the structure shown in the three-dimensional schematic diagram along line FF'. It should be noted that... Figures 2A to 13B This is a schematic diagram illustrating the complete fabrication process of a semiconductor device. Unmarked parts in some of the accompanying drawings can be shared. The following section will discuss this further. Figure 1 , Figures 2A to 13B The method for fabricating the semiconductor device provided in the embodiments of this disclosure will be described in detail.

[0082] It should be noted that, for ease of description, the various directions that may be used in the following description are first defined. A first direction (Z direction) is defined in a plane perpendicular to the substrate, and a second direction (X direction) and a third direction (Y direction) are defined in a plane parallel to the substrate. The X, Y, and Z directions can be mutually perpendicular. The third direction (Y direction) is the extension direction of the word line, and the first direction (Z direction) is the extension direction of the bit line.

[0083] The deposition processes involved in the embodiments of this disclosure include, but are not limited to: chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), sputtering, metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), and combinations thereof.

[0084] The etching processes involved in the embodiments of this disclosure include, but are not limited to, dry etching, wet etching, and combinations thereof.

[0085] The "patterning process" involved in the embodiments of this disclosure includes processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping, which are mature manufacturing processes in related technologies. Deposition can be performed using known processes such as sputtering, evaporation, and chemical vapor deposition; coating can be performed using known coating processes; and etching can be performed using known methods. No specific limitations are made here.

[0086] The semiconductor structure disclosed herein is at least a portion of the structure that will be used in subsequent processes to form the final device structure. Here, the final device may be a memory, such as DRAM, or other memory chips or processing chips containing DRAM memory cells.

[0087] refer to Figure 2A and Figure 2B A substrate is provided, the substrate including a substrate 1 and a stacked structure 20 formed on the substrate, the stacked structure 20 including a first insulating layer 21 and a second insulating layer 22 alternately disposed along a first direction.

[0088] In some embodiments, the method of forming a substrate includes: providing a substrate 1 and alternatingly stacking a first insulating layer 21 and a second insulating layer 22 on the substrate 1 by a deposition process to form a stacked structure 20.

[0089] In some embodiments, to avoid electrical connection between multiple rows of memory cells through the substrate 1, at least one isolation layer may be included between the substrate 1 and the stacked structure 20. The material of the isolation layer is an insulating material. For example, the isolation layer between the substrate 1 and the stacked structure 20 may be a second insulating layer 22.

[0090] It should be noted that, in this embodiment of the disclosure, identical structures located in the same layer (or in the same stacking layer) and arranged along a third direction (Y direction) are called rows, and identical structures arranged along a second direction (X direction) are called columns. For example, storage cells arranged along a third direction (Y direction) and located in the same layer are called storage cell rows or rows of storage cells, and storage cells arranged along the second direction (X direction) are called storage cell columns or columns of storage cells.

[0091] For example, the first insulating layer 21 and the second insulating layer 22 may have the same thickness or different thicknesses, and neither of them may be zero. The first insulating layer 21 may be formed of silicon nitride, and the second insulating layer 22 may be formed of silicon oxide, such that the stacked structure 20 is a nitride-oxide (NO) stack. It should be noted that... Figure 2A and Figure 2B The number of layers of the first insulating layer 21 and the second insulating layer 22 in the stacked structure 20 shown in the figure is only an example, and the specific number of layers of the first insulating layer 21 and the second insulating layer 22 in this disclosure is not limited to the number of layers shown in the figure.

[0092] This disclosure does not specifically limit the constituent materials of substrate 1. Exemplarily, substrate 1 can be composed of semiconductor materials, insulating materials, conductive materials, or any combination thereof. The substrate can be a single-layer structure or a multi-layer structure. For example, the substrate can be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, the substrate can be a layered substrate including, for example, a stack of Si and SiGe, a stack of Si and SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.

[0093] Continue to refer to Figure 2A and Figure 2B A first trench 31 is formed, penetrating the stacked structure 20 and extending in a third direction. The first insulating layer 21 is laterally etched through the first trench 31 to form first lateral grooves located on both sides of the first trench 31. The first trench 31 and the first lateral grooves constitute a first etched trench. At this time, the size of the first etched trench in the first insulating layer is larger than the size of the first etched trench in the second insulating layer. A gate structure layer is deposited on the inner wall of the first trench 31 and the first lateral groove, and a first filler layer 41 is formed by filling the first trench 31 and the first lateral groove. The gate structure layer and the first filler layer 42 within the first trench 31 are etched away, thereby ultimately forming an initial word line structure 40 from the gate structure layer and the first filler layer 41 located within the first lateral groove.

[0094] In some embodiments, the first trench can be formed by a patterning process, such as forming a hard mask layer and a patterned photoresist layer on the stacked structure 20, and etching the hard mask layer and the stacked structure 20 through the patterned photoresist layer to form a first trench 31 that penetrates the stacked structure 20 and extends in a third direction.

[0095] It should be noted that the number of first grooves shown in Figure 2 is only an example, and this disclosure does not limit the number of first grooves.

[0096] Here, the first transverse groove is used to define the forming area of ​​the character line, which includes a double-layer character line structure and a connecting character line structure, wherein the double-layer character line structure and the connecting character line structure are formed in different process steps. Since the first groove 31 extends along the third direction (Y direction), the first transverse groove also extends along the third direction (Y direction), and the first transverse grooves of different layers are isolated by the second insulating layer 22.

[0097] In some embodiments, the gate structure layer includes a gate layer 42 and a gate dielectric layer 43. The first fill layer 41, the gate layer 42, and the gate dielectric layer 43 within the first lateral groove constitute an initial word line structure 40.

[0098] For example, the material of the first filling layer 41 can be a conductive material or a non-conductive material different from the second insulating layer 22. The conductive material can be, for example, polysilicon.

[0099] For example, the material of the gate layer 42 can be any one or more of the following different types of materials: for example, metals containing tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it can be a metal alloy containing the aforementioned metals; it can also be a metal oxide, metal nitride, metal silicide, metal carbide, etc., such as highly conductive metal oxide materials like indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO); for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN); of course, it can also be a polycrystalline silicon material; it can also be a conductive material doped with a semiconductor material, such as conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc.; other materials that exhibit conductivity, etc.

[0100] For example, the gate dielectric layer 43 can be made of a high-k dielectric material, such as a dielectric material with a dielectric constant K greater than or equal to 3.9. This includes, but is not limited to, high-k materials such as hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), and zirconium oxide (ZrO2). The gate dielectric layer can be a single-layer or multi-layer structure. For example, it can include a two-layer structure formed of silicon oxide and hafnium oxide, wherein the silicon oxide layer contacts the channel region, and the hafnium oxide layer contacts the gate. The thickness of the gate dielectric layer can be set according to actual electrical requirements.

[0101] It should be noted that after the filling step, a post-processing step of planarizing the current structure is included to ensure that the top of the current structure is flat. This disclosure does not limit the planarization post-processing method; for example, planarization can be achieved based on a chemical mechanical polishing (CMP) process.

[0102] refer to Figure 3A and Figure 3B A second filling layer 44 is formed in the first trench 31; the second filling layer 44 is patterned by a patterning process to form a plurality of first etch holes 32 extending along the first direction and spaced apart along the third direction in the second filling layer 44; the first filling layer 41 in the initial gate structure 40 is partially etched through the first etch holes 32 to form a second lateral groove 33 located on both sides of the first etch holes 32.

[0103] For example, the material of the second filling layer 44 can be an insulating material. Insulating materials include, but are not limited to, silicon oxides, such as silicon dioxide (SiO2).

[0104] It should be noted that the spacing arrangement can be understood as a separate arrangement, which can be achieved by physical structural separation or electrical separation. For example, two adjacent first etched holes 32 are insulated by the remaining second filler layer 44 to achieve physical structural separation.

[0105] refer to Figure 4A and Figure 4B A third filling layer 45 is formed by filling the first etched hole 32 and the second transverse groove 33; the third filling layer 45 in the first etched hole 32 is removed, and a bit line 50 is formed in the first etched hole 32.

[0106] In some embodiments, the material of the third filler layer 45 is different from the material of the first filler layer 41.

[0107] For example, the material of the third filler layer 45 can be an insulating material. Insulating materials include, but are not limited to, silicon nitrides, such as silicon nitride (Si3N4).

[0108] In some embodiments, the material of bit line 50 may be the same as the material of gate layer 42.

[0109] For example, the material of bit line 50 includes a conductive material, including but not limited to any one or more of titanium (Ti), titanium nitride (TiN), and tungsten (W).

[0110] refer to Figure 5A and Figure 5B An isolation hole 34 is formed through the stacked structure 20; the gate structure layer in the exposed initial gate structure 40 is etched through the isolation hole 34.

[0111] In some embodiments, the isolation hole 34 may include an etched hole located within the first trench 31 and etched trenches located on both sides of the first trench 31 along a second direction; in other words, the etched hole and the etched trenches together constitute the isolation hole 34. Here, the isolation hole 34 is used to define the formation area of ​​the isolation structure. The isolation structure is used to achieve isolation between rows of memory cells.

[0112] In some embodiments, etching the gate structure layer in the exposed initial gate structure 40 through the isolation via 34 includes etching the exposed gate layer 42 and gate dielectric layer 43 through the isolation via 34 to expose the first filling layer 41.

[0113] refer to Figure 6A and Figure 6B A first sacrificial structure is formed within the isolation hole 34. A capacitor hole 35 penetrating the stacked structure 20 is formed on one side of the first etched hole along the second direction. The first insulating layer 21 is laterally etched through the capacitor hole 35 to form a first capacitor groove 36. The gate structure layer in the initial word line structure 40 is etched through the first capacitor groove 36, so that the gate structure layers covering the sidewall of the first filling layer 41 are disconnected from each other to form a first gate structure layer 48 and a second gate structure layer 49. The first gate structure layer 48, the second gate structure layer 49 and the remaining first filling layer 41 constitute a double-layer word line structure.

[0114] In some embodiments, the first sacrificial structure includes a first sacrificial layer 46 and a sixth filling layer 47. Forming the first sacrificial structure within the isolation hole 34 includes: depositing the first sacrificial layer 46 on the inner wall of the isolation hole 34 within the first trench, and filling the isolation holes 34 on both sides of the first trench 31 to form the sixth filling layer 47.

[0115] For example, the material of the first sacrificial layer 46 includes an insulating material. The insulating material includes, but is not limited to, silicon oxide, such as silicon oxide (SiO2).

[0116] For example, the material of the sixth filling layer 47 can be a conductive material. The conductive material can be, for example, polysilicon.

[0117] In some embodiments, the capacitor holes 35 are arranged in an array in the stacked structure, specifically including a plurality of capacitor holes 35 arranged along the second direction (X direction) and a plurality of capacitor holes 35 arranged along the third direction (Y direction). It should be noted that... Figure 6A and Figure 6B The number of capacitor holes 35 shown in the illustration is merely an example, and the number of capacitor holes 35 in this disclosure is not limited to this. Figure 6A and Figure 6B The quantity shown.

[0118] Here, the capacitor hole 35 and the first capacitor recess 36 are used to define the formation area of ​​the storage structure.

[0119] Combination Figure 5A , Figure 5B , Figure 6A and Figure 6B The gate structure layer in the formation region of the isolation structure is disconnected by etching the gate structure layer through the isolation hole 34, and the gate structure layer in the formation region of the memory structure is disconnected by etching the gate structure layer through the first capacitor groove 36, thereby achieving the complete disconnection of the gate structure layer covering the sidewall of the first filling layer 41.

[0120] Continue to refer to Figure 6A and Figure 6B After the gate structure layer covering the sidewall of the first filling layer 41 is etched away, the first filling layer 41 is exposed, and the exposed first filling layer 41 can be etched through the first capacitor groove 36.

[0121] refer to Figure 7A and Figure 7B The first filling layer 41 is etched through the first capacitor groove 36 to expose the third filling layer 45 to form a fourth transverse groove, and a seventh filling layer 51 is formed in the fourth transverse groove.

[0122] In some embodiments, the seventh filler layer 51 and the third filler layer 45 are made of the same material, thus the seventh filler layer 51 and the third filler layer 45 can be regarded as an integral structure 71. In this embodiment, "A and B are an integral structure" can mean that there are no obvious boundaries such as discontinuities or gaps in the microstructure. Generally, an integral structure is a film layer patterned to form a connected film layer. For example, A and B use the same material to form a single film layer and are simultaneously formed into a connected structure through the same patterning process.

[0123] Continue to refer to Figure 7A and Figure 7B A first electrode 52 is formed on the inner wall of the capacitor hole 35 and the first capacitor groove 36, and a fifth filling layer 53 is formed therein; the first electrode 52 and the fifth filling layer 53 in the capacitor hole 35 are removed.

[0124] refer to Figure 8A and Figure 8B A second sacrificial structure is formed within the capacitor hole 35, and the first sacrificial structure within the isolation hole 34 is removed.

[0125] In some embodiments, the second sacrificial structure includes a second sacrificial layer 54 and an eighth filler layer 55. Forming the second sacrificial structure within the capacitor hole 35 includes: depositing and forming the second sacrificial layer 54 on the inner wall of the capacitor hole 35, and filling the capacitor hole 35 to form the eighth filler layer 55.

[0126] For example, the material of the second sacrificial layer 54 includes an insulating material. The insulating material includes, but is not limited to, silicon oxide, such as silicon oxide (SiO2).

[0127] For example, the material of the eighth filler layer 55 can be a conductive material. The conductive material can be, for example, polysilicon.

[0128] In some embodiments, removing the first sacrificial structure in the isolation via 34 includes: exposing the first sacrificial structure through a patterning process, and then etching away the first sacrificial layer 46 and the sixth filling layer 47 in the isolation via 34. The step of removing the first sacrificial structure in the isolation via described above can be understood as the step of reopening the isolation via.

[0129] refer to Figure 9A and Figure 9BThe remaining first filler layer 41 in the dual-layer word line structure is removed through the isolation via 34, and a portion of the first gate structure layer 48 and the second gate structure layer 49 is etched away to form a word line recess. The first gate structure layer 48 includes a first gate layer and a first gate dielectric layer, and the second gate structure layer 49 includes a second gate layer and a second gate dielectric layer. A third gate dielectric layer 56 is formed by filling the word line recess with gate dielectric material. The gate dielectric material is etched to expose the first gate layer and the second gate layer, and gate material is filled to form a third gate layer 57. The third gate layer 57 and the remaining third gate dielectric layer 56 constitute a connecting word line structure.

[0130] In some embodiments, the first gate layer, the second gate layer, and the third gate layer 57 are made of the same material, thus the first gate layer, the second gate layer, and the third gate layer 57 can be considered as a single structure 72. The first gate dielectric layer, the second gate dielectric layer, and the third gate dielectric layer 56 are made of the same material, thus the first gate dielectric layer, the second gate dielectric layer, and the third gate dielectric layer 56 can be considered as a single structure 73. The word line structure and the remaining double-layer word line structure constitute a word line.

[0131] Here, the word lines of the ring grid structure are formed, referencing Figure 9B In Figure (e), the integrated structure 72 composed of the first gate layer, the second gate layer and the third gate layer 57 is the gate layer in the ring gate structure, and the integrated structure 73 composed of the first gate dielectric layer, the second gate dielectric layer and the third gate dielectric layer 56 is the gate dielectric layer in the ring gate structure.

[0132] refer to Figure 10A and Figure 10B The first sacrificial layer 46 is etched through the isolation hole 34 to expose the seventh fill layer 51 and the third fill layer 45, and the seventh fill layer 51 and the third fill layer 45 are removed to form the third transverse groove 38.

[0133] Here, the third lateral groove 38 is used to define the transistor formation area.

[0134] refer to Figure 11A and Figure 11B An initial semiconductor layer is formed on the inner wall of the isolation hole 34 and the third transverse groove 38, and an initial fourth filling layer is formed therein. The initial semiconductor layer and the initial fourth filling layer in the isolation hole 34 are etched away, and an isolation structure 58 is formed in the isolation hole 34.

[0135] In some embodiments, the remaining initial semiconductor layer located within the third lateral groove 38 constitutes semiconductor layer 61, and the remaining initial fourth fill layer located within the third lateral groove 38 constitutes fourth fill layer 62. Semiconductor layer 61 forms a first ring 61a and a second ring 61b along the second direction and the third direction, respectively. One end of the first ring 61a of semiconductor layer 61 is connected to bit line 50, and the other end is connected to first electrode 52. Word line surrounds the second ring 61b of semiconductor layer 61.

[0136] For example, the material of the isolation structure 58 is an insulating material. Insulating materials include, but are not limited to, silicon oxides, such as silicon dioxide (SiO2).

[0137] In some embodiments, the material of semiconductor layer 61 includes a metal oxide semiconductor, wherein the metal oxide semiconductor includes at least one element selected from indium, gallium, zinc, tin, and tungsten. The metal oxide semiconductor may also contain compounds of other elements, such as nitrogen (N) and silicon (Si); it may also contain other small amounts of doping elements. Furthermore, compared to other semiconductor materials, using metal oxide semiconductors allows for better control of the manufacturing cost of semiconductor devices.

[0138] In some embodiments, the metal oxide semiconductor material can be indium gallium zinc oxide (IGZO). When the metal oxide material is IGZO, the transistor leakage current is relatively small (leakage current less than or equal to 10). -15A), which ensures a low refresh rate for the storage unit. It should be noted that the metal oxide material can also be ITO or InSnOx (Indium Tin Oxide), IWO or InWO (Indium Tungsten Oxide), ZnOx (Zinc Oxide), InOx (Indium Oxide), In2O3 (Indium Oxide), SnO2 (Tin Dioxide), TiOx (Tin Dioxide), ZnxOyNz (Zinc Nitride Oxide), MgxZnyOz (Magnesium Zinc Oxide), InxZnyOz (Indium Zinc Oxide), InxGayZnzOa (Indium Gallium Zinc Oxide), ZrxInyZnzOa (Zirconium Indium Zinc Oxide), HfxInyZnzOa (Hafnium Indium Zinc Oxide). Indium Zinc Oxide, SnxInyZnzOa (Tin Indium Zinc Oxide), AlxSnyInzZnaOd (Aluminum Tin Indium Zinc Oxide), SixInyZnzOa (Silicon Indium Zinc Oxide), ZnxSnyOz (Zinc Tin Oxide), AlxZnySnzOa (Aluminum Indium Tin Oxide), GaxZnySnzOa (Gallium Indium Tin Oxide), ZrxZnySnzOa (Zirconium Indium Tin Oxide), InGaSiO (Indium Gallium Silicon Oxide), IAZO (Indium Aluminum Zinc Oxide), IGO (Indium Gallium Oxide). Materials such as indium gallium oxide (IGAO), indium zinc oxide (IZO), and indium zinc oxide (IZOx) are acceptable, as long as the leakage current of the transistor meets the requirements. The specific requirements can be adjusted according to the actual situation.

[0139] In some embodiments, the first ring 61a can be regarded as a cross-section of the semiconductor layer 61 along the DD' line, and the second ring 61b can be regarded as a cross-section of the semiconductor layer 61 along the EE' line. The rings of the first ring 61a and the second ring 61b can be rectangular, square, circular or elliptical.

[0140] In some embodiments, the connection points between the semiconductor layer 61 and the bit line 50, the first electrode 52 and the word line are all closed loops; otherwise, the semiconductor layer 61 is not disconnected from the connection points between the bit line 50, the first electrode 52 and the word line.

[0141] In some embodiments, the size of the semiconductor layer 61 in the third direction (Y direction) is larger than the size of the bit line 50 in the third direction (Y direction). Furthermore, the semiconductor layer 61 (first ring 61a) in contact with the bit line 50 is a closed ring, thereby increasing the contact area between the semiconductor layer 61 and the bit line 50 and improving the on-state current.

[0142] In some embodiments, the size of the semiconductor layer 61 in the third direction (Y direction) is larger than the size of the contact surface between the first electrode 52 and the semiconductor layer 61 in the third direction (Y direction). Furthermore, the semiconductor layer 61 (first ring 61a) in contact with the first electrode 52 is a closed ring, thereby increasing the contact area between the semiconductor layer 61 and the first electrode 52 and improving the on-state current.

[0143] In some embodiments, the size of the semiconductor layer 61 in the third direction (Y direction) is larger than the size of the semiconductor layer 61 in the second direction (X direction). This results in a smaller channel distance in the semiconductor layer compared to the ring gate structure, thereby further improving transistor performance.

[0144] In some embodiments, the semiconductor layer 61 is a thin film covering the inner wall of the third lateral groove 38. This avoids the semiconductor layer 61 from becoming too large, thereby improving the channel performance of the transistor.

[0145] In this embodiment, the transistor employs a gate-around structure (the gate surrounds the channel region) to achieve better switching control of the channel.

[0146] In some embodiments, the word line includes a gate surrounding a channel region of semiconductor layer 61 and a connection electrode between adjacent gates along a third direction. It is understood that, since the gate and connection electrode are made of the same material, the gate and connection electrode can also be considered as a single, integral structure 72.

[0147] It should be noted that, in order to show the projected shape of semiconductor layer 61 on substrate 1, Figure 11B The schematic diagram (a) shown in the figure (a cross-sectional view along line AA') is specifically a cross-section of semiconductor layer 61. Reference Figure 11BThe semiconductor layer 61 has a recessed region 61A that is recessed toward the interior of the semiconductor layer in the third direction, and the gate (integrated structure 72) has a raised region 72A that is raised toward the semiconductor layer 61 in the third direction. The raised region 72A of the gate (integrated structure 72) is fitted with the recessed region 61A of the semiconductor layer 61.

[0148] refer to Figure 12A and Figure 12B Remove the second sacrificial structure in the capacitor hole 35, and remove the fifth filling layer 53 in the first capacitor groove through the capacitor hole 35 to form the second capacitor groove 90.

[0149] In some embodiments, removing the second sacrificial structure in the capacitor via 35 includes: exposing the second sacrificial structure through a patterning process, and then etching away the second sacrificial layer 54 and the eighth filling layer 55 in the capacitor via 35. The step of removing the second sacrificial structure in the capacitor via 35 can be understood as reopening the capacitor via.

[0150] It should be noted that, in order to show the projected shape of semiconductor layer 61 on substrate 1, Figure 12B The figure shown in Figure (a) (a cross-sectional view along line AA') is specifically a cross-section of semiconductor layer 61.

[0151] refer to Figure 13A and Figure 13B Partial etching is performed on the isolation structure 58 exposed by the capacitor hole 35 to form a third capacitor groove. A dielectric layer 63 and a second electrode are formed sequentially in the capacitor hole 35, the second capacitor groove 90 and the third capacitor groove. The first electrode 52, the dielectric layer 63 and the second electrode constitute the storage structure.

[0152] In some embodiments, the second electrode includes a first conductive layer 64 and a second conductive layer 65, wherein the first conductive layer 64 and the second conductive layer 65 are made of different materials.

[0153] For example, the first conductive layer 64 is made of titanium nitride, the second conductive layer 65 is made of tungsten, and the second electrode is a stacked structure composed of titanium nitride and tungsten.

[0154] Combination Figures 12A to 13B Each first electrode 52 includes a recess facing the capacitor hole 35, and two adjacent first electrodes 52 along a first direction have a first gap. A dielectric layer 63 and a second electrode are formed between the recesses and in the first gap. This forms a structure as follows: Figure 13B The structure shown in (c) is as follows.

[0155] In this embodiment, the second electrode (first conductive layer 64 and second conductive layer 65) is respectively disposed on the inner and outer sides of the first electrode 52. The resulting storage structure is more compact, the contact area between the electrodes is larger, the storage structure has a larger capacity and a shorter length, which helps to reduce the size of the semiconductor device and also prevents the stacked structure from collapsing during fabrication.

[0156] It should be noted that, in order to show the projected shape of semiconductor layer 61 on substrate 1, Figure 13B The figure shown in Figure (a) (a cross-sectional view along line AA') is specifically a cross-section of semiconductor layer 61.

[0157] In some embodiments, by setting the bit line 50 to extend along a first direction (Z direction) and two adjacent memory cells along a second direction (X direction) to be connected to the same bit line, there is at least a pair of transistors and a pair of memory structures between the two adjacent bit lines 50 along the second direction (X direction). Based on this, the bit line spacing is greatly increased, the coupling between the bit lines is reduced, the bit line capacitance is effectively reduced, and the process complexity is reduced.

[0158] Figure 14 This is a three-dimensional schematic diagram of a semiconductor device provided in an embodiment of the present disclosure, such as... Figure 14 As shown, the semiconductor device includes: a plurality of memory cells distributed on different layers and stacked along a first direction; each memory cell includes a transistor, the transistor including a semiconductor layer 61; the semiconductor layer 61 forms a first ring along a second direction and a second ring along a third direction; the second direction and the third direction intersect and are both perpendicular to the first direction; a word line WL extends along the third direction and surrounds the second ring of the semiconductor layer 61.

[0159] In this embodiment, the transistor employs a gate-around structure (the gate surrounds the channel region) to achieve better switching control of the channel. Furthermore, by connecting the word line structure and the double-layer word line structure to form a word line, the RC delay between word lines can be further reduced, improving the device response rate and thus enhancing the overall device performance.

[0160] In some embodiments, the memory cell further includes a memory structure C, wherein the transistors of the same memory cell and the memory structure C are arranged along a second direction.

[0161] In some embodiments, the system further includes: a bit line 50 extending along the first direction; one end of the first ring of the semiconductor layer 61 is connected to the bit line 50, and the other end is connected to the memory structure C.

[0162] In some embodiments, a plurality of memory cells arranged along the first direction are connected to the same bit line 50, and two adjacent memory cells along the second direction are connected to the same bit line 50.

[0163] In this embodiment of the disclosure, by setting the bit line 50 to extend along the first direction (Z direction) and two adjacent memory cells along the second direction (X direction) to be connected to the same bit line, there is at least a pair of transistors and a pair of memory structures C between the two adjacent bit lines 50 along the second direction (X direction). Based on this, the bit line spacing is greatly increased, the coupling between the bit lines is reduced, the bit line capacitance is effectively reduced, and the process complexity is reduced.

[0164] In some embodiments, the method further includes: an isolation structure located between two adjacent bit lines 50 along the third direction and between the word line WL and the memory structure C; a fourth filling layer is provided within the first ring and the second ring of the semiconductor layer 50, the semiconductor layer 50 having an opening, and the fourth filling layer being connected to the isolation structure via the opening. It should be noted that, in order to illustrate the morphological structure of the transistor and the memory structure C, Figure 14 The isolation structure has been hidden.

[0165] In some embodiments, a gate layer 72 surrounding a channel region of the semiconductor layer is further included, and the gate layers 72 of the memory cells located on the same layer and arranged along the third direction are connected to form the word line WL. In some embodiments, a gate dielectric layer 73 is further included between the gate layer 72 and the semiconductor layer 61, and the gate dielectric layer 73 surrounds the outside of the semiconductor layer 61. Furthermore, the gate dielectric layer 73 surrounds a second ring around the semiconductor layer 61.

[0166] In some embodiments, the word line includes a gate surrounding a channel region of a semiconductor layer and a connection electrode between adjacent gates along a third direction. It is understood that, since the gate and connection electrode are made of the same material, the gate and connection electrode can also be considered as gate layer 72.

[0167] In some embodiments, the semiconductor layer 61 has a recessed region 61A that is recessed toward the interior of the semiconductor layer in a third direction, and the gate (gate layer 72) has a raised region 72A that is raised toward the semiconductor layer in a third direction, and the raised region 72A of the gate (gate layer 72) is fitted with the recessed region 61A of the semiconductor layer 61.

[0168] In some embodiments, first electrodes 52 in memory cells of different layers are spaced apart in a first direction; the first electrodes 52 are connected to one end of the first ring of the semiconductor layer 61; and the second electrodes of the plurality of memory structures arranged along the first direction are connected to form an integral structure.

[0169] In some embodiments, the second electrode includes a first conductive layer 64 and a second conductive layer 65, wherein the first conductive layer 64 and the second conductive layer 65 are made of different materials.

[0170] In some embodiments, a single first electrode 52 includes a recess away from the semiconductor layer 61, and two adjacent first electrodes 52 along a first direction also have a first gap away from the semiconductor layer 61, with a dielectric layer 63 and a second electrode (a first conductive layer 64 and a second conductive layer 65) formed between the recess and in the first gap.

[0171] In this embodiment, the second electrode (first conductive layer 64 and second conductive layer 65) is respectively disposed on the inner and outer sides of the first electrode 52. The resulting storage structure is more compact, the contact area between the electrodes is larger, the storage structure has a larger capacity and a shorter length, which helps to reduce the size of the semiconductor device and also prevents the stacked structure from collapsing during fabrication.

[0172] In some embodiments, the material of the semiconductor layer 61 includes a metal oxide semiconductor, wherein the metal oxide semiconductor includes at least one element selected from indium, gallium, zinc, tin, and tungsten.

[0173] In some embodiments, the semiconductor layer 61 may include two end faces and a side face along the second direction (X direction), with the source contact region and drain contact region located at least on the end faces, and the channel region located at least on the side face. One of the two end faces of the semiconductor layer 61 along the second direction (X direction) is connected to the memory structure C, and the other is connected to the bit line 50. The side face (channel region) of the semiconductor layer is surrounded by the gate layer 72. In a specific example, the region of the semiconductor layer 61 that contacts the first electrode 52 of the memory structure C is the source contact region, and the region of the semiconductor layer 61 that contacts the bit line 50 is the drain contact region.

[0174] In a specific example, the first electrode 52 of the memory structure C can be connected to the source contact area of ​​the semiconductor layer 61 to form a memory node (SN); then the bit line 50 is connected to the drain contact area of ​​the semiconductor layer 61.

[0175] In some embodiments, the size of the semiconductor layer 61 in the third direction (Y direction) is larger than the size of the bit line 50 in the third direction (Y direction). Furthermore, the semiconductor layer 61 (first ring 61a) in contact with the bit line 50 is a closed ring, thereby increasing the contact area between the semiconductor layer 61 and the bit line 50 and improving the on-state current.

[0176] In some embodiments, the size of the semiconductor layer 61 in the third direction (Y direction) is larger than the size of the contact surface between the first electrode 52 and the semiconductor layer 61 in the third direction (Y direction). Furthermore, the semiconductor layer 61 (first ring 61a) in contact with the first electrode 52 is a closed ring, thereby increasing the contact area between the semiconductor layer 61 and the first electrode 52 and improving the on-state current.

[0177] In some embodiments, the size of the semiconductor layer 61 in the third direction (Y direction) is larger than the size of the semiconductor layer 61 in the second direction (X direction). This results in a smaller channel distance in the semiconductor layer compared to the ring gate structure, thereby further improving transistor performance.

[0178] The semiconductor devices involved in the embodiments of this disclosure may be memory, such as DRAM, or other memory chips or processing chips containing DRAM memory cells.

[0179] Here, the specific structure and other details of the semiconductor device are similar to those of the semiconductor device obtained by the aforementioned preparation method. For any parts not mentioned, please refer to the above preparation method embodiments, which will not be repeated here.

[0180] This disclosure also provides an electronic device, including the semiconductor device described above, or a semiconductor device manufactured according to the method described above. The electronic device may be a storage device, smartphone, computer, tablet computer, artificial intelligence device, wearable device, or power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0181] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0182] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: Multiple memory cells are distributed on different layers and stacked along a first direction; each memory cell includes a transistor, and each transistor includes a semiconductor layer. The semiconductor layer forms a first ring along a second direction, and the semiconductor layer forms a second ring along a third direction; the second direction and the third direction intersect and are both perpendicular to the first direction. Word lines extend along the third direction and surround the second ring of the semiconductor layer.

2. The semiconductor device according to claim 1, characterized in that, Also includes: Bit lines and memory structures; one end of the first ring of the semiconductor layer is connected to the bit lines, and the other end is connected to the memory structures.

3. The semiconductor device according to claim 2, characterized in that, Also includes: isolation The isolation structure is located between two adjacent bit lines along the third direction and between the word line and the memory structure; The semiconductor layer has a fourth filling layer within the first and second rings, and the semiconductor layer has an opening through which the fourth filling layer is connected to the isolation structure.

4. The semiconductor device according to claim 1, characterized in that, The word line includes a gate surrounding a channel region of the semiconductor layer and a connection electrode between adjacent gates along the third direction.

5. The semiconductor device according to claim 4, characterized in that, The semiconductor layer has a recessed region in the third direction that is recessed toward the interior of the semiconductor layer, and the gate has a protruding region in the third direction that is protruding toward the semiconductor layer, wherein the protruding region of the gate is fitted into the recessed region of the semiconductor layer.

6. The semiconductor device according to claim 4, characterized in that, Also includes: The gate dielectric layer is located between the semiconductor layer and the gate. The gate dielectric layer surrounds the second ring of the semiconductor layer.

7. The semiconductor device according to claim 2, characterized in that, The bit line extends along the first direction; a plurality of memory cells arranged along the first direction are connected to the same bit line, and two adjacent memory cells along the second direction are connected to the same bit line.

8. The semiconductor device according to claim 2, characterized in that, The memory structure includes: a first electrode, a dielectric layer, and a second electrode; the first electrodes in the memory structures of different layers are spaced apart in the first direction; the first electrode includes a recess away from the semiconductor layer, and there is a first gap between two adjacent first electrodes along the first direction; the dielectric layer and the second electrode are formed in the recess and the first gap; the dielectric layer covers two opposing surfaces of the first electrode along the first direction; the first electrode is connected to the first annular connection of the semiconductor layer; the second electrodes of the plurality of memory structures arranged along the first direction are connected to form an integral structure.

9. The semiconductor device according to claim 8, characterized in that, The second electrode includes a first conductive layer and a second conductive layer, the first conductive layer and the second conductive layer being made of different materials.

10. The semiconductor device according to claim 1, characterized in that, The dimension of the semiconductor layer in the third direction is larger than the dimension of the bit line in the third direction.

11. The semiconductor device according to claim 1, characterized in that, The size of the semiconductor layer in the third direction is greater than the size of the semiconductor layer in the second direction.

12. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided, the substrate including a substrate and a stacked structure formed on the substrate, the stacked structure including a first insulating layer and a second insulating layer alternately disposed along a first direction; A first trench is formed that penetrates the stacked structure and extends in a third direction; Based on the first trench, the first insulating layer is etched laterally to form a plurality of first transverse grooves that extend along the third direction and are spaced apart along the first direction. An initial character line structure is formed within the first transverse groove; A capacitor hole is formed on one side of the first trench along the second direction, penetrating the stacked structure. The first insulating layer is laterally etched through the capacitor hole to form a first capacitor groove located on both sides of the capacitor hole. The initial word line structure is etched through the first capacitor groove to form a double-layer word line structure. An isolation hole is formed through the stacked structure, and the double-layer word line structure is partially etched through the isolation hole to form word line grooves; A connecting character line structure is formed within the character line groove, and the connecting character line structure and the remaining double-layer character line structure constitute a character line; A semiconductor layer is formed in the remaining space of the first transverse groove, the semiconductor layer forming a first ring along a second direction, the semiconductor layer forming a second ring along a third direction, and the word line surrounding the second ring of the semiconductor layer.

13. The preparation method according to claim 12, characterized in that, Forming an initial word line structure within the first lateral groove includes: sequentially forming a gate structure layer and a first fill layer within the first lateral groove, wherein the gate structure layer and the first fill layer constitute the initial word line structure.

14. The preparation method according to claim 13, characterized in that, Before forming a capacitor hole penetrating the stacked structure on one side of the first trench along the second direction, the method further includes: A second filling layer is formed within the first trench; A plurality of first etch holes are formed in the second fill layer, extending along the first direction and spaced apart along the third direction. The first fill layer in the initial gate structure is laterally etched through the first etch holes to form second lateral grooves located on both sides of the first etch holes.

15. The preparation method according to claim 14, characterized in that, The method further includes: A third filling layer is formed by filling the first etched hole and the second transverse groove; Remove the third filling layer inside the first etched hole and form a bit line inside the first etched hole.

16. The preparation method according to claim 15, characterized in that, Before forming a capacitor hole penetrating the stacked structure on one side of the first trench along the second direction, the method further includes: An isolation via is formed through the stacked structure; the gate structure layer in the exposed initial gate structure is etched through the isolation via; A first sacrificial structure is formed within the isolation hole.

17. The preparation method according to claim 16, characterized in that, Etching the initial word line structure through the first capacitor groove to form a double-layer word line structure includes: The gate structure layer in the initial word line structure is etched through the first capacitor groove, so that the gate structure layers covering the sidewall of the first fill layer are disconnected from each other to form a first gate structure layer and a second gate structure layer. The first gate structure layer, the second gate structure layer and the remaining first fill layer constitute the double-layer word line structure.

18. The preparation method according to claim 17, characterized in that, Before forming the isolation holes through the stacked structure, the method further includes: The first filler layer is etched through the first capacitor groove to expose the third filler layer to form a fourth lateral groove; A seventh filling layer is formed within the fourth transverse groove; A first electrode is formed within the first capacitor groove.

19. The preparation method according to claim 17, characterized in that, Forming an isolation hole through the stacked structure includes: Remove the first sacrificial structure within the isolation hole.

20. The preparation method according to claim 17, characterized in that, Partial etching of the double-layer character line structure through the isolation hole to form character line grooves includes: The remaining first fill layer in the dual word line structure is removed through the isolation hole, and a portion of the first gate structure layer and the second gate structure layer are etched away to form a word line groove; the first gate structure layer includes a first gate layer and a first gate dielectric layer, and the second gate structure layer includes a second gate layer and a second gate dielectric layer. Forming a connecting word line structure within the word line groove includes: filling the word line groove with a gate dielectric material to form a third gate dielectric layer; etching the gate dielectric material to expose the first gate layer and the second gate layer; filling the gate material with gate material to form a third gate layer; the third gate layer and the remaining third gate dielectric layer constitute the connecting word line structure.

21. The preparation method according to claim 20, characterized in that, A semiconductor layer is formed in the remaining space of the first transverse groove, including: The third filler layer and the seventh filler layer are removed through the isolation hole to form a third transverse groove; A semiconductor layer is formed on the inner wall of the third transverse groove and a fourth filling layer is formed therein; one end of the first annulus of the semiconductor layer is connected to the bit line and the other end is connected to the first electrode. An isolation structure is formed within the isolation hole.

22. The preparation method according to claim 21, characterized in that, Forming a first electrode within the first capacitor recess includes: A first electrode is formed on the inner wall of the capacitor hole and the first capacitor groove, and a fifth filling layer is formed therein. Remove the first electrode and the fifth filling layer from the capacitor hole; A second sacrificial structure is formed within the capacitor hole.

23. The preparation method according to claim 22, characterized in that, The method further includes: Remove the second sacrificial structure inside the capacitor hole, and remove the fifth filling layer inside the first capacitor groove through the capacitor hole to form a second capacitor groove; The exposed isolation structure is partially etched through the capacitor hole to form a third capacitor groove; A dielectric layer and a second electrode are sequentially formed in the capacitor hole, the second capacitor groove, and the third capacitor groove; The first electrode, the dielectric layer, and the second electrode constitute a storage structure.

24. An electronic device, characterized in that, This includes the semiconductor device as described in any one of claims 1 to 11, or the semiconductor device manufactured according to the method of manufacturing the semiconductor device as described in any one of claims 12 to 23.

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