Semiconductor structure and method of manufacturing the same, electronic device

Abstract

Embodiments of the present disclosure disclose a semiconductor structure, a manufacturing method thereof and an electronic device. The method comprises: alternately stacking first insulating layers and second insulating layers on a substrate to form a stack layer; forming a first hole, a second hole and a first trench through the stack layer; based on the second hole, laterally etching the first insulating layers to form a plurality of first grooves arranged at intervals along a first direction; sequentially forming a barrier layer and a sacrificial layer on inner walls of the first grooves; based on the second hole and the first grooves, forming an initial semiconductor layer covering the second hole and the inner walls of the first grooves, and a gate structure covering the initial semiconductor layer and filling the second hole and the first grooves; based on the first hole and the first trench, removing the sacrificial layer and retaining the barrier layer located in the first grooves, to expose side walls of the initial semiconductor layer towards the first hole and the first trench; removing the exposed side walls of the initial semiconductor layer to form a semiconductor layer.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of semiconductor manufacturing, specifically to a semiconductor structure and its manufacturing method, and an electronic device. Background Technology

[0002] With the technological advancements in manufacturing processes for semiconductor products such as memory and integrated circuits, the critical dimensions of devices are shrinking daily, and device density is increasing significantly. For example, memory structures have evolved from two-dimensional planar structures to three-dimensional stacked structures, resulting in a substantial improvement in memory storage capacity.

[0003] However, the manufacturing process of three-dimensional devices such as three-dimensional memory often requires complex and sophisticated manufacturing processes. Summary of the Invention

[0004] In view of the above, embodiments of the present disclosure provide a semiconductor structure, a method for manufacturing the same, and an electronic device.

[0005] On one hand, embodiments of this disclosure provide a method for manufacturing a semiconductor structure, the method comprising:

[0006] Provide substrate;

[0007] A stacked layer is formed by alternately stacking a first insulating layer and a second insulating layer along a first direction perpendicular to the substrate.

[0008] A first hole, a second hole, and a first trench are formed that penetrate the stacked layer and are spaced apart along a second direction parallel to the substrate surface; wherein the first trench extends along a third direction parallel to the substrate surface; the second hole is located between the first hole and the first trench, and the third direction intersects the second direction;

[0009] Based on the second hole, the first insulating layer is etched laterally to form a plurality of first grooves spaced apart along the first direction;

[0010] A barrier layer and a sacrificial layer are sequentially formed on the inner wall of the first groove;

[0011] Based on the second hole and the first groove, an initial semiconductor layer is formed covering the inner wall of the second hole and the first groove, and a gate structure is formed covering the initial semiconductor layer and filling the second hole and the first groove;

[0012] Based on the first hole and the first trench, the sacrificial layer is removed, and the barrier layer located in the first groove is retained, exposing the sidewalls of the initial semiconductor layer facing the first hole and the first trench;

[0013] Remove the exposed sidewalls of the initial semiconductor layer to form a semiconductor layer.

[0014] In some embodiments, the method further includes:

[0015] Before forming the barrier layer and the sacrificial layer, a portion of the sacrificial material in the first hole and the first trench is removed by etching the first groove.

[0016] In some embodiments, the removal of the sacrificial material from a portion of the first hole and the first trench by etching through the first groove includes:

[0017] The sacrificial material in the first hole and the first trench of the first thickness is removed by etching through the first groove;

[0018] The step of sequentially forming a barrier layer and a sacrificial layer on the inner wall of the first groove includes:

[0019] A barrier layer with a thickness less than or equal to the first thickness is formed on the inner wall of the first groove;

[0020] The sacrificial layer is formed on the surface of the barrier layer.

[0021] In some embodiments, the step of sequentially forming a barrier layer and a sacrificial layer on the inner wall of the first groove includes:

[0022] A barrier layer is formed covering the inner wall of the first groove and the inner wall of the second hole;

[0023] A sacrificial layer is formed to cover the barrier layer;

[0024] The barrier layer and the sacrificial layer on the sidewall of the second hole are at least removed through the second hole, so that the conductive material of the sidewall of the second hole is exposed to the second hole at intervals, while retaining at least a portion of the barrier layer and the sacrificial layer on the inner wall of the first groove.

[0025] In some embodiments, removing at least the barrier layer and the sacrificial layer on the sidewall of the second hole through the second hole includes:

[0026] The sacrificial layer of a second thickness, extending from the sidewall of the second hole into the first groove, is removed through the second hole.

[0027] Remove the barrier layer that is not covered by the remaining sacrificial layer.

[0028] In some embodiments, removing at least the barrier layer and the sacrificial layer on the sidewall of the second hole through the second hole includes:

[0029] The sacrificial layer on the inner wall of the second hole is removed through the second hole, exposing the barrier layer extending in a direction perpendicular to the substrate.

[0030] Remove the barrier layer that is not covered by all remaining sacrificial layers;

[0031] Remove the sacrificial layer of a second thickness extending into the first groove.

[0032] In some embodiments, the method further includes:

[0033] Before forming the first groove, sacrificial material is filled into the first hole and the first groove;

[0034] Before removing the sacrificial layer, the sacrificial material in the first hole and the first trench is removed, and the barrier layer located on the sidewalls of the first hole and the first trench extending along the first direction is removed to expose the sacrificial layer.

[0035] In some embodiments, the provision of the substrate includes:

[0036] The surface of the substrate is passivated to form the substrate covered with a passivation layer.

[0037] In some embodiments, forming the first hole, the second hole, and the first trench that penetrate the stacked layer and are spaced apart along a second direction parallel to the substrate surface includes:

[0038] Forming a first hole and a second hole through the stacked layers;

[0039] The substrate surfaces exposed at the bottom of the first and second holes are passivated.

[0040] A first isolation layer is formed on the sidewalls of the first hole and the second hole;

[0041] Sacrificial material is filled into the first and second holes where the isolation layer is formed;

[0042] Form a first protective layer covering the surface of the stacked layers;

[0043] Forming a first trench that penetrates the stacked layers;

[0044] The substrate surface exposed at the bottom of the first trench is passivated.

[0045] In some embodiments, the method further includes:

[0046] Based on the first trench, the second insulating layer is etched laterally to form a plurality of second grooves spaced apart along the first direction;

[0047] Conductive material is deposited in the second groove to form a first electrode structure; the first electrode structure serves as a bit line.

[0048] In some embodiments, the method further includes:

[0049] Based on the first hole, the second insulating layer is etched laterally to form a plurality of third grooves spaced apart along the first direction;

[0050] A conductive layer is formed on the inner wall of the third groove to form the second electrode structure; wherein the second electrode structure serves as the first electrode plate of the capacitor structure.

[0051] On the other hand, embodiments of this disclosure also provide a semiconductor structure, including:

[0052] Substrate;

[0053] A multilayer memory cell layer stacked on the substrate along a first direction perpendicular to the substrate; the memory cell layer includes a plurality of memory cells arranged in an array; the memory cell includes: a semiconductor layer and a gate structure;

[0054] The semiconductor layer is disposed around the circumferential sidewall of the gate structure, and the semiconductor layer is in contact with the first electrode structure and the second electrode structure in a second direction parallel to the substrate surface.

[0055] The first electrode structure and / or the second electrode structure have a barrier layer attached to at least a portion of the surface parallel to the substrate direction;

[0056] The semiconductor layer has contact surfaces with the barrier layer at both ends in the first direction.

[0057] In some embodiments, the semiconductor layer includes:

[0058] The first portion extending along the first direction;

[0059] Extending in a direction parallel to the substrate, and located at the second portion of the semiconductor layer connected to the first portion at both ends in the first direction; wherein the second portion of the semiconductor layer adjacent in the first direction is disconnected.

[0060] In some embodiments, the contact surface between the semiconductor layer and the barrier layer is located at the cross-section where the second portion is disconnected;

[0061] Alternatively, the contact surface between the barrier layer and the semiconductor layer is located on the surface between the second portion and the first electrode structure, and on the surface between the second portion and the second electrode structure.

[0062] In some embodiments, the first electrode structure is used as a bit line;

[0063] The second electrode structure serves as the first electrode plate of the capacitor structure;

[0064] The semiconductor structure further includes a second electrode of the capacitor structure and a dielectric layer located between the first electrode and the second electrode.

[0065] In some embodiments, the first electrode plate has an annular cross-section parallel to the substrate surface; and the first electrode plate includes a recessed structure along a direction parallel to the substrate surface.

[0066] The second electrode plate includes: a first sub-section extending along the first direction through the multilayer capacitor structure, a second sub-section connecting the first sub-section and extending into the recessed structure, and a plurality of third sub-sections connecting the first sub-section and extending into the gap between two adjacent first electrode plates.

[0067] In some embodiments, the gate structures of the memory cells located in the same straight line in the first direction are connected along the first direction;

[0068] Furthermore, the first electrode structure of the memory cell, which is located on the same straight line in a third direction parallel to the substrate, is connected along the third direction to serve as the bit line.

[0069] In another aspect, embodiments of this disclosure also provide an electronic device, including a semiconductor structure formed according to the manufacturing method of any of the above-described semiconductor structures, or any of the above-described semiconductor structures.

[0070] In the technical solution provided in this disclosure, a stacked layer is formed by alternately stacking a first insulating layer and a second insulating layer, and structures such as a first hole, a second hole, and a first trench are formed through the stacked layer. The first insulating layer is laterally etched to form a first groove, which allows for the formation of various multilayer stacked structures. During the formation of the semiconductor layer, a barrier layer and a sacrificial layer are first formed through the first groove, followed by the formation of an initial semiconductor layer penetrating the entire second hole. Then, the sacrificial layer is removed from the other side of the first groove, retaining the barrier layer, and the excess semiconductor layer exposed to the first groove is removed. Thus, the barrier layer protects the semiconductor layer, preventing damage to the effective semiconductor layer during the removal of excess semiconductor layer, thereby effectively improving the process stability. Attached Figure Description

[0071] Figure 1 A flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of this disclosure;

[0072] Figures 2 to 30A schematic diagram of the structure corresponding to each step in the manufacturing method provided in the embodiments of this disclosure;

[0073] Figure 31 A schematic diagram of a semiconductor structure provided in an embodiment of this disclosure;

[0074] Figure 32 Partial schematic diagram of the semiconductor structure provided in the embodiments of this disclosure Figure 1 ;

[0075] Figure 33 Partial schematic diagram of the semiconductor structure provided in the embodiments of this disclosure Figure 2 ;

[0076] Figure 34 This is a structural block diagram of an electronic device provided in an embodiment of the present disclosure.

[0077] Figure label:

[0078] Semiconductor structure - 100; Substrate - 110; Passivation layer - 112; Stacked layer - 120; First insulating layer - 121; Second insulating layer - 122; First via - 130; Second via - 140; First electrode structure - 141; Second electrode structure - 142; Gate structure - 143; Initial semiconductor layer - 144; Oxide layer - 145; Parasitic channel - 144a; Effective channel - 144b; First trench - 150; First recess - 160; Barrier layer - 161; Sacrificial layer - 162; Second recess - 180; Third recess - 190; Conductivity Layer-191; First isolation layer-211; First protective layer-212; Second isolation layer-221; Second protective layer-222; Third isolation layer-231; Third protective layer-232; Fourth protective layer-233; Fourth isolation layer-241; First surface-310; Second surface-320; Contact surface-330; First part-340; Second part-350; Capacitor structure-360; Dielectric layer-361; Second electrode plate-362; Transistor structure-380; Electronic device-400; Memory-410; Processor-420. Detailed Implementation

[0079] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0080] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0081] In this disclosure, the terms "first," "second," etc., are used to distinguish similar objects, and not to describe a specific order, sequence, quantity, or importance.

[0082] In the embodiments of this disclosure, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" may be used to describe the positional relationships of the constituent elements with reference to the accompanying drawings. These terms are used solely for ease of description and simplification and are not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed or operated in a specific orientation, and therefore should not be construed as a limitation on the embodiments of this disclosure. The positional relationships and orientations of the constituent elements may change depending on the placement direction of each constituent element.

[0083] In this embodiment of the disclosure, "parallel" means approximately parallel or nearly parallel, and the included angle between the two elements defined therein may be within the allowable range of process tolerance. Similarly, "perpendicular" means approximately perpendicular or nearly perpendicular, and the included angle between the two elements defined therein may be an error angle relative to a 90° right angle that is within the allowable range of process tolerance.

[0084] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict. In the methods involved in the embodiments of this disclosure, unless otherwise specified or described, the execution order of each step can be adjusted according to actual circumstances or needs. That is, different combinations of the sequences of steps involved in the embodiments of this disclosure all fall within the protection scope of this disclosure.

[0085] The transistor involved in the embodiments of this disclosure refers to a device that includes at least three terminals: a gate, a source, and a drain. The transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode). The gate can control the conductivity of the channel region, thereby enabling current to flow between the source, the channel region, and the drain based on gate control.

[0086] The deposition processes involved in the embodiments of this disclosure include, but are not limited to: chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), sputtering, metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), and combinations thereof.

[0087] The growth processes described in this disclosure include, but are not limited to: vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), molecular beam epitaxy (MBE), ion beam epitaxy, solid phase epitaxy, and combinations thereof.

[0088] The etching processes disclosed herein include, but are not limited to, dry etching, wet etching, and combinations thereof.

[0089] The semiconductor structure disclosed herein is at least a portion of the structure that will be used in subsequent processes to form the final device structure. Here, the final device may be a memory, such as DRAM (Dynamic Random Access Memory), or other memory chips or processing chips that contain DRAM memory cells.

[0090] This disclosure provides a method for manufacturing a semiconductor structure 100, the main steps of which are as follows: Figure 1 As shown, the specific process can be found by referring to [the diagram]. Figures 2 to 29 (For ease of explanation, the directions of the cross-section are marked in each figure: X direction, Y direction, and Z direction. In this embodiment of the disclosure, the first direction corresponds to the Z direction, the second direction corresponds to the X direction, and the third direction corresponds to the Y direction as an example.) The method includes:

[0091] Step S101: Provide substrate 110;

[0092] This disclosure does not specifically limit the constituent materials of the substrate 110. As an example, the substrate 110 can be constructed from semiconductor materials, insulating materials, conductive materials, or any combination thereof. The substrate 110 can be a single-layer structure or a multi-layer structure. For example, the substrate 110 can be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V or II / VI semiconductor substrates. Alternatively, for example, the substrate 110 can be a layered substrate comprising, for example, a stack of Si and SiGe, a stack of Si and SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.

[0093] Specifically, in some embodiments, such as Figure 2 As shown, providing substrate 110 may include:

[0094] The surface of the substrate 110 is passivated to form a substrate 110 covered with a passivation layer 112.

[0095] Here, the substrate 110 can be any of the aforementioned semiconductor materials or other materials used as a carrier. By passivating the surface of the substrate 110, a passivation layer 112 can be formed on the surface of the substrate 110, thereby reducing the surface recombination rate and improving device performance. For example, the passivation layer 112 can be a SiOF (fluorinated silicon oxide) thin film. The SiOF thin film can saturate the dangling bonds on the silicon surface, reducing the surface state density and the number of recombination centers within the band gap, thereby reducing the surface recombination rate of minority carriers. Furthermore, the SiOF thin film may contain a certain amount of fixed charge, which will form an electrostatic field at the interface, reducing the minority carrier concentration and further reducing surface recombination. In addition, the passivation layer 112 can also improve the electrical characteristics of the device, reduce leakage current, and protect the substrate 110.

[0096] Specifically, passivation can be achieved through oxidation, deposition, etching, or implantation, and the embodiments disclosed herein are not limited to these methods.

[0097] Step S102: Alternately stack a first insulating layer 121 and a second insulating layer 122 on the substrate 110 along a first direction (Z direction) perpendicular to the substrate to form a stacked layer 120, such as... Figure 3 As shown.

[0098] The first insulating layer 121 and the second insulating layer 122 are made of different insulating materials. For example, the first insulating layer 121 and the second insulating layer 122 can be silicon oxide and silicon nitride, respectively. It should be noted that the first insulating layer 121 and the second insulating layer 122 are used to position the layers of the multilayer transistor structure in subsequent steps. During the manufacturing process, the first insulating layer 121 and the second insulating layer 122 are partially or completely removed in each step, and other specific device structures are formed at the corresponding positions. Therefore, part or all of the first insulating layer 121 and the second insulating layer 122 serve as sacrificial layers for intermediate auxiliary structures throughout the entire manufacturing process. It is evident that the materials of the first insulating layer 121 and the second insulating layer 122 are not limited to the materials in the above example; any sacrificial material that can meet the specific requirements of the manufacturing process can be used as the first insulating layer 121 or the second insulating layer 122.

[0099] Step S103: Form a first hole 130, a second hole 140, and a first trench 150 that penetrate the stacked layer 120 and are spaced apart along a second direction (X direction) parallel to the substrate surface; wherein, the first trench 150 extends along a third direction (Y direction) parallel to the substrate surface; the second hole 140 is located between the first hole 130 and the first trench 150;

[0100] Here, the first aperture, the second aperture, and the first trench can be used to form a stacked memory structure, which, exemplarily, may include transistors and memory cells. For example, the first aperture can be used to form multiple stacked memory cells, such as capacitors or other structures. The second aperture can be used to form multiple stacked transistor structures, and the first trench can be used to form conductive lines connected to the transistors, such as bit lines in a memory cell array.

[0101] It should be noted that since the final capacitor structure, transistor structure, and bit line structure need to be electrically connected sequentially, the second hole 140 is located between the first hole 130 and the first trench 150. If there are multiple sets of the above structures arranged in an array, along the X direction, there can be multiple arrangements of the first hole 130, the second hole 140, and the first trench 150; or they can be arranged symmetrically with respect to the first trench 150, that is, a set of second holes 140 and a set of first holes 130 are respectively provided on both sides of the first trench 150. In the Y direction, there can be multiple first holes 130 and multiple second holes 140, and multiple first holes 130 are arranged at intervals along the Y direction, and multiple second holes 140 are arranged at intervals along the Y direction. In this way, a three-dimensional stacked memory array structure can be formed.

[0102] Specifically, in some embodiments, step S103 above can be implemented by the following process:

[0103] Step S31: Form a first hole 130 and a second hole 140 through the stacked layer 120;

[0104] Step S32: Passivate the substrate 110 surface exposed at the bottom of the first hole 130 and the second hole 140, such as... Figure 4 As shown.

[0105] The first hole 130 and the second hole 140 can be simultaneously formed on the stacked layer 120 using deep hole etching (TCH ETCH) technology. The etching process may damage the passivation layer 112 on the surface of the substrate 110, exposing the substrate 110 surface at the bottom of the hole. Therefore, the exposed substrate 110 surface at the bottom of the hole can be further passivated to restore the damaged passivation layer 112. For example, the passivation process can be achieved using plasma.

[0106] Step S33: Form a first isolation layer 211 on the sidewalls of the first hole 130 and the second hole 140;

[0107] Step S34: Fill the first hole 130 and the second hole 140, where the isolation layer is formed, with sacrificial material;

[0108] Step S35: Form a first protective layer 212 covering the surface of the stacked layer 120, such as... Figure 5 As shown.

[0109] The first isolation layer 211 can be an oxide layer, such as silicon oxide (SiO2), formed by oxidizing the inner walls of the first hole 130 and the second hole 140, or by depositing oxides, to cover the inner walls of the holes. Then, the first hole 130 and the second hole 140 are filled with a sacrificial material such as polysilicon. At this time, the sacrificial material at the top openings of the first hole 130 and the second hole 140 is exposed. Therefore, a first protective layer 212 needs to be applied to the surface of the stacked layer 120 to shield the sacrificial material. For example, the material of the first protective layer 212 can be an insulating material different from the first insulating layer 121 or the second insulating layer 122 on the top layer of the stacked layer 120. For example, if the top layer of the stacked layer 120 is silicon nitride, which is the second insulating layer 122, then the first protective layer 212 can be silicon oxide.

[0110] Step S36: Form a first trench 150 that penetrates the stacked layer 120;

[0111] Step S37: Passivate the surface of the substrate 110 exposed at the bottom of the first trench 150, such as... Figure 6 As shown.

[0112] Similar to the process of forming the first hole 130 and the second hole 140, the first trench 150 can be formed by deep trench etching (BLS ETCH) technology. The etching process may also damage the passivation layer 112 on the surface of the substrate 110, exposing the substrate 110 surface at the bottom of the first trench 150. Therefore, the same passivation treatment can be further performed on the substrate 110 surface exposed at the bottom of the first trench 150.

[0113] It should be noted that in this embodiment, considering that the etching requirements (such as size) of the first trench 150 are different from those of the first hole 130 and the second hole 140, two etching steps are used to form them separately, which facilitates the control of etching accuracy. In other embodiments, by selecting an appropriate etching method, the first hole 130, the second hole 140, and the first trench 150 can also be formed simultaneously in the same etching process, thereby simplifying the steps and improving manufacturing efficiency.

[0114] In some embodiments, the method may further include:

[0115] In step S201, a first electrode structure 141 and a second electrode structure 142 of the transistor are formed on both sides of the second hole 140 and at the position of the second insulating layer 122, respectively. The second electrode structure can serve as the first electrode plate of the capacitor structure.

[0116] Here, "the first electrode structure 141 and the second electrode structure 142 are located on both sides of the second hole 140" means that the first electrode structure 141, the second hole 140, and the second electrode structure 142 are arranged sequentially along the X direction.

[0117] Specifically, in some embodiments, step S201 above may include:

[0118] Step S41: Replace the second insulating layer 122 between the first trench 150 and the second hole 140 with a conductive material to form the first electrode structure 141 of the transistor;

[0119] Step S42: A second electrode structure 142 of the transistor is formed between the first hole 130 and the second hole 140, at the position of the second insulating layer 122.

[0120] For example, the first electrode structure 141 and the second electrode structure 142 described above are made of conductive materials. Specifically, they may include metallic or alloy materials, such as materials containing metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; or they may be metal oxide materials, including metal nitrides, metal silicides, and metal carbides, such as tin-doped indium oxide (ITO), indium-doped zinc oxide (IZO), indium oxide (InO), aluminum-doped zinc oxide (Al-doped ZnO, AZO), iridium oxide (IrOx), ruthenium oxide (RuOx), and other conductive metal oxide materials; or, for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN), and other metal nitride materials.

[0121] In some embodiments, the first electrode structure 141 described above can be formed through the following process for step S41:

[0122] Step S41-1: Based on the first trench 150, the second insulating layer 122 between the first trench 150 and the second hole 140 is etched laterally to form a plurality of second grooves 180 spaced apart along the first direction, such as... Figure 7 As shown;

[0123] Step S41-2: Deposit conductive material in the second groove 180 to form the first electrode structure 141, as shown below. Figure 8 As shown.

[0124] The first electrode structure 141 can be used as a bit line and also reused as the drain of a transistor.

[0125] In this embodiment, all device structures may be located within the multilayer first insulating layer 121 or within the second insulating layer 122. This embodiment takes the example where all device structures are located within the second insulating layer 122; the layer in contact with the substrate 110 may be the first insulating layer 121.

[0126] As can be seen in the above example, both the first electrode structure 141 and the second electrode structure 142 need to be formed at the location of the second insulating layer 122. Therefore, the second insulating layer 122 between the first trench 150 and the second hole 140 is removed first through the first trench 150, and the resulting second groove 180 serves as the space for the subsequent formation of the first electrode structure 141. The second grooves 180 are separated from each other by the original first insulating layer 121.

[0127] Then, conductive material can be deposited in the second groove 180 through the first trench 150. Specifically, the conductive material can fill the entire second groove 180 and the first trench 150, and then the conductive material in the first trench 150 can be removed. The conductive material extending into the second groove 180 to a certain thickness can also be removed, leaving only the portion of conductive material located within the second groove 180, as described above. Figure 8 As shown, this is to ensure that the conductive materials in each layer are isolated from each other, preventing leakage during device use.

[0128] Furthermore, in the above process, the first trench 150 may not need to be completely filled with conductive material, as long as sufficient conductive material is filled to the required positions within the second groove 180. Then, further etching is required to remove excess conductive material from the inner wall of the first trench 150, resulting in... Figure 8 The structure shown.

[0129] In some embodiments, after the formation of the first electrode structure 141 and the second electrode structure 142, or before the formation of the first groove, sacrificial material may be filled into the first hole 130 and the first trench 150, respectively.

[0130] Specifically, in some embodiments, such as Figure 9 As shown, after forming the first electrode structure 141, the following process can also be performed:

[0131] Step S43: Form a second isolation layer 221 in the first trench 150 covering the inner wall of the first trench 150 and the side wall of the first electrode structure 141;

[0132] Step S44: Fill the first trench 150 with sacrificial material;

[0133] Step S45: Form a second protective layer 222 covering the surface where the opening of the first trench 150 is located.

[0134] The second isolation layer 221 is an insulating material, such as silicon nitride or silicon oxide. It should be noted that the material of the second isolation layer 221 can be different from that of the first insulating layer 121. Therefore, if the first insulating layer 121 is silicon oxide, the second isolation layer 221 can be silicon nitride, thus protecting the first electrode structure 141 and isolating the first trench 150 during the subsequent fabrication process through the second hole 140.

[0135] Then, sacrificial material can be filled into the first trench 150 to facilitate the subsequent fabrication of the second electrode structure 142 and capacitor electrodes through the first hole 130. Furthermore, since the opening of the first trench 150 is exposed to the surface of the stacked structure after being filled with sacrificial material, specifically, the opening needs to be covered on the upper surface after the formation of the first protective layer 212 to prevent the sacrificial material in the first trench 150 from being removed in subsequent processes and affecting the structure on both sides of the bit line trench. Therefore, a second protective layer 222 is also needed to cover the top to cover the opening of the first trench 150. Exemplarily, the material of the second protective layer 222 can be the same as that of the first protective layer 212, for example, both being insulating materials such as silicon oxide or silicon nitride; the material of the second protective layer 222 can also be different from that of the first protective layer 212, which can be selected according to the requirements of subsequent processes, and this disclosure does not limit the choice.

[0136] In some embodiments, the second electrode structure 142 described above can be formed through the following process for step S42:

[0137] Step S42-1: Remove the sacrificial material from the first hole 130, such as... Figures 10 to 11 As shown.

[0138] Step S42-2: Based on the first hole 130, the second insulating layer 122 is etched laterally to form a multi-layered third groove 190 with spacing, as shown. Figure 12 As shown;

[0139] Step S42-3: A conductive layer 191 is formed on the inner wall of the third groove 190 to form the second electrode structure 142. Figure 13 The conductive layer 191 is shown; wherein, the second electrode structure 142 serves as the first electrode of the capacitor structure. The first electrode can be the upper electrode or the lower electrode of the capacitor structure. Here, the conductive layer 191 can be annular around the first hole 130. Figure 13 The conductive layer 191 shown is a cross-section at the center of the first hole 130.

[0140] During the formation of the first electrode structure 141, the first hole 130 is filled with sacrificial material. Therefore, it is necessary to remove the sacrificial material (such as poly) from the first hole 130. Specifically, this can be done in two steps: the first step is as described above. Figure 10 The sacrificial material inside the first hole 130 is etched using a dry etching process. This process allows for the control of retaining a portion of the sacrificial material on the inner wall of the first hole 130, preventing etching to the bottom of the first hole 130 and thus avoiding damage to the passivation layer 112. The second step is as described above. Figure 11 The remaining sacrificial material is removed by wet etching.

[0141] It should be noted that, since the first isolation layer 211 can be covered on the inner wall of the first hole 130 during the previous step of filling the first hole 130, after removing the remaining sacrificial material in the second step, it is necessary to further remove the first isolation layer 211 so that the sidewalls of the first insulating layer 121 and the second insulating layer 122 are exposed so that the second insulating layer 122 can be removed.

[0142] Then, the second insulating layer 122 around the first hole 130 is removed by wet lateral etching, thereby forming a structure as shown in the figure. Figure 11 The annular third groove 190 shown serves as a space for accommodating the second electrode structure 142 and other structures of the capacitor structure.

[0143] Next, a second electrode structure 142 can be formed by depositing conductive material on the inner wall of the third groove 190. During this process, the sidewall of the first hole 130 may also be covered with conductive material. Therefore, after depositing the conductive material, the conductive material covering the sidewall of the first hole 130 at the location of the first insulating layer 121 can be removed, thereby forming the aforementioned conductive layer 191 as the second electrode structure 142. Here, considering that the first electrode plate of the capacitor structure needs to be in the form of a conductive material film, the second electrode structure 142 of the transistor is different in form from the first electrode structure 141. That is, the first electrode structure 141 is composed of conductive material filling the second groove 180, while the second electrode structure 142 is composed of the conductive layer 191 covering the inner wall of the third groove 190.

[0144] In other embodiments, the second electrode structure 142 described above may also have a similar shape to the first electrode structure 141, formed by filling the third groove 190 with conductive material. In this case, a suitable capacitor structure can be selected, and relevant solutions can be referenced for design; details will not be elaborated here.

[0145] In some embodiments, after the first electrode structure 141 and the second electrode structure 142 are formed, sacrificial material is filled into the first hole 130 and the first trench 150, respectively.

[0146] For example, in some embodiments, after forming the second electrode structure 142, the following process may also be performed:

[0147] Step S46: Fill the third groove 190, where the conductive layer 191 is formed, with insulating material, such as... Figure 13 As shown.

[0148] Step S47: Form a third isolation layer 231 on the sidewall of the first hole 130;

[0149] Step S48: Fill the first hole 130, where the third isolation layer 231 is formed, with sacrificial material.

[0150] Step S49: Form a third protective layer 232 covering the surface where the opening of the first hole 130 is located, such as... Figure 14 As shown.

[0151] In this embodiment, after depositing the conductive material, an insulating material (also a sacrificial material), such as silicon oxide or polysilicon, can be filled into the third groove 190 and the first hole 130. Then, the sacrificial material in the first hole 130 is removed, and the conductive material covering the sidewall of the first hole 130 at the location of the first insulating layer 121 is further removed, achieving the separation between the electrode layers, resulting in... Figure 13 The structure shown.

[0152] The first hole 130 needs to be sealed to allow for subsequent manufacturing processes. Similar to steps S43 to S45 above, a third isolation layer 231 can be formed on the sidewall of the first hole 130 by oxidation or deposition. The third isolation layer 231 can be an insulating material, such as silicon oxide or silicon nitride.

[0153] The sacrificial material is then refilled, and a third protective layer 232 is further formed to cover the sacrificial material at the opening of the first hole 130, so that subsequent steps can be performed. Here, the third protective layer 232 can be the same material as the second protective layer 222, or it can be a different material.

[0154] Step S104, as follows Figures 15 to 17 As shown, the first insulating layer 121 is etched laterally based on the second hole 140 to form a plurality of first grooves 160 arranged at intervals along the first direction (Z direction).

[0155] Specifically, the sacrificial material inside the second hole 140 can be removed first by dry etching. At this time, some sacrificial material on the sidewalls and bottom of the second hole 140 can be left unremoved, such as... Figure 15 As shown, this avoids etching the passivation layer at the bottom of the second hole 140, which could damage the substrate 110.

[0156] The remaining sacrificial material in the second hole 140 can then be removed by wet etching, and the first isolation layer 211 covering the inner wall of the hole can be further removed, such as... Figures 15 to 16 The process is shown below.

[0157] Finally, wet etching is used to laterally etch the first insulating layer 121 through the second hole 140, forming the first groove 160. During this process, the etching solution selectively etches the first insulating layer, while the passivation layer remains stable, resulting in the desired effect. Figure 17 The structure shown.

[0158] Furthermore, it should be noted that because the processes of filling the sacrificial material in the first groove 150 and the first hole 130 are performed sequentially, their tops are not on the same plane, such as... Figure 15 As shown. Therefore, in order to facilitate the execution of subsequent processes, when executing as... Figure 15 Before and after the steps shown, the top can be planarized so that the top of the first hole 130 and the top of the first trench 150 are on the same plane. This process will remove the original second protective layer 222 and third protective layer 232, and may also remove part of the first protective layer 212. Then, an insulating material can be deposited on the surface to form a fourth protective layer 233, such as... Figure 16 The portion shown.

[0159] This step is to remove the first insulating layer 121 above and below the first electrode structure 141 and the second electrode structure 142 to create space for forming the transistor gate structure 143. It should be noted that the outermost part of the transistor gate structure 143 is the initial semiconductor layer 144, which extends perpendicularly to the surface of the substrate 110. The initial semiconductor layer 144 located at the second insulating layer 122, which contacts the first electrode structure 141 and the second electrode structure 142, is the semiconductor layer required in the final structure, serving as the effective channel 144b of the transistor. A set of first electrode structures 141, second electrode structures 142, effective channel 144b, gate oxide layer 145, and gate electrode constitutes a transistor structure. Therefore, the initial semiconductor layer 144 between adjacent effective channels 144b of each transistor layer is a parasitic channel 144a, which needs to be removed in subsequent steps.

[0160] In this embodiment of the disclosure, a portion of the first groove 160 formed near the second hole 140 can be used to accommodate a portion of the parasitic channel 144a, while a portion of the first groove 160 away from the second hole 140 can be used to fill sacrificial material to form a sacrificial layer 162, so as to serve as an etching channel in the subsequent removal of the parasitic channel 144a.

[0161] Understandably, during the subsequent removal of the parasitic channel 144a, the sacrificial layer 162 within the first groove 160 can be removed from the first trench 150 and the first hole 130, exposing the parasitic channel 144a within the first groove 160 for easier removal. For example, the parasitic channel 144a can be removed by wet etching after removing the sacrificial layer 162. However, the thickness of the sacrificial layer 162 in the direction parallel to the substrate 110 affects the process window for removing the parasitic channel 144a. If the thickness of the sacrificial layer 162 is too small, it can easily damage the effective channel 144b; however, if the thickness of the sacrificial layer 162 is too large, it will increase the device size, waste device area, and hinder the improvement of device density.

[0162] In some embodiments, such as Figure 18 As shown, a portion of the sacrificial material in the first hole 130 and the first trench 150 can be removed by etching through the first groove 160.

[0163] After forming the first groove 160 with multiple layers, the sacrificial material on both sides is further etched, so that the first groove 160 continues to extend into the first hole 130 and the first trench on both sides, thereby increasing the thickness space of the sacrificial layer 162 outside the parasitic channel 144a. This also provides enough space to accommodate the part of the parasitic channel 144a that protrudes into the effective channel 144b, thereby increasing the process window, improving the etching quality, and reducing damage to the effective channel 144b during the removal of the parasitic channel 144a.

[0164] In some embodiments, the thickness of the sacrificial material removed from the first hole 130 and the first trench 150 can be a first thickness.

[0165] In other words, after removing the sacrificial material in the first groove 160, the sacrificial material extending into the first hole 130 and the first trench 150 can be further over-etched to obtain a groove of the first thickness, thereby increasing the depth of the first groove 160 by the first thickness.

[0166] Step S105: A barrier layer 161 and a sacrificial layer 162 are sequentially formed on the inner wall of the first groove 160;

[0167] In some embodiments, the thickness of the barrier layer 161 formed in step S105 may be less than or equal to the first thickness.

[0168] In the disclosed embodiment, when forming the sacrificial layer 162 outside the parasitic channel 144a, an additional step is added to cover the inner wall of the first groove 160 with a barrier layer 161. The material of the barrier layer 161 is different from that of the sacrificial layer 162, and can be a material that can serve as a mask during the subsequent removal of the parasitic channel 144a, or another material that can protect the effective channel 144b from etching. The material of the barrier layer 161 can be silicon nitride or silicon oxide, etc. Exemplarily, silicon nitride can be deposited by ALD or similar methods to form the barrier layer 161, and then polysilicon can be deposited on the surface of the barrier layer 161 as the sacrificial layer 162.

[0169] Following step 105, a portion of the sacrificial material located within the first hole 130 and the first trench 150 is further etched through the first groove 160, increasing the depth of the first groove 160 by a first thickness. Therefore, the thickness of the barrier layer 161 formed here will not significantly affect the device size. If the thickness of the barrier layer 161 is less than or equal to the aforementioned first thickness, the barrier layer 161 will not occupy additional dimensions in the direction parallel to the substrate 110, thereby facilitating the integrated and miniaturized design of the device.

[0170] In some embodiments, step S105 may include the following specific steps:

[0171] Step S51: Form a barrier layer 161 covering the inner wall of the first groove 160 and the inner wall of the second hole 140;

[0172] Step S52: Form a sacrificial layer 162 covering the barrier layer 161, such as Figure 19 As shown.

[0173] Step S53: Remove at least the barrier layer 161 and sacrificial layer 162 on the sidewall of the second hole 140 through the second hole 140, so that the conductive material of the sidewall of the second hole 140 is exposed to the second hole 140 at intervals, while retaining at least a portion of the barrier layer 161 and sacrificial layer 162 on the inner wall of the first groove 160.

[0174] It can be seen that the formed barrier layer 161 within the first groove 160 can just utilize the space formed by etching into the first hole 130 and the first trench 150, such as Figure 18 The position is indicated by the dashed circle in the middle. In this way, the barrier layer 161 and the sacrificial layer 162 can occupy more of the width of the first groove 160, and the impact on the width of the device (the portion of the parasitic channel 144a that is subsequently formed extending into the first groove 160) can be reduced.

[0175] In this way, on the one hand, the process stability of the subsequent removal of parasitic channels 144a can be improved, damage to the effective channels 144b can be reduced, and product yield can be improved. On the other hand, the design of the sacrificial layer 162 and the barrier layer 161 will not affect the device size, and there is no need to increase the device size, which is conducive to the miniaturization and high integration of product design.

[0176] The step of removing the redundant blocking layer 161 and sacrificial layer 162 in step S53 above can be achieved in two ways, each with its own advantages, which are explained in detail below:

[0177] In some embodiments, such as Figures 20 to 21 As shown, step S53 above can be implemented through the following first method:

[0178] Step S53a-1: Remove the sacrificial layer 162 of the second thickness on the inner wall of the second hole 140 and extending from the side wall of the second hole 140 into the first groove 160 through the second hole 140.

[0179] Step S53a-2: Remove the barrier layer 161 that is not covered by the remaining sacrificial layer 162.

[0180] After forming the barrier layer 161 and sacrificial layer 162 covering the inner walls of the second hole 140 and the first groove 160, it is necessary to disconnect the sacrificial layer 162 and the barrier layer 161 between each layer of the first groove 160. Here, the sacrificial layer 162 can be wet-etched through the second hole 140 to expose the barrier layer 161 at the source and drain positions of the transistor, that is, the barrier layer 161 extending perpendicularly to the surface of the substrate 110 at both ends of the first electrode structure 141 and the second electrode structure 142. Then, further etching is performed to remove part of the sacrificial layer 162 located in the first groove 160, leaving space for the parasitic channel 144a to extend into the first groove 160, such as... Figure 20 As shown.

[0181] Then, using the remaining sacrificial layer 162 as a mask, the barrier layer 161 not covered by it is removed, making the barrier layer 161 and the sacrificial layer 162 flush in a direction perpendicular to the substrate 110. The first electrode structure 141 and the second electrode structure 142 protrude toward the second hole 140 relative to the sacrificial layer 162 and the barrier layer 161, thereby forming a... Figure 21The structure shown is as follows. At this time, the space of the second hole 140 and extending into the first groove 160 can be used to form the gate structure 143 of the transistor in subsequent steps. Furthermore, the effective channel 144b can be located on the sidewall of the space of the second hole 140, and the parasitic channel 144a protrudes into the first groove 160, making it easier to remove the parasitic channel 144a. The barrier layer 161 can block the boundary between the two ends of the effective channel 144b and the parasitic channel 144a, thus protecting the effective channel 144b from damage by the etching solution, thereby improving the stability of the etching process during the removal of the parasitic channel 144a.

[0182] In other embodiments, such as Figures 22 to 24 As shown, step S53 above can also be implemented through the following second method:

[0183] Step S53b-1: Remove the sacrificial layer 162 on the inner wall of the second hole 140 through the second hole 140, exposing the barrier layer 161 extending in a direction perpendicular to the substrate 110, as shown. Figure 22 As shown;

[0184] Step S53b-2: Remove the barrier layer 161 that is not covered by all remaining sacrificial layers 162, such as... Figure 23 As shown;

[0185] Step S53b-3: Remove the sacrificial layer 162 of the second thickness extending into the first groove 160, as follows: Figure 24 As shown.

[0186] In this embodiment, the sacrificial layer 162 located within the second hole 140 is first removed through the second hole 140. For example, a wet etching method can also be used. At this time, the sacrificial layer 162 and the barrier layer 161 inside the first groove 160 are retained. Then, on the inner wall of the second hole 140, the barrier layer 161 (located at the position of the second insulating layer 122 and above and below the opening of the first groove 160) and the sacrificial layer 162 (located in the middle of the opening of the first groove 160) are exposed at intervals.

[0187] Next, the barrier layer 161 exposed on the sidewall of the second hole 140 can be removed using wet etching. Of course, the etching solution used to remove the barrier layer 161 is different from the etching solution used to remove the sacrificial layer 162, thereby achieving selective etching of the two film layers.

[0188] At this time, the sacrificial layers 162 are all located in the first groove 160, and protrude into the second hole 140 relative to the barrier layer 161 at the opening of the first groove 160. The thickness of the protruding part is approximately the thickness of the barrier layer 161.

[0189] Subsequently, in order to reserve space for the parasitic channel 144a to extend into the first groove 160, it is necessary to continue etching the sacrificial layer 162, removing a portion of the thickness of the sacrificial layer 162 located within the first groove 160, to obtain the following... Figure 24 The structure shown.

[0190] Compared to the first method in the above embodiments, the barrier layer 161 obtained by this method has a wider coverage area. When the gate structure 143 is subsequently formed, the parasitic channel 144a is isolated from the electrode structure by the barrier layer 161. On the one hand, it can increase the area of ​​the effective channel 144b protected by the barrier layer 161, reducing the probability that the effective channel 144b will be damaged and affect the device performance. On the other hand, during the formation of the gate structure 143, if the initial semiconductor layer 144 is an oxide semiconductor material, the area of ​​the surface of the first electrode structure 141 and the second electrode structure 142 that is oxidized during the formation of the initial semiconductor layer 144 can be reduced, thereby improving the conductivity of the transistor.

[0191] Step S106, as follows Figure 25 As shown, based on the second hole 140 and the first groove 160, an initial semiconductor layer 144 is formed covering the inner walls of the second hole 140 and the first groove 160, and a gate structure 143 is formed covering the initial semiconductor layer 144 and filling the second hole 140 and the first groove 160.

[0192] It is understood that the gate structure 143 here refers to the gate structure 143 shared by multiple transistors stacked in multiple layers perpendicular to the substrate 110, which penetrates the second hole 140. Its gate electrode penetrates the entire second hole 140 and can play the role of synchronously controlling the multiple stacked transistors.

[0193] In some embodiments, step S106 above may include the following steps:

[0194] Step S61: Sequentially form an initial semiconductor layer 144 and an oxide layer 145 covering the inner wall of the second hole 140;

[0195] Step S62: Fill the oxide layer 145 with conductive material to form the gate structure 143, such as... Figure 25 As shown.

[0196] Here, the initial semiconductor layer 144 is used to form the conductive channel required for the transistor. Specifically, the material of the initial semiconductor layer 144 of the transistor can be an intrinsic semiconductor material, such as single-crystal or polycrystalline materials like silicon or germanium; it can also be a metal oxide semiconductor material, such as an oxide containing at least one of the following metal elements: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may also contain compounds of other elements, such as nitrogen (N) or silicon (Si); it may also contain other small amounts of doping elements.

[0197] In some embodiments, the metal oxide material can be indium gallium zinc oxide (IGZO). When the metal oxide material is IGZO, the transistor leakage current is relatively small (leakage current less than or equal to 10). -15A), thus ensuring a low refresh rate for the dynamic memory. It should be noted that the metal oxide material can also be ITO or InSnOx (Indium Tin Oxide), IWO or InWO (Indium Tungsten Oxide), ZnOx (Zinc Oxide), InOx (Indium Oxide), In2O3 (Indium Oxide), SnO2 (Tin Dioxide), TiOx (Tin Dioxide), ZnxOyNz (ZincNitride Oxide), MgxZnyOz (Magnesium Zinc Oxide), InxZnyOz (Indium Zinc Oxide), InxGayZnzOa (Indium Gallium Zinc Oxide), ZrxInyZnzOa (Zirconium Indium Zinc Oxide). (Zinc Indium Zinc Oxide), HfxInyZnzOa (Hafnium Indium Zinc Oxide), SnxInyZnzOa (Tin Indium Zinc Oxide), AlxSnyInzZnaOd (Aluminum Tin Indium Zinc Oxide), SixInyZnzOa (Silicon Indium Zinc Oxide), ZnxSnyOz (Zinc Tin Oxide), AlxZnySnzOa (Aluminum Indium Tin Oxide), GaxZnySnzOa (Gallium Indium Tin Oxide), ZrxZnySnzOa (Zirconium Indium Tin Oxide), InGaSiO (Indium Gallium Silicon Oxide), IAZO (Indium Aluminum Indium Zinc Oxide). Materials such as ZincOxide (indium aluminum zinc oxide), IGO (indium gallium oxide), IZO (indium zinc oxide), and IZOx (indium zinc oxide) are all acceptable as long as the leakage current of the transistor meets the requirements. The specific requirements can be adjusted according to the actual situation.

[0198] The initial semiconductor layer 144 can be deposited using methods such as ALD, thereby uniformly covering all inner walls of the second via 140 and the portion of the space extending into the first recess 160. Then, an oxide layer 145 can be formed as the gate oxide layer by depositing an oxide. The oxide can be an HK (High K, high dielectric constant) material, for example, a dielectric material with a dielectric constant K greater than or equal to 3.9. Specifically, it can include, but is not limited to, HK materials such as hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), and zirconium oxide (ZrO2).

[0199] Finally, conductive material is filled into the second hole 140 covered with oxide layer 145 as a gate electrode, and the gate electrode and the gate oxide layer constitute the gate structure 143 described above. Specifically, the conductive material can be a metal material or an alloy material, such as a material containing metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can also be a metal oxide material, including metal nitrides, metal silicides, and metal carbides, such as tin-doped indium oxide (ITO), indium-doped zinc oxide (IZO), indium oxide (InO), aluminum-doped zinc oxide (Al-doped ZnO, AZO), iridium oxide (IrOx), and ruthenium oxide (RuOx); and metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN).

[0200] After the gate structure 143 is formed, the parasitic channels 144a between each layer of transistors are removed to obtain the remaining semiconductor layers, i.e., the effective channels 144b are isolated from each other. In this way, a multi-layer stacked transistor array can be formed between the gate structure 143, the effective channels 144b and each first electrode structure 141 and second electrode structure 142.

[0201] In some embodiments, after the gate structure 143 is formed, the sacrificial material in the first hole 130 and the first trench 150 can be removed, and the barrier layer 161 located on the sidewall of the first hole 130 and the first trench 150 extending along the first direction (Z direction) can be removed to expose the sacrificial layer 162.

[0202] Specifically, such as Figure 26 As shown, the protective layer covering the top opening of the first trench 150 and the first hole 130 is first etched away. For example, the protective layer can be silicon nitride material. After the protective layer is removed by dry etching, the sacrificial material of the first hole 130 and the first trench 150 is exposed.

[0203] Next, wet etching can be used to remove the sacrificial material in the first hole 130 and the first trench 150, exposing the barrier layer 161 at the junction of the first groove 160 and the first hole 130 or the first trench 150. Then, wet etching is used to further remove the exposed barrier layer 161, exposing the sacrificial layer 162 in the first groove 160, resulting in... Figure 27 The structure shown is as follows. It should be noted that, since the sacrificial material and the barrier layer 161 are made of different materials, the etching solutions used in the two wet etching steps are different, and the material is etched and removed in two separate steps.

[0204] Then through, as Figures 28 to 29 As shown, the sacrificial layer 162 and the parasitic channel 144a are removed sequentially from the position of the first groove 160. Specifically:

[0205] Step S107: Based on the first hole 130 and the first trench 150, remove the sacrificial layer 162 and retain the barrier layer 161 located in the first groove 160;

[0206] Step S108: Remove the sidewalls (parasitic channel 144a) of the exposed initial semiconductor layer 144 to form a semiconductor layer (effective channel 144b), as shown. Figure 29 As shown.

[0207] Understandably, a barrier layer 161 covers the sidewall of the first groove 160, and there is a contact surface between the barrier layer 161 and the semiconductor layer. The semiconductor layer covered by the barrier layer 161 serves as redundant space for wet etching during the removal of parasitic channels 144a, increasing the process window and effectively improving process stability.

[0208] The contact surface between the barrier layer 161 formed in the first manner in the above embodiments and the semiconductor layer is a surface in the first direction. Its area is determined by the thickness and width of the barrier layer 161. At this position, the barrier layer 161 can block the etching solution when removing the parasitic channel 144a, so that the effective channel 144b can be protected during the removal of the parasitic channel 144a.

[0209] The contact surface 330 between the barrier layer 161 and the conductive channel formed in the second manner in the above embodiments is the portion of the barrier layer 161 exposed on the sidewall of the second hole 140 that contacts the conductive channel. The area of ​​this surface is determined by the thickness and width of the barrier layer 161. Furthermore, the barrier layer 161 also has a portion of its contact surface 330 with the semiconductor layer in a direction parallel to the substrate 110. The area of ​​this surface is determined by the depth of the parasitic channel 144a extending into the first groove 160 and the width of the barrier layer 161. It is evident that the contact surface 330 corresponding to the second scheme has a larger area, which can reduce the oxidation of the first electrode structure 141 and the second electrode structure 142 during the formation of the conductive channel, thereby improving device performance.

[0210] Furthermore, it should be noted that during the process of lateral etching to remove the sacrificial layer 162 and expose the parasitic channel 144a, the passivation layer 112 at the bottom of the first hole 130 and the first trench 150 can effectively isolate the etching solution from the silicon substrate portion of the substrate 110, preventing damage to the silicon substrate.

[0211] In some embodiments, such as Figure 30 As shown, the method also includes:

[0212] After removing the parasitic channel 144a, a fourth isolation layer 241 is formed covering the inner wall of the first hole 130 and the inner wall of the first groove 150.

[0213] Sacrificial material is filled into the first hole 130 and the first groove 150 to obtain the following result: Figure 30 The structure shown.

[0214] The fourth isolation layer 241 is an insulating material that can fill the position after removing the parasitic channel 144a, thereby isolating the effective channel 144b between the layers. Here, the steps of filling the sacrificial material in the first hole 130 and the first trench 150 can be set in a specific order according to the needs of subsequent steps. For example, the above-mentioned fourth isolation layer 241 can be formed and the sacrificial material filled in the first hole 130 and the first trench 150 simultaneously. When it is necessary to form a bit line structure, the sacrificial material in the first trench and the excess fourth isolation layer 241 are removed; when forming a capacitor structure, the sacrificial material in the first hole 130 and the excess fourth isolation layer 241 are removed.

[0215] In some embodiments, the method of manufacturing the semiconductor structure further includes:

[0216] Step S202: Form the dielectric layer and the second electrode plate of the capacitor structure in the first hole 130.

[0217] In the above embodiment, a first electrode plate (i.e., a second electrode structure) of a capacitor structure is formed. Subsequently, a second electrode plate and a dielectric layer between the first and second electrode plates can be further formed. Before forming the dielectric layer of the capacitor structure, the sacrificial material within the first hole 130 can be removed, and the unwanted portion of the fourth isolation layer 241 can be removed. Then, the dielectric layer and the second electrode plate of the capacitor structure can be further formed. The specific implementation process can be designed according to the morphological structure of the capacitor. For example, after removing the sacrificial material within the first hole 130, the dielectric material filling the third groove (i.e., the annular groove surrounding the first hole 130) can be further removed, exposing the second electrode structure attached to the surface of the third groove. Then, an oxide layer, such as silicon oxide, is deposited on the entire exposed surface of the first hole 130 and the third groove to form a structure like... Figure 31The dielectric layer 361 is shown. Finally, conductive material is filled into the gaps (including the first hole 130 and the third groove) where the dielectric layer 361 is attached, forming a second electrode plate 362 that penetrates the first hole 130. The second electrode plate 362 can be led out through the opening at the top of the first hole and grounded or connected to a common electrode. In this way, the second electrode structure 142 (i.e., the first electrode plate of the capacitor structure), the dielectric layer 361, and the second electrode plate 362 constitute a stacked plurality of capacitor structures 360.

[0218] Based on the same inventive concept, this disclosure also provides a semiconductor structure 100, such as... Figure 31 As shown, it includes:

[0219] Substrate 110;

[0220] A multilayer memory cell layer is stacked on the substrate 110 along a first direction (Z direction) perpendicular to the substrate 110; the memory cell layer includes a plurality of memory cells arranged in an array; the memory cell includes: a semiconductor layer (effective channel 144b) and a gate structure 143;

[0221] A semiconductor layer (effective channel 144b) is disposed around the circumferential sidewall of the gate structure 143, and the semiconductor layer (effective channel 144b) contacts the first electrode structure 141 and the second electrode structure 142 in a second direction (X direction) parallel to the surface of the substrate 110.

[0222] The first electrode structure 141 and / or the second electrode structure 142 have a barrier layer 161 attached to at least a portion of their surfaces in a direction parallel to the substrate 110.

[0223] The semiconductor layer (effective channel 144b) has contact surfaces with the barrier layer 161 at both ends in the first direction (Z direction).

[0224] like Figure 32 and 33 As shown, at positions on both sides of the second hole 140, a barrier layer 161 covers at least a portion of the first surface 310 of the first electrode structure 141 and at least a portion of the second surface 320 of the second electrode structure 142; wherein the first surface 310 and the second surface 320 are both surfaces parallel to the substrate 110; the semiconductor layer (effective channel 144b) has a contact surface 330 with the barrier layer 161.

[0225] In some embodiments, the semiconductor layer (effective channel 144b) includes:

[0226] The first portion 340 extends along the first perpendicular direction (Z direction);

[0227] A second portion 350 extends parallel to the surface of the substrate and is located at both ends of the semiconductor layer (effective channel 144b) connected to the first portion 340 in the first direction; wherein the second portion 350 of the semiconductor layer (effective channel 144b) adjacent in the first direction is disconnected.

[0228] In some embodiments, the contact surface 330 between the semiconductor layer (effective channel 144b) and the barrier layer 161 is located at the section where the second portion 350 is disconnected, such as... Figure 32 As shown;

[0229] Alternatively, the contact surface 330 between the barrier layer 161 and the semiconductor layer (effective channel 144b) is located on the surface between the second portion 350 and the first electrode structure 141, and on the surface between the second portion 350 and the second electrode structure 142, such as... Figure 33 As shown.

[0230] Continue to refer to Figure 31 In some embodiments, the first electrode structure 141 is used as a bit line;

[0231] The second electrode structure 142 serves as the first electrode plate of the capacitor structure 360;

[0232] The semiconductor structure 100 also includes a second electrode 362 of a capacitor structure 360 ​​and a dielectric layer 361 located between the first electrode and the second electrode 362.

[0233] In some embodiments, the first electrode plate has an annular cross-section parallel to the substrate surface; and the first electrode plate includes a recessed structure along a direction parallel to the substrate surface.

[0234] The second electrode 362 includes: a first sub-part 362a extending through the multilayer capacitor structure 360 ​​along a first direction (Z direction), a second sub-part 362b connecting the first sub-part and extending into the recessed structure, and a plurality of third sub-parts 362c connecting the first sub-part and extending into the gap between two adjacent first electrodes.

[0235] In some embodiments, the gate structures 143 of memory cells located on the same straight line in the first direction (Z direction) are connected along the first direction (Z direction);

[0236] Furthermore, the first electrode structure 141 of the memory cell located on the same straight line in the third direction (Y direction) is connected along the third direction (Y direction) to serve as a bit line.

[0237] The semiconductor structure 100 described above can be manufactured by the method involved in any of the embodiments provided in this disclosure. For a detailed understanding of the specific structure and implementation, please refer to the description in any of the above embodiments. It will not be repeated here.

[0238] Based on the same inventive concept, this disclosure also provides an electronic device, such as... Figure 34 As shown, the electronic device 400 may include a memory 410 and / or a processor 420. The memory and / or processor may include the semiconductor structure 100 formed by the manufacturing method of the semiconductor structure 100 provided in any of the above embodiments, or include the semiconductor structure 100 provided in any of the above embodiments. The electronic device may be various types of electronic devices such as storage devices, smartphones, computers, tablets, artificial intelligence devices, wearable devices, or power banks. Storage devices may include memory in a computer, etc., and are not limited thereto.

[0239] It should be understood that the phrases "some embodiments," "one embodiment," or "an embodiment" throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0240] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0241] The above description is merely an embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, The method includes: Provide substrate; A stacked layer is formed by alternately stacking a first insulating layer and a second insulating layer along a first direction perpendicular to the substrate. A first hole, a second hole, and a first trench are formed that penetrate the stacked layer and are spaced apart along a second direction parallel to the substrate surface; wherein the first trench extends along a third direction parallel to the substrate surface; the second hole is located between the first hole and the first trench, and the third direction intersects the second direction; Based on the second hole, the first insulating layer is etched laterally to form a plurality of first grooves spaced apart along the first direction; A barrier layer and a sacrificial layer are sequentially formed on the inner wall of the first groove; Based on the second hole and the first groove, an initial semiconductor layer is formed covering the inner wall of the second hole and the first groove, and a gate structure is formed covering the initial semiconductor layer and filling the second hole and the first groove; Based on the first hole and the first trench, the sacrificial layer is removed, and the barrier layer located in the first groove is retained, exposing the sidewalls of the initial semiconductor layer facing the first hole and the first trench; Remove the exposed sidewalls of the initial semiconductor layer to form a semiconductor layer.

2. The manufacturing method according to claim 1, characterized in that, The method further includes: Before forming the barrier layer and the sacrificial layer, a portion of the sacrificial material in the first hole and the first trench is removed by etching the first groove.

3. The manufacturing method according to claim 2, characterized in that, The step of removing a portion of the sacrificial material in the first hole and the first trench by etching through the first groove includes: The sacrificial material in the first hole and the first trench of the first thickness is removed by etching through the first groove; The step of sequentially forming a barrier layer and a sacrificial layer on the inner wall of the first groove includes: A barrier layer with a thickness less than or equal to the first thickness is formed on the inner wall of the first groove; The sacrificial layer is formed on the surface of the barrier layer.

4. The manufacturing method according to claim 1, characterized in that, The step of sequentially forming a barrier layer and a sacrificial layer on the inner wall of the first groove includes: A barrier layer is formed covering the inner wall of the first groove and the inner wall of the second hole; A sacrificial layer is formed to cover the barrier layer; The barrier layer and the sacrificial layer on the sidewall of the second hole are at least removed through the second hole, so that the conductive material of the sidewall of the second hole is exposed to the second hole at intervals, while retaining at least a portion of the barrier layer and the sacrificial layer on the inner wall of the first groove.

5. The manufacturing method according to claim 4, characterized in that, The removal of at least the barrier layer and the sacrificial layer on the sidewall of the second hole through the second hole includes: The sacrificial layer of a second thickness, extending from the sidewall of the second hole into the first groove, is removed through the second hole. Remove the barrier layer that is not covered by the remaining sacrificial layer.

6. The manufacturing method according to claim 4, characterized in that, The removal of at least the barrier layer and the sacrificial layer on the sidewall of the second hole through the second hole includes: The sacrificial layer on the inner wall of the second hole is removed through the second hole, exposing the barrier layer extending in a direction perpendicular to the substrate. Remove the barrier layer that is not covered by all remaining sacrificial layers; Remove the sacrificial layer of a second thickness extending into the first groove.

7. The manufacturing method according to claim 1, characterized in that, The method further includes: Before forming the first groove, sacrificial material is filled into the first hole and the first groove; Before removing the sacrificial layer, the sacrificial material in the first hole and the first trench is removed, and the barrier layer located on the sidewalls of the first hole and the first trench extending along the first direction is removed to expose the sacrificial layer.

8. The manufacturing method according to claim 1, characterized in that, The substrate provided includes: The surface of the substrate is passivated to form the substrate covered with a passivation layer.

9. The manufacturing method according to any one of claims 1 to 8, characterized in that, The formation of the first hole, the second hole, and the first trench, which penetrate the stacked layer and are spaced apart along a second direction parallel to the surface of the substrate, includes: Forming a first hole and a second hole penetrating the stacked layers; The substrate surfaces exposed at the bottom of the first and second holes are passivated. A first isolation layer is formed on the sidewalls of the first hole and the second hole; Sacrificial material is filled into the first and second holes where the isolation layer is formed. Form a first protective layer covering the surface of the stacked layers; Forming a first trench that penetrates the stacked layers; The substrate surface exposed at the bottom of the first trench is passivated.

10. The manufacturing method according to any one of claims 1 to 8, characterized in that, Also includes: Based on the first trench, the second insulating layer is etched laterally to form a plurality of second grooves spaced apart along the first direction; Conductive material is deposited in the second groove to form a first electrode structure, which serves as a bit line.

11. The manufacturing method according to any one of claims 1 to 8, characterized in that, Also includes: Based on the first hole, the second insulating layer is etched laterally to form a plurality of third grooves spaced apart along the first direction; A conductive layer is formed on the inner wall of the third groove to form a second electrode structure; wherein the second electrode structure serves as the first electrode plate of the capacitor structure.

12. A semiconductor structure, characterized in that, include: Substrate; A multilayer of memory cells stacked on the substrate along a first direction perpendicular to the substrate; The storage unit layer includes multiple storage units arranged in an array; The memory cell includes: a semiconductor layer and a gate structure; The semiconductor layer is disposed around the circumferential sidewall of the gate structure, and the semiconductor layer is in contact with the first electrode structure and the second electrode structure in a second direction parallel to the substrate surface. The first electrode structure and / or the second electrode structure have a barrier layer attached to at least a portion of the surface parallel to the substrate direction; The semiconductor layer has contact surfaces with the barrier layer at both ends in the first direction.

13. The semiconductor structure according to claim 12, characterized in that, The semiconductor layer includes: The first portion extending along the first direction; Extending in a direction parallel to the substrate, and located at the second portion of the semiconductor layer connected to the first portion at both ends in the first direction; wherein the second portion of the semiconductor layer adjacent in the first direction is disconnected.

14. The semiconductor structure according to claim 13, characterized in that, The contact surface between the semiconductor layer and the barrier layer is located at the section where the second part is disconnected; Alternatively, the contact surface between the barrier layer and the semiconductor layer is located on the surface between the second portion and the first electrode structure, and on the surface between the second portion and the second electrode structure.

15. The semiconductor structure according to claim 12, characterized in that, The first electrode structure is used as a bit line; The second electrode structure serves as the first electrode plate of the capacitor structure; The semiconductor structure further includes a second electrode of the capacitor structure and a dielectric layer located between the first electrode and the second electrode.

16. The semiconductor structure according to claim 15, characterized in that, The first electrode plate has an annular cross-section parallel to the substrate surface; and the first electrode plate includes a recessed structure along a direction parallel to the substrate surface. The second electrode plate includes: a first sub-section extending along the first direction through the multilayer capacitor structure, a second sub-section connecting the first sub-section and extending into the recessed structure, and a plurality of third sub-sections connecting the first sub-section and extending into the gap between two adjacent first electrode plates.

17. The semiconductor structure according to claim 15, characterized in that, The gate structure of the memory cell located on the same straight line in the first direction is connected along the first direction; Furthermore, the first electrode structure of the memory cell, which is located on the same straight line in a third direction parallel to the substrate, is connected along the third direction to serve as the bit line.

18. An electronic device, characterized in that, This includes a semiconductor structure formed by the manufacturing method of the semiconductor structure according to any one of claims 1 to 11, or a semiconductor structure according to any one of claims 12 to 17.

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