Semiconductor device and manufacturing method thereof, electronic device

Abstract

A semiconductor device and a manufacturing method thereof, and an electronic device, the semiconductor device comprising: a plurality of memory cells distributed in different layers stacked along a vertical substrate direction; a bit line extending along the vertical substrate direction through the memory cells in different layers; a plurality of word lines distributed in different layers, the word lines and the bit line being distributed along a first direction parallel to the substrate, the word lines extending along a second direction parallel to the substrate; the memory cell comprising a transistor, the transistor comprising a semiconductor layer extending along the first direction, the plurality of semiconductor layers of the plurality of memory cells being connected to the bit line; the word line surrounding one of a side of the semiconductor layer facing away from the substrate and a side of the semiconductor layer facing the substrate, and the semiconductor layer being oppositely arranged on two sides along the second direction. The scheme provided by the embodiment can reduce the size of the device in the vertical direction and reduce the process difficulty.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, device design and manufacturing in the field of semiconductor technology, and particularly to a semiconductor device and its manufacturing method, and electronic equipment. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that any slight difference in the manufacturing process can affect the performance of the devices.

[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This application provides a semiconductor device and its manufacturing method, as well as an electronic device, which can reduce device size and lower process complexity.

[0006] This application provides a semiconductor device, including:

[0007] Multiple memory cells are stacked along the vertical substrate direction, distributed across different layers;

[0008] Bit lines extend through the memory cells in different layers along a direction perpendicular to the substrate;

[0009] Multiple word lines are distributed in different layers. The word lines and the bit lines are distributed along a first direction parallel to the substrate, and the word lines extend along a second direction parallel to the substrate. The first direction and the second direction intersect.

[0010] The memory cell includes a transistor, the transistor including a semiconductor layer extending along a first direction, and a plurality of semiconductor layers of the plurality of memory cells being connected to the bit line; the word line surrounds the semiconductor layer on the side away from the substrate, and the semiconductor layer is disposed opposite to each other on the side facing the substrate along the second direction, and is not distributed on the side facing the substrate of the semiconductor layer; or, the word line surrounds the semiconductor layer on the side facing the substrate, and the semiconductor layer is disposed opposite to each other on the side facing the substrate along the second direction, and is not distributed on the side facing the substrate of the semiconductor layer.

[0011] In some embodiments, the semiconductor device includes: a multilayer memory cell array, each layer of the memory cell array including a plurality of memory cells arrayed along a first direction and a second direction; word lines surrounding a plurality of semiconductor layers of a plurality of transistors arrayed in the same column along a second direction, the word lines including a horizontal portion extending along the second direction and a plurality of vertical portions extending from the horizontal portion to adjacent semiconductor layers along the second direction, wherein the horizontal portion and the vertical portion are integral structures.

[0012] In some embodiments, the vertical portion includes a first recessed region on the side facing the bit line, and the vertical portion includes a second recessed region on the side away from the bit line. The first recessed region and the second recessed region are disposed opposite to each other along a first direction and have opposite recessed directions.

[0013] In some embodiments, the semiconductor layer has protrusions on opposite sides along the second direction that protrude parallel to the substrate direction. From the location of the protrusion toward the bit line, the size of the semiconductor layer along the second direction decreases sequentially; from the location of the protrusion away from the bit line, the size of the semiconductor layer along the second direction decreases sequentially.

[0014] In some embodiments, the transistor further includes a first connection layer disposed between the semiconductor layer and the bit line, the first connection layer covering the semiconductor layer on the side facing the bit line, and the semiconductor layer being connected to the bit line through the first connection layer.

[0015] In some embodiments, the transistor further includes a first electrode disposed on the side of the semiconductor layer away from the bit line, the first electrode forming an annular groove with an opening direction parallel to the substrate, and a second connection layer disposed between the semiconductor layer and the first electrode, the second connection layer covering the side of the semiconductor layer facing the first electrode and connecting the outer bottom wall of the first electrode and the semiconductor layer.

[0016] In some embodiments, the semiconductor layer includes a first region, a channel region, and a second region sequentially disposed along the first direction, the word line portion surrounds the channel region and is not distributed in the first region and the second region, the second region is disposed in the first region on the side facing the bit line, and the transistor further includes a gate insulating layer disposed between the semiconductor layer and the word line, the gate insulating layer being distributed in the channel region and the second region of the semiconductor layer.

[0017] In some embodiments, the semiconductor device further includes: a first isolation sublayer disposed between adjacent bit lines along a second direction and penetrating multiple layers, and a second isolation sublayer disposed between adjacent semiconductor layers along the second direction and penetrating multiple layers, wherein the first isolation sublayer is connected to a first recessed region of a plurality of word lines spaced apart along a direction perpendicular to the substrate and to two bit lines adjacent along the second direction; and the second isolation sublayer is connected to a second recessed region of a plurality of word lines spaced apart along a direction perpendicular to the substrate and to two first electrodes adjacent along the second direction.

[0018] In some embodiments, the storage cell further includes: a capacitor, the capacitor including a first sub-electrode and a second sub-electrode, the first electrode surrounding the first sub-electrode, the first sub-electrode being distributed on the inner wall of the annular groove formed by the first electrode; the first sub-electrodes of storage cells at the same position in different layers are connected to form an integral structure; the second sub-electrode is distributed on a portion of the outer bottom wall of the annular groove formed by the first electrode.

[0019] In some embodiments, the second sub-electrodes of capacitors in the same column distributed along the second direction in the same layer are connected to form an integral structure; the second sub-electrode includes a connecting portion extending along a direction perpendicular to the substrate and a plurality of horizontal extension portions spaced apart along a direction perpendicular to the substrate and extending along a direction parallel to the substrate, the horizontal extension portions being distributed on a portion of the outer bottom wall of the annular groove formed by the first electrode.

[0020] This disclosure provides a method for manufacturing a semiconductor device, including:

[0021] A stacked structure comprising a plurality of sequentially stacked first insulating layers, first dummy layers, and first sacrificial layers is formed on a substrate; or, a stacked structure comprising a plurality of sequentially stacked first insulating layers, first sacrificial layers, and first dummy layers is formed.

[0022] A plurality of first holes are formed that penetrate the stacked structure along a direction perpendicular to the substrate and are spaced apart along a second direction parallel to the substrate;

[0023] A first trench is formed that penetrates the stacked structure in a direction perpendicular to the substrate and extends in a second direction. Based on the first trench, the first dummy layer and the first sacrificial layer are etched in a direction parallel to the substrate until the first hole is away from the first trench, forming a first lateral trench.

[0024] A second hole is formed on the side of the first hole away from the first trench, penetrating the stacked structure perpendicular to the substrate direction, and the first hole and the second hole are spaced apart along a first direction parallel to the substrate;

[0025] A third and a fourth hole are formed through the stacked structure in a direction perpendicular to the substrate. The third and fourth holes are spaced apart in a first direction. The fourth hole is disposed between adjacent second holes in a second direction. The third hole is disposed on the side of the fourth hole facing the first trench and on the side of the first hole facing away from the first trench. The first dummy layer is etched based on the third and fourth holes to form a second groove surrounding the third hole and a third groove surrounding the fourth hole. The first dummy layer forms a plurality of dummy sublayers spaced apart in a second direction.

[0026] A second sacrificial layer is formed to fill the second and third grooves. The dummy sublayer is removed based on the first and second holes to form a channel communicating with the first and second holes. A semiconductor layer is formed in the channel. The first and second sacrificial layers are etched based on the second hole to expose a portion of the semiconductor layer facing the side of the first sacrificial layer connected to the semiconductor layer, and a portion of the two sides disposed opposite to each other along the second direction. Word lines are formed around the semiconductor layer facing the side of the first sacrificial layer connected to the semiconductor layer, and the two sides of the semiconductor layer disposed opposite to each other along the second direction.

[0027] A bit line is formed in the second hole, extending in a direction perpendicular to the substrate, and the bit line connects multiple semiconductor layers in multiple channels communicating with the second hole.

[0028] In some embodiments, before forming word lines on both sides of the semiconductor layer facing the first sacrificial layer connected to the semiconductor layer, and before forming word lines on both sides of the semiconductor layer that are disposed opposite to each other along the second direction, the method further includes: thermally oxidizing the exposed surface of the semiconductor layer to form a gate insulating layer;

[0029] Before the second hole is formed with a bit line extending perpendicular to the substrate, the method further includes: performing metallization on the end face of the semiconductor layer facing the second hole to form a first interconnect layer.

[0030] In some embodiments, before forming a first trench that extends through the stacked structure in a direction perpendicular to the substrate and extends in a second direction, the method further includes: etching the first dummy layer and the first sacrificial layer in a direction parallel to the substrate based on the first hole to form a first groove;

[0031] After the second hole is formed with a bit line extending perpendicular to the substrate direction, the method further includes: performing metallization treatment on the end face of the semiconductor layer facing the first hole to form a second interconnect layer;

[0032] A first electrode is formed on the inner wall of the first groove and connected to the second connecting layer.

[0033] This disclosure provides an electronic device, including any of the semiconductor devices described above, or a semiconductor device formed according to the manufacturing method of the semiconductor device described above.

[0034] This application includes a semiconductor device and a method for manufacturing the same, as well as an electronic device. The semiconductor device includes: a plurality of memory cells stacked in different layers along a direction perpendicular to a substrate; bit lines extending through the memory cells in different layers along a direction perpendicular to the substrate; a plurality of word lines distributed in different layers, the word lines and the bit lines being distributed along a first direction parallel to the substrate, the word lines extending along a second direction parallel to the substrate, the first direction and the second direction intersecting; each memory cell includes a transistor, the transistor including a semiconductor layer extending along the first direction, and the plurality of semiconductor layers of the plurality of memory cells being connected to the bit lines; the word lines surround the semiconductor layer on a side away from the substrate, and are located on two opposite sides of the semiconductor layer along the second direction, but are not distributed on the side of the semiconductor layer facing the substrate; or, alternatively, the word lines surround the semiconductor layer on a side facing the substrate, and are located on two opposite sides of the semiconductor layer along the second direction, but are not distributed on the side of the semiconductor layer away from the substrate. The solution provided by this disclosure, where the word lines are distributed on one side of the opposite sides of the semiconductor layer along the direction perpendicular to the substrate, reduces the size of the device along the direction perpendicular to the substrate, lowers the process difficulty, and maintains good gate control performance.

[0035] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the embodiments described in the description and the accompanying drawings.

[0036] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0037] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0038] Figures 1A to 1D These are cross-sectional views of the semiconductor device provided in the embodiments of this disclosure along the A1A1' direction parallel to the substrate, the B1B1' direction, the CC' direction perpendicular to the substrate, and the DD' direction, respectively.

[0039] Figures 2A to 2D Cross-sectional views along the AA', BB', CC', and DD' directions after the formation of the first hole are provided in some embodiments;

[0040] Figures 3A to 3C Cross-sectional views along the AA', BB', and CC' directions after the formation of the first groove are provided in some embodiments;

[0041] Figures 4A to 4C Cross-sectional views along the AA', BB', and CC' directions after the formation of the first trench and the first transverse trench, respectively, are provided in some embodiments.

[0042] Figures 5A to 5C Cross-sectional views along the AA', BB', and CC' directions after the formation of the fifth insulating layer and the third dummy layer, respectively, are provided in some embodiments.

[0043] Figures 6A to 6C Cross-sectional views along the AA', BB', and CC' directions after the second hole is formed, provided in some embodiments;

[0044] Figures 7A to 7C Cross-sectional views along the AA' direction, B1B1' direction, and DD' direction after forming the third hole, fourth hole, second groove, and third groove, respectively, according to some embodiments;

[0045] Figures 8A to 8C Cross-sectional views along the AA' direction, B1B1' direction, and DD' direction after the formation of the second sacrificial layer and the eighth insulating layer are provided in some embodiments;

[0046] Figures 9A to 9D Cross-sectional views along the AA', B1B1', CC', and DD' directions after the channel is formed, provided in some embodiments;

[0047] Figures 10A to 10D Cross-sectional views along the AA', B1B1', CC', and DD' directions after the formation of the ninth insulating layer and the fifth dummy layer, respectively, are provided in some embodiments.

[0048] Figures 11A to 11D These are cross-sectional views along the AA', B1B1', CC', and DD' directions after the word lines have been formed, provided in some embodiments.

[0049] Figures 12A to 12C These are cross-sectional views along the AA', B1B1', and CC' directions after the bit lines are formed, provided in some embodiments. Detailed Implementation

[0050] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the embodiments of this disclosure and the features thereof can be combined arbitrarily with each other.

[0051] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains.

[0052] The embodiments disclosed herein are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this disclosure are not limited to the shapes or values ​​shown in the drawings.

[0053] The ordinal numbers “first,” “second,” “third,” etc., used in this disclosure are provided to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0054] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the disclosure is not limited to the terms used herein and may be appropriately replaced as appropriate.

[0055] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to physical or signal connections, contact or integral connections; direct connections, indirect connections via intermediate components, or internal communication between two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure according to the specific circumstances.

[0056] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0057] In this disclosure, the first electrode may be the drain electrode and the second electrode may be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0058] In this disclosure, "connection" includes the situation where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0059] In this disclosure, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0060] In this embodiment of the disclosure, "A and B are an integral structure" can refer to a structure without obvious boundaries such as discontinuities or gaps in its microstructure. Generally, an integral structure is formed by patterning interconnected membrane layers on a single membrane layer. For example, A and B may be formed using the same material as a single membrane layer and simultaneously created through the same patterning process, resulting in a structure with interconnected relationships.

[0061] Figures 1A to 1D These are cross-sectional views of a semiconductor device provided in this disclosure along the A1A1' direction parallel to the substrate, the B1B1' direction, the CC' direction perpendicular to the substrate 1, and the DD' direction. The A1A1' direction passes through the film layer containing the word line 40 but does not pass through the semiconductor layer 23; the B1B1' direction passes through the semiconductor layer 23; the CC' direction passes through the semiconductor layer 23 and the bit line 30; and the DD' direction passes through the semiconductor layer 23 and the word line 40. Figures 1A to 1D As shown, this disclosure provides a semiconductor device, including:

[0062] Multiple memory cells are stacked along the direction perpendicular to substrate 1, distributed across different layers;

[0063] Bit line 30 extends through the memory cells in different layers along a direction perpendicular to the substrate 1;

[0064] Multiple word lines 40 are distributed in different layers. The word lines 40 and the bit lines 30 are distributed along a first direction X parallel to the substrate 1. The first direction X intersects with the second direction Y. The word lines 40 extend along the second direction Y parallel to the substrate.

[0065] The memory cell includes a transistor, the transistor including a semiconductor layer 23 extending along a first direction X. A word line 40 surrounds the semiconductor layer 23 on the side facing away from the substrate 1, and the semiconductor layer 23 has two opposite sides disposed along a second direction Y, but not distributed on the side facing the substrate 1. Alternatively, the word line 40 surrounds the semiconductor layer 23 on the side facing the substrate 1, and the semiconductor layer 23 has two opposite sides disposed along the second direction Y, but not distributed on the side facing away from the substrate 1. Multiple semiconductor layers 23 of the plurality of memory cells are connected to the bit line 30. Figures 1A to 1D The diagram shows a structure where word lines 40 are distributed on the side of semiconductor layer 23 away from substrate 1. A similar structure exists where word lines 40 are distributed on the side of semiconductor layer 23 facing substrate 1; the word lines 40 simply extend parallel to substrate 1 on the side of semiconductor layer 23 facing substrate 1.

[0066] The solution provided in this embodiment distributes word lines on one side of the semiconductor layer that are opposite each other along the direction perpendicular to the substrate, and not on the other side. This can reduce the size of the memory cell along the direction perpendicular to the substrate while maintaining good gate control performance, thereby reducing the device size. Furthermore, it can reduce the depth of the vertically etched holes during manufacturing, thus reducing the difficulty of the process.

[0067] In some embodiments, the semiconductor layer 23 may be a solid structure.

[0068] In some embodiments, the first direction X and the second direction Y can be perpendicular.

[0069] In some embodiments, the semiconductor device includes: a multilayer memory cell array, each layer of the memory cell array including a plurality of memory cells distributed along the first direction X and the second direction Y.

[0070] In some embodiments, the word line 40 includes a horizontal portion extending along a second direction Y and a plurality of vertical portions extending from the horizontal portion to adjacent semiconductor layers 23 along the second direction Y. The horizontal portion and the vertical portion can be an integral structure. The solution provided in this embodiment can form the horizontal and vertical portions of the word line in one step, simplifying the process and reducing costs.

[0071] In some embodiments, such as Figure 1B As shown, the semiconductor layer 23 has protrusions on both sides opposite to each other along the second direction Y, which are parallel to the substrate 1. From the location of the protrusion toward the bit line 30, the size of the semiconductor layer 23 along the second direction Y decreases sequentially; from the location of the protrusion away from the bit line 30, the size of the semiconductor layer 23 along the second direction Y decreases sequentially.

[0072] In some embodiments, the semiconductor layer 23 includes a first region, a channel region, and a second region sequentially disposed along a first direction X. The word line 40 partially surrounds the channel region and is not distributed in the first region and the second region. The second region is disposed on the side of the first region facing the bit line 30.

[0073] In some embodiments, the vertical portion includes a first recessed region on the side facing the bit line 30, and the vertical portion includes a second recessed region on the side away from the bit line 30. The first recessed region and the second recessed region are arranged opposite to each other along a first direction X and have opposite recessed directions. The recessed direction of the first recessed region is away from the bit line 30, and the recessed direction of the second recessed region is towards the bit line 30.

[0074] In some embodiments, the transistor may further include a first connection layer 61 disposed between the semiconductor layer 23 and the bit line 30 and connecting the semiconductor layer 23 and the bit line 30, the first connection layer 61 covering the semiconductor layer 23 on the side facing the bit line 30.

[0075] In some embodiments, the dimension of the bit line 30 along the second direction Y can be larger than the dimension of the semiconductor layer 23 facing the bit line 30 along the second direction Y. The solution provided in this disclosure allows for a larger bit line 30, maximizing the contact area with the semiconductor layer 23 facing the bit line 30 and reducing contact resistance.

[0076] In some embodiments, the transistor may further include a second interconnect layer 62 and a first electrode (i.e., a first capacitor electrode 41) disposed on the side of the semiconductor layer 23 opposite to the bit line 30. The first electrode forms an annular groove with its opening direction parallel to the substrate 1. The second interconnect layer 62 is distributed between the semiconductor layer 23 and the first electrode and connects the outer bottom wall of the semiconductor layer 23 and the first electrode. The second interconnect layer 62 covers the side of the semiconductor layer 23 facing the first electrode. Here, the side of the semiconductor layer 23 facing the first electrode is the end face of the semiconductor layer 23 furthest from the bit line 30. The annular groove formed by the first electrode includes a bottom wall and side walls. The bottom wall includes an inner bottom wall located inside the annular groove and an outer bottom wall located outside the annular groove.

[0077] In some embodiments, the dimension of the first electrode in the direction perpendicular to the substrate 1 is larger than the dimension of the semiconductor layer 23 in the direction perpendicular to the substrate 1.

[0078] In some embodiments, the semiconductor layer 23 may be monocrystalline silicon, and the first interconnect layer 61 and the second interconnect layer 62 may be metal silicides.

[0079] In some embodiments, the transistor further includes a gate insulating layer 24 disposed between the semiconductor layer 23 and the word line 40, and multiple gate insulating layers 24 of multiple transistors distributed in the same column along the second direction Y are connected to form an integral structure, and the gate insulating layer 24 is distributed in the channel region and the second region of the semiconductor layer 23.

[0080] In some embodiments, the gate insulating layer 24 can be an oxide formed by oxidizing the same semiconductor material as the semiconductor layer 23. That is, a semiconductor film layer can be formed, and the surface of the semiconductor film layer can be oxidized to form the gate insulating layer 24, with the remaining unoxidized semiconductor film layer serving as the semiconductor layer 23. However, the embodiments of this disclosure are not limited to this; the gate insulating layer 24 can be formed without oxidizing the semiconductor film layer, and can be obtained by depositing a dielectric film layer on the semiconductor film layer.

[0081] In some embodiments, the semiconductor device further includes: a first isolation sublayer 81 disposed between adjacent bit lines 30 along the second direction Y and penetrating multiple layers, and a second isolation sublayer 82 disposed between adjacent semiconductor layers 23 along the second direction and penetrating multiple layers. The first isolation sublayer 81 is connected to a first recessed region of a plurality of word lines 40 spaced apart along a direction perpendicular to the substrate 1 and to two bit lines 30 adjacent along the second direction Y; the second isolation sublayer 82 is connected to a second recessed region of a plurality of word lines 40 spaced apart along a direction perpendicular to the substrate 1 and to two first electrodes adjacent along the second direction Y. In subsequent manufacturing process embodiments, the eighth insulating layer 18 includes the first isolation sublayer 81 and the second isolation sublayer 82.

[0082] In some embodiments, the storage unit may further include: a capacitor, the capacitor including a first sub-electrode 421, the first electrode surrounding the first sub-electrode 421, a first dielectric layer 431 disposed between the first electrode and the first sub-electrode 421, the first sub-electrode 421 being distributed on the inner wall of the annular groove formed by the first electrode; the first sub-electrodes 421 of storage units at the same position in different layers are connected to form an integral structure.

[0083] In some embodiments, the capacitor further includes a second sub-electrode 422 and a second dielectric layer 432, the second sub-electrode 422 being distributed on a portion of the outer bottom wall of the annular groove formed by the first electrode, and the second dielectric layer 432 being disposed between the second sub-electrode 422 and the first electrode.

[0084] In some embodiments, the second sub-electrodes 422 of capacitors at the same location in different layers can be connected to form an integral structure.

[0085] In some embodiments, the second dielectric layer 432 of capacitors at the same location on different layers can be connected to form an integral structure.

[0086] In some embodiments, the second sub-electrodes 422 of capacitors distributed in the same column along the second direction Y in the same layer can be connected to form an integral structure. The second sub-electrode 422 may include a connecting portion (which may be a planar film layer) extending in a direction perpendicular to the substrate 1 and a plurality of horizontal extension portions spaced apart in a direction perpendicular to the substrate 1 and extending in a direction parallel to the substrate 1, the horizontal extension portions being distributed on a portion of the outer bottom wall of the annular groove formed by the first electrode.

[0087] In some embodiments, the second dielectric layers 432 of capacitors distributed in the same column along the second direction Y in the same layer can be connected to form an integral structure.

[0088] The technical solution of this embodiment is further illustrated below through the manufacturing process of the semiconductor device in this embodiment. In this embodiment, a film pattern is formed through a "patterning process" or a "photolithography process." The "patterning process" includes processes such as film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, which are mature manufacturing processes in related technologies. The "photolithography process" in this embodiment includes film coating, mask exposure, and development, which are mature manufacturing processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations. In the description of this embodiment, it should be understood that a "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or photolithography process during the entire manufacturing process, it can also be called a "layer." If the "thin film" requires a patterning process or photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning or photolithography process contains at least one "pattern".

[0089] In one exemplary embodiment, the manufacturing process of the semiconductor device may include:

[0090] 1) Form the first hole K1;

[0091] A substrate 1 is provided, and a first insulating film, a first dummy layer film, and a first sacrificial layer film are sequentially deposited on the substrate 1. This process is repeated multiple times to form a stacked structure comprising multiple sequentially arranged first insulating layers 11, first dummy layers 71, and first sacrificial layers 5. A second insulating film may be deposited on the top layer of the stacked structure to form a second insulating layer 12 covering the stacked structure.

[0092] The second insulating layer 12 and the stacked structure are etched from the top to the bottom along a direction perpendicular to the substrate 1 (etching may stop at the bottommost first insulating layer 11, but is not limited thereto; the substrate 1 may or may not be exposed), forming a plurality of first holes K1 spaced apart along the second direction Y; when manufacturing the memory array, the plurality of first holes K1 spaced apart along the second direction Y are referred to as a row of first holes K1, and multiple rows of first holes K1 spaced apart along the first direction X can be formed; such as Figures 2A to 2D As shown, Figures 2A to 2D These are cross-sectional views along the AA', BB', CC', and DD' directions after the formation of the first hole K1, provided in some embodiments.

[0093] In some embodiments, substrate 1 may be a conventional silicon substrate or other bulk substrate including a semiconductor material layer.

[0094] In some embodiments, the first insulating film may be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide (SiO2), etc. The materials of the subsequent second to eleventh insulating films are similar to those of the first insulating film, and will not be described again.

[0095] In some embodiments, the first sacrificial layer film may be a film layer with an etching selectivity ratio to the first insulating film, such as silicon nitride (SiN). The material of the subsequent second sacrificial layer film is similar to that of the first sacrificial layer film, and will not be described again.

[0096] In some embodiments, the first dummy layer film may be a material with an etching selectivity ratio to the first insulating film and the first sacrificial layer film, such as polysilicon. The materials of the subsequent second to sixth dummy layer films are similar to those of the first dummy layer film and will not be described again.

[0097] 2) Form the first groove;

[0098] Based on the first hole K1, the first dummy layer 71 and the first sacrificial layer 5 are etched laterally (along the direction parallel to the substrate 1) to form the first groove;

[0099] After sequentially depositing a third insulating film and a second dummy layer film, the layers are ground smooth. The third insulating film covers the bottom and side walls of the first hole K1, as well as the inner wall of the first groove. The second dummy layer film fills the first hole K1 and the first groove, forming a third insulating layer 13 and a second dummy layer 72. Figures 3A to 3C As shown, Figures 3A to 3C These are cross-sectional views along the AA', BB', and CC' directions after the formation of the first groove, provided in some embodiments.

[0100] 3) Form the first trench T1 and the first transverse trench L1;

[0101] A fourth insulating film is deposited to form a fourth insulating layer 14, which covers the aforementioned structure, including covering the side of the second dummy layer 72 away from the substrate 1, so as to protect the second dummy layer 72 in subsequent operations.

[0102] The fourth insulating layer 14, the second insulating layer 12, and the stacked structure are etched along a direction perpendicular to the substrate 1 to form a first trench T1 penetrating the stacked structure; the first trench T1 extends along the second direction Y.

[0103] Based on the first trench T1, the first dummy layer 71 and the first sacrificial layer 5 are laterally etched to the side of the first hole K1 away from the first trench T1, forming a first lateral trench L1. At this time, the third insulating layer 13 in the first hole K1 is located in the outer wall between the adjacent first insulating layers 11. The area away from the first trench T1 is covered by the first dummy layer 71 and the first sacrificial layer 5, while the rest is exposed, such as... Figures 4A to 4C As shown, Figures 4A to 4C These are cross-sectional views along the AA', BB', and CC' directions after the formation of the first trench T1 and the first transverse trench L1, respectively, provided in some embodiments.

[0104] 4) Form the fifth insulating layer 15 and the third dummy layer 73;

[0105] A fifth insulating film and a third dummy layer film are deposited sequentially. The fifth insulating film covers the bottom and sidewalls of the first trench T1 and the inner wall of the first transverse trench L1. The third dummy layer 73 fills the first trench T1 and the first transverse trench L1, forming the fifth insulating layer 15 and the third dummy layer 73. Figures 5A to 5C As shown, Figures 5A to 5C These are cross-sectional views along the AA', BB', and CC' directions after the formation of the fifth insulating layer 15 and the third dummy layer 73, respectively, provided in some embodiments.

[0106] 5) Form the second hole K2;

[0107] The fourth insulating layer 14 (which was chemically mechanically polished (CMP) during the formation of the fifth insulating layer 15 and the third dummy layer 73, so the remaining portion of the fourth insulating layer 14 may or may not remain; therefore, the film etched here may or may not contain the fourth insulating layer 14), the second insulating layer 12, and the stacked structure are etched along a direction perpendicular to the substrate 1 to form a plurality of second holes K2 penetrating the stacked structure; the plurality of second holes K2 are spaced apart along the second direction Y; the first hole K1 and the second hole K2 are spaced apart along the first direction X; the bottom wall of the second hole K2 may expose the substrate 1.

[0108] After sequentially depositing a sixth insulating film and a fourth dummy layer film, the layers are ground smooth. The sixth insulating film covers the bottom and sidewalls of the second hole K2, and the fourth dummy layer film fills the second hole K2, forming a sixth insulating layer 16 and a fourth dummy layer 74. After grinding, the side of the fourth dummy layer 74 facing away from the substrate 1 is flush with the side of the second dummy layer 72 facing away from the substrate 1 and the side of the third dummy layer 73 facing away from the substrate 1. Figures 6A to 6C As shown, Figures 6A to 6C These are cross-sectional views along the AA', BB', and CC' directions after the formation of the second hole K2, provided in some embodiments.

[0109] 6) Form the third hole K3, the fourth hole K4, the second groove, and the third groove;

[0110] A seventh insulating film is deposited to form a seventh insulating layer 17 covering the structure formed above;

[0111] The seventh insulating layer 17, the second insulating layer 12, and the stacked structure are etched along a direction perpendicular to the substrate 1 to form a plurality of third holes K3 and a plurality of fourth holes K4 penetrating the stacked structure. The third holes K3 and fourth holes K4 are spaced apart along a first direction X. The plurality of third holes K3 are spaced apart along a second direction Y. The plurality of fourth holes K4 are spaced apart along a second direction Y. The fourth holes K4 are disposed between adjacent second holes K2 along the second direction Y. The third holes K3 are disposed on the side of the fourth holes K4 facing the first trench T1. The first holes K1 are on the side facing away from the first trench T1. The size of the fourth holes K4 along the first direction X is larger than the size of the second holes K2 along the first direction X.

[0112] Based on the third hole K3 and the fourth hole K4, the first dummy layer 71 is etched to form a second groove surrounding the third hole K3 and a third groove surrounding the fourth hole K4, and to form a plurality of dummy sub-layers 71' in the first dummy layer 71; the dummy sub-layers 71' are disposed between the first hole K1 and the second hole K2, and adjacent dummy sub-layers 71' are disconnected along the second direction Y. The dummy sub-layers 71' are connected to the third insulating layer 13 in the first groove and to the sixth insulating layer 16 in the second hole K2. The third hole K3 and the fourth hole K4 adjacent along the first direction X are connected in the film layer where the first dummy layer 71 is located, that is, the second groove and the third groove are connected. Figures 7A to 7C As shown, Figures 7A to 7C These are cross-sectional views along the AA', B1B1', and DD' directions after the formation of the third hole K3, fourth hole K4, second groove, and third groove, respectively, according to some embodiments. In these views, adjacent third holes K3 along the second direction Y are kept disconnected, and adjacent fourth holes K4 along the second direction Y are also kept disconnected.

[0113] In some embodiments, when etching the first dummy layer 71, the fifth insulating layer 15 may be etched to expose the third dummy layer 73. Etching the exposed third dummy layer 73 causes the second groove to extend between adjacent first holes K1 along the second direction Y. However, the embodiments of this disclosure are not limited to this, and the fifth insulating layer 15 may not be etched.

[0114] 7) Form the second sacrificial layer 6 and the eighth insulating layer 18;

[0115] A second sacrificial layer film is deposited, which covers the bottom wall and sidewall of the third hole K3, fills the second groove, covers the bottom wall and sidewall of the fourth hole K4, and fills the third groove; the second sacrificial layer film on the bottom wall and sidewall of the third hole K3 and the fourth hole K4 is etched away, and the second sacrificial layer film in the second groove and the third groove is retained to form the second sacrificial layer 6;

[0116] After depositing the eighth insulating film, it is ground smooth to form the eighth insulating layer 18 filling the third hole K3 and the fourth hole K4; as shown. Figures 8A to 8C As shown, Figures 8A to 8C These are cross-sectional views along the AA', B1B1', and DD' directions respectively, provided in some embodiments after the formation of the second sacrificial layer 6 and the eighth insulating layer 18.

[0117] 8) Form channel B1;

[0118] The seventh insulating layer 17 is etched to expose the second dummy layer 72 in the first hole K1 and the fourth dummy layer 74 in the second hole K2;

[0119] The second dummy layer 72 and the fourth dummy layer 74 are etched away to expose the first hole K1, the first groove, and the second hole K2; the third insulating layer 13 is etched so that the sidewall of the first hole K1 exposes the dummy sublayer 71'; and the sixth insulating layer 16 is etched so that the sidewall of the second hole K2 exposes the dummy sublayer 71'; at this time, the third dummy layer 73 is not exposed in the first hole K1; the bottom wall of the second hole K2 can expose the substrate 1.

[0120] Based on the first hole K1, the first groove, and the second hole K2, the dummy sublayer 71' is etched away to form channel B1; adjacent first holes K1 and second holes K2 along the first direction X are connected through channel B1, such as... Figures 9A to 9D As shown, Figures 9A to 9D These are cross-sectional views along the AA', B1B1', CC', and DD' directions after the formation of channel B1, provided in some embodiments.

[0121] 9) Form the ninth insulating layer 19 and the fifth dummy layer 75;

[0122] A semiconductor structure layer 23' is formed by epitaxial growth of a semiconductor thin film in the first hole K1, the first groove, the second hole K2, and the channel B1. The semiconductor structure layer 23' covers the bottom wall and sidewalls of the first hole K1, fills the first groove and the channel B1, and covers the bottom wall and sidewalls of the second hole K2. In this embodiment, the semiconductor structure layer 23' is formed by epitaxial growth based on the silicon substrate exposed by the bottom wall of the second hole K2. However, the embodiments of this disclosure are not limited to this. In some embodiments, the bottom wall of the first hole K1 may expose the silicon substrate, and the semiconductor structure layer 23' can be formed by epitaxial growth through the silicon substrate exposed by the bottom wall of the first hole K1.

[0123] The semiconductor film in the bottom and sidewalls of the first hole K1 and the bottom and sidewalls of the second hole K2 is removed by etching, while the semiconductor film in the first groove and the channel B1 is retained.

[0124] After sequentially depositing the ninth insulating film and the fifth dummy layer film, the layers are smoothed. The ninth insulating film covers the bottom and sidewalls of the first hole K1 and the second hole K2. The fifth dummy layer film fills the first hole K1 and the second hole K2, forming the ninth insulating layer 19 and the fifth dummy layer 75. The side of the fifth dummy layer 75 facing away from the substrate 1 is flush with the side of the third dummy layer 73 facing away from the substrate 1. Figures 10A to 10D As shown, Figures 10A to 10D These are cross-sectional views along the AA', B1B1', CC', and DD' directions after the formation of the ninth insulating layer 19 and the fifth dummy layer 75, respectively, provided in some embodiments.

[0125] In some embodiments, the semiconductor thin film may be, for example, single-crystal silicon, silicon-germanium, etc.

[0126] 10) Forming a character line 40;

[0127] A tenth insulating film is deposited on the aforementioned structure to form a tenth insulating layer 20, which covers the aforementioned structure. At this time, the fifth dummy layer 75 and the third dummy layer 73 are covered by the tenth insulating layer 20.

[0128] The tenth insulating layer 20 is etched to expose the fifth dummy layer 75 in the second hole K2 on the side away from the substrate 1. The fifth dummy layer 75 in the second hole K2 is etched away, and the ninth insulating layer 19 in the second hole K2 is etched away, so that the first sacrificial layer 5 and the second sacrificial layer 6 are exposed on the sidewall of the second hole K2.

[0129] Based on the second hole K2, the first sacrificial layer 5 and the second sacrificial layer 6 are etched, and the first sacrificial layer 5 is etched along the first direction X for a first preset length, retaining a portion of the first sacrificial layer 5; the second sacrificial layer 6 in the third groove is etched away, and a portion of the second sacrificial layer 6 in the second groove is etched away and a portion is retained. At this time, a portion of the surface of the semiconductor structure layer 23' is exposed, including a portion of the surface facing away from the substrate 1, and a portion of the surfaces on both sides disposed opposite to each other along the second direction Y; the semiconductor structure layer 23' includes a semiconductor layer 23 disposed in the channel B1 and a semiconductor thin film disposed in the first groove.

[0130] The exposed surface of the semiconductor structure layer 23' is subjected to thermal oxidation treatment to form a gate insulating layer 24 covering the surface of the semiconductor structure layer 23'.

[0131] A first conductive film is deposited, covering the bottom and sidewalls of the second hole K2, filling the cavity formed after the first sacrificial layer 5 and the second sacrificial layer 6 are etched away. A second conductive film is then etched away from the bottom and sidewalls of the second hole K2. Finally, the second conductive film filling the cavity formed after the first sacrificial layer 5 and the second sacrificial layer 6 are etched along the first direction X for a second predetermined length (so that there is a certain distance between the subsequently formed word line 40 and the bit line 30), forming the word line 40. Figures 11A to 11D As shown, Figures 11A to 11D These are cross-sectional views along the AA', B1B1', CC', and DD' directions after forming the word line 40, as provided in some embodiments.

[0132] In some embodiments, the first conductive film may be one or more of the following different types of materials:

[0133] For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can be a metal alloy containing these metals.

[0134] Alternatively, it can be conductive metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as conductive metal oxide materials like indium tin oxide (ITO), indium zinc oxide (IZO), and indium oxide (InO); or conductive metal nitride materials like titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN).

[0135] Alternatively, it could be polycrystalline silicon, silicon, germanium, silicon-germanium, etc., which become conductive after doping.

[0136] The materials of the subsequent second to fourth conductive films are similar to those of the first conductive film, and will not be described in detail here.

[0137] 11) Forming bit line 30;

[0138] An eleventh insulating film is deposited, which covers the bottom wall and sidewall of the second hole K2 and fills the area between the word line 40 and the second hole K2. The eleventh insulating film is etched away from the bottom wall and sidewall of the second hole K2 to form an eleventh insulating layer 21. The gate insulating layer 24 covering the semiconductor structure layer 23' facing the second hole K2 is etched to expose the semiconductor structure layer 23'.

[0139] A first interconnect layer thin film is deposited and subjected to high-temperature heat treatment to form a first interconnect layer 61; the first interconnect layer 61 covers the semiconductor structure layer 23' on the side facing the second hole K2.

[0140] After depositing the second conductive film, it is smoothed out. The second conductive film fills the second hole K2, forming bit line 30. The bit line 30 is flush with the side of the tenth insulating layer 20 facing away from the substrate 1. Figures 12A to 12C As shown, Figures 12A to 12C These are cross-sectional views along the AA', B1B1', and CC' directions after the bit line 30 is formed, provided in some embodiments.

[0141] In some embodiments, the first interconnect layer 61 may be a silicide of titanium (Ti), cobalt (Co), nickel (Ni), or nickel-platinum (NiPt), such as titanium disilicide (TiSi2), cobalt disilicide (CoSi2), and nickel-platinum silicide (NiPtSi). That is, the first interconnect layer 61 is formed by metallizing the end face of the semiconductor structure layer 23' facing the second hole K2. The first interconnect layer 61 can reduce the contact resistance between the semiconductor structure layer 23' and the subsequently formed bit line 30. The material of the subsequent second interconnect layer 62 is similar and will not be described further.

[0142] In this embodiment, bit line 30 is a solid structure, but the embodiments disclosed herein are not limited to this. In some embodiments, bit line 30 may be a hollow structure.

[0143] In this embodiment, adjacent memory cells along the first direction X are connected to the same bit line 30. However, this embodiment is not limited to this; adjacent memory cells along the first direction X may be connected to different bit lines 30.

[0144] In some embodiments, bit lines 30 may be etched to increase the distance between adjacent bit lines 30 along the second direction Y and reduce the coupling between adjacent bit lines 30 along the second direction Y.

[0145] 12) Forming a capacitor structure;

[0146] The tenth insulating layer 20 is etched to expose the first hole K1;

[0147] The fifth dummy layer 75 in the first hole K1 is etched away, and the ninth insulating layer 19 in the first hole K1 is etched away, exposing the semiconductor structure layer 23' in the first groove;

[0148] The semiconductor structure layer 23' in the first groove is etched away, while the semiconductor structure layer 23' in the channel B1 is retained, forming a semiconductor layer 23; at this time, the second sacrificial layer 6 is exposed; the second sacrificial layer 6 is etched away, a twelfth insulating film is deposited, the twelfth insulating film in the first hole K1 and the first groove is etched away, while the twelfth insulating film in the area where the second sacrificial layer 6 is located is retained, forming a twelfth insulating layer, that is, the twelfth insulating layer 6 is replaced by the twelfth insulating layer; in some embodiments, the second sacrificial layer 6 may not be replaced.

[0149] A second connecting layer thin film is deposited, and the second connecting layer thin film is subjected to high-temperature heat treatment to form a second connecting layer 62. The second connecting layer 62 covers the semiconductor structure layer 23' on the side facing the first hole K1. The second connecting layer 62 connects the subsequently formed first capacitor electrode 41 (i.e., the first electrode) and the semiconductor layer 23. That is, by performing metal silicide treatment on the end face of the semiconductor structure layer 23' facing the first hole K1 to form the second connecting layer 62, the contact resistance between the first capacitor electrode 41 and the semiconductor layer 23 can be reduced.

[0150] A third conductive film and a sixth dummy layer film are deposited sequentially. The third conductive film covers the inner wall of the first groove, as well as the bottom wall and side wall of the first hole K1. The sixth dummy layer film fills the first groove and covers the bottom wall and side wall of the first hole K1. The sixth dummy layer film and the third conductive film in the first hole K1 are etched away to form a first capacitor electrode 41 and a sixth dummy layer. The first capacitor electrode 41 covers the inner wall of the first groove, and the sixth dummy layer fills the first groove.

[0151] The sixth dummy layer in the first groove is etched away, and the sixth dummy layer in the first groove is etched away, and the third dummy layer 73 in the first trench T1 and the first transverse trench L1 is etched away, and the fifth insulating layer 15 is etched away to expose the first capacitor electrode 41.

[0152] A dielectric layer film and a fourth conductive film are deposited sequentially. The dielectric layer film covers the bottom and sidewalls of the first hole K1, and the inner walls of the first trench T1 and the first lateral trench L1. The fourth conductive film fills the first hole K1, the first trench T1, and the first lateral trench L1, forming a first dielectric layer 431 covering the bottom and sidewalls of the first hole K1, a second dielectric layer 432 covering the inner walls of the first trench T1 and the first lateral trench L1, a first sub-electrode 421 filling the first hole K1, and a second sub-electrode 422 filling the first trench T1 and the first lateral trench L1. Figures 1A to 1D As shown.

[0153] In some embodiments, the dielectric film may be a Low-K material, such as silicon oxide. Alternatively, it may be a High-K material, such as a dielectric material with a dielectric constant K ≥ 3.9. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary examples include, but are not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and other high-K materials.

[0154] The capacitor structure shown in this embodiment is merely an example, and the embodiments disclosed herein are not limited thereto.

[0155] In some embodiments, in step 1), a stacked structure comprising a plurality of first insulating layers 11, first sacrificial layers 5, and first dummy layers 71 arranged sequentially can be formed, i.e., the positions of the first sacrificial layers 5 and the first dummy layers 71 are interchanged. In subsequent manufacturing processes, the formed semiconductor structure layer 23' is located on the side of the first sacrificial layer 5 facing away from the substrate 1. Correspondingly, the formed word lines 40 surround the semiconductor structure layer 23' on the side facing the substrate 1, and are arranged opposite to each other along the second direction Y. The manufacturing process can be referred to the previous embodiment, and will not be repeated here.

[0156] This disclosure also provides an electronic device, including the semiconductor device described in any of the foregoing embodiments, or a semiconductor device formed by the manufacturing method of the semiconductor device described in any of the foregoing embodiments. The electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0157] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection for this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A semiconductor device, characterized in that, include: Multiple memory cells are stacked along the vertical substrate direction, distributed across different layers; Bit lines extend through the memory cells in different layers along a direction perpendicular to the substrate; Multiple word lines are distributed in different layers. The word lines and the bit lines are distributed along a first direction parallel to the substrate, and the word lines extend along a second direction parallel to the substrate. The first direction and the second direction intersect. The memory cell includes a transistor, the transistor including a semiconductor layer extending along a first direction, and the semiconductor layers of the plurality of memory cells are connected to the bit line; The word lines surround the semiconductor layer on the side away from the substrate, and are disposed on both sides of the semiconductor layer opposite to each other along the second direction, and are not distributed on the side of the semiconductor layer facing the substrate; or, the word lines surround the semiconductor layer on the side facing the substrate, and are disposed on both sides of the semiconductor layer opposite to each other along the second direction, and are not distributed on the side of the semiconductor layer away from the substrate.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor device includes: a multilayer memory cell array, each layer of the memory cell array including a plurality of memory cells distributed along the first direction and the second direction; word lines surrounding a plurality of semiconductor layers of a plurality of transistors distributed in the same column along the second direction, the word lines including a horizontal portion extending along the second direction and a plurality of vertical portions extending from the horizontal portion to adjacent semiconductor layers along the second direction, and the horizontal portion and the vertical portion being an integral structure.

3. The semiconductor device according to claim 2, characterized in that, The vertical portion facing the bit line includes a first recessed area, and the vertical portion away from the bit line includes a second recessed area. The first recessed area and the second recessed area are arranged opposite to each other along a first direction and have opposite recessed directions.

4. The semiconductor device according to claim 1, characterized in that, The semiconductor layer has protrusions on opposite sides along the second direction that protrude parallel to the substrate. From the location of the protrusion toward the bit line, the size of the semiconductor layer along the second direction decreases sequentially; from the location of the protrusion away from the bit line, the size of the semiconductor layer along the second direction decreases sequentially.

5. The semiconductor device according to claim 1, characterized in that, The transistor further includes a first connection layer disposed between the semiconductor layer and the bit line, the first connection layer covering the semiconductor layer on the side facing the bit line, and the semiconductor layer being connected to the bit line through the first connection layer.

6. The semiconductor device according to claim 3, characterized in that, The transistor further includes a first electrode disposed on the side of the semiconductor layer away from the bit line, the first electrode forming an annular groove with an opening direction parallel to the substrate, and a second connection layer disposed between the semiconductor layer and the first electrode, the second connection layer covering the side of the semiconductor layer facing the first electrode and connecting the outer bottom wall of the first electrode and the semiconductor layer.

7. The semiconductor device according to claim 1, characterized in that, The semiconductor layer includes a first region, a channel region, and a second region sequentially disposed along the first direction. The word line portion surrounds the channel region and is not distributed in the first region and the second region. The second region is disposed on the side of the first region facing the bit line. The transistor further includes a gate insulating layer disposed between the semiconductor layer and the word line. The gate insulating layer is distributed in the channel region and the second region of the semiconductor layer.

8. The semiconductor device according to claim 6, characterized in that, The semiconductor device further includes: a first isolation sublayer disposed between adjacent bit lines along a second direction and penetrating multiple layers, and a second isolation sublayer disposed between adjacent semiconductor layers along a second direction and penetrating multiple layers, wherein the first isolation sublayer is connected to a first recessed region of a plurality of word lines spaced apart along a direction perpendicular to the substrate and to two bit lines adjacent along the second direction; and the second isolation sublayer is connected to a second recessed region of a plurality of word lines spaced apart along a direction perpendicular to the substrate and to two first electrodes adjacent along the second direction.

9. The semiconductor device according to claim 6, characterized in that, The storage unit further includes: a capacitor, the capacitor including a first sub-electrode and a second sub-electrode, the first electrode surrounding the first sub-electrode, the first sub-electrode being distributed on the inner wall of the annular groove formed by the first electrode; the first sub-electrodes of storage units at the same position in different layers are connected to form an integral structure; the second sub-electrode is distributed on a portion of the outer bottom wall of the annular groove formed by the first electrode.

10. The semiconductor device according to claim 9, characterized in that, The second sub-electrodes of capacitors in the same column distributed along the second direction in the same layer are connected to form an integral structure; the second sub-electrode includes a connecting portion extending along a direction perpendicular to the substrate and a plurality of horizontal extension portions distributed at intervals along a direction perpendicular to the substrate and extending along a direction parallel to the substrate, the horizontal extension portions being distributed on a portion of the outer bottom wall of the annular groove formed by the first electrode.

11. A method for manufacturing a semiconductor device, characterized in that, include: A stacked structure comprising multiple sequentially stacked first insulating layers, first dummy layers, and first sacrificial layers is formed on a substrate; Alternatively, a stacked structure comprising multiple sequentially stacked first insulating layers, first sacrificial layers, and first dummy layers can be formed. A plurality of first holes are formed that penetrate the stacked structure along a direction perpendicular to the substrate and are spaced apart along a second direction parallel to the substrate; A first trench is formed that penetrates the stacked structure in a direction perpendicular to the substrate and extends in a second direction. Based on the first trench, the first dummy layer and the first sacrificial layer are etched in a direction parallel to the substrate until the first hole is away from the first trench, forming a first lateral trench. A second hole is formed on the side of the first hole away from the first trench, penetrating the stacked structure perpendicular to the substrate direction, and the first hole and the second hole are spaced apart along a first direction parallel to the substrate; A third and a fourth hole are formed through the stacked structure in a direction perpendicular to the substrate. The third and fourth holes are spaced apart in a first direction. The fourth hole is disposed between adjacent second holes in a second direction. The third hole is disposed on the side of the fourth hole facing the first trench and on the side of the first hole facing away from the first trench. The first dummy layer is etched based on the third and fourth holes to form a second groove surrounding the third hole and a third groove surrounding the fourth hole. The first dummy layer forms a plurality of dummy sublayers spaced apart in a second direction. A second sacrificial layer is formed to fill the second and third grooves. The dummy sublayer is removed based on the first and second holes to form a channel communicating with the first and second holes. A semiconductor layer is formed in the channel. Based on the second hole, the first sacrificial layer and the second sacrificial layer are etched to expose a portion of the semiconductor layer facing the first sacrificial layer connected to the semiconductor layer, and a portion of the two sides disposed opposite to each other along the second direction; Word lines are formed around the semiconductor layer toward the first sacrificial layer connected to the semiconductor layer, and on both sides of the semiconductor layer disposed opposite to each other along the second direction; A bit line is formed in the second hole, extending in a direction perpendicular to the substrate, and the bit line connects multiple semiconductor layers in multiple channels communicating with the second hole.

12. The method for manufacturing a semiconductor device according to claim 11, characterized in that, Before forming word lines on both sides of the semiconductor layer facing the first sacrificial layer connected to the semiconductor layer, and before forming word lines on both sides of the semiconductor layer opposite to each other along the second direction, the method further includes: thermally oxidizing the exposed surface of the semiconductor layer to form a gate insulating layer; Before the second hole is formed with a bit line extending perpendicular to the substrate, the method further includes: performing metallization on the end face of the semiconductor layer facing the second hole to form a first interconnect layer.

13. The method for manufacturing a semiconductor device according to claim 11, characterized in that, Before forming the first trench that penetrates the stacked structure perpendicular to the substrate and extends along the second direction, the method further includes: etching the first dummy layer and the first sacrificial layer along the direction parallel to the substrate based on the first hole to form a first groove; After the second hole is formed with a bit line extending perpendicular to the substrate direction, the method further includes: performing metallization treatment on the end face of the semiconductor layer facing the first hole to form a second interconnect layer; A first electrode is formed on the inner wall of the first groove and connected to the second connecting layer.

14. An electronic device, characterized in that, This includes the semiconductor device as described in any one of claims 1 to 10, or the semiconductor device formed by the manufacturing method of the semiconductor device as described in any one of claims 11 to 13.

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